| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| 2 | |* *| |
| 3 | |* Global Instruction Selector for the AArch64 target *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | #ifdef GET_GLOBALISEL_PREDICATE_BITSET |
| 10 | const unsigned MAX_SUBTARGET_PREDICATES = 38; |
| 11 | using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>; |
| 12 | #endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET |
| 13 | |
| 14 | #ifdef GET_GLOBALISEL_TEMPORARIES_DECL |
| 15 | mutable MatcherState State; |
| 16 | typedef ComplexRendererFns(AArch64InstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const; |
| 17 | typedef void(AArch64InstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const; |
| 18 | const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo; |
| 19 | static AArch64InstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[]; |
| 20 | static AArch64InstructionSelector::CustomRendererFn CustomRenderers[]; |
| 21 | bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override; |
| 22 | bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override; |
| 23 | bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override; |
| 24 | const int64_t *getMatchTable() const override; |
| 25 | bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const std::array<const MachineOperand *, 3> &Operands) const override; |
| 26 | #endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL |
| 27 | |
| 28 | #ifdef GET_GLOBALISEL_TEMPORARIES_INIT |
| 29 | , State(1), |
| 30 | ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers) |
| 31 | #endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT |
| 32 | |
| 33 | #ifdef GET_GLOBALISEL_IMPL |
| 34 | // Bits for subtarget features that participate in instruction matching. |
| 35 | enum SubtargetFeatureBits : uint8_t { |
| 36 | Feature_HasJSBit = 7, |
| 37 | Feature_HasComplxNumBit = 24, |
| 38 | Feature_HasFPARMv8Bit = 6, |
| 39 | Feature_HasNEONBit = 5, |
| 40 | Feature_HasSHA2Bit = 14, |
| 41 | Feature_HasAESBit = 13, |
| 42 | Feature_HasDotProdBit = 1, |
| 43 | Feature_HasCRCBit = 9, |
| 44 | Feature_HasLSEBit = 22, |
| 45 | Feature_HasRDMBit = 12, |
| 46 | Feature_HasPerfMonBit = 25, |
| 47 | Feature_HasFullFP16Bit = 11, |
| 48 | Feature_HasFP16FMLBit = 4, |
| 49 | Feature_HasFuseAESBit = 33, |
| 50 | Feature_HasSVEBit = 0, |
| 51 | Feature_HasSVE2Bit = 15, |
| 52 | Feature_HasSVE2AESBit = 18, |
| 53 | Feature_HasSVE2SM4Bit = 19, |
| 54 | Feature_HasSVE2SHA3Bit = 20, |
| 55 | Feature_HasSVE2BitPermBit = 21, |
| 56 | Feature_HasMTEBit = 10, |
| 57 | Feature_HasTMEBit = 8, |
| 58 | Feature_HasBF16Bit = 2, |
| 59 | Feature_HasMatMulInt8Bit = 3, |
| 60 | Feature_HasMatMulFP32Bit = 23, |
| 61 | Feature_HasMatMulFP64Bit = 16, |
| 62 | Feature_HasLS64Bit = 37, |
| 63 | Feature_IsLEBit = 29, |
| 64 | Feature_IsBEBit = 34, |
| 65 | Feature_UseExperimentalZeroingPseudosBit = 17, |
| 66 | Feature_UseAlternateSExtLoadCVTF32Bit = 32, |
| 67 | Feature_NotForCodeSizeBit = 31, |
| 68 | Feature_UseSTRQroBit = 30, |
| 69 | Feature_UseBTIBit = 36, |
| 70 | Feature_NotUseBTIBit = 35, |
| 71 | Feature_SLSBLRMitigationBit = 28, |
| 72 | Feature_NoSLSBLRMitigationBit = 27, |
| 73 | Feature_OptimizedGISelOrOtherSelectorBit = 26, |
| 74 | }; |
| 75 | |
| 76 | PredicateBitset AArch64InstructionSelector:: |
| 77 | computeAvailableModuleFeatures(const AArch64Subtarget *Subtarget) const { |
| 78 | PredicateBitset Features; |
| 79 | if (Subtarget->hasJS()) |
| 80 | Features.set(Feature_HasJSBit); |
| 81 | if (Subtarget->hasComplxNum()) |
| 82 | Features.set(Feature_HasComplxNumBit); |
| 83 | if (Subtarget->hasFPARMv8()) |
| 84 | Features.set(Feature_HasFPARMv8Bit); |
| 85 | if (Subtarget->hasNEON()) |
| 86 | Features.set(Feature_HasNEONBit); |
| 87 | if (Subtarget->hasSHA2()) |
| 88 | Features.set(Feature_HasSHA2Bit); |
| 89 | if (Subtarget->hasAES()) |
| 90 | Features.set(Feature_HasAESBit); |
| 91 | if (Subtarget->hasDotProd()) |
| 92 | Features.set(Feature_HasDotProdBit); |
| 93 | if (Subtarget->hasCRC()) |
| 94 | Features.set(Feature_HasCRCBit); |
| 95 | if (Subtarget->hasLSE()) |
| 96 | Features.set(Feature_HasLSEBit); |
| 97 | if (Subtarget->hasRDM()) |
| 98 | Features.set(Feature_HasRDMBit); |
| 99 | if (Subtarget->hasPerfMon()) |
| 100 | Features.set(Feature_HasPerfMonBit); |
| 101 | if (Subtarget->hasFullFP16()) |
| 102 | Features.set(Feature_HasFullFP16Bit); |
| 103 | if (Subtarget->hasFP16FML()) |
| 104 | Features.set(Feature_HasFP16FMLBit); |
| 105 | if (Subtarget->hasFuseAES()) |
| 106 | Features.set(Feature_HasFuseAESBit); |
| 107 | if (Subtarget->hasSVE()) |
| 108 | Features.set(Feature_HasSVEBit); |
| 109 | if (Subtarget->hasSVE2()) |
| 110 | Features.set(Feature_HasSVE2Bit); |
| 111 | if (Subtarget->hasSVE2AES()) |
| 112 | Features.set(Feature_HasSVE2AESBit); |
| 113 | if (Subtarget->hasSVE2SM4()) |
| 114 | Features.set(Feature_HasSVE2SM4Bit); |
| 115 | if (Subtarget->hasSVE2SHA3()) |
| 116 | Features.set(Feature_HasSVE2SHA3Bit); |
| 117 | if (Subtarget->hasSVE2BitPerm()) |
| 118 | Features.set(Feature_HasSVE2BitPermBit); |
| 119 | if (Subtarget->hasMTE()) |
| 120 | Features.set(Feature_HasMTEBit); |
| 121 | if (Subtarget->hasTME()) |
| 122 | Features.set(Feature_HasTMEBit); |
| 123 | if (Subtarget->hasBF16()) |
| 124 | Features.set(Feature_HasBF16Bit); |
| 125 | if (Subtarget->hasMatMulInt8()) |
| 126 | Features.set(Feature_HasMatMulInt8Bit); |
| 127 | if (Subtarget->hasMatMulFP32()) |
| 128 | Features.set(Feature_HasMatMulFP32Bit); |
| 129 | if (Subtarget->hasMatMulFP64()) |
| 130 | Features.set(Feature_HasMatMulFP64Bit); |
| 131 | if (Subtarget->hasLS64()) |
| 132 | Features.set(Feature_HasLS64Bit); |
| 133 | if (Subtarget->isLittleEndian()) |
| 134 | Features.set(Feature_IsLEBit); |
| 135 | if (!Subtarget->isLittleEndian()) |
| 136 | Features.set(Feature_IsBEBit); |
| 137 | if (Subtarget->useExperimentalZeroingPseudos()) |
| 138 | Features.set(Feature_UseExperimentalZeroingPseudosBit); |
| 139 | if (Subtarget->useAlternateSExtLoadCVTF32Pattern()) |
| 140 | Features.set(Feature_UseAlternateSExtLoadCVTF32Bit); |
| 141 | return Features; |
| 142 | } |
| 143 | |
| 144 | void AArch64InstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) { |
| 145 | AvailableFunctionFeatures = computeAvailableFunctionFeatures((const AArch64Subtarget *)&MF.getSubtarget(), &MF); |
| 146 | } |
| 147 | static bool shouldOptForSize(const MachineFunction *MF) { |
| 148 | return MF->getFunction().hasOptSize(); |
| 149 | } |
| 150 | |
| 151 | PredicateBitset AArch64InstructionSelector:: |
| 152 | computeAvailableFunctionFeatures(const AArch64Subtarget *Subtarget, const MachineFunction *MF) const { |
| 153 | PredicateBitset Features; |
| 154 | if (!shouldOptForSize(MF)) |
| 155 | Features.set(Feature_NotForCodeSizeBit); |
| 156 | if (!Subtarget->isSTRQroSlow() || shouldOptForSize(MF)) |
| 157 | Features.set(Feature_UseSTRQroBit); |
| 158 | if ( MF->getInfo<AArch64FunctionInfo>()->branchTargetEnforcement() ) |
| 159 | Features.set(Feature_UseBTIBit); |
| 160 | if ( !MF->getInfo<AArch64FunctionInfo>()->branchTargetEnforcement() ) |
| 161 | Features.set(Feature_NotUseBTIBit); |
| 162 | if ( MF->getSubtarget<AArch64Subtarget>().hardenSlsBlr() ) |
| 163 | Features.set(Feature_SLSBLRMitigationBit); |
| 164 | if ( !MF->getSubtarget<AArch64Subtarget>().hardenSlsBlr() ) |
| 165 | Features.set(Feature_NoSLSBLRMitigationBit); |
| 166 | if (!MF->getFunction().hasOptNone() || MF->getProperties().hasProperty(MachineFunctionProperties::Property::FailedISel) || !MF->getProperties().hasProperty(MachineFunctionProperties::Property::Legalized)) |
| 167 | Features.set(Feature_OptimizedGISelOrOtherSelectorBit); |
| 168 | return Features; |
| 169 | } |
| 170 | |
| 171 | // LLT Objects. |
| 172 | enum { |
| 173 | GILLT_s16, |
| 174 | GILLT_s32, |
| 175 | GILLT_s64, |
| 176 | GILLT_s128, |
| 177 | GILLT_v2s32, |
| 178 | GILLT_v2s64, |
| 179 | GILLT_v4s16, |
| 180 | GILLT_v4s32, |
| 181 | GILLT_v8s8, |
| 182 | GILLT_v8s16, |
| 183 | GILLT_v16s8, |
| 184 | }; |
| 185 | const static size_t NumTypeObjects = 11; |
| 186 | const static LLT TypeObjects[] = { |
| 187 | LLT::scalar(16), |
| 188 | LLT::scalar(32), |
| 189 | LLT::scalar(64), |
| 190 | LLT::scalar(128), |
| 191 | LLT::vector(2, 32), |
| 192 | LLT::vector(2, 64), |
| 193 | LLT::vector(4, 16), |
| 194 | LLT::vector(4, 32), |
| 195 | LLT::vector(8, 8), |
| 196 | LLT::vector(8, 16), |
| 197 | LLT::vector(16, 8), |
| 198 | }; |
| 199 | |
| 200 | // Feature bitsets. |
| 201 | enum { |
| 202 | GIFBS_Invalid, |
| 203 | GIFBS_HasAES, |
| 204 | GIFBS_HasBF16, |
| 205 | GIFBS_HasCRC, |
| 206 | GIFBS_HasDotProd, |
| 207 | GIFBS_HasFPARMv8, |
| 208 | GIFBS_HasFullFP16, |
| 209 | GIFBS_HasFuseAES, |
| 210 | GIFBS_HasLSE, |
| 211 | GIFBS_HasMTE, |
| 212 | GIFBS_HasMatMulInt8, |
| 213 | GIFBS_HasNEON, |
| 214 | GIFBS_HasPerfMon, |
| 215 | GIFBS_HasRDM, |
| 216 | GIFBS_HasSHA2, |
| 217 | GIFBS_HasSVE, |
| 218 | GIFBS_HasTME, |
| 219 | GIFBS_IsBE, |
| 220 | GIFBS_IsLE, |
| 221 | GIFBS_NotForCodeSize, |
| 222 | GIFBS_OptimizedGISelOrOtherSelector, |
| 223 | GIFBS_UseSTRQro, |
| 224 | GIFBS_HasComplxNum_HasNEON, |
| 225 | GIFBS_HasFP16FML_HasNEON, |
| 226 | GIFBS_HasFPARMv8_HasJS, |
| 227 | GIFBS_HasFullFP16_HasNEON, |
| 228 | GIFBS_HasNEON_HasRDM, |
| 229 | GIFBS_IsLE_UseSTRQro, |
| 230 | GIFBS_NotForCodeSize_UseAlternateSExtLoadCVTF32, |
| 231 | GIFBS_HasComplxNum_HasFullFP16_HasNEON, |
| 232 | }; |
| 233 | const static PredicateBitset FeatureBitsets[] { |
| 234 | {}, // GIFBS_Invalid |
| 235 | {Feature_HasAESBit, }, |
| 236 | {Feature_HasBF16Bit, }, |
| 237 | {Feature_HasCRCBit, }, |
| 238 | {Feature_HasDotProdBit, }, |
| 239 | {Feature_HasFPARMv8Bit, }, |
| 240 | {Feature_HasFullFP16Bit, }, |
| 241 | {Feature_HasFuseAESBit, }, |
| 242 | {Feature_HasLSEBit, }, |
| 243 | {Feature_HasMTEBit, }, |
| 244 | {Feature_HasMatMulInt8Bit, }, |
| 245 | {Feature_HasNEONBit, }, |
| 246 | {Feature_HasPerfMonBit, }, |
| 247 | {Feature_HasRDMBit, }, |
| 248 | {Feature_HasSHA2Bit, }, |
| 249 | {Feature_HasSVEBit, }, |
| 250 | {Feature_HasTMEBit, }, |
| 251 | {Feature_IsBEBit, }, |
| 252 | {Feature_IsLEBit, }, |
| 253 | {Feature_NotForCodeSizeBit, }, |
| 254 | {Feature_OptimizedGISelOrOtherSelectorBit, }, |
| 255 | {Feature_UseSTRQroBit, }, |
| 256 | {Feature_HasComplxNumBit, Feature_HasNEONBit, }, |
| 257 | {Feature_HasFP16FMLBit, Feature_HasNEONBit, }, |
| 258 | {Feature_HasFPARMv8Bit, Feature_HasJSBit, }, |
| 259 | {Feature_HasFullFP16Bit, Feature_HasNEONBit, }, |
| 260 | {Feature_HasNEONBit, Feature_HasRDMBit, }, |
| 261 | {Feature_IsLEBit, Feature_UseSTRQroBit, }, |
| 262 | {Feature_NotForCodeSizeBit, Feature_UseAlternateSExtLoadCVTF32Bit, }, |
| 263 | {Feature_HasComplxNumBit, Feature_HasFullFP16Bit, Feature_HasNEONBit, }, |
| 264 | }; |
| 265 | |
| 266 | // ComplexPattern predicates. |
| 267 | enum { |
| 268 | GICP_Invalid, |
| 269 | GICP_gi_addsub_shifted_imm32, |
| 270 | GICP_gi_addsub_shifted_imm64, |
| 271 | GICP_gi_am_indexed128, |
| 272 | GICP_gi_am_indexed16, |
| 273 | GICP_gi_am_indexed32, |
| 274 | GICP_gi_am_indexed64, |
| 275 | GICP_gi_am_indexed8, |
| 276 | GICP_gi_am_unscaled128, |
| 277 | GICP_gi_am_unscaled16, |
| 278 | GICP_gi_am_unscaled32, |
| 279 | GICP_gi_am_unscaled64, |
| 280 | GICP_gi_am_unscaled8, |
| 281 | GICP_gi_arith_extended_reg32_i32, |
| 282 | GICP_gi_arith_extended_reg32_i64, |
| 283 | GICP_gi_arith_extended_reg32to64_i64, |
| 284 | GICP_gi_arith_shifted_reg32, |
| 285 | GICP_gi_arith_shifted_reg64, |
| 286 | GICP_gi_logical_shifted_reg32, |
| 287 | GICP_gi_logical_shifted_reg64, |
| 288 | GICP_gi_neg_addsub_shifted_imm32, |
| 289 | GICP_gi_neg_addsub_shifted_imm64, |
| 290 | GICP_gi_ro_Windexed128, |
| 291 | GICP_gi_ro_Windexed16, |
| 292 | GICP_gi_ro_Windexed32, |
| 293 | GICP_gi_ro_Windexed64, |
| 294 | GICP_gi_ro_Windexed8, |
| 295 | GICP_gi_ro_Xindexed128, |
| 296 | GICP_gi_ro_Xindexed16, |
| 297 | GICP_gi_ro_Xindexed32, |
| 298 | GICP_gi_ro_Xindexed64, |
| 299 | GICP_gi_ro_Xindexed8, |
| 300 | }; |
| 301 | // See constructor for table contents |
| 302 | |
| 303 | // PatFrag predicates. |
| 304 | enum { |
| 305 | GIPFP_I64_Predicate_VectorIndex1 = GIPFP_I64_Invalid + 1, |
| 306 | GIPFP_I64_Predicate_VectorIndex132b, |
| 307 | GIPFP_I64_Predicate_VectorIndex132b_timm, |
| 308 | GIPFP_I64_Predicate_VectorIndex1_timm, |
| 309 | GIPFP_I64_Predicate_VectorIndexB, |
| 310 | GIPFP_I64_Predicate_VectorIndexB32b, |
| 311 | GIPFP_I64_Predicate_VectorIndexB32b_timm, |
| 312 | GIPFP_I64_Predicate_VectorIndexB_timm, |
| 313 | GIPFP_I64_Predicate_VectorIndexD, |
| 314 | GIPFP_I64_Predicate_VectorIndexD32b, |
| 315 | GIPFP_I64_Predicate_VectorIndexD32b_timm, |
| 316 | GIPFP_I64_Predicate_VectorIndexD_timm, |
| 317 | GIPFP_I64_Predicate_VectorIndexH, |
| 318 | GIPFP_I64_Predicate_VectorIndexH32b, |
| 319 | GIPFP_I64_Predicate_VectorIndexH32b_timm, |
| 320 | GIPFP_I64_Predicate_VectorIndexH_timm, |
| 321 | GIPFP_I64_Predicate_VectorIndexS, |
| 322 | GIPFP_I64_Predicate_VectorIndexS32b, |
| 323 | GIPFP_I64_Predicate_VectorIndexS32b_timm, |
| 324 | GIPFP_I64_Predicate_VectorIndexS_timm, |
| 325 | GIPFP_I64_Predicate_complexrotateop, |
| 326 | GIPFP_I64_Predicate_complexrotateopodd, |
| 327 | GIPFP_I64_Predicate_i32_imm0_65535, |
| 328 | GIPFP_I64_Predicate_i64_imm0_65535, |
| 329 | GIPFP_I64_Predicate_i64imm_32bit, |
| 330 | GIPFP_I64_Predicate_imm0_1, |
| 331 | GIPFP_I64_Predicate_imm0_127, |
| 332 | GIPFP_I64_Predicate_imm0_127_64b, |
| 333 | GIPFP_I64_Predicate_imm0_15, |
| 334 | GIPFP_I64_Predicate_imm0_255, |
| 335 | GIPFP_I64_Predicate_imm0_31, |
| 336 | GIPFP_I64_Predicate_imm0_63, |
| 337 | GIPFP_I64_Predicate_imm0_7, |
| 338 | GIPFP_I64_Predicate_imm32_0_15, |
| 339 | GIPFP_I64_Predicate_imm32_0_31, |
| 340 | GIPFP_I64_Predicate_imm32_0_7, |
| 341 | GIPFP_I64_Predicate_maski16_or_more, |
| 342 | GIPFP_I64_Predicate_maski8_or_more, |
| 343 | GIPFP_I64_Predicate_s64imm_32bit, |
| 344 | GIPFP_I64_Predicate_simm4s1, |
| 345 | GIPFP_I64_Predicate_simm4s16, |
| 346 | GIPFP_I64_Predicate_simm4s2, |
| 347 | GIPFP_I64_Predicate_simm4s3, |
| 348 | GIPFP_I64_Predicate_simm4s32, |
| 349 | GIPFP_I64_Predicate_simm4s4, |
| 350 | GIPFP_I64_Predicate_simm5_16b, |
| 351 | GIPFP_I64_Predicate_simm5_32b, |
| 352 | GIPFP_I64_Predicate_simm5_64b, |
| 353 | GIPFP_I64_Predicate_simm5_8b, |
| 354 | GIPFP_I64_Predicate_simm6_32b, |
| 355 | GIPFP_I64_Predicate_simm6s1, |
| 356 | GIPFP_I64_Predicate_simm8, |
| 357 | GIPFP_I64_Predicate_simm9, |
| 358 | GIPFP_I64_Predicate_sve_elm_idx_extdup_b, |
| 359 | GIPFP_I64_Predicate_sve_elm_idx_extdup_b_timm, |
| 360 | GIPFP_I64_Predicate_sve_elm_idx_extdup_d, |
| 361 | GIPFP_I64_Predicate_sve_elm_idx_extdup_d_timm, |
| 362 | GIPFP_I64_Predicate_sve_elm_idx_extdup_h, |
| 363 | GIPFP_I64_Predicate_sve_elm_idx_extdup_h_timm, |
| 364 | GIPFP_I64_Predicate_sve_elm_idx_extdup_q, |
| 365 | GIPFP_I64_Predicate_sve_elm_idx_extdup_q_timm, |
| 366 | GIPFP_I64_Predicate_sve_elm_idx_extdup_s, |
| 367 | GIPFP_I64_Predicate_sve_elm_idx_extdup_s_timm, |
| 368 | GIPFP_I64_Predicate_sve_incdec_imm, |
| 369 | GIPFP_I64_Predicate_sve_pred_enum, |
| 370 | GIPFP_I64_Predicate_sve_prfop, |
| 371 | GIPFP_I64_Predicate_tbz_imm0_31_diag, |
| 372 | GIPFP_I64_Predicate_tbz_imm0_31_nodiag, |
| 373 | GIPFP_I64_Predicate_tbz_imm32_63, |
| 374 | GIPFP_I64_Predicate_timm0_1, |
| 375 | GIPFP_I64_Predicate_timm0_31, |
| 376 | GIPFP_I64_Predicate_tuimm5s2, |
| 377 | GIPFP_I64_Predicate_tuimm5s4, |
| 378 | GIPFP_I64_Predicate_tuimm5s8, |
| 379 | GIPFP_I64_Predicate_tvecshiftL16, |
| 380 | GIPFP_I64_Predicate_tvecshiftL32, |
| 381 | GIPFP_I64_Predicate_tvecshiftL64, |
| 382 | GIPFP_I64_Predicate_tvecshiftL8, |
| 383 | GIPFP_I64_Predicate_tvecshiftR16, |
| 384 | GIPFP_I64_Predicate_tvecshiftR32, |
| 385 | GIPFP_I64_Predicate_tvecshiftR64, |
| 386 | GIPFP_I64_Predicate_tvecshiftR8, |
| 387 | GIPFP_I64_Predicate_ubsan_trap_imm, |
| 388 | GIPFP_I64_Predicate_uimm16, |
| 389 | GIPFP_I64_Predicate_uimm5s2, |
| 390 | GIPFP_I64_Predicate_uimm5s4, |
| 391 | GIPFP_I64_Predicate_uimm5s8, |
| 392 | GIPFP_I64_Predicate_uimm6, |
| 393 | GIPFP_I64_Predicate_uimm6s1, |
| 394 | GIPFP_I64_Predicate_uimm6s16, |
| 395 | GIPFP_I64_Predicate_uimm6s2, |
| 396 | GIPFP_I64_Predicate_uimm6s4, |
| 397 | GIPFP_I64_Predicate_uimm6s8, |
| 398 | GIPFP_I64_Predicate_vecshiftL16, |
| 399 | GIPFP_I64_Predicate_vecshiftL32, |
| 400 | GIPFP_I64_Predicate_vecshiftL64, |
| 401 | GIPFP_I64_Predicate_vecshiftL8, |
| 402 | GIPFP_I64_Predicate_vecshiftR16, |
| 403 | GIPFP_I64_Predicate_vecshiftR16Narrow, |
| 404 | GIPFP_I64_Predicate_vecshiftR32, |
| 405 | GIPFP_I64_Predicate_vecshiftR32Narrow, |
| 406 | GIPFP_I64_Predicate_vecshiftR64, |
| 407 | GIPFP_I64_Predicate_vecshiftR64Narrow, |
| 408 | GIPFP_I64_Predicate_vecshiftR8, |
| 409 | }; |
| 410 | bool AArch64InstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const { |
| 411 | switch (PredicateID) { |
| 412 | case GIPFP_I64_Predicate_VectorIndex1: { |
| 413 | return ((uint64_t)Imm) == 1; |
| 414 | llvm_unreachable("ImmediateCode should have returned" ); |
| 415 | return false; |
| 416 | } |
| 417 | case GIPFP_I64_Predicate_VectorIndex132b: { |
| 418 | return ((uint64_t)Imm) == 1; |
| 419 | llvm_unreachable("ImmediateCode should have returned" ); |
| 420 | return false; |
| 421 | } |
| 422 | case GIPFP_I64_Predicate_VectorIndex132b_timm: { |
| 423 | return ((uint64_t)Imm) == 1; |
| 424 | llvm_unreachable("ImmediateCode should have returned" ); |
| 425 | return false; |
| 426 | } |
| 427 | case GIPFP_I64_Predicate_VectorIndex1_timm: { |
| 428 | return ((uint64_t)Imm) == 1; |
| 429 | llvm_unreachable("ImmediateCode should have returned" ); |
| 430 | return false; |
| 431 | } |
| 432 | case GIPFP_I64_Predicate_VectorIndexB: { |
| 433 | return ((uint64_t)Imm) < 16; |
| 434 | llvm_unreachable("ImmediateCode should have returned" ); |
| 435 | return false; |
| 436 | } |
| 437 | case GIPFP_I64_Predicate_VectorIndexB32b: { |
| 438 | return ((uint64_t)Imm) < 16; |
| 439 | llvm_unreachable("ImmediateCode should have returned" ); |
| 440 | return false; |
| 441 | } |
| 442 | case GIPFP_I64_Predicate_VectorIndexB32b_timm: { |
| 443 | return ((uint64_t)Imm) < 16; |
| 444 | llvm_unreachable("ImmediateCode should have returned" ); |
| 445 | return false; |
| 446 | } |
| 447 | case GIPFP_I64_Predicate_VectorIndexB_timm: { |
| 448 | return ((uint64_t)Imm) < 16; |
| 449 | llvm_unreachable("ImmediateCode should have returned" ); |
| 450 | return false; |
| 451 | } |
| 452 | case GIPFP_I64_Predicate_VectorIndexD: { |
| 453 | return ((uint64_t)Imm) < 2; |
| 454 | llvm_unreachable("ImmediateCode should have returned" ); |
| 455 | return false; |
| 456 | } |
| 457 | case GIPFP_I64_Predicate_VectorIndexD32b: { |
| 458 | return ((uint64_t)Imm) < 2; |
| 459 | llvm_unreachable("ImmediateCode should have returned" ); |
| 460 | return false; |
| 461 | } |
| 462 | case GIPFP_I64_Predicate_VectorIndexD32b_timm: { |
| 463 | return ((uint64_t)Imm) < 2; |
| 464 | llvm_unreachable("ImmediateCode should have returned" ); |
| 465 | return false; |
| 466 | } |
| 467 | case GIPFP_I64_Predicate_VectorIndexD_timm: { |
| 468 | return ((uint64_t)Imm) < 2; |
| 469 | llvm_unreachable("ImmediateCode should have returned" ); |
| 470 | return false; |
| 471 | } |
| 472 | case GIPFP_I64_Predicate_VectorIndexH: { |
| 473 | return ((uint64_t)Imm) < 8; |
| 474 | llvm_unreachable("ImmediateCode should have returned" ); |
| 475 | return false; |
| 476 | } |
| 477 | case GIPFP_I64_Predicate_VectorIndexH32b: { |
| 478 | return ((uint64_t)Imm) < 8; |
| 479 | llvm_unreachable("ImmediateCode should have returned" ); |
| 480 | return false; |
| 481 | } |
| 482 | case GIPFP_I64_Predicate_VectorIndexH32b_timm: { |
| 483 | return ((uint64_t)Imm) < 8; |
| 484 | llvm_unreachable("ImmediateCode should have returned" ); |
| 485 | return false; |
| 486 | } |
| 487 | case GIPFP_I64_Predicate_VectorIndexH_timm: { |
| 488 | return ((uint64_t)Imm) < 8; |
| 489 | llvm_unreachable("ImmediateCode should have returned" ); |
| 490 | return false; |
| 491 | } |
| 492 | case GIPFP_I64_Predicate_VectorIndexS: { |
| 493 | return ((uint64_t)Imm) < 4; |
| 494 | llvm_unreachable("ImmediateCode should have returned" ); |
| 495 | return false; |
| 496 | } |
| 497 | case GIPFP_I64_Predicate_VectorIndexS32b: { |
| 498 | return ((uint64_t)Imm) < 4; |
| 499 | llvm_unreachable("ImmediateCode should have returned" ); |
| 500 | return false; |
| 501 | } |
| 502 | case GIPFP_I64_Predicate_VectorIndexS32b_timm: { |
| 503 | return ((uint64_t)Imm) < 4; |
| 504 | llvm_unreachable("ImmediateCode should have returned" ); |
| 505 | return false; |
| 506 | } |
| 507 | case GIPFP_I64_Predicate_VectorIndexS_timm: { |
| 508 | return ((uint64_t)Imm) < 4; |
| 509 | llvm_unreachable("ImmediateCode should have returned" ); |
| 510 | return false; |
| 511 | } |
| 512 | case GIPFP_I64_Predicate_complexrotateop: { |
| 513 | return Imm >= 0 && Imm <= 270; |
| 514 | llvm_unreachable("ImmediateCode should have returned" ); |
| 515 | return false; |
| 516 | } |
| 517 | case GIPFP_I64_Predicate_complexrotateopodd: { |
| 518 | return Imm >= 0 && Imm <= 270; |
| 519 | llvm_unreachable("ImmediateCode should have returned" ); |
| 520 | return false; |
| 521 | } |
| 522 | case GIPFP_I64_Predicate_i32_imm0_65535: { |
| 523 | |
| 524 | return ((uint32_t)Imm) < 65536; |
| 525 | |
| 526 | llvm_unreachable("ImmediateCode should have returned" ); |
| 527 | return false; |
| 528 | } |
| 529 | case GIPFP_I64_Predicate_i64_imm0_65535: { |
| 530 | |
| 531 | return ((uint64_t)Imm) < 65536; |
| 532 | |
| 533 | llvm_unreachable("ImmediateCode should have returned" ); |
| 534 | return false; |
| 535 | } |
| 536 | case GIPFP_I64_Predicate_i64imm_32bit: { |
| 537 | |
| 538 | return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm); |
| 539 | |
| 540 | llvm_unreachable("ImmediateCode should have returned" ); |
| 541 | return false; |
| 542 | } |
| 543 | case GIPFP_I64_Predicate_imm0_1: { |
| 544 | |
| 545 | return ((uint64_t)Imm) < 2; |
| 546 | |
| 547 | llvm_unreachable("ImmediateCode should have returned" ); |
| 548 | return false; |
| 549 | } |
| 550 | case GIPFP_I64_Predicate_imm0_127: { |
| 551 | |
| 552 | return ((uint32_t)Imm) < 128; |
| 553 | |
| 554 | llvm_unreachable("ImmediateCode should have returned" ); |
| 555 | return false; |
| 556 | } |
| 557 | case GIPFP_I64_Predicate_imm0_127_64b: { |
| 558 | |
| 559 | return ((uint64_t)Imm) < 128; |
| 560 | |
| 561 | llvm_unreachable("ImmediateCode should have returned" ); |
| 562 | return false; |
| 563 | } |
| 564 | case GIPFP_I64_Predicate_imm0_15: { |
| 565 | |
| 566 | return ((uint64_t)Imm) < 16; |
| 567 | |
| 568 | llvm_unreachable("ImmediateCode should have returned" ); |
| 569 | return false; |
| 570 | } |
| 571 | case GIPFP_I64_Predicate_imm0_255: { |
| 572 | |
| 573 | return ((uint32_t)Imm) < 256; |
| 574 | |
| 575 | llvm_unreachable("ImmediateCode should have returned" ); |
| 576 | return false; |
| 577 | } |
| 578 | case GIPFP_I64_Predicate_imm0_31: { |
| 579 | |
| 580 | return ((uint64_t)Imm) < 32; |
| 581 | |
| 582 | llvm_unreachable("ImmediateCode should have returned" ); |
| 583 | return false; |
| 584 | } |
| 585 | case GIPFP_I64_Predicate_imm0_63: { |
| 586 | |
| 587 | return ((uint64_t)Imm) < 64; |
| 588 | |
| 589 | llvm_unreachable("ImmediateCode should have returned" ); |
| 590 | return false; |
| 591 | } |
| 592 | case GIPFP_I64_Predicate_imm0_7: { |
| 593 | |
| 594 | return ((uint64_t)Imm) < 8; |
| 595 | |
| 596 | llvm_unreachable("ImmediateCode should have returned" ); |
| 597 | return false; |
| 598 | } |
| 599 | case GIPFP_I64_Predicate_imm32_0_15: { |
| 600 | |
| 601 | return ((uint32_t)Imm) < 16; |
| 602 | |
| 603 | llvm_unreachable("ImmediateCode should have returned" ); |
| 604 | return false; |
| 605 | } |
| 606 | case GIPFP_I64_Predicate_imm32_0_31: { |
| 607 | |
| 608 | return ((uint64_t)Imm) < 32; |
| 609 | |
| 610 | llvm_unreachable("ImmediateCode should have returned" ); |
| 611 | return false; |
| 612 | } |
| 613 | case GIPFP_I64_Predicate_imm32_0_7: { |
| 614 | |
| 615 | return ((uint32_t)Imm) < 8; |
| 616 | |
| 617 | llvm_unreachable("ImmediateCode should have returned" ); |
| 618 | return false; |
| 619 | } |
| 620 | case GIPFP_I64_Predicate_maski16_or_more: { |
| 621 | return (Imm & 0xffff) == 0xffff; |
| 622 | llvm_unreachable("ImmediateCode should have returned" ); |
| 623 | return false; |
| 624 | } |
| 625 | case GIPFP_I64_Predicate_maski8_or_more: { |
| 626 | return (Imm & 0xff) == 0xff; |
| 627 | llvm_unreachable("ImmediateCode should have returned" ); |
| 628 | return false; |
| 629 | } |
| 630 | case GIPFP_I64_Predicate_s64imm_32bit: { |
| 631 | |
| 632 | int64_t Imm64 = static_cast<int64_t>(Imm); |
| 633 | return Imm64 >= std::numeric_limits<int32_t>::min() && |
| 634 | Imm64 <= std::numeric_limits<int32_t>::max(); |
| 635 | |
| 636 | llvm_unreachable("ImmediateCode should have returned" ); |
| 637 | return false; |
| 638 | } |
| 639 | case GIPFP_I64_Predicate_simm4s1: { |
| 640 | return Imm >=-8 && Imm <= 7; |
| 641 | llvm_unreachable("ImmediateCode should have returned" ); |
| 642 | return false; |
| 643 | } |
| 644 | case GIPFP_I64_Predicate_simm4s16: { |
| 645 | return Imm >=-128 && Imm <= 112 && (Imm % 16) == 0x0; |
| 646 | llvm_unreachable("ImmediateCode should have returned" ); |
| 647 | return false; |
| 648 | } |
| 649 | case GIPFP_I64_Predicate_simm4s2: { |
| 650 | return Imm >=-16 && Imm <= 14 && (Imm % 2) == 0x0; |
| 651 | llvm_unreachable("ImmediateCode should have returned" ); |
| 652 | return false; |
| 653 | } |
| 654 | case GIPFP_I64_Predicate_simm4s3: { |
| 655 | return Imm >=-24 && Imm <= 21 && (Imm % 3) == 0x0; |
| 656 | llvm_unreachable("ImmediateCode should have returned" ); |
| 657 | return false; |
| 658 | } |
| 659 | case GIPFP_I64_Predicate_simm4s32: { |
| 660 | return Imm >=-256 && Imm <= 224 && (Imm % 32) == 0x0; |
| 661 | llvm_unreachable("ImmediateCode should have returned" ); |
| 662 | return false; |
| 663 | } |
| 664 | case GIPFP_I64_Predicate_simm4s4: { |
| 665 | return Imm >=-32 && Imm <= 28 && (Imm % 4) == 0x0; |
| 666 | llvm_unreachable("ImmediateCode should have returned" ); |
| 667 | return false; |
| 668 | } |
| 669 | case GIPFP_I64_Predicate_simm5_16b: { |
| 670 | return (int16_t)Imm >= -16 && (int16_t)Imm < 16; |
| 671 | llvm_unreachable("ImmediateCode should have returned" ); |
| 672 | return false; |
| 673 | } |
| 674 | case GIPFP_I64_Predicate_simm5_32b: { |
| 675 | return Imm >= -16 && Imm < 16; |
| 676 | llvm_unreachable("ImmediateCode should have returned" ); |
| 677 | return false; |
| 678 | } |
| 679 | case GIPFP_I64_Predicate_simm5_64b: { |
| 680 | return Imm >= -16 && Imm < 16; |
| 681 | llvm_unreachable("ImmediateCode should have returned" ); |
| 682 | return false; |
| 683 | } |
| 684 | case GIPFP_I64_Predicate_simm5_8b: { |
| 685 | return (int8_t)Imm >= -16 && (int8_t)Imm < 16; |
| 686 | llvm_unreachable("ImmediateCode should have returned" ); |
| 687 | return false; |
| 688 | } |
| 689 | case GIPFP_I64_Predicate_simm6_32b: { |
| 690 | return Imm >= -32 && Imm < 32; |
| 691 | llvm_unreachable("ImmediateCode should have returned" ); |
| 692 | return false; |
| 693 | } |
| 694 | case GIPFP_I64_Predicate_simm6s1: { |
| 695 | return Imm >= -32 && Imm < 32; |
| 696 | llvm_unreachable("ImmediateCode should have returned" ); |
| 697 | return false; |
| 698 | } |
| 699 | case GIPFP_I64_Predicate_simm8: { |
| 700 | return Imm >= -128 && Imm < 128; |
| 701 | llvm_unreachable("ImmediateCode should have returned" ); |
| 702 | return false; |
| 703 | } |
| 704 | case GIPFP_I64_Predicate_simm9: { |
| 705 | return Imm >= -256 && Imm < 256; |
| 706 | llvm_unreachable("ImmediateCode should have returned" ); |
| 707 | return false; |
| 708 | } |
| 709 | case GIPFP_I64_Predicate_sve_elm_idx_extdup_b: { |
| 710 | return ((uint64_t)Imm) < 64; |
| 711 | llvm_unreachable("ImmediateCode should have returned" ); |
| 712 | return false; |
| 713 | } |
| 714 | case GIPFP_I64_Predicate_sve_elm_idx_extdup_b_timm: { |
| 715 | return ((uint64_t)Imm) < 64; |
| 716 | llvm_unreachable("ImmediateCode should have returned" ); |
| 717 | return false; |
| 718 | } |
| 719 | case GIPFP_I64_Predicate_sve_elm_idx_extdup_d: { |
| 720 | return ((uint64_t)Imm) < 8; |
| 721 | llvm_unreachable("ImmediateCode should have returned" ); |
| 722 | return false; |
| 723 | } |
| 724 | case GIPFP_I64_Predicate_sve_elm_idx_extdup_d_timm: { |
| 725 | return ((uint64_t)Imm) < 8; |
| 726 | llvm_unreachable("ImmediateCode should have returned" ); |
| 727 | return false; |
| 728 | } |
| 729 | case GIPFP_I64_Predicate_sve_elm_idx_extdup_h: { |
| 730 | return ((uint64_t)Imm) < 32; |
| 731 | llvm_unreachable("ImmediateCode should have returned" ); |
| 732 | return false; |
| 733 | } |
| 734 | case GIPFP_I64_Predicate_sve_elm_idx_extdup_h_timm: { |
| 735 | return ((uint64_t)Imm) < 32; |
| 736 | llvm_unreachable("ImmediateCode should have returned" ); |
| 737 | return false; |
| 738 | } |
| 739 | case GIPFP_I64_Predicate_sve_elm_idx_extdup_q: { |
| 740 | return ((uint64_t)Imm) < 4; |
| 741 | llvm_unreachable("ImmediateCode should have returned" ); |
| 742 | return false; |
| 743 | } |
| 744 | case GIPFP_I64_Predicate_sve_elm_idx_extdup_q_timm: { |
| 745 | return ((uint64_t)Imm) < 4; |
| 746 | llvm_unreachable("ImmediateCode should have returned" ); |
| 747 | return false; |
| 748 | } |
| 749 | case GIPFP_I64_Predicate_sve_elm_idx_extdup_s: { |
| 750 | return ((uint64_t)Imm) < 16; |
| 751 | llvm_unreachable("ImmediateCode should have returned" ); |
| 752 | return false; |
| 753 | } |
| 754 | case GIPFP_I64_Predicate_sve_elm_idx_extdup_s_timm: { |
| 755 | return ((uint64_t)Imm) < 16; |
| 756 | llvm_unreachable("ImmediateCode should have returned" ); |
| 757 | return false; |
| 758 | } |
| 759 | case GIPFP_I64_Predicate_sve_incdec_imm: { |
| 760 | |
| 761 | return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17); |
| 762 | |
| 763 | llvm_unreachable("ImmediateCode should have returned" ); |
| 764 | return false; |
| 765 | } |
| 766 | case GIPFP_I64_Predicate_sve_pred_enum: { |
| 767 | |
| 768 | return (((uint32_t)Imm) < 32); |
| 769 | |
| 770 | llvm_unreachable("ImmediateCode should have returned" ); |
| 771 | return false; |
| 772 | } |
| 773 | case GIPFP_I64_Predicate_sve_prfop: { |
| 774 | |
| 775 | return (((uint32_t)Imm) <= 15); |
| 776 | |
| 777 | llvm_unreachable("ImmediateCode should have returned" ); |
| 778 | return false; |
| 779 | } |
| 780 | case GIPFP_I64_Predicate_tbz_imm0_31_diag: { |
| 781 | |
| 782 | return (((uint32_t)Imm) < 32); |
| 783 | |
| 784 | llvm_unreachable("ImmediateCode should have returned" ); |
| 785 | return false; |
| 786 | } |
| 787 | case GIPFP_I64_Predicate_tbz_imm0_31_nodiag: { |
| 788 | |
| 789 | return (((uint32_t)Imm) < 32); |
| 790 | |
| 791 | llvm_unreachable("ImmediateCode should have returned" ); |
| 792 | return false; |
| 793 | } |
| 794 | case GIPFP_I64_Predicate_tbz_imm32_63: { |
| 795 | |
| 796 | return (((uint32_t)Imm) > 31) && (((uint32_t)Imm) < 64); |
| 797 | |
| 798 | llvm_unreachable("ImmediateCode should have returned" ); |
| 799 | return false; |
| 800 | } |
| 801 | case GIPFP_I64_Predicate_timm0_1: { |
| 802 | |
| 803 | return ((uint64_t)Imm) < 2; |
| 804 | |
| 805 | llvm_unreachable("ImmediateCode should have returned" ); |
| 806 | return false; |
| 807 | } |
| 808 | case GIPFP_I64_Predicate_timm0_31: { |
| 809 | |
| 810 | return ((uint64_t)Imm) < 32; |
| 811 | |
| 812 | llvm_unreachable("ImmediateCode should have returned" ); |
| 813 | return false; |
| 814 | } |
| 815 | case GIPFP_I64_Predicate_tuimm5s2: { |
| 816 | return Imm >= 0 && Imm < (32*2) && ((Imm % 2) == 0); |
| 817 | llvm_unreachable("ImmediateCode should have returned" ); |
| 818 | return false; |
| 819 | } |
| 820 | case GIPFP_I64_Predicate_tuimm5s4: { |
| 821 | return Imm >= 0 && Imm < (32*4) && ((Imm % 4) == 0); |
| 822 | llvm_unreachable("ImmediateCode should have returned" ); |
| 823 | return false; |
| 824 | } |
| 825 | case GIPFP_I64_Predicate_tuimm5s8: { |
| 826 | return Imm >= 0 && Imm < (32*8) && ((Imm % 8) == 0); |
| 827 | llvm_unreachable("ImmediateCode should have returned" ); |
| 828 | return false; |
| 829 | } |
| 830 | case GIPFP_I64_Predicate_tvecshiftL16: { |
| 831 | |
| 832 | return (((uint32_t)Imm) < 16); |
| 833 | |
| 834 | llvm_unreachable("ImmediateCode should have returned" ); |
| 835 | return false; |
| 836 | } |
| 837 | case GIPFP_I64_Predicate_tvecshiftL32: { |
| 838 | |
| 839 | return (((uint32_t)Imm) < 32); |
| 840 | |
| 841 | llvm_unreachable("ImmediateCode should have returned" ); |
| 842 | return false; |
| 843 | } |
| 844 | case GIPFP_I64_Predicate_tvecshiftL64: { |
| 845 | |
| 846 | return (((uint32_t)Imm) < 64); |
| 847 | |
| 848 | llvm_unreachable("ImmediateCode should have returned" ); |
| 849 | return false; |
| 850 | } |
| 851 | case GIPFP_I64_Predicate_tvecshiftL8: { |
| 852 | |
| 853 | return (((uint32_t)Imm) < 8); |
| 854 | |
| 855 | llvm_unreachable("ImmediateCode should have returned" ); |
| 856 | return false; |
| 857 | } |
| 858 | case GIPFP_I64_Predicate_tvecshiftR16: { |
| 859 | |
| 860 | return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17); |
| 861 | |
| 862 | llvm_unreachable("ImmediateCode should have returned" ); |
| 863 | return false; |
| 864 | } |
| 865 | case GIPFP_I64_Predicate_tvecshiftR32: { |
| 866 | |
| 867 | return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33); |
| 868 | |
| 869 | llvm_unreachable("ImmediateCode should have returned" ); |
| 870 | return false; |
| 871 | } |
| 872 | case GIPFP_I64_Predicate_tvecshiftR64: { |
| 873 | |
| 874 | return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65); |
| 875 | |
| 876 | llvm_unreachable("ImmediateCode should have returned" ); |
| 877 | return false; |
| 878 | } |
| 879 | case GIPFP_I64_Predicate_tvecshiftR8: { |
| 880 | |
| 881 | return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9); |
| 882 | |
| 883 | llvm_unreachable("ImmediateCode should have returned" ); |
| 884 | return false; |
| 885 | } |
| 886 | case GIPFP_I64_Predicate_ubsan_trap_imm: { |
| 887 | |
| 888 | return isUInt<8>(Imm); |
| 889 | |
| 890 | llvm_unreachable("ImmediateCode should have returned" ); |
| 891 | return false; |
| 892 | } |
| 893 | case GIPFP_I64_Predicate_uimm16: { |
| 894 | return Imm >= 0 && Imm < 65536; |
| 895 | llvm_unreachable("ImmediateCode should have returned" ); |
| 896 | return false; |
| 897 | } |
| 898 | case GIPFP_I64_Predicate_uimm5s2: { |
| 899 | return Imm >= 0 && Imm < (32*2) && ((Imm % 2) == 0); |
| 900 | llvm_unreachable("ImmediateCode should have returned" ); |
| 901 | return false; |
| 902 | } |
| 903 | case GIPFP_I64_Predicate_uimm5s4: { |
| 904 | return Imm >= 0 && Imm < (32*4) && ((Imm % 4) == 0); |
| 905 | llvm_unreachable("ImmediateCode should have returned" ); |
| 906 | return false; |
| 907 | } |
| 908 | case GIPFP_I64_Predicate_uimm5s8: { |
| 909 | return Imm >= 0 && Imm < (32*8) && ((Imm % 8) == 0); |
| 910 | llvm_unreachable("ImmediateCode should have returned" ); |
| 911 | return false; |
| 912 | } |
| 913 | case GIPFP_I64_Predicate_uimm6: { |
| 914 | return Imm >= 0 && Imm < 64; |
| 915 | llvm_unreachable("ImmediateCode should have returned" ); |
| 916 | return false; |
| 917 | } |
| 918 | case GIPFP_I64_Predicate_uimm6s1: { |
| 919 | return Imm >= 0 && Imm < 64; |
| 920 | llvm_unreachable("ImmediateCode should have returned" ); |
| 921 | return false; |
| 922 | } |
| 923 | case GIPFP_I64_Predicate_uimm6s16: { |
| 924 | return Imm >= 0 && Imm < (64*16) && ((Imm % 16) == 0); |
| 925 | llvm_unreachable("ImmediateCode should have returned" ); |
| 926 | return false; |
| 927 | } |
| 928 | case GIPFP_I64_Predicate_uimm6s2: { |
| 929 | return Imm >= 0 && Imm < (64*2) && ((Imm % 2) == 0); |
| 930 | llvm_unreachable("ImmediateCode should have returned" ); |
| 931 | return false; |
| 932 | } |
| 933 | case GIPFP_I64_Predicate_uimm6s4: { |
| 934 | return Imm >= 0 && Imm < (64*4) && ((Imm % 4) == 0); |
| 935 | llvm_unreachable("ImmediateCode should have returned" ); |
| 936 | return false; |
| 937 | } |
| 938 | case GIPFP_I64_Predicate_uimm6s8: { |
| 939 | return Imm >= 0 && Imm < (64*8) && ((Imm % 8) == 0); |
| 940 | llvm_unreachable("ImmediateCode should have returned" ); |
| 941 | return false; |
| 942 | } |
| 943 | case GIPFP_I64_Predicate_vecshiftL16: { |
| 944 | |
| 945 | return (((uint32_t)Imm) < 16); |
| 946 | |
| 947 | llvm_unreachable("ImmediateCode should have returned" ); |
| 948 | return false; |
| 949 | } |
| 950 | case GIPFP_I64_Predicate_vecshiftL32: { |
| 951 | |
| 952 | return (((uint32_t)Imm) < 32); |
| 953 | |
| 954 | llvm_unreachable("ImmediateCode should have returned" ); |
| 955 | return false; |
| 956 | } |
| 957 | case GIPFP_I64_Predicate_vecshiftL64: { |
| 958 | |
| 959 | return (((uint32_t)Imm) < 64); |
| 960 | |
| 961 | llvm_unreachable("ImmediateCode should have returned" ); |
| 962 | return false; |
| 963 | } |
| 964 | case GIPFP_I64_Predicate_vecshiftL8: { |
| 965 | |
| 966 | return (((uint32_t)Imm) < 8); |
| 967 | |
| 968 | llvm_unreachable("ImmediateCode should have returned" ); |
| 969 | return false; |
| 970 | } |
| 971 | case GIPFP_I64_Predicate_vecshiftR16: { |
| 972 | |
| 973 | return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17); |
| 974 | |
| 975 | llvm_unreachable("ImmediateCode should have returned" ); |
| 976 | return false; |
| 977 | } |
| 978 | case GIPFP_I64_Predicate_vecshiftR16Narrow: { |
| 979 | |
| 980 | return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9); |
| 981 | |
| 982 | llvm_unreachable("ImmediateCode should have returned" ); |
| 983 | return false; |
| 984 | } |
| 985 | case GIPFP_I64_Predicate_vecshiftR32: { |
| 986 | |
| 987 | return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33); |
| 988 | |
| 989 | llvm_unreachable("ImmediateCode should have returned" ); |
| 990 | return false; |
| 991 | } |
| 992 | case GIPFP_I64_Predicate_vecshiftR32Narrow: { |
| 993 | |
| 994 | return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17); |
| 995 | |
| 996 | llvm_unreachable("ImmediateCode should have returned" ); |
| 997 | return false; |
| 998 | } |
| 999 | case GIPFP_I64_Predicate_vecshiftR64: { |
| 1000 | |
| 1001 | return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65); |
| 1002 | |
| 1003 | llvm_unreachable("ImmediateCode should have returned" ); |
| 1004 | return false; |
| 1005 | } |
| 1006 | case GIPFP_I64_Predicate_vecshiftR64Narrow: { |
| 1007 | |
| 1008 | return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33); |
| 1009 | |
| 1010 | llvm_unreachable("ImmediateCode should have returned" ); |
| 1011 | return false; |
| 1012 | } |
| 1013 | case GIPFP_I64_Predicate_vecshiftR8: { |
| 1014 | |
| 1015 | return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9); |
| 1016 | |
| 1017 | llvm_unreachable("ImmediateCode should have returned" ); |
| 1018 | return false; |
| 1019 | } |
| 1020 | } |
| 1021 | llvm_unreachable("Unknown predicate" ); |
| 1022 | return false; |
| 1023 | } |
| 1024 | // PatFrag predicates. |
| 1025 | enum { |
| 1026 | GIPFP_APFloat_Predicate_fpimm0 = GIPFP_APFloat_Invalid + 1, |
| 1027 | GIPFP_APFloat_Predicate_fpimm16, |
| 1028 | GIPFP_APFloat_Predicate_fpimm32, |
| 1029 | GIPFP_APFloat_Predicate_fpimm64, |
| 1030 | GIPFP_APFloat_Predicate_simdimmtype10, |
| 1031 | }; |
| 1032 | bool AArch64InstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const { |
| 1033 | switch (PredicateID) { |
| 1034 | case GIPFP_APFloat_Predicate_fpimm0: { |
| 1035 | |
| 1036 | return Imm.isExactlyValue(+0.0); |
| 1037 | |
| 1038 | llvm_unreachable("ImmediateCode should have returned" ); |
| 1039 | return false; |
| 1040 | } |
| 1041 | case GIPFP_APFloat_Predicate_fpimm16: { |
| 1042 | |
| 1043 | return AArch64_AM::getFP16Imm(Imm) != -1; |
| 1044 | |
| 1045 | llvm_unreachable("ImmediateCode should have returned" ); |
| 1046 | return false; |
| 1047 | } |
| 1048 | case GIPFP_APFloat_Predicate_fpimm32: { |
| 1049 | |
| 1050 | return AArch64_AM::getFP32Imm(Imm) != -1; |
| 1051 | |
| 1052 | llvm_unreachable("ImmediateCode should have returned" ); |
| 1053 | return false; |
| 1054 | } |
| 1055 | case GIPFP_APFloat_Predicate_fpimm64: { |
| 1056 | |
| 1057 | return AArch64_AM::getFP64Imm(Imm) != -1; |
| 1058 | |
| 1059 | llvm_unreachable("ImmediateCode should have returned" ); |
| 1060 | return false; |
| 1061 | } |
| 1062 | case GIPFP_APFloat_Predicate_simdimmtype10: { |
| 1063 | |
| 1064 | return AArch64_AM::isAdvSIMDModImmType10( |
| 1065 | Imm.bitcastToAPInt().getZExtValue()); |
| 1066 | |
| 1067 | llvm_unreachable("ImmediateCode should have returned" ); |
| 1068 | return false; |
| 1069 | } |
| 1070 | } |
| 1071 | llvm_unreachable("Unknown predicate" ); |
| 1072 | return false; |
| 1073 | } |
| 1074 | // PatFrag predicates. |
| 1075 | enum { |
| 1076 | GIPFP_APInt_Predicate_logical_imm32 = GIPFP_APInt_Invalid + 1, |
| 1077 | GIPFP_APInt_Predicate_logical_imm64, |
| 1078 | }; |
| 1079 | bool AArch64InstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const { |
| 1080 | switch (PredicateID) { |
| 1081 | case GIPFP_APInt_Predicate_logical_imm32: { |
| 1082 | |
| 1083 | return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 32); |
| 1084 | |
| 1085 | llvm_unreachable("ImmediateCode should have returned" ); |
| 1086 | return false; |
| 1087 | } |
| 1088 | case GIPFP_APInt_Predicate_logical_imm64: { |
| 1089 | |
| 1090 | return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 64); |
| 1091 | |
| 1092 | llvm_unreachable("ImmediateCode should have returned" ); |
| 1093 | return false; |
| 1094 | } |
| 1095 | } |
| 1096 | llvm_unreachable("Unknown predicate" ); |
| 1097 | return false; |
| 1098 | } |
| 1099 | // PatFrag predicates. |
| 1100 | enum { |
| 1101 | GIPFP_MI_Predicate_ldaxr_1 = GIPFP_MI_Invalid + 1, |
| 1102 | GIPFP_MI_Predicate_ldaxr_2, |
| 1103 | GIPFP_MI_Predicate_ldaxr_4, |
| 1104 | GIPFP_MI_Predicate_ldaxr_8, |
| 1105 | GIPFP_MI_Predicate_ldxr_1, |
| 1106 | GIPFP_MI_Predicate_ldxr_2, |
| 1107 | GIPFP_MI_Predicate_ldxr_4, |
| 1108 | GIPFP_MI_Predicate_ldxr_8, |
| 1109 | GIPFP_MI_Predicate_stlxr_1, |
| 1110 | GIPFP_MI_Predicate_stlxr_2, |
| 1111 | GIPFP_MI_Predicate_stlxr_4, |
| 1112 | GIPFP_MI_Predicate_stlxr_8, |
| 1113 | GIPFP_MI_Predicate_stxr_1, |
| 1114 | GIPFP_MI_Predicate_stxr_2, |
| 1115 | GIPFP_MI_Predicate_stxr_4, |
| 1116 | GIPFP_MI_Predicate_stxr_8, |
| 1117 | }; |
| 1118 | bool AArch64InstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const std::array<const MachineOperand *, 3> &Operands) const { |
| 1119 | const MachineFunction &MF = *MI.getParent()->getParent(); |
| 1120 | const MachineRegisterInfo &MRI = MF.getRegInfo(); |
| 1121 | (void)MRI; |
| 1122 | switch (PredicateID) { |
| 1123 | case GIPFP_MI_Predicate_ldaxr_1: { |
| 1124 | return isLoadStoreOfNumBytes(MI, 1); |
| 1125 | llvm_unreachable("GISelPredicateCode should have returned" ); |
| 1126 | return false; |
| 1127 | } |
| 1128 | case GIPFP_MI_Predicate_ldaxr_2: { |
| 1129 | return isLoadStoreOfNumBytes(MI, 2); |
| 1130 | llvm_unreachable("GISelPredicateCode should have returned" ); |
| 1131 | return false; |
| 1132 | } |
| 1133 | case GIPFP_MI_Predicate_ldaxr_4: { |
| 1134 | return isLoadStoreOfNumBytes(MI, 4); |
| 1135 | llvm_unreachable("GISelPredicateCode should have returned" ); |
| 1136 | return false; |
| 1137 | } |
| 1138 | case GIPFP_MI_Predicate_ldaxr_8: { |
| 1139 | return isLoadStoreOfNumBytes(MI, 8); |
| 1140 | llvm_unreachable("GISelPredicateCode should have returned" ); |
| 1141 | return false; |
| 1142 | } |
| 1143 | case GIPFP_MI_Predicate_ldxr_1: { |
| 1144 | return isLoadStoreOfNumBytes(MI, 1); |
| 1145 | llvm_unreachable("GISelPredicateCode should have returned" ); |
| 1146 | return false; |
| 1147 | } |
| 1148 | case GIPFP_MI_Predicate_ldxr_2: { |
| 1149 | return isLoadStoreOfNumBytes(MI, 2); |
| 1150 | llvm_unreachable("GISelPredicateCode should have returned" ); |
| 1151 | return false; |
| 1152 | } |
| 1153 | case GIPFP_MI_Predicate_ldxr_4: { |
| 1154 | return isLoadStoreOfNumBytes(MI, 4); |
| 1155 | llvm_unreachable("GISelPredicateCode should have returned" ); |
| 1156 | return false; |
| 1157 | } |
| 1158 | case GIPFP_MI_Predicate_ldxr_8: { |
| 1159 | return isLoadStoreOfNumBytes(MI, 8); |
| 1160 | llvm_unreachable("GISelPredicateCode should have returned" ); |
| 1161 | return false; |
| 1162 | } |
| 1163 | case GIPFP_MI_Predicate_stlxr_1: { |
| 1164 | return isLoadStoreOfNumBytes(MI, 1); |
| 1165 | llvm_unreachable("GISelPredicateCode should have returned" ); |
| 1166 | return false; |
| 1167 | } |
| 1168 | case GIPFP_MI_Predicate_stlxr_2: { |
| 1169 | return isLoadStoreOfNumBytes(MI, 2); |
| 1170 | llvm_unreachable("GISelPredicateCode should have returned" ); |
| 1171 | return false; |
| 1172 | } |
| 1173 | case GIPFP_MI_Predicate_stlxr_4: { |
| 1174 | return isLoadStoreOfNumBytes(MI, 4); |
| 1175 | llvm_unreachable("GISelPredicateCode should have returned" ); |
| 1176 | return false; |
| 1177 | } |
| 1178 | case GIPFP_MI_Predicate_stlxr_8: { |
| 1179 | return isLoadStoreOfNumBytes(MI, 8); |
| 1180 | llvm_unreachable("GISelPredicateCode should have returned" ); |
| 1181 | return false; |
| 1182 | } |
| 1183 | case GIPFP_MI_Predicate_stxr_1: { |
| 1184 | return isLoadStoreOfNumBytes(MI, 1); |
| 1185 | llvm_unreachable("GISelPredicateCode should have returned" ); |
| 1186 | return false; |
| 1187 | } |
| 1188 | case GIPFP_MI_Predicate_stxr_2: { |
| 1189 | return isLoadStoreOfNumBytes(MI, 2); |
| 1190 | llvm_unreachable("GISelPredicateCode should have returned" ); |
| 1191 | return false; |
| 1192 | } |
| 1193 | case GIPFP_MI_Predicate_stxr_4: { |
| 1194 | return isLoadStoreOfNumBytes(MI, 4); |
| 1195 | llvm_unreachable("GISelPredicateCode should have returned" ); |
| 1196 | return false; |
| 1197 | } |
| 1198 | case GIPFP_MI_Predicate_stxr_8: { |
| 1199 | return isLoadStoreOfNumBytes(MI, 8); |
| 1200 | llvm_unreachable("GISelPredicateCode should have returned" ); |
| 1201 | return false; |
| 1202 | } |
| 1203 | } |
| 1204 | llvm_unreachable("Unknown predicate" ); |
| 1205 | return false; |
| 1206 | } |
| 1207 | |
| 1208 | AArch64InstructionSelector::ComplexMatcherMemFn |
| 1209 | AArch64InstructionSelector::ComplexPredicateFns[] = { |
| 1210 | nullptr, // GICP_Invalid |
| 1211 | &AArch64InstructionSelector::selectArithImmed, // gi_addsub_shifted_imm32 |
| 1212 | &AArch64InstructionSelector::selectArithImmed, // gi_addsub_shifted_imm64 |
| 1213 | &AArch64InstructionSelector::selectAddrModeIndexed<128>, // gi_am_indexed128 |
| 1214 | &AArch64InstructionSelector::selectAddrModeIndexed<16>, // gi_am_indexed16 |
| 1215 | &AArch64InstructionSelector::selectAddrModeIndexed<32>, // gi_am_indexed32 |
| 1216 | &AArch64InstructionSelector::selectAddrModeIndexed<64>, // gi_am_indexed64 |
| 1217 | &AArch64InstructionSelector::selectAddrModeIndexed<8>, // gi_am_indexed8 |
| 1218 | &AArch64InstructionSelector::selectAddrModeUnscaled128, // gi_am_unscaled128 |
| 1219 | &AArch64InstructionSelector::selectAddrModeUnscaled16, // gi_am_unscaled16 |
| 1220 | &AArch64InstructionSelector::selectAddrModeUnscaled32, // gi_am_unscaled32 |
| 1221 | &AArch64InstructionSelector::selectAddrModeUnscaled64, // gi_am_unscaled64 |
| 1222 | &AArch64InstructionSelector::selectAddrModeUnscaled8, // gi_am_unscaled8 |
| 1223 | &AArch64InstructionSelector::selectArithExtendedRegister, // gi_arith_extended_reg32_i32 |
| 1224 | &AArch64InstructionSelector::selectArithExtendedRegister, // gi_arith_extended_reg32_i64 |
| 1225 | &AArch64InstructionSelector::selectArithExtendedRegister, // gi_arith_extended_reg32to64_i64 |
| 1226 | &AArch64InstructionSelector::selectArithShiftedRegister, // gi_arith_shifted_reg32 |
| 1227 | &AArch64InstructionSelector::selectArithShiftedRegister, // gi_arith_shifted_reg64 |
| 1228 | &AArch64InstructionSelector::selectLogicalShiftedRegister, // gi_logical_shifted_reg32 |
| 1229 | &AArch64InstructionSelector::selectLogicalShiftedRegister, // gi_logical_shifted_reg64 |
| 1230 | &AArch64InstructionSelector::selectNegArithImmed, // gi_neg_addsub_shifted_imm32 |
| 1231 | &AArch64InstructionSelector::selectNegArithImmed, // gi_neg_addsub_shifted_imm64 |
| 1232 | &AArch64InstructionSelector::selectAddrModeWRO<128>, // gi_ro_Windexed128 |
| 1233 | &AArch64InstructionSelector::selectAddrModeWRO<16>, // gi_ro_Windexed16 |
| 1234 | &AArch64InstructionSelector::selectAddrModeWRO<32>, // gi_ro_Windexed32 |
| 1235 | &AArch64InstructionSelector::selectAddrModeWRO<64>, // gi_ro_Windexed64 |
| 1236 | &AArch64InstructionSelector::selectAddrModeWRO<8>, // gi_ro_Windexed8 |
| 1237 | &AArch64InstructionSelector::selectAddrModeXRO<128>, // gi_ro_Xindexed128 |
| 1238 | &AArch64InstructionSelector::selectAddrModeXRO<16>, // gi_ro_Xindexed16 |
| 1239 | &AArch64InstructionSelector::selectAddrModeXRO<32>, // gi_ro_Xindexed32 |
| 1240 | &AArch64InstructionSelector::selectAddrModeXRO<64>, // gi_ro_Xindexed64 |
| 1241 | &AArch64InstructionSelector::selectAddrModeXRO<8>, // gi_ro_Xindexed8 |
| 1242 | }; |
| 1243 | |
| 1244 | // Custom renderers. |
| 1245 | enum { |
| 1246 | GICR_Invalid, |
| 1247 | GICR_renderLogicalImm32, |
| 1248 | GICR_renderLogicalImm64, |
| 1249 | GICR_renderTruncImm, |
| 1250 | }; |
| 1251 | AArch64InstructionSelector::CustomRendererFn |
| 1252 | AArch64InstructionSelector::CustomRenderers[] = { |
| 1253 | nullptr, // GICR_Invalid |
| 1254 | &AArch64InstructionSelector::renderLogicalImm32, // gi_logical_imm32_XFORM |
| 1255 | &AArch64InstructionSelector::renderLogicalImm64, // gi_logical_imm64_XFORM |
| 1256 | &AArch64InstructionSelector::renderTruncImm, // gi_trunc_imm |
| 1257 | }; |
| 1258 | |
| 1259 | bool AArch64InstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const { |
| 1260 | MachineFunction &MF = *I.getParent()->getParent(); |
| 1261 | MachineRegisterInfo &MRI = MF.getRegInfo(); |
| 1262 | const PredicateBitset AvailableFeatures = getAvailableFeatures(); |
| 1263 | NewMIVector OutMIs; |
| 1264 | State.MIs.clear(); |
| 1265 | State.MIs.push_back(&I); |
| 1266 | |
| 1267 | if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) { |
| 1268 | return true; |
| 1269 | } |
| 1270 | |
| 1271 | return false; |
| 1272 | } |
| 1273 | |
| 1274 | const int64_t *AArch64InstructionSelector::getMatchTable() const { |
| 1275 | constexpr static int64_t MatchTable0[] = { |
| 1276 | GIM_SwitchOpcode, /*MI*/0, /*[*/39, 491, /*)*//*default:*//*Label 98*/ 167847, |
| 1277 | /*TargetOpcode::G_ADD*//*Label 0*/ 457, |
| 1278 | /*TargetOpcode::G_SUB*//*Label 1*/ 11346, |
| 1279 | /*TargetOpcode::G_MUL*//*Label 2*/ 15192, |
| 1280 | /*TargetOpcode::G_SDIV*//*Label 3*/ 16507, |
| 1281 | /*TargetOpcode::G_UDIV*//*Label 4*/ 16576, 0, 0, |
| 1282 | /*TargetOpcode::G_AND*//*Label 5*/ 16645, |
| 1283 | /*TargetOpcode::G_OR*//*Label 6*/ 20264, |
| 1284 | /*TargetOpcode::G_XOR*//*Label 7*/ 36619, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 1285 | /*TargetOpcode::G_CONCAT_VECTORS*//*Label 8*/ 39308, 0, 0, |
| 1286 | /*TargetOpcode::G_BITCAST*//*Label 9*/ 47026, 0, |
| 1287 | /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 10*/ 56257, |
| 1288 | /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 11*/ 56466, |
| 1289 | /*TargetOpcode::G_INTRINSIC_LRINT*//*Label 12*/ 56675, 0, |
| 1290 | /*TargetOpcode::G_READCYCLECOUNTER*//*Label 13*/ 56942, |
| 1291 | /*TargetOpcode::G_LOAD*//*Label 14*/ 56970, |
| 1292 | /*TargetOpcode::G_SEXTLOAD*//*Label 15*/ 63712, |
| 1293 | /*TargetOpcode::G_ZEXTLOAD*//*Label 16*/ 64683, 0, 0, 0, |
| 1294 | /*TargetOpcode::G_STORE*//*Label 17*/ 66726, 0, 0, |
| 1295 | /*TargetOpcode::G_ATOMIC_CMPXCHG*//*Label 18*/ 72745, |
| 1296 | /*TargetOpcode::G_ATOMICRMW_XCHG*//*Label 19*/ 73942, |
| 1297 | /*TargetOpcode::G_ATOMICRMW_ADD*//*Label 20*/ 74971, |
| 1298 | /*TargetOpcode::G_ATOMICRMW_SUB*//*Label 21*/ 76000, |
| 1299 | /*TargetOpcode::G_ATOMICRMW_AND*//*Label 22*/ 77429, 0, |
| 1300 | /*TargetOpcode::G_ATOMICRMW_OR*//*Label 23*/ 78858, |
| 1301 | /*TargetOpcode::G_ATOMICRMW_XOR*//*Label 24*/ 79887, |
| 1302 | /*TargetOpcode::G_ATOMICRMW_MAX*//*Label 25*/ 80916, |
| 1303 | /*TargetOpcode::G_ATOMICRMW_MIN*//*Label 26*/ 81945, |
| 1304 | /*TargetOpcode::G_ATOMICRMW_UMAX*//*Label 27*/ 82974, |
| 1305 | /*TargetOpcode::G_ATOMICRMW_UMIN*//*Label 28*/ 84003, 0, 0, |
| 1306 | /*TargetOpcode::G_FENCE*//*Label 29*/ 85032, 0, 0, |
| 1307 | /*TargetOpcode::G_INTRINSIC*//*Label 30*/ 85084, |
| 1308 | /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 31*/ 128509, |
| 1309 | /*TargetOpcode::G_ANYEXT*//*Label 32*/ 131374, |
| 1310 | /*TargetOpcode::G_TRUNC*//*Label 33*/ 131551, |
| 1311 | /*TargetOpcode::G_CONSTANT*//*Label 34*/ 132375, |
| 1312 | /*TargetOpcode::G_FCONSTANT*//*Label 35*/ 132483, 0, 0, |
| 1313 | /*TargetOpcode::G_SEXT*//*Label 36*/ 132561, 0, |
| 1314 | /*TargetOpcode::G_ZEXT*//*Label 37*/ 132817, |
| 1315 | /*TargetOpcode::G_SHL*//*Label 38*/ 133276, |
| 1316 | /*TargetOpcode::G_LSHR*//*Label 39*/ 133589, |
| 1317 | /*TargetOpcode::G_ASHR*//*Label 40*/ 133974, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 1318 | /*TargetOpcode::G_UMULH*//*Label 41*/ 134469, |
| 1319 | /*TargetOpcode::G_SMULH*//*Label 42*/ 134902, |
| 1320 | /*TargetOpcode::G_UADDSAT*//*Label 43*/ 135335, |
| 1321 | /*TargetOpcode::G_SADDSAT*//*Label 44*/ 135573, |
| 1322 | /*TargetOpcode::G_USUBSAT*//*Label 45*/ 135811, |
| 1323 | /*TargetOpcode::G_SSUBSAT*//*Label 46*/ 136049, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 1324 | /*TargetOpcode::G_FADD*//*Label 47*/ 136287, |
| 1325 | /*TargetOpcode::G_FSUB*//*Label 48*/ 137181, |
| 1326 | /*TargetOpcode::G_FMUL*//*Label 49*/ 137454, |
| 1327 | /*TargetOpcode::G_FMA*//*Label 50*/ 139321, 0, |
| 1328 | /*TargetOpcode::G_FDIV*//*Label 51*/ 149524, 0, 0, 0, 0, 0, 0, 0, 0, |
| 1329 | /*TargetOpcode::G_FNEG*//*Label 52*/ 149797, |
| 1330 | /*TargetOpcode::G_FPEXT*//*Label 53*/ 150345, |
| 1331 | /*TargetOpcode::G_FPTRUNC*//*Label 54*/ 150474, |
| 1332 | /*TargetOpcode::G_FPTOSI*//*Label 55*/ 150603, |
| 1333 | /*TargetOpcode::G_FPTOUI*//*Label 56*/ 151503, |
| 1334 | /*TargetOpcode::G_SITOFP*//*Label 57*/ 152403, |
| 1335 | /*TargetOpcode::G_UITOFP*//*Label 58*/ 154853, |
| 1336 | /*TargetOpcode::G_FABS*//*Label 59*/ 156607, 0, 0, |
| 1337 | /*TargetOpcode::G_FMINNUM*//*Label 60*/ 157164, |
| 1338 | /*TargetOpcode::G_FMAXNUM*//*Label 61*/ 157449, 0, 0, 0, 0, 0, 0, |
| 1339 | /*TargetOpcode::G_SMIN*//*Label 62*/ 157734, |
| 1340 | /*TargetOpcode::G_SMAX*//*Label 63*/ 157940, |
| 1341 | /*TargetOpcode::G_UMIN*//*Label 64*/ 158146, |
| 1342 | /*TargetOpcode::G_UMAX*//*Label 65*/ 158352, |
| 1343 | /*TargetOpcode::G_ABS*//*Label 66*/ 158558, |
| 1344 | /*TargetOpcode::G_BR*//*Label 67*/ 159008, 0, 0, |
| 1345 | /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 68*/ 159021, 0, |
| 1346 | /*TargetOpcode::G_CTTZ*//*Label 69*/ 159543, 0, |
| 1347 | /*TargetOpcode::G_CTLZ*//*Label 70*/ 159646, 0, |
| 1348 | /*TargetOpcode::G_CTPOP*//*Label 71*/ 160269, |
| 1349 | /*TargetOpcode::G_BSWAP*//*Label 72*/ 160327, |
| 1350 | /*TargetOpcode::G_BITREVERSE*//*Label 73*/ 160380, |
| 1351 | /*TargetOpcode::G_FCEIL*//*Label 74*/ 160433, 0, 0, |
| 1352 | /*TargetOpcode::G_FSQRT*//*Label 75*/ 160642, |
| 1353 | /*TargetOpcode::G_FFLOOR*//*Label 76*/ 160851, |
| 1354 | /*TargetOpcode::G_FRINT*//*Label 77*/ 161060, |
| 1355 | /*TargetOpcode::G_FNEARBYINT*//*Label 78*/ 161269, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 1356 | /*AArch64::G_DUP*//*Label 79*/ 161478, |
| 1357 | /*AArch64::G_DUPLANE16*//*Label 80*/ 163057, |
| 1358 | /*AArch64::G_DUPLANE32*//*Label 81*/ 163310, |
| 1359 | /*AArch64::G_DUPLANE64*//*Label 82*/ 163497, |
| 1360 | /*AArch64::G_DUPLANE8*//*Label 83*/ 163589, |
| 1361 | /*AArch64::G_EXT*//*Label 84*/ 163703, |
| 1362 | /*AArch64::G_REV16*//*Label 85*/ 164527, |
| 1363 | /*AArch64::G_REV32*//*Label 86*/ 164585, |
| 1364 | /*AArch64::G_REV64*//*Label 87*/ 164735, |
| 1365 | /*AArch64::G_SITOF*//*Label 88*/ 164959, |
| 1366 | /*AArch64::G_TRN1*//*Label 89*/ 165041, |
| 1367 | /*AArch64::G_TRN2*//*Label 90*/ 165349, |
| 1368 | /*AArch64::G_UITOF*//*Label 91*/ 165657, |
| 1369 | /*AArch64::G_UZP1*//*Label 92*/ 165739, |
| 1370 | /*AArch64::G_UZP2*//*Label 93*/ 166047, |
| 1371 | /*AArch64::G_VASHR*//*Label 94*/ 166355, |
| 1372 | /*AArch64::G_VLSHR*//*Label 95*/ 166793, |
| 1373 | /*AArch64::G_ZIP1*//*Label 96*/ 167231, |
| 1374 | /*AArch64::G_ZIP2*//*Label 97*/ 167539, |
| 1375 | // Label 0: @457 |
| 1376 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 108*/ 11345, |
| 1377 | /*GILLT_s32*//*Label 99*/ 473, |
| 1378 | /*GILLT_s64*//*Label 100*/ 778, 0, |
| 1379 | /*GILLT_v2s32*//*Label 101*/ 2704, |
| 1380 | /*GILLT_v2s64*//*Label 102*/ 3443, |
| 1381 | /*GILLT_v4s16*//*Label 103*/ 5434, |
| 1382 | /*GILLT_v4s32*//*Label 104*/ 6173, |
| 1383 | /*GILLT_v8s8*//*Label 105*/ 8420, |
| 1384 | /*GILLT_v8s16*//*Label 106*/ 8951, |
| 1385 | /*GILLT_v16s8*//*Label 107*/ 10814, |
| 1386 | // Label 99: @473 |
| 1387 | GIM_Try, /*On fail goto*//*Label 109*/ 777, |
| 1388 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 1389 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 1390 | GIM_Try, /*On fail goto*//*Label 110*/ 517, // Rule ID 7532 // |
| 1391 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, |
| 1392 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32spRegClassID, |
| 1393 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm32, |
| 1394 | // (add:{ *:[i32] } addsub_shifted_imm32:{ *:[i32] }:$imm, GPR32sp:{ *:[i32] }:$Rn) => (ADDWri:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm) |
| 1395 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri, |
| 1396 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 1397 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 1398 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm |
| 1399 | GIR_EraseFromParent, /*InsnID*/0, |
| 1400 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1401 | // GIR_Coverage, 7532, |
| 1402 | GIR_Done, |
| 1403 | // Label 110: @517 |
| 1404 | GIM_Try, /*On fail goto*//*Label 111*/ 551, // Rule ID 82 // |
| 1405 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, |
| 1406 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID, |
| 1407 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm32, |
| 1408 | // (add:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm) => (ADDWri:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm) |
| 1409 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri, |
| 1410 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 1411 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 1412 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm |
| 1413 | GIR_EraseFromParent, /*InsnID*/0, |
| 1414 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1415 | // GIR_Coverage, 82, |
| 1416 | GIR_Done, |
| 1417 | // Label 111: @551 |
| 1418 | GIM_Try, /*On fail goto*//*Label 112*/ 585, // Rule ID 7536 // |
| 1419 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, |
| 1420 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32spRegClassID, |
| 1421 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_arith_extended_reg32_i32, |
| 1422 | // (add:{ *:[i32] } arith_extended_reg32_i32:{ *:[i32] }:$R3, GPR32sp:{ *:[i32] }:$R2) => (ADDWrx:{ *:[i32] } GPR32sp:{ *:[i32] }:$R2, arith_extended_reg32_i32:{ *:[i32] }:$R3) |
| 1423 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWrx, |
| 1424 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // R1 |
| 1425 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // R2 |
| 1426 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // R3 |
| 1427 | GIR_EraseFromParent, /*InsnID*/0, |
| 1428 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1429 | // GIR_Coverage, 7536, |
| 1430 | GIR_Done, |
| 1431 | // Label 112: @585 |
| 1432 | GIM_Try, /*On fail goto*//*Label 113*/ 619, // Rule ID 7918 // |
| 1433 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 1434 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 1435 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_neg_addsub_shifted_imm32, |
| 1436 | // (add:{ *:[i32] } neg_addsub_shifted_imm32:{ *:[i32] }:$imm, GPR32:{ *:[i32] }:$Rn) => (SUBSWri:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm) |
| 1437 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWri, |
| 1438 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 1439 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 1440 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm |
| 1441 | GIR_EraseFromParent, /*InsnID*/0, |
| 1442 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1443 | // GIR_Coverage, 7918, |
| 1444 | GIR_Done, |
| 1445 | // Label 113: @619 |
| 1446 | GIM_Try, /*On fail goto*//*Label 114*/ 653, // Rule ID 88 // |
| 1447 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, |
| 1448 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID, |
| 1449 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_arith_extended_reg32_i32, |
| 1450 | // (add:{ *:[i32] } GPR32sp:{ *:[i32] }:$R2, arith_extended_reg32_i32:{ *:[i32] }:$R3) => (ADDWrx:{ *:[i32] } GPR32sp:{ *:[i32] }:$R2, arith_extended_reg32_i32:{ *:[i32] }:$R3) |
| 1451 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWrx, |
| 1452 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // R1 |
| 1453 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // R2 |
| 1454 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // R3 |
| 1455 | GIR_EraseFromParent, /*InsnID*/0, |
| 1456 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1457 | // GIR_Coverage, 88, |
| 1458 | GIR_Done, |
| 1459 | // Label 114: @653 |
| 1460 | GIM_Try, /*On fail goto*//*Label 115*/ 687, // Rule ID 3467 // |
| 1461 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 1462 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 1463 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_neg_addsub_shifted_imm32, |
| 1464 | // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm) => (SUBSWri:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm) |
| 1465 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWri, |
| 1466 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 1467 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 1468 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm |
| 1469 | GIR_EraseFromParent, /*InsnID*/0, |
| 1470 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1471 | // GIR_Coverage, 3467, |
| 1472 | GIR_Done, |
| 1473 | // Label 115: @687 |
| 1474 | GIM_Try, /*On fail goto*//*Label 116*/ 721, // Rule ID 7534 // |
| 1475 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 1476 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 1477 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_arith_shifted_reg32, |
| 1478 | // (add:{ *:[i32] } arith_shifted_reg32:{ *:[i32] }:$Rm, GPR32:{ *:[i32] }:$Rn) => (ADDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm) |
| 1479 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWrs, |
| 1480 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 1481 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 1482 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 1483 | GIR_EraseFromParent, /*InsnID*/0, |
| 1484 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1485 | // GIR_Coverage, 7534, |
| 1486 | GIR_Done, |
| 1487 | // Label 116: @721 |
| 1488 | GIM_Try, /*On fail goto*//*Label 117*/ 755, // Rule ID 86 // |
| 1489 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 1490 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 1491 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_arith_shifted_reg32, |
| 1492 | // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm) => (ADDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm) |
| 1493 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWrs, |
| 1494 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 1495 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 1496 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 1497 | GIR_EraseFromParent, /*InsnID*/0, |
| 1498 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1499 | // GIR_Coverage, 86, |
| 1500 | GIR_Done, |
| 1501 | // Label 117: @755 |
| 1502 | GIM_Try, /*On fail goto*//*Label 118*/ 776, // Rule ID 84 // |
| 1503 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 1504 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 1505 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 1506 | // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (ADDWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 1507 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDWrr, |
| 1508 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1509 | // GIR_Coverage, 84, |
| 1510 | GIR_Done, |
| 1511 | // Label 118: @776 |
| 1512 | GIM_Reject, |
| 1513 | // Label 109: @777 |
| 1514 | GIM_Reject, |
| 1515 | // Label 100: @778 |
| 1516 | GIM_Try, /*On fail goto*//*Label 119*/ 2703, |
| 1517 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 1518 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 1519 | GIM_Try, /*On fail goto*//*Label 120*/ 857, // Rule ID 5331 // |
| 1520 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 1521 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1522 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 1523 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 1524 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 1525 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 1526 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 0, |
| 1527 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 1528 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 1529 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 1530 | // MIs[2] Rn |
| 1531 | GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 1532 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, |
| 1533 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 1534 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 1535 | // (add:{ *:[i64] } (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 1:{ *:[i64] })) => (ADDPv2i64p:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn) |
| 1536 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv2i64p, |
| 1537 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 1538 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 1539 | GIR_EraseFromParent, /*InsnID*/0, |
| 1540 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1541 | // GIR_Coverage, 5331, |
| 1542 | GIR_Done, |
| 1543 | // Label 120: @857 |
| 1544 | GIM_Try, /*On fail goto*//*Label 121*/ 926, // Rule ID 8016 // |
| 1545 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 1546 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1547 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 1548 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 1549 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 1550 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 1551 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, |
| 1552 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 1553 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 1554 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 1555 | // MIs[2] Rn |
| 1556 | GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 1557 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 0, |
| 1558 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 1559 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 1560 | // (add:{ *:[i64] } (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] })) => (ADDPv2i64p:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn) |
| 1561 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv2i64p, |
| 1562 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 1563 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 1564 | GIR_EraseFromParent, /*InsnID*/0, |
| 1565 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1566 | // GIR_Coverage, 8016, |
| 1567 | GIR_Done, |
| 1568 | // Label 121: @926 |
| 1569 | GIM_Try, /*On fail goto*//*Label 122*/ 960, // Rule ID 7533 // |
| 1570 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, |
| 1571 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, |
| 1572 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm64, |
| 1573 | // (add:{ *:[i64] } addsub_shifted_imm64:{ *:[i64] }:$imm, GPR64sp:{ *:[i64] }:$Rn) => (ADDXri:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm) |
| 1574 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri, |
| 1575 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 1576 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 1577 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm |
| 1578 | GIR_EraseFromParent, /*InsnID*/0, |
| 1579 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1580 | // GIR_Coverage, 7533, |
| 1581 | GIR_Done, |
| 1582 | // Label 122: @960 |
| 1583 | GIM_Try, /*On fail goto*//*Label 123*/ 1056, // Rule ID 3517 // |
| 1584 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 1585 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1586 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 1587 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 1588 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 1589 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1590 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, |
| 1591 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1592 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 1593 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1594 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 1595 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit, |
| 1596 | // MIs[3] Operand 1 |
| 1597 | // No operand predicates |
| 1598 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 1599 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 1600 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 1601 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 1602 | // (add:{ *:[i64] } (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C), GPR64:{ *:[i64] }:$Ra) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra) |
| 1603 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 1604 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, |
| 1605 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 1606 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C |
| 1607 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 1608 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr, |
| 1609 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 1610 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1611 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 1612 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra |
| 1613 | GIR_EraseFromParent, /*InsnID*/0, |
| 1614 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1615 | // GIR_Coverage, 3517, |
| 1616 | GIR_Done, |
| 1617 | // Label 123: @1056 |
| 1618 | GIM_Try, /*On fail goto*//*Label 124*/ 1152, // Rule ID 3518 // |
| 1619 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 1620 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1621 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 1622 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 1623 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 1624 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1625 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, |
| 1626 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1627 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 1628 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1629 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 1630 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit, |
| 1631 | // MIs[3] Operand 1 |
| 1632 | // No operand predicates |
| 1633 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 1634 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 1635 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 1636 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 1637 | // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C), GPR64:{ *:[i64] }:$Ra) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra) |
| 1638 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 1639 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, |
| 1640 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 1641 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C |
| 1642 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 1643 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr, |
| 1644 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 1645 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1646 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 1647 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra |
| 1648 | GIR_EraseFromParent, /*InsnID*/0, |
| 1649 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1650 | // GIR_Coverage, 3518, |
| 1651 | GIR_Done, |
| 1652 | // Label 124: @1152 |
| 1653 | GIM_Try, /*On fail goto*//*Label 125*/ 1186, // Rule ID 83 // |
| 1654 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, |
| 1655 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 1656 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm64, |
| 1657 | // (add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm) => (ADDXri:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm) |
| 1658 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri, |
| 1659 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 1660 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 1661 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm |
| 1662 | GIR_EraseFromParent, /*InsnID*/0, |
| 1663 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1664 | // GIR_Coverage, 83, |
| 1665 | GIR_Done, |
| 1666 | // Label 125: @1186 |
| 1667 | GIM_Try, /*On fail goto*//*Label 126*/ 1282, // Rule ID 7926 // |
| 1668 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 1669 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 1670 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1671 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 1672 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 1673 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 1674 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1675 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, |
| 1676 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1677 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 1678 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1679 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 1680 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit, |
| 1681 | // MIs[3] Operand 1 |
| 1682 | // No operand predicates |
| 1683 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 1684 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 1685 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 1686 | // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C)) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra) |
| 1687 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 1688 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, |
| 1689 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 1690 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C |
| 1691 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 1692 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr, |
| 1693 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 1694 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1695 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 1696 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra |
| 1697 | GIR_EraseFromParent, /*InsnID*/0, |
| 1698 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1699 | // GIR_Coverage, 7926, |
| 1700 | GIR_Done, |
| 1701 | // Label 126: @1282 |
| 1702 | GIM_Try, /*On fail goto*//*Label 127*/ 1378, // Rule ID 7927 // |
| 1703 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 1704 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 1705 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1706 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 1707 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 1708 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 1709 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1710 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, |
| 1711 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1712 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 1713 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1714 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 1715 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit, |
| 1716 | // MIs[3] Operand 1 |
| 1717 | // No operand predicates |
| 1718 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 1719 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 1720 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 1721 | // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C)) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra) |
| 1722 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 1723 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, |
| 1724 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 1725 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C |
| 1726 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 1727 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr, |
| 1728 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 1729 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1730 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 1731 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra |
| 1732 | GIR_EraseFromParent, /*InsnID*/0, |
| 1733 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1734 | // GIR_Coverage, 7927, |
| 1735 | GIR_Done, |
| 1736 | // Label 127: @1378 |
| 1737 | GIM_Try, /*On fail goto*//*Label 128*/ 1463, // Rule ID 7544 // |
| 1738 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 1739 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1740 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 1741 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 1742 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 1743 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1744 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, |
| 1745 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1746 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 1747 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1748 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT, |
| 1749 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1750 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 1751 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 1752 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 1753 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 1754 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 1755 | // (add:{ *:[i64] } (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra) |
| 1756 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr, |
| 1757 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 1758 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1759 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1760 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra |
| 1761 | GIR_EraseFromParent, /*InsnID*/0, |
| 1762 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1763 | // GIR_Coverage, 7544, |
| 1764 | GIR_Done, |
| 1765 | // Label 128: @1463 |
| 1766 | GIM_Try, /*On fail goto*//*Label 129*/ 1548, // Rule ID 7545 // |
| 1767 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 1768 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1769 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 1770 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 1771 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 1772 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1773 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, |
| 1774 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1775 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 1776 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1777 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT, |
| 1778 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1779 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 1780 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 1781 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 1782 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 1783 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 1784 | // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra) |
| 1785 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr, |
| 1786 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 1787 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1788 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1789 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra |
| 1790 | GIR_EraseFromParent, /*InsnID*/0, |
| 1791 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1792 | // GIR_Coverage, 7545, |
| 1793 | GIR_Done, |
| 1794 | // Label 129: @1548 |
| 1795 | GIM_Try, /*On fail goto*//*Label 130*/ 1633, // Rule ID 114 // |
| 1796 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 1797 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 1798 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1799 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 1800 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 1801 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 1802 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1803 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, |
| 1804 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1805 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 1806 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1807 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT, |
| 1808 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1809 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 1810 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 1811 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 1812 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 1813 | // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra) |
| 1814 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr, |
| 1815 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 1816 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1817 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1818 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra |
| 1819 | GIR_EraseFromParent, /*InsnID*/0, |
| 1820 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1821 | // GIR_Coverage, 114, |
| 1822 | GIR_Done, |
| 1823 | // Label 130: @1633 |
| 1824 | GIM_Try, /*On fail goto*//*Label 131*/ 1718, // Rule ID 116 // |
| 1825 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 1826 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 1827 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1828 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 1829 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 1830 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 1831 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1832 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, |
| 1833 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1834 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 1835 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1836 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT, |
| 1837 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1838 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 1839 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 1840 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 1841 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 1842 | // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra) |
| 1843 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr, |
| 1844 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 1845 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1846 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1847 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra |
| 1848 | GIR_EraseFromParent, /*InsnID*/0, |
| 1849 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1850 | // GIR_Coverage, 116, |
| 1851 | GIR_Done, |
| 1852 | // Label 131: @1718 |
| 1853 | GIM_Try, /*On fail goto*//*Label 132*/ 1752, // Rule ID 7537 // |
| 1854 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, |
| 1855 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, |
| 1856 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_arith_extended_reg32to64_i64, |
| 1857 | // (add:{ *:[i64] } arith_extended_reg32to64_i64:{ *:[i64] }:$R3, GPR64sp:{ *:[i64] }:$R2) => (ADDXrx:{ *:[i64] } GPR64sp:{ *:[i64] }:$R2, arith_extended_reg32to64_i64:{ *:[i64] }:$R3) |
| 1858 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXrx, |
| 1859 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // R1 |
| 1860 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // R2 |
| 1861 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // R3 |
| 1862 | GIR_EraseFromParent, /*InsnID*/0, |
| 1863 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1864 | // GIR_Coverage, 7537, |
| 1865 | GIR_Done, |
| 1866 | // Label 132: @1752 |
| 1867 | GIM_Try, /*On fail goto*//*Label 133*/ 1786, // Rule ID 7919 // |
| 1868 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 1869 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 1870 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_neg_addsub_shifted_imm64, |
| 1871 | // (add:{ *:[i64] } neg_addsub_shifted_imm64:{ *:[i64] }:$imm, GPR64:{ *:[i64] }:$Rn) => (SUBSXri:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm) |
| 1872 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXri, |
| 1873 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 1874 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 1875 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm |
| 1876 | GIR_EraseFromParent, /*InsnID*/0, |
| 1877 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1878 | // GIR_Coverage, 7919, |
| 1879 | GIR_Done, |
| 1880 | // Label 133: @1786 |
| 1881 | GIM_Try, /*On fail goto*//*Label 134*/ 1820, // Rule ID 89 // |
| 1882 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, |
| 1883 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 1884 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_arith_extended_reg32to64_i64, |
| 1885 | // (add:{ *:[i64] } GPR64sp:{ *:[i64] }:$R2, arith_extended_reg32to64_i64:{ *:[i64] }:$R3) => (ADDXrx:{ *:[i64] } GPR64sp:{ *:[i64] }:$R2, arith_extended_reg32to64_i64:{ *:[i64] }:$R3) |
| 1886 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXrx, |
| 1887 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // R1 |
| 1888 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // R2 |
| 1889 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // R3 |
| 1890 | GIR_EraseFromParent, /*InsnID*/0, |
| 1891 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1892 | // GIR_Coverage, 89, |
| 1893 | GIR_Done, |
| 1894 | // Label 134: @1820 |
| 1895 | GIM_Try, /*On fail goto*//*Label 135*/ 1854, // Rule ID 3468 // |
| 1896 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 1897 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 1898 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_neg_addsub_shifted_imm64, |
| 1899 | // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm) => (SUBSXri:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm) |
| 1900 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXri, |
| 1901 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 1902 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 1903 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm |
| 1904 | GIR_EraseFromParent, /*InsnID*/0, |
| 1905 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1906 | // GIR_Coverage, 3468, |
| 1907 | GIR_Done, |
| 1908 | // Label 135: @1854 |
| 1909 | GIM_Try, /*On fail goto*//*Label 136*/ 1888, // Rule ID 7535 // |
| 1910 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 1911 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 1912 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_arith_shifted_reg64, |
| 1913 | // (add:{ *:[i64] } arith_shifted_reg64:{ *:[i64] }:$Rm, GPR64:{ *:[i64] }:$Rn) => (ADDXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm) |
| 1914 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXrs, |
| 1915 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 1916 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 1917 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 1918 | GIR_EraseFromParent, /*InsnID*/0, |
| 1919 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1920 | // GIR_Coverage, 7535, |
| 1921 | GIR_Done, |
| 1922 | // Label 136: @1888 |
| 1923 | GIM_Try, /*On fail goto*//*Label 137*/ 1922, // Rule ID 87 // |
| 1924 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 1925 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 1926 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_arith_shifted_reg64, |
| 1927 | // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm) => (ADDXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm) |
| 1928 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXrs, |
| 1929 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 1930 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 1931 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 1932 | GIR_EraseFromParent, /*InsnID*/0, |
| 1933 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1934 | // GIR_Coverage, 87, |
| 1935 | GIR_Done, |
| 1936 | // Label 137: @1922 |
| 1937 | GIM_Try, /*On fail goto*//*Label 138*/ 1978, // Rule ID 7613 // |
| 1938 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 1939 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 1940 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1941 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 1942 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 1943 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, |
| 1944 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 1945 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 1946 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 1947 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 1948 | // (add:{ *:[v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 427:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd) => (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn) |
| 1949 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv2i32_v1i64, |
| 1950 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 1951 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 1952 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 1953 | GIR_EraseFromParent, /*InsnID*/0, |
| 1954 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1955 | // GIR_Coverage, 7613, |
| 1956 | GIR_Done, |
| 1957 | // Label 138: @1978 |
| 1958 | GIM_Try, /*On fail goto*//*Label 139*/ 2034, // Rule ID 7619 // |
| 1959 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 1960 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 1961 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1962 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 1963 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 1964 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, |
| 1965 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 1966 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 1967 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 1968 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 1969 | // (add:{ *:[v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 490:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd) => (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn) |
| 1970 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv2i32_v1i64, |
| 1971 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 1972 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 1973 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 1974 | GIR_EraseFromParent, /*InsnID*/0, |
| 1975 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1976 | // GIR_Coverage, 7619, |
| 1977 | GIR_Done, |
| 1978 | // Label 139: @2034 |
| 1979 | GIM_Try, /*On fail goto*//*Label 140*/ 2090, // Rule ID 816 // |
| 1980 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 1981 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 1982 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 1983 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1984 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 1985 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 1986 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, |
| 1987 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 1988 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 1989 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 1990 | // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (intrinsic_wo_chain:{ *:[v1i64] } 427:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)) => (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn) |
| 1991 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv2i32_v1i64, |
| 1992 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 1993 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 1994 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 1995 | GIR_EraseFromParent, /*InsnID*/0, |
| 1996 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1997 | // GIR_Coverage, 816, |
| 1998 | GIR_Done, |
| 1999 | // Label 140: @2090 |
| 2000 | GIM_Try, /*On fail goto*//*Label 141*/ 2146, // Rule ID 860 // |
| 2001 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2002 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 2003 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 2004 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2005 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 2006 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 2007 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, |
| 2008 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2009 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2010 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2011 | // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (intrinsic_wo_chain:{ *:[v1i64] } 490:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)) => (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn) |
| 2012 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv2i32_v1i64, |
| 2013 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2014 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 2015 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2016 | GIR_EraseFromParent, /*InsnID*/0, |
| 2017 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2018 | // GIR_Coverage, 860, |
| 2019 | GIR_Done, |
| 2020 | // Label 141: @2146 |
| 2021 | GIM_Try, /*On fail goto*//*Label 142*/ 2210, // Rule ID 7783 // |
| 2022 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2023 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 2024 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2025 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, |
| 2026 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2027 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 2028 | // MIs[1] imm |
| 2029 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 2030 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 2031 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 2032 | // MIs[2] Operand 1 |
| 2033 | // No operand predicates |
| 2034 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2035 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2036 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 2037 | // (add:{ *:[i64] } (AArch64vashr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), FPR64:{ *:[i64] }:$Rd) => (SSRAd:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 2038 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAd, |
| 2039 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2040 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 2041 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2042 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 2043 | GIR_EraseFromParent, /*InsnID*/0, |
| 2044 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2045 | // GIR_Coverage, 7783, |
| 2046 | GIR_Done, |
| 2047 | // Label 142: @2210 |
| 2048 | GIM_Try, /*On fail goto*//*Label 143*/ 2274, // Rule ID 8013 // |
| 2049 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2050 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 2051 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2052 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, |
| 2053 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2054 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 2055 | // MIs[1] imm |
| 2056 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 2057 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 2058 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 2059 | // MIs[2] Operand 1 |
| 2060 | // No operand predicates |
| 2061 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2062 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2063 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 2064 | // (add:{ *:[v1i64] } (AArch64vashr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), FPR64:{ *:[v1i64] }:$Rd) => (SSRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) |
| 2065 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAd, |
| 2066 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2067 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 2068 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2069 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 2070 | GIR_EraseFromParent, /*InsnID*/0, |
| 2071 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2072 | // GIR_Coverage, 8013, |
| 2073 | GIR_Done, |
| 2074 | // Label 143: @2274 |
| 2075 | GIM_Try, /*On fail goto*//*Label 144*/ 2338, // Rule ID 7785 // |
| 2076 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2077 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 2078 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2079 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 2080 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2081 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 2082 | // MIs[1] imm |
| 2083 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 2084 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 2085 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 2086 | // MIs[2] Operand 1 |
| 2087 | // No operand predicates |
| 2088 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2089 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2090 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 2091 | // (add:{ *:[i64] } (AArch64vlshr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), FPR64:{ *:[i64] }:$Rd) => (USRAd:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 2092 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAd, |
| 2093 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2094 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 2095 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2096 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 2097 | GIR_EraseFromParent, /*InsnID*/0, |
| 2098 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2099 | // GIR_Coverage, 7785, |
| 2100 | GIR_Done, |
| 2101 | // Label 144: @2338 |
| 2102 | GIM_Try, /*On fail goto*//*Label 145*/ 2402, // Rule ID 8015 // |
| 2103 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2104 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 2105 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2106 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 2107 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2108 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 2109 | // MIs[1] imm |
| 2110 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 2111 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 2112 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 2113 | // MIs[2] Operand 1 |
| 2114 | // No operand predicates |
| 2115 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2116 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2117 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 2118 | // (add:{ *:[v1i64] } (AArch64vlshr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), FPR64:{ *:[v1i64] }:$Rd) => (USRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) |
| 2119 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAd, |
| 2120 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2121 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 2122 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2123 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 2124 | GIR_EraseFromParent, /*InsnID*/0, |
| 2125 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2126 | // GIR_Coverage, 8015, |
| 2127 | GIR_Done, |
| 2128 | // Label 145: @2402 |
| 2129 | GIM_Try, /*On fail goto*//*Label 146*/ 2466, // Rule ID 1778 // |
| 2130 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2131 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 2132 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 2133 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2134 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, |
| 2135 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2136 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 2137 | // MIs[1] imm |
| 2138 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 2139 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 2140 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 2141 | // MIs[2] Operand 1 |
| 2142 | // No operand predicates |
| 2143 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2144 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 2145 | // (add:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, (AArch64vashr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)) => (SSRAd:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 2146 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAd, |
| 2147 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2148 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 2149 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2150 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 2151 | GIR_EraseFromParent, /*InsnID*/0, |
| 2152 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2153 | // GIR_Coverage, 1778, |
| 2154 | GIR_Done, |
| 2155 | // Label 146: @2466 |
| 2156 | GIM_Try, /*On fail goto*//*Label 147*/ 2530, // Rule ID 4731 // |
| 2157 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2158 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 2159 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 2160 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2161 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, |
| 2162 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2163 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 2164 | // MIs[1] imm |
| 2165 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 2166 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 2167 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 2168 | // MIs[2] Operand 1 |
| 2169 | // No operand predicates |
| 2170 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2171 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 2172 | // (add:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, (AArch64vashr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)) => (SSRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) |
| 2173 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAd, |
| 2174 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2175 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 2176 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2177 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 2178 | GIR_EraseFromParent, /*InsnID*/0, |
| 2179 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2180 | // GIR_Coverage, 4731, |
| 2181 | GIR_Done, |
| 2182 | // Label 147: @2530 |
| 2183 | GIM_Try, /*On fail goto*//*Label 148*/ 2594, // Rule ID 1786 // |
| 2184 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2185 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 2186 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 2187 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2188 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 2189 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2190 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 2191 | // MIs[1] imm |
| 2192 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 2193 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 2194 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 2195 | // MIs[2] Operand 1 |
| 2196 | // No operand predicates |
| 2197 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2198 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 2199 | // (add:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, (AArch64vlshr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)) => (USRAd:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 2200 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAd, |
| 2201 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2202 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 2203 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2204 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 2205 | GIR_EraseFromParent, /*InsnID*/0, |
| 2206 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2207 | // GIR_Coverage, 1786, |
| 2208 | GIR_Done, |
| 2209 | // Label 148: @2594 |
| 2210 | GIM_Try, /*On fail goto*//*Label 149*/ 2658, // Rule ID 4736 // |
| 2211 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2212 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 2213 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 2214 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2215 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 2216 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2217 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 2218 | // MIs[1] imm |
| 2219 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 2220 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 2221 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 2222 | // MIs[2] Operand 1 |
| 2223 | // No operand predicates |
| 2224 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2225 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 2226 | // (add:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, (AArch64vlshr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)) => (USRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) |
| 2227 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAd, |
| 2228 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2229 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 2230 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2231 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 2232 | GIR_EraseFromParent, /*InsnID*/0, |
| 2233 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2234 | // GIR_Coverage, 4736, |
| 2235 | GIR_Done, |
| 2236 | // Label 149: @2658 |
| 2237 | GIM_Try, /*On fail goto*//*Label 150*/ 2679, // Rule ID 85 // |
| 2238 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 2239 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 2240 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 2241 | // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (ADDXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) |
| 2242 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDXrr, |
| 2243 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2244 | // GIR_Coverage, 85, |
| 2245 | GIR_Done, |
| 2246 | // Label 150: @2679 |
| 2247 | GIM_Try, /*On fail goto*//*Label 151*/ 2702, // Rule ID 1327 // |
| 2248 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2249 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 2250 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 2251 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2252 | // (add:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (ADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) |
| 2253 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv1i64, |
| 2254 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2255 | // GIR_Coverage, 1327, |
| 2256 | GIR_Done, |
| 2257 | // Label 151: @2702 |
| 2258 | GIM_Reject, |
| 2259 | // Label 119: @2703 |
| 2260 | GIM_Reject, |
| 2261 | // Label 101: @2704 |
| 2262 | GIM_Try, /*On fail goto*//*Label 152*/ 3442, |
| 2263 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 2264 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2265 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 2266 | GIM_Try, /*On fail goto*//*Label 153*/ 2782, // Rule ID 7642 // |
| 2267 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2268 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2269 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 2270 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 2271 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 2272 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2273 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 2274 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2275 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 2276 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2277 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2278 | // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 426:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd) => (SABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 2279 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv2i32, |
| 2280 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2281 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 2282 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2283 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 2284 | GIR_EraseFromParent, /*InsnID*/0, |
| 2285 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2286 | // GIR_Coverage, 7642, |
| 2287 | GIR_Done, |
| 2288 | // Label 153: @2782 |
| 2289 | GIM_Try, /*On fail goto*//*Label 154*/ 2846, // Rule ID 7654 // |
| 2290 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2291 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2292 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 2293 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 2294 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 2295 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2296 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 2297 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2298 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 2299 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2300 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2301 | // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 489:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd) => (UABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 2302 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv2i32, |
| 2303 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2304 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 2305 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2306 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 2307 | GIR_EraseFromParent, /*InsnID*/0, |
| 2308 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2309 | // GIR_Coverage, 7654, |
| 2310 | GIR_Done, |
| 2311 | // Label 154: @2846 |
| 2312 | GIM_Try, /*On fail goto*//*Label 155*/ 2898, // Rule ID 7611 // |
| 2313 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2314 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2315 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 2316 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 2317 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, |
| 2318 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 2319 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2320 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2321 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2322 | // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 427:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd) => (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn) |
| 2323 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i16_v2i32, |
| 2324 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2325 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 2326 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2327 | GIR_EraseFromParent, /*InsnID*/0, |
| 2328 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2329 | // GIR_Coverage, 7611, |
| 2330 | GIR_Done, |
| 2331 | // Label 155: @2898 |
| 2332 | GIM_Try, /*On fail goto*//*Label 156*/ 2950, // Rule ID 7617 // |
| 2333 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2334 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2335 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 2336 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 2337 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, |
| 2338 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 2339 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2340 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2341 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2342 | // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 490:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd) => (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn) |
| 2343 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i16_v2i32, |
| 2344 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2345 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 2346 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2347 | GIR_EraseFromParent, /*InsnID*/0, |
| 2348 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2349 | // GIR_Coverage, 7617, |
| 2350 | GIR_Done, |
| 2351 | // Label 156: @2950 |
| 2352 | GIM_Try, /*On fail goto*//*Label 157*/ 3014, // Rule ID 1083 // |
| 2353 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2354 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 2355 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2356 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 2357 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 2358 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 2359 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2360 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 2361 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2362 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 2363 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2364 | // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 426:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 2365 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv2i32, |
| 2366 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2367 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 2368 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2369 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 2370 | GIR_EraseFromParent, /*InsnID*/0, |
| 2371 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2372 | // GIR_Coverage, 1083, |
| 2373 | GIR_Done, |
| 2374 | // Label 157: @3014 |
| 2375 | GIM_Try, /*On fail goto*//*Label 158*/ 3078, // Rule ID 1206 // |
| 2376 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2377 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 2378 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2379 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 2380 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 2381 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 2382 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2383 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 2384 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2385 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 2386 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2387 | // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 489:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (UABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 2388 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv2i32, |
| 2389 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2390 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 2391 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2392 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 2393 | GIR_EraseFromParent, /*InsnID*/0, |
| 2394 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2395 | // GIR_Coverage, 1206, |
| 2396 | GIR_Done, |
| 2397 | // Label 158: @3078 |
| 2398 | GIM_Try, /*On fail goto*//*Label 159*/ 3130, // Rule ID 814 // |
| 2399 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2400 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 2401 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2402 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 2403 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 2404 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, |
| 2405 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 2406 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2407 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2408 | // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 427:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)) => (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn) |
| 2409 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i16_v2i32, |
| 2410 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2411 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 2412 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2413 | GIR_EraseFromParent, /*InsnID*/0, |
| 2414 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2415 | // GIR_Coverage, 814, |
| 2416 | GIR_Done, |
| 2417 | // Label 159: @3130 |
| 2418 | GIM_Try, /*On fail goto*//*Label 160*/ 3182, // Rule ID 858 // |
| 2419 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2420 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 2421 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2422 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 2423 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 2424 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, |
| 2425 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 2426 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2427 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2428 | // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 490:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)) => (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn) |
| 2429 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i16_v2i32, |
| 2430 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2431 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 2432 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2433 | GIR_EraseFromParent, /*InsnID*/0, |
| 2434 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2435 | // GIR_Coverage, 858, |
| 2436 | GIR_Done, |
| 2437 | // Label 160: @3182 |
| 2438 | GIM_Try, /*On fail goto*//*Label 161*/ 3242, // Rule ID 7797 // |
| 2439 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2440 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2441 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, |
| 2442 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 2443 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 2444 | // MIs[1] imm |
| 2445 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 2446 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 2447 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, |
| 2448 | // MIs[2] Operand 1 |
| 2449 | // No operand predicates |
| 2450 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2451 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2452 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 2453 | // (add:{ *:[v2i32] } (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V64:{ *:[v2i32] }:$Rd) => (SSRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 2454 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv2i32_shift, |
| 2455 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2456 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 2457 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2458 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 2459 | GIR_EraseFromParent, /*InsnID*/0, |
| 2460 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2461 | // GIR_Coverage, 7797, |
| 2462 | GIR_Done, |
| 2463 | // Label 161: @3242 |
| 2464 | GIM_Try, /*On fail goto*//*Label 162*/ 3302, // Rule ID 7811 // |
| 2465 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2466 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2467 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 2468 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 2469 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 2470 | // MIs[1] imm |
| 2471 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 2472 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 2473 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, |
| 2474 | // MIs[2] Operand 1 |
| 2475 | // No operand predicates |
| 2476 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2477 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2478 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 2479 | // (add:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V64:{ *:[v2i32] }:$Rd) => (USRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 2480 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv2i32_shift, |
| 2481 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2482 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 2483 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2484 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 2485 | GIR_EraseFromParent, /*InsnID*/0, |
| 2486 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2487 | // GIR_Coverage, 7811, |
| 2488 | GIR_Done, |
| 2489 | // Label 162: @3302 |
| 2490 | GIM_Try, /*On fail goto*//*Label 163*/ 3362, // Rule ID 1886 // |
| 2491 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2492 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 2493 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2494 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, |
| 2495 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 2496 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 2497 | // MIs[1] imm |
| 2498 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 2499 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 2500 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, |
| 2501 | // MIs[2] Operand 1 |
| 2502 | // No operand predicates |
| 2503 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2504 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 2505 | // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)) => (SSRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 2506 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv2i32_shift, |
| 2507 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2508 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 2509 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2510 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 2511 | GIR_EraseFromParent, /*InsnID*/0, |
| 2512 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2513 | // GIR_Coverage, 1886, |
| 2514 | GIR_Done, |
| 2515 | // Label 163: @3362 |
| 2516 | GIM_Try, /*On fail goto*//*Label 164*/ 3422, // Rule ID 1938 // |
| 2517 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2518 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 2519 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2520 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 2521 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 2522 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 2523 | // MIs[1] imm |
| 2524 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 2525 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 2526 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, |
| 2527 | // MIs[2] Operand 1 |
| 2528 | // No operand predicates |
| 2529 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2530 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 2531 | // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (AArch64vlshr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)) => (USRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 2532 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv2i32_shift, |
| 2533 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2534 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 2535 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2536 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 2537 | GIR_EraseFromParent, /*InsnID*/0, |
| 2538 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2539 | // GIR_Coverage, 1938, |
| 2540 | GIR_Done, |
| 2541 | // Label 164: @3422 |
| 2542 | GIM_Try, /*On fail goto*//*Label 165*/ 3441, // Rule ID 894 // |
| 2543 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2544 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 2545 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2546 | // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (ADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 2547 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv2i32, |
| 2548 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2549 | // GIR_Coverage, 894, |
| 2550 | GIR_Done, |
| 2551 | // Label 165: @3441 |
| 2552 | GIM_Reject, |
| 2553 | // Label 152: @3442 |
| 2554 | GIM_Reject, |
| 2555 | // Label 102: @3443 |
| 2556 | GIM_Try, /*On fail goto*//*Label 166*/ 5433, |
| 2557 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 2558 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 2559 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 2560 | GIM_Try, /*On fail goto*//*Label 167*/ 3553, // Rule ID 7776 // |
| 2561 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2562 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2563 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 2564 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 2565 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, |
| 2566 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2567 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 2568 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2569 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 2570 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 2571 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2572 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 2573 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 2574 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 2575 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 2576 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 2577 | // MIs[3] Operand 1 |
| 2578 | // No operand predicates |
| 2579 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 2580 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2581 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 2582 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 2583 | // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 444:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v2i64] }:$Rd) => (SMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 2584 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv2i32_indexed, |
| 2585 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2586 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 2587 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2588 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 2589 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 2590 | GIR_EraseFromParent, /*InsnID*/0, |
| 2591 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2592 | // GIR_Coverage, 7776, |
| 2593 | GIR_Done, |
| 2594 | // Label 167: @3553 |
| 2595 | GIM_Try, /*On fail goto*//*Label 168*/ 3649, // Rule ID 7780 // |
| 2596 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2597 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2598 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 2599 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 2600 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, |
| 2601 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2602 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 2603 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2604 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 2605 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 2606 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2607 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 2608 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 2609 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 2610 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 2611 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 2612 | // MIs[3] Operand 1 |
| 2613 | // No operand predicates |
| 2614 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 2615 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2616 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 2617 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 2618 | // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 503:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v2i64] }:$Rd) => (UMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 2619 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv2i32_indexed, |
| 2620 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2621 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 2622 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2623 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 2624 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 2625 | GIR_EraseFromParent, /*InsnID*/0, |
| 2626 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2627 | // GIR_Coverage, 7780, |
| 2628 | GIR_Done, |
| 2629 | // Label 168: @3649 |
| 2630 | GIM_Try, /*On fail goto*//*Label 169*/ 3745, // Rule ID 1720 // |
| 2631 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2632 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 2633 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2634 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 2635 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 2636 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, |
| 2637 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2638 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 2639 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2640 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 2641 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 2642 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2643 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 2644 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 2645 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 2646 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 2647 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 2648 | // MIs[3] Operand 1 |
| 2649 | // No operand predicates |
| 2650 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2651 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 2652 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 2653 | // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 444:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (SMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 2654 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv2i32_indexed, |
| 2655 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2656 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 2657 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2658 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 2659 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 2660 | GIR_EraseFromParent, /*InsnID*/0, |
| 2661 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2662 | // GIR_Coverage, 1720, |
| 2663 | GIR_Done, |
| 2664 | // Label 169: @3745 |
| 2665 | GIM_Try, /*On fail goto*//*Label 170*/ 3841, // Rule ID 1756 // |
| 2666 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2667 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 2668 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2669 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 2670 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 2671 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, |
| 2672 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2673 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 2674 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2675 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 2676 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 2677 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2678 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 2679 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 2680 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 2681 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 2682 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 2683 | // MIs[3] Operand 1 |
| 2684 | // No operand predicates |
| 2685 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2686 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 2687 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 2688 | // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 503:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (UMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 2689 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv2i32_indexed, |
| 2690 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2691 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 2692 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2693 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 2694 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 2695 | GIR_EraseFromParent, /*InsnID*/0, |
| 2696 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2697 | // GIR_Coverage, 1756, |
| 2698 | GIR_Done, |
| 2699 | // Label 170: @3841 |
| 2700 | GIM_Try, /*On fail goto*//*Label 171*/ 3918, // Rule ID 7709 // |
| 2701 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2702 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2703 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 2704 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 2705 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2706 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, |
| 2707 | GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, |
| 2708 | GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 2709 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2710 | GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32, |
| 2711 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2712 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 2713 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 2714 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2715 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 2716 | // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 426:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd) => (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 2717 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv2i32_v2i64, |
| 2718 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2719 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 2720 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn |
| 2721 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm |
| 2722 | GIR_EraseFromParent, /*InsnID*/0, |
| 2723 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2724 | // GIR_Coverage, 7709, |
| 2725 | GIR_Done, |
| 2726 | // Label 171: @3918 |
| 2727 | GIM_Try, /*On fail goto*//*Label 172*/ 3995, // Rule ID 7733 // |
| 2728 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2729 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2730 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 2731 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 2732 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2733 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, |
| 2734 | GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, |
| 2735 | GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 2736 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2737 | GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32, |
| 2738 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2739 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 2740 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 2741 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2742 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 2743 | // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 489:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd) => (UABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 2744 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv2i32_v2i64, |
| 2745 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2746 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 2747 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn |
| 2748 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm |
| 2749 | GIR_EraseFromParent, /*InsnID*/0, |
| 2750 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2751 | // GIR_Coverage, 7733, |
| 2752 | GIR_Done, |
| 2753 | // Label 172: @3995 |
| 2754 | GIM_Try, /*On fail goto*//*Label 173*/ 4072, // Rule ID 1414 // |
| 2755 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2756 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 2757 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2758 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 2759 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 2760 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2761 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, |
| 2762 | GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, |
| 2763 | GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 2764 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2765 | GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32, |
| 2766 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2767 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 2768 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2769 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 2770 | // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 426:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))) => (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 2771 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv2i32_v2i64, |
| 2772 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2773 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 2774 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn |
| 2775 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm |
| 2776 | GIR_EraseFromParent, /*InsnID*/0, |
| 2777 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2778 | // GIR_Coverage, 1414, |
| 2779 | GIR_Done, |
| 2780 | // Label 173: @4072 |
| 2781 | GIM_Try, /*On fail goto*//*Label 174*/ 4149, // Rule ID 1492 // |
| 2782 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2783 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 2784 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2785 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 2786 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 2787 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2788 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, |
| 2789 | GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, |
| 2790 | GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 2791 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2792 | GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32, |
| 2793 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2794 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 2795 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2796 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 2797 | // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 489:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))) => (UABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 2798 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv2i32_v2i64, |
| 2799 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2800 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 2801 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn |
| 2802 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm |
| 2803 | GIR_EraseFromParent, /*InsnID*/0, |
| 2804 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2805 | // GIR_Coverage, 1492, |
| 2806 | GIR_Done, |
| 2807 | // Label 174: @4149 |
| 2808 | GIM_Try, /*On fail goto*//*Label 175*/ 4213, // Rule ID 7722 // |
| 2809 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2810 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2811 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 2812 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 2813 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, |
| 2814 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2815 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 2816 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2817 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 2818 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 2819 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2820 | // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 444:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd) => (SMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 2821 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv2i32_v2i64, |
| 2822 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2823 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 2824 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2825 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 2826 | GIR_EraseFromParent, /*InsnID*/0, |
| 2827 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2828 | // GIR_Coverage, 7722, |
| 2829 | GIR_Done, |
| 2830 | // Label 175: @4213 |
| 2831 | GIM_Try, /*On fail goto*//*Label 176*/ 4277, // Rule ID 7752 // |
| 2832 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2833 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2834 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 2835 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 2836 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, |
| 2837 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2838 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 2839 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2840 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 2841 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 2842 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2843 | // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 503:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd) => (UMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 2844 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv2i32_v2i64, |
| 2845 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2846 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 2847 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2848 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 2849 | GIR_EraseFromParent, /*InsnID*/0, |
| 2850 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2851 | // GIR_Coverage, 7752, |
| 2852 | GIR_Done, |
| 2853 | // Label 176: @4277 |
| 2854 | GIM_Try, /*On fail goto*//*Label 177*/ 4329, // Rule ID 7614 // |
| 2855 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2856 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2857 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 2858 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 2859 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, |
| 2860 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 2861 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 2862 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 2863 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2864 | // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 427:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd) => (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn) |
| 2865 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i32_v2i64, |
| 2866 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2867 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 2868 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2869 | GIR_EraseFromParent, /*InsnID*/0, |
| 2870 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2871 | // GIR_Coverage, 7614, |
| 2872 | GIR_Done, |
| 2873 | // Label 177: @4329 |
| 2874 | GIM_Try, /*On fail goto*//*Label 178*/ 4381, // Rule ID 7620 // |
| 2875 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2876 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2877 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 2878 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 2879 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, |
| 2880 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 2881 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 2882 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 2883 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2884 | // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 490:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd) => (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn) |
| 2885 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i32_v2i64, |
| 2886 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2887 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 2888 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2889 | GIR_EraseFromParent, /*InsnID*/0, |
| 2890 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2891 | // GIR_Coverage, 7620, |
| 2892 | GIR_Done, |
| 2893 | // Label 178: @4381 |
| 2894 | GIM_Try, /*On fail goto*//*Label 179*/ 4445, // Rule ID 1445 // |
| 2895 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2896 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 2897 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2898 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 2899 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 2900 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, |
| 2901 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2902 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 2903 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2904 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 2905 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2906 | // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 444:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 2907 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv2i32_v2i64, |
| 2908 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2909 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 2910 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2911 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 2912 | GIR_EraseFromParent, /*InsnID*/0, |
| 2913 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2914 | // GIR_Coverage, 1445, |
| 2915 | GIR_Done, |
| 2916 | // Label 179: @4445 |
| 2917 | GIM_Try, /*On fail goto*//*Label 180*/ 4509, // Rule ID 1535 // |
| 2918 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2919 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 2920 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2921 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 2922 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 2923 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, |
| 2924 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 2925 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 2926 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 2927 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 2928 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2929 | // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 503:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (UMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 2930 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv2i32_v2i64, |
| 2931 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2932 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 2933 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2934 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 2935 | GIR_EraseFromParent, /*InsnID*/0, |
| 2936 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2937 | // GIR_Coverage, 1535, |
| 2938 | GIR_Done, |
| 2939 | // Label 180: @4509 |
| 2940 | GIM_Try, /*On fail goto*//*Label 181*/ 4561, // Rule ID 817 // |
| 2941 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2942 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 2943 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2944 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 2945 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 2946 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, |
| 2947 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 2948 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 2949 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2950 | // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 427:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)) => (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn) |
| 2951 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv4i32_v2i64, |
| 2952 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2953 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 2954 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2955 | GIR_EraseFromParent, /*InsnID*/0, |
| 2956 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2957 | // GIR_Coverage, 817, |
| 2958 | GIR_Done, |
| 2959 | // Label 181: @4561 |
| 2960 | GIM_Try, /*On fail goto*//*Label 182*/ 4613, // Rule ID 861 // |
| 2961 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2962 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 2963 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2964 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 2965 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 2966 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, |
| 2967 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 2968 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 2969 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2970 | // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 490:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)) => (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn) |
| 2971 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv4i32_v2i64, |
| 2972 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2973 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 2974 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2975 | GIR_EraseFromParent, /*InsnID*/0, |
| 2976 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2977 | // GIR_Coverage, 861, |
| 2978 | GIR_Done, |
| 2979 | // Label 182: @4613 |
| 2980 | GIM_Try, /*On fail goto*//*Label 183*/ 4673, // Rule ID 7799 // |
| 2981 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 2982 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2983 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, |
| 2984 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 2985 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 2986 | // MIs[1] imm |
| 2987 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 2988 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 2989 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 2990 | // MIs[2] Operand 1 |
| 2991 | // No operand predicates |
| 2992 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 2993 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2994 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 2995 | // (add:{ *:[v2i64] } (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), V128:{ *:[v2i64] }:$Rd) => (SSRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 2996 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv2i64_shift, |
| 2997 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 2998 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 2999 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 3000 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 3001 | GIR_EraseFromParent, /*InsnID*/0, |
| 3002 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3003 | // GIR_Coverage, 7799, |
| 3004 | GIR_Done, |
| 3005 | // Label 183: @4673 |
| 3006 | GIM_Try, /*On fail goto*//*Label 184*/ 4733, // Rule ID 7813 // |
| 3007 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3008 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3009 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 3010 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3011 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 3012 | // MIs[1] imm |
| 3013 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 3014 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 3015 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 3016 | // MIs[2] Operand 1 |
| 3017 | // No operand predicates |
| 3018 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 3019 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3020 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 3021 | // (add:{ *:[v2i64] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), V128:{ *:[v2i64] }:$Rd) => (USRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 3022 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv2i64_shift, |
| 3023 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3024 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 3025 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 3026 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 3027 | GIR_EraseFromParent, /*InsnID*/0, |
| 3028 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3029 | // GIR_Coverage, 7813, |
| 3030 | GIR_Done, |
| 3031 | // Label 184: @4733 |
| 3032 | GIM_Try, /*On fail goto*//*Label 185*/ 4793, // Rule ID 1888 // |
| 3033 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3034 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 3035 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3036 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, |
| 3037 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3038 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 3039 | // MIs[1] imm |
| 3040 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 3041 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 3042 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 3043 | // MIs[2] Operand 1 |
| 3044 | // No operand predicates |
| 3045 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3046 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 3047 | // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)) => (SSRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 3048 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv2i64_shift, |
| 3049 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3050 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 3051 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 3052 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 3053 | GIR_EraseFromParent, /*InsnID*/0, |
| 3054 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3055 | // GIR_Coverage, 1888, |
| 3056 | GIR_Done, |
| 3057 | // Label 185: @4793 |
| 3058 | GIM_Try, /*On fail goto*//*Label 186*/ 4853, // Rule ID 1940 // |
| 3059 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3060 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 3061 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3062 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 3063 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3064 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 3065 | // MIs[1] imm |
| 3066 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 3067 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 3068 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 3069 | // MIs[2] Operand 1 |
| 3070 | // No operand predicates |
| 3071 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3072 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 3073 | // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)) => (USRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 3074 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv2i64_shift, |
| 3075 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3076 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 3077 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 3078 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 3079 | GIR_EraseFromParent, /*InsnID*/0, |
| 3080 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3081 | // GIR_Coverage, 1940, |
| 3082 | GIR_Done, |
| 3083 | // Label 186: @4853 |
| 3084 | GIM_Try, /*On fail goto*//*Label 187*/ 4911, // Rule ID 1514 // |
| 3085 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3086 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3087 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, |
| 3088 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3089 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3090 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3091 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT, |
| 3092 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3093 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3094 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3095 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 3096 | // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 3097 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv2i32_v2i64, |
| 3098 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 3099 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 3100 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 3101 | GIR_EraseFromParent, /*InsnID*/0, |
| 3102 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3103 | // GIR_Coverage, 1514, |
| 3104 | GIR_Done, |
| 3105 | // Label 187: @4911 |
| 3106 | GIM_Try, /*On fail goto*//*Label 188*/ 4969, // Rule ID 1513 // |
| 3107 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3108 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3109 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, |
| 3110 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3111 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3112 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3113 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, |
| 3114 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3115 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3116 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3117 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 3118 | // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 3119 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv2i32_v2i64, |
| 3120 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 3121 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 3122 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 3123 | GIR_EraseFromParent, /*InsnID*/0, |
| 3124 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3125 | // GIR_Coverage, 1513, |
| 3126 | GIR_Done, |
| 3127 | // Label 188: @4969 |
| 3128 | GIM_Try, /*On fail goto*//*Label 189*/ 5027, // Rule ID 1433 // |
| 3129 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3130 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3131 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, |
| 3132 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3133 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3134 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3135 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, |
| 3136 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3137 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3138 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3139 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 3140 | // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (SADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 3141 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv2i32_v2i64, |
| 3142 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 3143 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 3144 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 3145 | GIR_EraseFromParent, /*InsnID*/0, |
| 3146 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3147 | // GIR_Coverage, 1433, |
| 3148 | GIR_Done, |
| 3149 | // Label 189: @5027 |
| 3150 | GIM_Try, /*On fail goto*//*Label 190*/ 5085, // Rule ID 1512 // |
| 3151 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3152 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3153 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 3154 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3155 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3156 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3157 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT, |
| 3158 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3159 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3160 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3161 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 3162 | // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 3163 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv2i32_v2i64, |
| 3164 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 3165 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 3166 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 3167 | GIR_EraseFromParent, /*InsnID*/0, |
| 3168 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3169 | // GIR_Coverage, 1512, |
| 3170 | GIR_Done, |
| 3171 | // Label 190: @5085 |
| 3172 | GIM_Try, /*On fail goto*//*Label 191*/ 5143, // Rule ID 1511 // |
| 3173 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3174 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3175 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 3176 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3177 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3178 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3179 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, |
| 3180 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3181 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3182 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3183 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 3184 | // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 3185 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv2i32_v2i64, |
| 3186 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 3187 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 3188 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 3189 | GIR_EraseFromParent, /*InsnID*/0, |
| 3190 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3191 | // GIR_Coverage, 1511, |
| 3192 | GIR_Done, |
| 3193 | // Label 191: @5143 |
| 3194 | GIM_Try, /*On fail goto*//*Label 192*/ 5188, // Rule ID 7745 // |
| 3195 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3196 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3197 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, |
| 3198 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3199 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3200 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 3201 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3202 | // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn) => (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 3203 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv2i32_v2i64, |
| 3204 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 3205 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 3206 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 3207 | GIR_EraseFromParent, /*InsnID*/0, |
| 3208 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3209 | // GIR_Coverage, 7745, |
| 3210 | GIR_Done, |
| 3211 | // Label 192: @5188 |
| 3212 | GIM_Try, /*On fail goto*//*Label 193*/ 5233, // Rule ID 7716 // |
| 3213 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3214 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3215 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, |
| 3216 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3217 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3218 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 3219 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3220 | // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn) => (SADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 3221 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv2i32_v2i64, |
| 3222 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 3223 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 3224 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 3225 | GIR_EraseFromParent, /*InsnID*/0, |
| 3226 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3227 | // GIR_Coverage, 7716, |
| 3228 | GIR_Done, |
| 3229 | // Label 193: @5233 |
| 3230 | GIM_Try, /*On fail goto*//*Label 194*/ 5278, // Rule ID 7744 // |
| 3231 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3232 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3233 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 3234 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3235 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3236 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 3237 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3238 | // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn) => (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 3239 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv2i32_v2i64, |
| 3240 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 3241 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 3242 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 3243 | GIR_EraseFromParent, /*InsnID*/0, |
| 3244 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3245 | // GIR_Coverage, 7744, |
| 3246 | GIR_Done, |
| 3247 | // Label 194: @5278 |
| 3248 | GIM_Try, /*On fail goto*//*Label 195*/ 5323, // Rule ID 1528 // |
| 3249 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3250 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 3251 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3252 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, |
| 3253 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3254 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3255 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3256 | // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 3257 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv2i32_v2i64, |
| 3258 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 3259 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 3260 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 3261 | GIR_EraseFromParent, /*InsnID*/0, |
| 3262 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3263 | // GIR_Coverage, 1528, |
| 3264 | GIR_Done, |
| 3265 | // Label 195: @5323 |
| 3266 | GIM_Try, /*On fail goto*//*Label 196*/ 5368, // Rule ID 1439 // |
| 3267 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3268 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 3269 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3270 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, |
| 3271 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3272 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3273 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3274 | // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (SADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 3275 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv2i32_v2i64, |
| 3276 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 3277 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 3278 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 3279 | GIR_EraseFromParent, /*InsnID*/0, |
| 3280 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3281 | // GIR_Coverage, 1439, |
| 3282 | GIR_Done, |
| 3283 | // Label 196: @5368 |
| 3284 | GIM_Try, /*On fail goto*//*Label 197*/ 5413, // Rule ID 1527 // |
| 3285 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3286 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 3287 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3288 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 3289 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3290 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3291 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3292 | // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 3293 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv2i32_v2i64, |
| 3294 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 3295 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 3296 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 3297 | GIR_EraseFromParent, /*InsnID*/0, |
| 3298 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3299 | // GIR_Coverage, 1527, |
| 3300 | GIR_Done, |
| 3301 | // Label 197: @5413 |
| 3302 | GIM_Try, /*On fail goto*//*Label 198*/ 5432, // Rule ID 896 // |
| 3303 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3304 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 3305 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 3306 | // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (ADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 3307 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv2i64, |
| 3308 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3309 | // GIR_Coverage, 896, |
| 3310 | GIR_Done, |
| 3311 | // Label 198: @5432 |
| 3312 | GIM_Reject, |
| 3313 | // Label 166: @5433 |
| 3314 | GIM_Reject, |
| 3315 | // Label 103: @5434 |
| 3316 | GIM_Try, /*On fail goto*//*Label 199*/ 6172, |
| 3317 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3318 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3319 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 3320 | GIM_Try, /*On fail goto*//*Label 200*/ 5512, // Rule ID 7638 // |
| 3321 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3322 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3323 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 3324 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 3325 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 3326 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3327 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 3328 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 3329 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 3330 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 3331 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3332 | // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 426:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd) => (SABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 3333 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i16, |
| 3334 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3335 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 3336 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 3337 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 3338 | GIR_EraseFromParent, /*InsnID*/0, |
| 3339 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3340 | // GIR_Coverage, 7638, |
| 3341 | GIR_Done, |
| 3342 | // Label 200: @5512 |
| 3343 | GIM_Try, /*On fail goto*//*Label 201*/ 5576, // Rule ID 7650 // |
| 3344 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3345 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3346 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 3347 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 3348 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 3349 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3350 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 3351 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 3352 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 3353 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 3354 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3355 | // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 489:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd) => (UABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 3356 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i16, |
| 3357 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3358 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 3359 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 3360 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 3361 | GIR_EraseFromParent, /*InsnID*/0, |
| 3362 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3363 | // GIR_Coverage, 7650, |
| 3364 | GIR_Done, |
| 3365 | // Label 201: @5576 |
| 3366 | GIM_Try, /*On fail goto*//*Label 202*/ 5628, // Rule ID 7609 // |
| 3367 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3368 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3369 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 3370 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 3371 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, |
| 3372 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 3373 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 3374 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 3375 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3376 | // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 427:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd) => (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn) |
| 3377 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i8_v4i16, |
| 3378 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3379 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 3380 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 3381 | GIR_EraseFromParent, /*InsnID*/0, |
| 3382 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3383 | // GIR_Coverage, 7609, |
| 3384 | GIR_Done, |
| 3385 | // Label 202: @5628 |
| 3386 | GIM_Try, /*On fail goto*//*Label 203*/ 5680, // Rule ID 7615 // |
| 3387 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3388 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3389 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 3390 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 3391 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, |
| 3392 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 3393 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 3394 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 3395 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3396 | // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 490:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd) => (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn) |
| 3397 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i8_v4i16, |
| 3398 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3399 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 3400 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 3401 | GIR_EraseFromParent, /*InsnID*/0, |
| 3402 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3403 | // GIR_Coverage, 7615, |
| 3404 | GIR_Done, |
| 3405 | // Label 203: @5680 |
| 3406 | GIM_Try, /*On fail goto*//*Label 204*/ 5744, // Rule ID 1079 // |
| 3407 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3408 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3409 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3410 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 3411 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 3412 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 3413 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3414 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 3415 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 3416 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 3417 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3418 | // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 426:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 3419 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i16, |
| 3420 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3421 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 3422 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 3423 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 3424 | GIR_EraseFromParent, /*InsnID*/0, |
| 3425 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3426 | // GIR_Coverage, 1079, |
| 3427 | GIR_Done, |
| 3428 | // Label 204: @5744 |
| 3429 | GIM_Try, /*On fail goto*//*Label 205*/ 5808, // Rule ID 1202 // |
| 3430 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3431 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3432 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3433 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 3434 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 3435 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 3436 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3437 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 3438 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 3439 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 3440 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3441 | // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 489:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (UABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 3442 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i16, |
| 3443 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3444 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 3445 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 3446 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 3447 | GIR_EraseFromParent, /*InsnID*/0, |
| 3448 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3449 | // GIR_Coverage, 1202, |
| 3450 | GIR_Done, |
| 3451 | // Label 205: @5808 |
| 3452 | GIM_Try, /*On fail goto*//*Label 206*/ 5860, // Rule ID 812 // |
| 3453 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3454 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3455 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3456 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 3457 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 3458 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, |
| 3459 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 3460 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 3461 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3462 | // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 427:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)) => (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn) |
| 3463 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i8_v4i16, |
| 3464 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3465 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 3466 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 3467 | GIR_EraseFromParent, /*InsnID*/0, |
| 3468 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3469 | // GIR_Coverage, 812, |
| 3470 | GIR_Done, |
| 3471 | // Label 206: @5860 |
| 3472 | GIM_Try, /*On fail goto*//*Label 207*/ 5912, // Rule ID 856 // |
| 3473 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3474 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3475 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3476 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 3477 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 3478 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, |
| 3479 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 3480 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 3481 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3482 | // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 490:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)) => (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn) |
| 3483 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i8_v4i16, |
| 3484 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3485 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 3486 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 3487 | GIR_EraseFromParent, /*InsnID*/0, |
| 3488 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3489 | // GIR_Coverage, 856, |
| 3490 | GIR_Done, |
| 3491 | // Label 207: @5912 |
| 3492 | GIM_Try, /*On fail goto*//*Label 208*/ 5972, // Rule ID 7795 // |
| 3493 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3494 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3495 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, |
| 3496 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3497 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3498 | // MIs[1] imm |
| 3499 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 3500 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 3501 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, |
| 3502 | // MIs[2] Operand 1 |
| 3503 | // No operand predicates |
| 3504 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 3505 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3506 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 3507 | // (add:{ *:[v4i16] } (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V64:{ *:[v4i16] }:$Rd) => (SSRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 3508 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv4i16_shift, |
| 3509 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3510 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 3511 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 3512 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 3513 | GIR_EraseFromParent, /*InsnID*/0, |
| 3514 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3515 | // GIR_Coverage, 7795, |
| 3516 | GIR_Done, |
| 3517 | // Label 208: @5972 |
| 3518 | GIM_Try, /*On fail goto*//*Label 209*/ 6032, // Rule ID 7809 // |
| 3519 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3520 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3521 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 3522 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3523 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3524 | // MIs[1] imm |
| 3525 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 3526 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 3527 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, |
| 3528 | // MIs[2] Operand 1 |
| 3529 | // No operand predicates |
| 3530 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 3531 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3532 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 3533 | // (add:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V64:{ *:[v4i16] }:$Rd) => (USRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 3534 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv4i16_shift, |
| 3535 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3536 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 3537 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 3538 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 3539 | GIR_EraseFromParent, /*InsnID*/0, |
| 3540 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3541 | // GIR_Coverage, 7809, |
| 3542 | GIR_Done, |
| 3543 | // Label 209: @6032 |
| 3544 | GIM_Try, /*On fail goto*//*Label 210*/ 6092, // Rule ID 1884 // |
| 3545 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3546 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3547 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3548 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, |
| 3549 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3550 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3551 | // MIs[1] imm |
| 3552 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 3553 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 3554 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, |
| 3555 | // MIs[2] Operand 1 |
| 3556 | // No operand predicates |
| 3557 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3558 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 3559 | // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)) => (SSRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 3560 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv4i16_shift, |
| 3561 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3562 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 3563 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 3564 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 3565 | GIR_EraseFromParent, /*InsnID*/0, |
| 3566 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3567 | // GIR_Coverage, 1884, |
| 3568 | GIR_Done, |
| 3569 | // Label 210: @6092 |
| 3570 | GIM_Try, /*On fail goto*//*Label 211*/ 6152, // Rule ID 1936 // |
| 3571 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3572 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3573 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3574 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 3575 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3576 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3577 | // MIs[1] imm |
| 3578 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 3579 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 3580 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, |
| 3581 | // MIs[2] Operand 1 |
| 3582 | // No operand predicates |
| 3583 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3584 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 3585 | // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (AArch64vlshr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)) => (USRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 3586 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv4i16_shift, |
| 3587 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3588 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 3589 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 3590 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 3591 | GIR_EraseFromParent, /*InsnID*/0, |
| 3592 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3593 | // GIR_Coverage, 1936, |
| 3594 | GIR_Done, |
| 3595 | // Label 211: @6152 |
| 3596 | GIM_Try, /*On fail goto*//*Label 212*/ 6171, // Rule ID 892 // |
| 3597 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3598 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 3599 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 3600 | // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (ADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 3601 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv4i16, |
| 3602 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3603 | // GIR_Coverage, 892, |
| 3604 | GIR_Done, |
| 3605 | // Label 212: @6171 |
| 3606 | GIM_Reject, |
| 3607 | // Label 199: @6172 |
| 3608 | GIM_Reject, |
| 3609 | // Label 104: @6173 |
| 3610 | GIM_Try, /*On fail goto*//*Label 213*/ 8419, |
| 3611 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3612 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 3613 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 3614 | GIM_Try, /*On fail goto*//*Label 214*/ 6283, // Rule ID 7774 // |
| 3615 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3616 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3617 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 3618 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 3619 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, |
| 3620 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3621 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 3622 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 3623 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 3624 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, |
| 3625 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3626 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 3627 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 3628 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 3629 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 3630 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 3631 | // MIs[3] Operand 1 |
| 3632 | // No operand predicates |
| 3633 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 3634 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3635 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 3636 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 3637 | // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 444:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V128:{ *:[v4i32] }:$Rd) => (SMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 3638 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv4i16_indexed, |
| 3639 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3640 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 3641 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 3642 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 3643 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 3644 | GIR_EraseFromParent, /*InsnID*/0, |
| 3645 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3646 | // GIR_Coverage, 7774, |
| 3647 | GIR_Done, |
| 3648 | // Label 214: @6283 |
| 3649 | GIM_Try, /*On fail goto*//*Label 215*/ 6379, // Rule ID 7778 // |
| 3650 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3651 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3652 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 3653 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 3654 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, |
| 3655 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3656 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 3657 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 3658 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 3659 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, |
| 3660 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3661 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 3662 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 3663 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 3664 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 3665 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 3666 | // MIs[3] Operand 1 |
| 3667 | // No operand predicates |
| 3668 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 3669 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3670 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 3671 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 3672 | // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 503:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V128:{ *:[v4i32] }:$Rd) => (UMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 3673 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv4i16_indexed, |
| 3674 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3675 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 3676 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 3677 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 3678 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 3679 | GIR_EraseFromParent, /*InsnID*/0, |
| 3680 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3681 | // GIR_Coverage, 7778, |
| 3682 | GIR_Done, |
| 3683 | // Label 215: @6379 |
| 3684 | GIM_Try, /*On fail goto*//*Label 216*/ 6475, // Rule ID 1718 // |
| 3685 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3686 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 3687 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3688 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 3689 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 3690 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, |
| 3691 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3692 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 3693 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 3694 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 3695 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, |
| 3696 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3697 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 3698 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 3699 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 3700 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 3701 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 3702 | // MIs[3] Operand 1 |
| 3703 | // No operand predicates |
| 3704 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3705 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 3706 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 3707 | // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 444:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))) => (SMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 3708 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv4i16_indexed, |
| 3709 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3710 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 3711 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 3712 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 3713 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 3714 | GIR_EraseFromParent, /*InsnID*/0, |
| 3715 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3716 | // GIR_Coverage, 1718, |
| 3717 | GIR_Done, |
| 3718 | // Label 216: @6475 |
| 3719 | GIM_Try, /*On fail goto*//*Label 217*/ 6571, // Rule ID 1754 // |
| 3720 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3721 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 3722 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3723 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 3724 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 3725 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, |
| 3726 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3727 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 3728 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 3729 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 3730 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, |
| 3731 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3732 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 3733 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 3734 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 3735 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 3736 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 3737 | // MIs[3] Operand 1 |
| 3738 | // No operand predicates |
| 3739 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3740 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 3741 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 3742 | // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 503:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))) => (UMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 3743 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv4i16_indexed, |
| 3744 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3745 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 3746 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 3747 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 3748 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 3749 | GIR_EraseFromParent, /*InsnID*/0, |
| 3750 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3751 | // GIR_Coverage, 1754, |
| 3752 | GIR_Done, |
| 3753 | // Label 217: @6571 |
| 3754 | GIM_Try, /*On fail goto*//*Label 218*/ 6648, // Rule ID 7705 // |
| 3755 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3756 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3757 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 3758 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3759 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 3760 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, |
| 3761 | GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, |
| 3762 | GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 3763 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3764 | GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16, |
| 3765 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 3766 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 3767 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 3768 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3769 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 3770 | // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 426:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd) => (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 3771 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv4i16_v4i32, |
| 3772 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3773 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 3774 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn |
| 3775 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm |
| 3776 | GIR_EraseFromParent, /*InsnID*/0, |
| 3777 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3778 | // GIR_Coverage, 7705, |
| 3779 | GIR_Done, |
| 3780 | // Label 218: @6648 |
| 3781 | GIM_Try, /*On fail goto*//*Label 219*/ 6725, // Rule ID 7729 // |
| 3782 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3783 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3784 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 3785 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3786 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 3787 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, |
| 3788 | GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, |
| 3789 | GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 3790 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3791 | GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16, |
| 3792 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 3793 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 3794 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 3795 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3796 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 3797 | // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 489:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd) => (UABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 3798 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv4i16_v4i32, |
| 3799 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3800 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 3801 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn |
| 3802 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm |
| 3803 | GIR_EraseFromParent, /*InsnID*/0, |
| 3804 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3805 | // GIR_Coverage, 7729, |
| 3806 | GIR_Done, |
| 3807 | // Label 219: @6725 |
| 3808 | GIM_Try, /*On fail goto*//*Label 220*/ 6802, // Rule ID 1410 // |
| 3809 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3810 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 3811 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3812 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 3813 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3814 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 3815 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, |
| 3816 | GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, |
| 3817 | GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 3818 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3819 | GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16, |
| 3820 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 3821 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 3822 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3823 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 3824 | // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 426:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))) => (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 3825 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv4i16_v4i32, |
| 3826 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3827 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 3828 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn |
| 3829 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm |
| 3830 | GIR_EraseFromParent, /*InsnID*/0, |
| 3831 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3832 | // GIR_Coverage, 1410, |
| 3833 | GIR_Done, |
| 3834 | // Label 220: @6802 |
| 3835 | GIM_Try, /*On fail goto*//*Label 221*/ 6879, // Rule ID 1488 // |
| 3836 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3837 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 3838 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3839 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 3840 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3841 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 3842 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, |
| 3843 | GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, |
| 3844 | GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 3845 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3846 | GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16, |
| 3847 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 3848 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 3849 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3850 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 3851 | // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 489:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))) => (UABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 3852 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv4i16_v4i32, |
| 3853 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3854 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 3855 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn |
| 3856 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm |
| 3857 | GIR_EraseFromParent, /*InsnID*/0, |
| 3858 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3859 | // GIR_Coverage, 1488, |
| 3860 | GIR_Done, |
| 3861 | // Label 221: @6879 |
| 3862 | GIM_Try, /*On fail goto*//*Label 222*/ 6943, // Rule ID 7644 // |
| 3863 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3864 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3865 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 3866 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 3867 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 3868 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 3869 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, |
| 3870 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 3871 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 3872 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 3873 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3874 | // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 426:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd) => (SABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 3875 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i32, |
| 3876 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3877 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 3878 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 3879 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 3880 | GIR_EraseFromParent, /*InsnID*/0, |
| 3881 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3882 | // GIR_Coverage, 7644, |
| 3883 | GIR_Done, |
| 3884 | // Label 222: @6943 |
| 3885 | GIM_Try, /*On fail goto*//*Label 223*/ 7007, // Rule ID 7656 // |
| 3886 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3887 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3888 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 3889 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 3890 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 3891 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 3892 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, |
| 3893 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 3894 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 3895 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 3896 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3897 | // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 489:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd) => (UABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 3898 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i32, |
| 3899 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3900 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 3901 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 3902 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 3903 | GIR_EraseFromParent, /*InsnID*/0, |
| 3904 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3905 | // GIR_Coverage, 7656, |
| 3906 | GIR_Done, |
| 3907 | // Label 223: @7007 |
| 3908 | GIM_Try, /*On fail goto*//*Label 224*/ 7071, // Rule ID 7720 // |
| 3909 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3910 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3911 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 3912 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 3913 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, |
| 3914 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3915 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 3916 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 3917 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 3918 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 3919 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3920 | // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 444:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rd) => (SMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 3921 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv4i16_v4i32, |
| 3922 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3923 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 3924 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 3925 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 3926 | GIR_EraseFromParent, /*InsnID*/0, |
| 3927 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3928 | // GIR_Coverage, 7720, |
| 3929 | GIR_Done, |
| 3930 | // Label 224: @7071 |
| 3931 | GIM_Try, /*On fail goto*//*Label 225*/ 7135, // Rule ID 7750 // |
| 3932 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3933 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3934 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 3935 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 3936 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, |
| 3937 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3938 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 3939 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 3940 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 3941 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 3942 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3943 | // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 503:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rd) => (UMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 3944 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv4i16_v4i32, |
| 3945 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3946 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 3947 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 3948 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 3949 | GIR_EraseFromParent, /*InsnID*/0, |
| 3950 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3951 | // GIR_Coverage, 7750, |
| 3952 | GIR_Done, |
| 3953 | // Label 225: @7135 |
| 3954 | GIM_Try, /*On fail goto*//*Label 226*/ 7187, // Rule ID 7612 // |
| 3955 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3956 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3957 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 3958 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 3959 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, |
| 3960 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 3961 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 3962 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 3963 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3964 | // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 427:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd) => (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn) |
| 3965 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i16_v4i32, |
| 3966 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3967 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 3968 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 3969 | GIR_EraseFromParent, /*InsnID*/0, |
| 3970 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3971 | // GIR_Coverage, 7612, |
| 3972 | GIR_Done, |
| 3973 | // Label 226: @7187 |
| 3974 | GIM_Try, /*On fail goto*//*Label 227*/ 7239, // Rule ID 7618 // |
| 3975 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3976 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3977 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 3978 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 3979 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, |
| 3980 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 3981 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 3982 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 3983 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 3984 | // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 490:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd) => (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn) |
| 3985 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i16_v4i32, |
| 3986 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3987 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 3988 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 3989 | GIR_EraseFromParent, /*InsnID*/0, |
| 3990 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3991 | // GIR_Coverage, 7618, |
| 3992 | GIR_Done, |
| 3993 | // Label 227: @7239 |
| 3994 | GIM_Try, /*On fail goto*//*Label 228*/ 7303, // Rule ID 1085 // |
| 3995 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 3996 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 3997 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3998 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 3999 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 4000 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 4001 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4002 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, |
| 4003 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 4004 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 4005 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4006 | // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 426:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (SABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 4007 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv4i32, |
| 4008 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4009 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 4010 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 4011 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 4012 | GIR_EraseFromParent, /*InsnID*/0, |
| 4013 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4014 | // GIR_Coverage, 1085, |
| 4015 | GIR_Done, |
| 4016 | // Label 228: @7303 |
| 4017 | GIM_Try, /*On fail goto*//*Label 229*/ 7367, // Rule ID 1208 // |
| 4018 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4019 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 4020 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4021 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 4022 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 4023 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 4024 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4025 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, |
| 4026 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 4027 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 4028 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4029 | // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 489:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (UABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 4030 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv4i32, |
| 4031 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4032 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 4033 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 4034 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 4035 | GIR_EraseFromParent, /*InsnID*/0, |
| 4036 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4037 | // GIR_Coverage, 1208, |
| 4038 | GIR_Done, |
| 4039 | // Label 229: @7367 |
| 4040 | GIM_Try, /*On fail goto*//*Label 230*/ 7431, // Rule ID 1443 // |
| 4041 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4042 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 4043 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4044 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 4045 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 4046 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, |
| 4047 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 4048 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 4049 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 4050 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 4051 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4052 | // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 444:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 4053 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv4i16_v4i32, |
| 4054 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4055 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 4056 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 4057 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 4058 | GIR_EraseFromParent, /*InsnID*/0, |
| 4059 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4060 | // GIR_Coverage, 1443, |
| 4061 | GIR_Done, |
| 4062 | // Label 230: @7431 |
| 4063 | GIM_Try, /*On fail goto*//*Label 231*/ 7495, // Rule ID 1533 // |
| 4064 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4065 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 4066 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4067 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 4068 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 4069 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, |
| 4070 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 4071 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 4072 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 4073 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 4074 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4075 | // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 503:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (UMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 4076 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv4i16_v4i32, |
| 4077 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4078 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 4079 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 4080 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 4081 | GIR_EraseFromParent, /*InsnID*/0, |
| 4082 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4083 | // GIR_Coverage, 1533, |
| 4084 | GIR_Done, |
| 4085 | // Label 231: @7495 |
| 4086 | GIM_Try, /*On fail goto*//*Label 232*/ 7547, // Rule ID 815 // |
| 4087 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4088 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 4089 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4090 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 4091 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 4092 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, |
| 4093 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 4094 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 4095 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4096 | // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 427:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn) |
| 4097 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv8i16_v4i32, |
| 4098 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4099 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 4100 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 4101 | GIR_EraseFromParent, /*InsnID*/0, |
| 4102 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4103 | // GIR_Coverage, 815, |
| 4104 | GIR_Done, |
| 4105 | // Label 232: @7547 |
| 4106 | GIM_Try, /*On fail goto*//*Label 233*/ 7599, // Rule ID 859 // |
| 4107 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4108 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 4109 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4110 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 4111 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 4112 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, |
| 4113 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 4114 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 4115 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4116 | // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 490:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn) |
| 4117 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv8i16_v4i32, |
| 4118 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4119 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 4120 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 4121 | GIR_EraseFromParent, /*InsnID*/0, |
| 4122 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4123 | // GIR_Coverage, 859, |
| 4124 | GIR_Done, |
| 4125 | // Label 233: @7599 |
| 4126 | GIM_Try, /*On fail goto*//*Label 234*/ 7659, // Rule ID 7798 // |
| 4127 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4128 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4129 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, |
| 4130 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4131 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 4132 | // MIs[1] imm |
| 4133 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 4134 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 4135 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, |
| 4136 | // MIs[2] Operand 1 |
| 4137 | // No operand predicates |
| 4138 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 4139 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4140 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 4141 | // (add:{ *:[v4i32] } (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V128:{ *:[v4i32] }:$Rd) => (SSRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4142 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv4i32_shift, |
| 4143 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4144 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 4145 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 4146 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 4147 | GIR_EraseFromParent, /*InsnID*/0, |
| 4148 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4149 | // GIR_Coverage, 7798, |
| 4150 | GIR_Done, |
| 4151 | // Label 234: @7659 |
| 4152 | GIM_Try, /*On fail goto*//*Label 235*/ 7719, // Rule ID 7812 // |
| 4153 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4154 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4155 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 4156 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4157 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 4158 | // MIs[1] imm |
| 4159 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 4160 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 4161 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, |
| 4162 | // MIs[2] Operand 1 |
| 4163 | // No operand predicates |
| 4164 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 4165 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4166 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 4167 | // (add:{ *:[v4i32] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V128:{ *:[v4i32] }:$Rd) => (USRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4168 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv4i32_shift, |
| 4169 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4170 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 4171 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 4172 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 4173 | GIR_EraseFromParent, /*InsnID*/0, |
| 4174 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4175 | // GIR_Coverage, 7812, |
| 4176 | GIR_Done, |
| 4177 | // Label 235: @7719 |
| 4178 | GIM_Try, /*On fail goto*//*Label 236*/ 7779, // Rule ID 1887 // |
| 4179 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4180 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 4181 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4182 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, |
| 4183 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4184 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 4185 | // MIs[1] imm |
| 4186 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 4187 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 4188 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, |
| 4189 | // MIs[2] Operand 1 |
| 4190 | // No operand predicates |
| 4191 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4192 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 4193 | // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)) => (SSRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4194 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv4i32_shift, |
| 4195 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4196 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 4197 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 4198 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 4199 | GIR_EraseFromParent, /*InsnID*/0, |
| 4200 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4201 | // GIR_Coverage, 1887, |
| 4202 | GIR_Done, |
| 4203 | // Label 236: @7779 |
| 4204 | GIM_Try, /*On fail goto*//*Label 237*/ 7839, // Rule ID 1939 // |
| 4205 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4206 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 4207 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4208 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 4209 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4210 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 4211 | // MIs[1] imm |
| 4212 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 4213 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 4214 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, |
| 4215 | // MIs[2] Operand 1 |
| 4216 | // No operand predicates |
| 4217 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4218 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 4219 | // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)) => (USRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4220 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv4i32_shift, |
| 4221 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4222 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 4223 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 4224 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 4225 | GIR_EraseFromParent, /*InsnID*/0, |
| 4226 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4227 | // GIR_Coverage, 1939, |
| 4228 | GIR_Done, |
| 4229 | // Label 237: @7839 |
| 4230 | GIM_Try, /*On fail goto*//*Label 238*/ 7897, // Rule ID 1506 // |
| 4231 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4232 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4233 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, |
| 4234 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4235 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 4236 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4237 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT, |
| 4238 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4239 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 4240 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4241 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 4242 | // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 4243 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv4i16_v4i32, |
| 4244 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 4245 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 4246 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 4247 | GIR_EraseFromParent, /*InsnID*/0, |
| 4248 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4249 | // GIR_Coverage, 1506, |
| 4250 | GIR_Done, |
| 4251 | // Label 238: @7897 |
| 4252 | GIM_Try, /*On fail goto*//*Label 239*/ 7955, // Rule ID 1505 // |
| 4253 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4254 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4255 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, |
| 4256 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4257 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 4258 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4259 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, |
| 4260 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4261 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 4262 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4263 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 4264 | // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 4265 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv4i16_v4i32, |
| 4266 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 4267 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 4268 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 4269 | GIR_EraseFromParent, /*InsnID*/0, |
| 4270 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4271 | // GIR_Coverage, 1505, |
| 4272 | GIR_Done, |
| 4273 | // Label 239: @7955 |
| 4274 | GIM_Try, /*On fail goto*//*Label 240*/ 8013, // Rule ID 1431 // |
| 4275 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4276 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4277 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, |
| 4278 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4279 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 4280 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4281 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, |
| 4282 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4283 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 4284 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4285 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 4286 | // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (SADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 4287 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv4i16_v4i32, |
| 4288 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 4289 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 4290 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 4291 | GIR_EraseFromParent, /*InsnID*/0, |
| 4292 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4293 | // GIR_Coverage, 1431, |
| 4294 | GIR_Done, |
| 4295 | // Label 240: @8013 |
| 4296 | GIM_Try, /*On fail goto*//*Label 241*/ 8071, // Rule ID 1504 // |
| 4297 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4298 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4299 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 4300 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4301 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 4302 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4303 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT, |
| 4304 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4305 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 4306 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4307 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 4308 | // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 4309 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv4i16_v4i32, |
| 4310 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 4311 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 4312 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 4313 | GIR_EraseFromParent, /*InsnID*/0, |
| 4314 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4315 | // GIR_Coverage, 1504, |
| 4316 | GIR_Done, |
| 4317 | // Label 241: @8071 |
| 4318 | GIM_Try, /*On fail goto*//*Label 242*/ 8129, // Rule ID 1503 // |
| 4319 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4320 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4321 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 4322 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4323 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 4324 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4325 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, |
| 4326 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4327 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 4328 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4329 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 4330 | // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 4331 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv4i16_v4i32, |
| 4332 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 4333 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 4334 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 4335 | GIR_EraseFromParent, /*InsnID*/0, |
| 4336 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4337 | // GIR_Coverage, 1503, |
| 4338 | GIR_Done, |
| 4339 | // Label 242: @8129 |
| 4340 | GIM_Try, /*On fail goto*//*Label 243*/ 8174, // Rule ID 7741 // |
| 4341 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4342 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4343 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, |
| 4344 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4345 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 4346 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 4347 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4348 | // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn) => (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 4349 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv4i16_v4i32, |
| 4350 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 4351 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 4352 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 4353 | GIR_EraseFromParent, /*InsnID*/0, |
| 4354 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4355 | // GIR_Coverage, 7741, |
| 4356 | GIR_Done, |
| 4357 | // Label 243: @8174 |
| 4358 | GIM_Try, /*On fail goto*//*Label 244*/ 8219, // Rule ID 7714 // |
| 4359 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4360 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4361 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, |
| 4362 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4363 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 4364 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 4365 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4366 | // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn) => (SADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 4367 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv4i16_v4i32, |
| 4368 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 4369 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 4370 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 4371 | GIR_EraseFromParent, /*InsnID*/0, |
| 4372 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4373 | // GIR_Coverage, 7714, |
| 4374 | GIR_Done, |
| 4375 | // Label 244: @8219 |
| 4376 | GIM_Try, /*On fail goto*//*Label 245*/ 8264, // Rule ID 7740 // |
| 4377 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4378 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4379 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 4380 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4381 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 4382 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 4383 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4384 | // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn) => (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 4385 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv4i16_v4i32, |
| 4386 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 4387 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 4388 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 4389 | GIR_EraseFromParent, /*InsnID*/0, |
| 4390 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4391 | // GIR_Coverage, 7740, |
| 4392 | GIR_Done, |
| 4393 | // Label 245: @8264 |
| 4394 | GIM_Try, /*On fail goto*//*Label 246*/ 8309, // Rule ID 1524 // |
| 4395 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4396 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 4397 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4398 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, |
| 4399 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4400 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 4401 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4402 | // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 4403 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv4i16_v4i32, |
| 4404 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 4405 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 4406 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 4407 | GIR_EraseFromParent, /*InsnID*/0, |
| 4408 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4409 | // GIR_Coverage, 1524, |
| 4410 | GIR_Done, |
| 4411 | // Label 246: @8309 |
| 4412 | GIM_Try, /*On fail goto*//*Label 247*/ 8354, // Rule ID 1437 // |
| 4413 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4414 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 4415 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4416 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, |
| 4417 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4418 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 4419 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4420 | // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (SADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 4421 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv4i16_v4i32, |
| 4422 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 4423 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 4424 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 4425 | GIR_EraseFromParent, /*InsnID*/0, |
| 4426 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4427 | // GIR_Coverage, 1437, |
| 4428 | GIR_Done, |
| 4429 | // Label 247: @8354 |
| 4430 | GIM_Try, /*On fail goto*//*Label 248*/ 8399, // Rule ID 1523 // |
| 4431 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4432 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 4433 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4434 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 4435 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4436 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 4437 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4438 | // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 4439 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv4i16_v4i32, |
| 4440 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 4441 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 4442 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 4443 | GIR_EraseFromParent, /*InsnID*/0, |
| 4444 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4445 | // GIR_Coverage, 1523, |
| 4446 | GIR_Done, |
| 4447 | // Label 248: @8399 |
| 4448 | GIM_Try, /*On fail goto*//*Label 249*/ 8418, // Rule ID 895 // |
| 4449 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4450 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 4451 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 4452 | // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (ADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 4453 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv4i32, |
| 4454 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4455 | // GIR_Coverage, 895, |
| 4456 | GIR_Done, |
| 4457 | // Label 249: @8418 |
| 4458 | GIM_Reject, |
| 4459 | // Label 213: @8419 |
| 4460 | GIM_Reject, |
| 4461 | // Label 105: @8420 |
| 4462 | GIM_Try, /*On fail goto*//*Label 250*/ 8950, |
| 4463 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4464 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4465 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 4466 | GIM_Try, /*On fail goto*//*Label 251*/ 8498, // Rule ID 7634 // |
| 4467 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4468 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4469 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 4470 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 4471 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 4472 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4473 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, |
| 4474 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 4475 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 4476 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 4477 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4478 | // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 426:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd) => (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 4479 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i8, |
| 4480 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4481 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 4482 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 4483 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 4484 | GIR_EraseFromParent, /*InsnID*/0, |
| 4485 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4486 | // GIR_Coverage, 7634, |
| 4487 | GIR_Done, |
| 4488 | // Label 251: @8498 |
| 4489 | GIM_Try, /*On fail goto*//*Label 252*/ 8562, // Rule ID 7646 // |
| 4490 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4491 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4492 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 4493 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 4494 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 4495 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4496 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, |
| 4497 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 4498 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 4499 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 4500 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4501 | // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 489:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd) => (UABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 4502 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i8, |
| 4503 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4504 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 4505 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 4506 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 4507 | GIR_EraseFromParent, /*InsnID*/0, |
| 4508 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4509 | // GIR_Coverage, 7646, |
| 4510 | GIR_Done, |
| 4511 | // Label 252: @8562 |
| 4512 | GIM_Try, /*On fail goto*//*Label 253*/ 8626, // Rule ID 1075 // |
| 4513 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4514 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 4515 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4516 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 4517 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 4518 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 4519 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4520 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, |
| 4521 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 4522 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 4523 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4524 | // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 426:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 4525 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i8, |
| 4526 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4527 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 4528 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 4529 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 4530 | GIR_EraseFromParent, /*InsnID*/0, |
| 4531 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4532 | // GIR_Coverage, 1075, |
| 4533 | GIR_Done, |
| 4534 | // Label 253: @8626 |
| 4535 | GIM_Try, /*On fail goto*//*Label 254*/ 8690, // Rule ID 1198 // |
| 4536 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4537 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 4538 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4539 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 4540 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 4541 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 4542 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4543 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, |
| 4544 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 4545 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 4546 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4547 | // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 489:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (UABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 4548 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i8, |
| 4549 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4550 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 4551 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 4552 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 4553 | GIR_EraseFromParent, /*InsnID*/0, |
| 4554 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4555 | // GIR_Coverage, 1198, |
| 4556 | GIR_Done, |
| 4557 | // Label 254: @8690 |
| 4558 | GIM_Try, /*On fail goto*//*Label 255*/ 8750, // Rule ID 7793 // |
| 4559 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4560 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4561 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, |
| 4562 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4563 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 4564 | // MIs[1] imm |
| 4565 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 4566 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 4567 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, |
| 4568 | // MIs[2] Operand 1 |
| 4569 | // No operand predicates |
| 4570 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 4571 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4572 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 4573 | // (add:{ *:[v8i8] } (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V64:{ *:[v8i8] }:$Rd) => (SSRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4574 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv8i8_shift, |
| 4575 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4576 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 4577 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 4578 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 4579 | GIR_EraseFromParent, /*InsnID*/0, |
| 4580 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4581 | // GIR_Coverage, 7793, |
| 4582 | GIR_Done, |
| 4583 | // Label 255: @8750 |
| 4584 | GIM_Try, /*On fail goto*//*Label 256*/ 8810, // Rule ID 7807 // |
| 4585 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4586 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4587 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 4588 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4589 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 4590 | // MIs[1] imm |
| 4591 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 4592 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 4593 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, |
| 4594 | // MIs[2] Operand 1 |
| 4595 | // No operand predicates |
| 4596 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 4597 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4598 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 4599 | // (add:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V64:{ *:[v8i8] }:$Rd) => (USRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4600 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv8i8_shift, |
| 4601 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4602 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 4603 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 4604 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 4605 | GIR_EraseFromParent, /*InsnID*/0, |
| 4606 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4607 | // GIR_Coverage, 7807, |
| 4608 | GIR_Done, |
| 4609 | // Label 256: @8810 |
| 4610 | GIM_Try, /*On fail goto*//*Label 257*/ 8870, // Rule ID 1882 // |
| 4611 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4612 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 4613 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4614 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, |
| 4615 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4616 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 4617 | // MIs[1] imm |
| 4618 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 4619 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 4620 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, |
| 4621 | // MIs[2] Operand 1 |
| 4622 | // No operand predicates |
| 4623 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4624 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 4625 | // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm)) => (SSRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4626 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv8i8_shift, |
| 4627 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4628 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 4629 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 4630 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 4631 | GIR_EraseFromParent, /*InsnID*/0, |
| 4632 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4633 | // GIR_Coverage, 1882, |
| 4634 | GIR_Done, |
| 4635 | // Label 257: @8870 |
| 4636 | GIM_Try, /*On fail goto*//*Label 258*/ 8930, // Rule ID 1934 // |
| 4637 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4638 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 4639 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4640 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 4641 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4642 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 4643 | // MIs[1] imm |
| 4644 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 4645 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 4646 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, |
| 4647 | // MIs[2] Operand 1 |
| 4648 | // No operand predicates |
| 4649 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4650 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 4651 | // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (AArch64vlshr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm)) => (USRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4652 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv8i8_shift, |
| 4653 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4654 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 4655 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 4656 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 4657 | GIR_EraseFromParent, /*InsnID*/0, |
| 4658 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4659 | // GIR_Coverage, 1934, |
| 4660 | GIR_Done, |
| 4661 | // Label 258: @8930 |
| 4662 | GIM_Try, /*On fail goto*//*Label 259*/ 8949, // Rule ID 890 // |
| 4663 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4664 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 4665 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 4666 | // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (ADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 4667 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv8i8, |
| 4668 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4669 | // GIR_Coverage, 890, |
| 4670 | GIR_Done, |
| 4671 | // Label 259: @8949 |
| 4672 | GIM_Reject, |
| 4673 | // Label 250: @8950 |
| 4674 | GIM_Reject, |
| 4675 | // Label 106: @8951 |
| 4676 | GIM_Try, /*On fail goto*//*Label 260*/ 10813, |
| 4677 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 4678 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 4679 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 4680 | GIM_Try, /*On fail goto*//*Label 261*/ 9042, // Rule ID 7701 // |
| 4681 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4682 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4683 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 4684 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4685 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4686 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, |
| 4687 | GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, |
| 4688 | GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 4689 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4690 | GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8, |
| 4691 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 4692 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 4693 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 4694 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4695 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 4696 | // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 426:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd) => (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 4697 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv8i8_v8i16, |
| 4698 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4699 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 4700 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn |
| 4701 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm |
| 4702 | GIR_EraseFromParent, /*InsnID*/0, |
| 4703 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4704 | // GIR_Coverage, 7701, |
| 4705 | GIR_Done, |
| 4706 | // Label 261: @9042 |
| 4707 | GIM_Try, /*On fail goto*//*Label 262*/ 9119, // Rule ID 7725 // |
| 4708 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4709 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4710 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 4711 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4712 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4713 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, |
| 4714 | GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, |
| 4715 | GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 4716 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4717 | GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8, |
| 4718 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 4719 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 4720 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 4721 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4722 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 4723 | // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 489:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd) => (UABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 4724 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv8i8_v8i16, |
| 4725 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4726 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 4727 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn |
| 4728 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm |
| 4729 | GIR_EraseFromParent, /*InsnID*/0, |
| 4730 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4731 | // GIR_Coverage, 7725, |
| 4732 | GIR_Done, |
| 4733 | // Label 262: @9119 |
| 4734 | GIM_Try, /*On fail goto*//*Label 263*/ 9196, // Rule ID 1406 // |
| 4735 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4736 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 4737 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4738 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 4739 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4740 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4741 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, |
| 4742 | GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, |
| 4743 | GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 4744 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4745 | GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8, |
| 4746 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 4747 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 4748 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4749 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 4750 | // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 426:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))) => (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 4751 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABALv8i8_v8i16, |
| 4752 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4753 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 4754 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn |
| 4755 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm |
| 4756 | GIR_EraseFromParent, /*InsnID*/0, |
| 4757 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4758 | // GIR_Coverage, 1406, |
| 4759 | GIR_Done, |
| 4760 | // Label 263: @9196 |
| 4761 | GIM_Try, /*On fail goto*//*Label 264*/ 9273, // Rule ID 1484 // |
| 4762 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4763 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 4764 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4765 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 4766 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4767 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4768 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, |
| 4769 | GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, |
| 4770 | GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 4771 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4772 | GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8, |
| 4773 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 4774 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 4775 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4776 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 4777 | // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 489:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))) => (UABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 4778 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABALv8i8_v8i16, |
| 4779 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4780 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 4781 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn |
| 4782 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm |
| 4783 | GIR_EraseFromParent, /*InsnID*/0, |
| 4784 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4785 | // GIR_Coverage, 1484, |
| 4786 | GIR_Done, |
| 4787 | // Label 264: @9273 |
| 4788 | GIM_Try, /*On fail goto*//*Label 265*/ 9337, // Rule ID 7640 // |
| 4789 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4790 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4791 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 4792 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 4793 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 4794 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 4795 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, |
| 4796 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 4797 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 4798 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 4799 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4800 | // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 426:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd) => (SABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 4801 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i16, |
| 4802 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4803 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 4804 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 4805 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 4806 | GIR_EraseFromParent, /*InsnID*/0, |
| 4807 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4808 | // GIR_Coverage, 7640, |
| 4809 | GIR_Done, |
| 4810 | // Label 265: @9337 |
| 4811 | GIM_Try, /*On fail goto*//*Label 266*/ 9401, // Rule ID 7652 // |
| 4812 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4813 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4814 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 4815 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 4816 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 4817 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 4818 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, |
| 4819 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 4820 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 4821 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 4822 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4823 | // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 489:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd) => (UABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 4824 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i16, |
| 4825 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4826 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 4827 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 4828 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 4829 | GIR_EraseFromParent, /*InsnID*/0, |
| 4830 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4831 | // GIR_Coverage, 7652, |
| 4832 | GIR_Done, |
| 4833 | // Label 266: @9401 |
| 4834 | GIM_Try, /*On fail goto*//*Label 267*/ 9465, // Rule ID 7718 // |
| 4835 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4836 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4837 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 4838 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 4839 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, |
| 4840 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4841 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, |
| 4842 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 4843 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 4844 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 4845 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4846 | // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 444:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rd) => (SMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 4847 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv8i8_v8i16, |
| 4848 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4849 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 4850 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 4851 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 4852 | GIR_EraseFromParent, /*InsnID*/0, |
| 4853 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4854 | // GIR_Coverage, 7718, |
| 4855 | GIR_Done, |
| 4856 | // Label 267: @9465 |
| 4857 | GIM_Try, /*On fail goto*//*Label 268*/ 9529, // Rule ID 7748 // |
| 4858 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4859 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4860 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 4861 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 4862 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, |
| 4863 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4864 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, |
| 4865 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 4866 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 4867 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 4868 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4869 | // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 503:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rd) => (UMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 4870 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv8i8_v8i16, |
| 4871 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4872 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 4873 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 4874 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 4875 | GIR_EraseFromParent, /*InsnID*/0, |
| 4876 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4877 | // GIR_Coverage, 7748, |
| 4878 | GIR_Done, |
| 4879 | // Label 268: @9529 |
| 4880 | GIM_Try, /*On fail goto*//*Label 269*/ 9581, // Rule ID 7610 // |
| 4881 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4882 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4883 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 4884 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 4885 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, |
| 4886 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 4887 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 4888 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 4889 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4890 | // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 427:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd) => (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn) |
| 4891 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv16i8_v8i16, |
| 4892 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4893 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 4894 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 4895 | GIR_EraseFromParent, /*InsnID*/0, |
| 4896 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4897 | // GIR_Coverage, 7610, |
| 4898 | GIR_Done, |
| 4899 | // Label 269: @9581 |
| 4900 | GIM_Try, /*On fail goto*//*Label 270*/ 9633, // Rule ID 7616 // |
| 4901 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4902 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4903 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 4904 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 4905 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, |
| 4906 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 4907 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 4908 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 4909 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4910 | // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 490:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd) => (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn) |
| 4911 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv16i8_v8i16, |
| 4912 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4913 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 4914 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 4915 | GIR_EraseFromParent, /*InsnID*/0, |
| 4916 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4917 | // GIR_Coverage, 7616, |
| 4918 | GIR_Done, |
| 4919 | // Label 270: @9633 |
| 4920 | GIM_Try, /*On fail goto*//*Label 271*/ 9697, // Rule ID 1081 // |
| 4921 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4922 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 4923 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4924 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 4925 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 4926 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 4927 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 4928 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, |
| 4929 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 4930 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 4931 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4932 | // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 426:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (SABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 4933 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv8i16, |
| 4934 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4935 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 4936 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 4937 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 4938 | GIR_EraseFromParent, /*InsnID*/0, |
| 4939 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4940 | // GIR_Coverage, 1081, |
| 4941 | GIR_Done, |
| 4942 | // Label 271: @9697 |
| 4943 | GIM_Try, /*On fail goto*//*Label 272*/ 9761, // Rule ID 1204 // |
| 4944 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4945 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 4946 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4947 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 4948 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 4949 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 4950 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 4951 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, |
| 4952 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 4953 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 4954 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4955 | // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 489:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (UABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 4956 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv8i16, |
| 4957 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4958 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 4959 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 4960 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 4961 | GIR_EraseFromParent, /*InsnID*/0, |
| 4962 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4963 | // GIR_Coverage, 1204, |
| 4964 | GIR_Done, |
| 4965 | // Label 272: @9761 |
| 4966 | GIM_Try, /*On fail goto*//*Label 273*/ 9825, // Rule ID 1441 // |
| 4967 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4968 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 4969 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4970 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 4971 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 4972 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, |
| 4973 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4974 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, |
| 4975 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 4976 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 4977 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4978 | // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 444:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (SMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 4979 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLALv8i8_v8i16, |
| 4980 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4981 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 4982 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 4983 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 4984 | GIR_EraseFromParent, /*InsnID*/0, |
| 4985 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4986 | // GIR_Coverage, 1441, |
| 4987 | GIR_Done, |
| 4988 | // Label 273: @9825 |
| 4989 | GIM_Try, /*On fail goto*//*Label 274*/ 9889, // Rule ID 1531 // |
| 4990 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 4991 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 4992 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4993 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 4994 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 4995 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, |
| 4996 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4997 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, |
| 4998 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 4999 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 5000 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5001 | // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 503:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (UMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 5002 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLALv8i8_v8i16, |
| 5003 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 5004 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 5005 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 5006 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 5007 | GIR_EraseFromParent, /*InsnID*/0, |
| 5008 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5009 | // GIR_Coverage, 1531, |
| 5010 | GIR_Done, |
| 5011 | // Label 274: @9889 |
| 5012 | GIM_Try, /*On fail goto*//*Label 275*/ 9941, // Rule ID 813 // |
| 5013 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5014 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 5015 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5016 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 5017 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 5018 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_saddlp, |
| 5019 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5020 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 5021 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5022 | // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 427:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)) => (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn) |
| 5023 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADALPv16i8_v8i16, |
| 5024 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 5025 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 5026 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 5027 | GIR_EraseFromParent, /*InsnID*/0, |
| 5028 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5029 | // GIR_Coverage, 813, |
| 5030 | GIR_Done, |
| 5031 | // Label 275: @9941 |
| 5032 | GIM_Try, /*On fail goto*//*Label 276*/ 9993, // Rule ID 857 // |
| 5033 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5034 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 5035 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5036 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 5037 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 5038 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, |
| 5039 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5040 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 5041 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5042 | // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 490:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)) => (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn) |
| 5043 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADALPv16i8_v8i16, |
| 5044 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 5045 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 5046 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 5047 | GIR_EraseFromParent, /*InsnID*/0, |
| 5048 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5049 | // GIR_Coverage, 857, |
| 5050 | GIR_Done, |
| 5051 | // Label 276: @9993 |
| 5052 | GIM_Try, /*On fail goto*//*Label 277*/ 10053, // Rule ID 7796 // |
| 5053 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5054 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5055 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, |
| 5056 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 5057 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 5058 | // MIs[1] imm |
| 5059 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 5060 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 5061 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, |
| 5062 | // MIs[2] Operand 1 |
| 5063 | // No operand predicates |
| 5064 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 5065 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5066 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 5067 | // (add:{ *:[v8i16] } (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V128:{ *:[v8i16] }:$Rd) => (SSRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 5068 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv8i16_shift, |
| 5069 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 5070 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 5071 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5072 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 5073 | GIR_EraseFromParent, /*InsnID*/0, |
| 5074 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5075 | // GIR_Coverage, 7796, |
| 5076 | GIR_Done, |
| 5077 | // Label 277: @10053 |
| 5078 | GIM_Try, /*On fail goto*//*Label 278*/ 10113, // Rule ID 7810 // |
| 5079 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5080 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5081 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 5082 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 5083 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 5084 | // MIs[1] imm |
| 5085 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 5086 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 5087 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, |
| 5088 | // MIs[2] Operand 1 |
| 5089 | // No operand predicates |
| 5090 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 5091 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5092 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 5093 | // (add:{ *:[v8i16] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V128:{ *:[v8i16] }:$Rd) => (USRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 5094 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv8i16_shift, |
| 5095 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 5096 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 5097 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5098 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 5099 | GIR_EraseFromParent, /*InsnID*/0, |
| 5100 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5101 | // GIR_Coverage, 7810, |
| 5102 | GIR_Done, |
| 5103 | // Label 278: @10113 |
| 5104 | GIM_Try, /*On fail goto*//*Label 279*/ 10173, // Rule ID 1885 // |
| 5105 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5106 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 5107 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5108 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, |
| 5109 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 5110 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 5111 | // MIs[1] imm |
| 5112 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 5113 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 5114 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, |
| 5115 | // MIs[2] Operand 1 |
| 5116 | // No operand predicates |
| 5117 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5118 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 5119 | // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)) => (SSRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 5120 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv8i16_shift, |
| 5121 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 5122 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 5123 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5124 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 5125 | GIR_EraseFromParent, /*InsnID*/0, |
| 5126 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5127 | // GIR_Coverage, 1885, |
| 5128 | GIR_Done, |
| 5129 | // Label 279: @10173 |
| 5130 | GIM_Try, /*On fail goto*//*Label 280*/ 10233, // Rule ID 1937 // |
| 5131 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5132 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 5133 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5134 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 5135 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 5136 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 5137 | // MIs[1] imm |
| 5138 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 5139 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 5140 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, |
| 5141 | // MIs[2] Operand 1 |
| 5142 | // No operand predicates |
| 5143 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5144 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 5145 | // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)) => (USRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 5146 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv8i16_shift, |
| 5147 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 5148 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 5149 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5150 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 5151 | GIR_EraseFromParent, /*InsnID*/0, |
| 5152 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5153 | // GIR_Coverage, 1937, |
| 5154 | GIR_Done, |
| 5155 | // Label 280: @10233 |
| 5156 | GIM_Try, /*On fail goto*//*Label 281*/ 10291, // Rule ID 1498 // |
| 5157 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5158 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5159 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, |
| 5160 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5161 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 5162 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5163 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT, |
| 5164 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5165 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 5166 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5167 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 5168 | // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 5169 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv8i8_v8i16, |
| 5170 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 5171 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5172 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5173 | GIR_EraseFromParent, /*InsnID*/0, |
| 5174 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5175 | // GIR_Coverage, 1498, |
| 5176 | GIR_Done, |
| 5177 | // Label 281: @10291 |
| 5178 | GIM_Try, /*On fail goto*//*Label 282*/ 10349, // Rule ID 1497 // |
| 5179 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5180 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5181 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, |
| 5182 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5183 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 5184 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5185 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, |
| 5186 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5187 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 5188 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5189 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 5190 | // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 5191 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv8i8_v8i16, |
| 5192 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 5193 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5194 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5195 | GIR_EraseFromParent, /*InsnID*/0, |
| 5196 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5197 | // GIR_Coverage, 1497, |
| 5198 | GIR_Done, |
| 5199 | // Label 282: @10349 |
| 5200 | GIM_Try, /*On fail goto*//*Label 283*/ 10407, // Rule ID 1429 // |
| 5201 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5202 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5203 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, |
| 5204 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5205 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 5206 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5207 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, |
| 5208 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5209 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 5210 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5211 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 5212 | // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (SADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 5213 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLv8i8_v8i16, |
| 5214 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 5215 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5216 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5217 | GIR_EraseFromParent, /*InsnID*/0, |
| 5218 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5219 | // GIR_Coverage, 1429, |
| 5220 | GIR_Done, |
| 5221 | // Label 283: @10407 |
| 5222 | GIM_Try, /*On fail goto*//*Label 284*/ 10465, // Rule ID 1496 // |
| 5223 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5224 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5225 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 5226 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5227 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 5228 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5229 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT, |
| 5230 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5231 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 5232 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5233 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 5234 | // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 5235 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv8i8_v8i16, |
| 5236 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 5237 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5238 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5239 | GIR_EraseFromParent, /*InsnID*/0, |
| 5240 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5241 | // GIR_Coverage, 1496, |
| 5242 | GIR_Done, |
| 5243 | // Label 284: @10465 |
| 5244 | GIM_Try, /*On fail goto*//*Label 285*/ 10523, // Rule ID 1495 // |
| 5245 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5246 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5247 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 5248 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5249 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 5250 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5251 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, |
| 5252 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5253 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 5254 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5255 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 5256 | // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 5257 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLv8i8_v8i16, |
| 5258 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 5259 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5260 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5261 | GIR_EraseFromParent, /*InsnID*/0, |
| 5262 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5263 | // GIR_Coverage, 1495, |
| 5264 | GIR_Done, |
| 5265 | // Label 285: @10523 |
| 5266 | GIM_Try, /*On fail goto*//*Label 286*/ 10568, // Rule ID 7737 // |
| 5267 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5268 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5269 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, |
| 5270 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5271 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 5272 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 5273 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5274 | // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn) => (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 5275 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv8i8_v8i16, |
| 5276 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 5277 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 5278 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 5279 | GIR_EraseFromParent, /*InsnID*/0, |
| 5280 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5281 | // GIR_Coverage, 7737, |
| 5282 | GIR_Done, |
| 5283 | // Label 286: @10568 |
| 5284 | GIM_Try, /*On fail goto*//*Label 287*/ 10613, // Rule ID 7712 // |
| 5285 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5286 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5287 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, |
| 5288 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5289 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 5290 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 5291 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5292 | // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn) => (SADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 5293 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv8i8_v8i16, |
| 5294 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 5295 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 5296 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 5297 | GIR_EraseFromParent, /*InsnID*/0, |
| 5298 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5299 | // GIR_Coverage, 7712, |
| 5300 | GIR_Done, |
| 5301 | // Label 287: @10613 |
| 5302 | GIM_Try, /*On fail goto*//*Label 288*/ 10658, // Rule ID 7736 // |
| 5303 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5304 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5305 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 5306 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5307 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 5308 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 5309 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5310 | // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn) => (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 5311 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv8i8_v8i16, |
| 5312 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 5313 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 5314 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 5315 | GIR_EraseFromParent, /*InsnID*/0, |
| 5316 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5317 | // GIR_Coverage, 7736, |
| 5318 | GIR_Done, |
| 5319 | // Label 288: @10658 |
| 5320 | GIM_Try, /*On fail goto*//*Label 289*/ 10703, // Rule ID 1520 // |
| 5321 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5322 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 5323 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5324 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, |
| 5325 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5326 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 5327 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5328 | // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 5329 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv8i8_v8i16, |
| 5330 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 5331 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 5332 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 5333 | GIR_EraseFromParent, /*InsnID*/0, |
| 5334 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5335 | // GIR_Coverage, 1520, |
| 5336 | GIR_Done, |
| 5337 | // Label 289: @10703 |
| 5338 | GIM_Try, /*On fail goto*//*Label 290*/ 10748, // Rule ID 1435 // |
| 5339 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5340 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 5341 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5342 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, |
| 5343 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5344 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 5345 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5346 | // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (SADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 5347 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDWv8i8_v8i16, |
| 5348 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 5349 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 5350 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 5351 | GIR_EraseFromParent, /*InsnID*/0, |
| 5352 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5353 | // GIR_Coverage, 1435, |
| 5354 | GIR_Done, |
| 5355 | // Label 290: @10748 |
| 5356 | GIM_Try, /*On fail goto*//*Label 291*/ 10793, // Rule ID 1519 // |
| 5357 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5358 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 5359 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5360 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 5361 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5362 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 5363 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5364 | // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 5365 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDWv8i8_v8i16, |
| 5366 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 5367 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 5368 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 5369 | GIR_EraseFromParent, /*InsnID*/0, |
| 5370 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5371 | // GIR_Coverage, 1519, |
| 5372 | GIR_Done, |
| 5373 | // Label 291: @10793 |
| 5374 | GIM_Try, /*On fail goto*//*Label 292*/ 10812, // Rule ID 893 // |
| 5375 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5376 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 5377 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 5378 | // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (ADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 5379 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv8i16, |
| 5380 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5381 | // GIR_Coverage, 893, |
| 5382 | GIR_Done, |
| 5383 | // Label 292: @10812 |
| 5384 | GIM_Reject, |
| 5385 | // Label 260: @10813 |
| 5386 | GIM_Reject, |
| 5387 | // Label 107: @10814 |
| 5388 | GIM_Try, /*On fail goto*//*Label 293*/ 11344, |
| 5389 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 5390 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5391 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 5392 | GIM_Try, /*On fail goto*//*Label 294*/ 10892, // Rule ID 7636 // |
| 5393 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5394 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5395 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 5396 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 5397 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 5398 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5399 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, |
| 5400 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 5401 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 5402 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 5403 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5404 | // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 426:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd) => (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 5405 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv16i8, |
| 5406 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 5407 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 5408 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 5409 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 5410 | GIR_EraseFromParent, /*InsnID*/0, |
| 5411 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5412 | // GIR_Coverage, 7636, |
| 5413 | GIR_Done, |
| 5414 | // Label 294: @10892 |
| 5415 | GIM_Try, /*On fail goto*//*Label 295*/ 10956, // Rule ID 7648 // |
| 5416 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5417 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5418 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 5419 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 5420 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 5421 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5422 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, |
| 5423 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 5424 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 5425 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 5426 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5427 | // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 489:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd) => (UABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 5428 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv16i8, |
| 5429 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 5430 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 5431 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 5432 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 5433 | GIR_EraseFromParent, /*InsnID*/0, |
| 5434 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5435 | // GIR_Coverage, 7648, |
| 5436 | GIR_Done, |
| 5437 | // Label 295: @10956 |
| 5438 | GIM_Try, /*On fail goto*//*Label 296*/ 11020, // Rule ID 1077 // |
| 5439 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5440 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 5441 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5442 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 5443 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 5444 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 5445 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5446 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, |
| 5447 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 5448 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 5449 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5450 | // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (intrinsic_wo_chain:{ *:[v16i8] } 426:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)) => (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 5451 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABAv16i8, |
| 5452 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 5453 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 5454 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 5455 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 5456 | GIR_EraseFromParent, /*InsnID*/0, |
| 5457 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5458 | // GIR_Coverage, 1077, |
| 5459 | GIR_Done, |
| 5460 | // Label 296: @11020 |
| 5461 | GIM_Try, /*On fail goto*//*Label 297*/ 11084, // Rule ID 1200 // |
| 5462 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5463 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 5464 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5465 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 5466 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 5467 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 5468 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5469 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, |
| 5470 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 5471 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 5472 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5473 | // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (intrinsic_wo_chain:{ *:[v16i8] } 489:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)) => (UABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 5474 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABAv16i8, |
| 5475 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 5476 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 5477 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 5478 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 5479 | GIR_EraseFromParent, /*InsnID*/0, |
| 5480 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5481 | // GIR_Coverage, 1200, |
| 5482 | GIR_Done, |
| 5483 | // Label 297: @11084 |
| 5484 | GIM_Try, /*On fail goto*//*Label 298*/ 11144, // Rule ID 7794 // |
| 5485 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5486 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5487 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, |
| 5488 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 5489 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 5490 | // MIs[1] imm |
| 5491 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 5492 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 5493 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, |
| 5494 | // MIs[2] Operand 1 |
| 5495 | // No operand predicates |
| 5496 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 5497 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5498 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 5499 | // (add:{ *:[v16i8] } (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V128:{ *:[v16i8] }:$Rd) => (SSRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 5500 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv16i8_shift, |
| 5501 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 5502 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 5503 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5504 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 5505 | GIR_EraseFromParent, /*InsnID*/0, |
| 5506 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5507 | // GIR_Coverage, 7794, |
| 5508 | GIR_Done, |
| 5509 | // Label 298: @11144 |
| 5510 | GIM_Try, /*On fail goto*//*Label 299*/ 11204, // Rule ID 7808 // |
| 5511 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5512 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5513 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 5514 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 5515 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 5516 | // MIs[1] imm |
| 5517 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 5518 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 5519 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, |
| 5520 | // MIs[2] Operand 1 |
| 5521 | // No operand predicates |
| 5522 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 5523 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5524 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 5525 | // (add:{ *:[v16i8] } (AArch64vlshr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V128:{ *:[v16i8] }:$Rd) => (USRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 5526 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv16i8_shift, |
| 5527 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 5528 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 5529 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5530 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 5531 | GIR_EraseFromParent, /*InsnID*/0, |
| 5532 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5533 | // GIR_Coverage, 7808, |
| 5534 | GIR_Done, |
| 5535 | // Label 299: @11204 |
| 5536 | GIM_Try, /*On fail goto*//*Label 300*/ 11264, // Rule ID 1883 // |
| 5537 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5538 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 5539 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5540 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, |
| 5541 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 5542 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 5543 | // MIs[1] imm |
| 5544 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 5545 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 5546 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, |
| 5547 | // MIs[2] Operand 1 |
| 5548 | // No operand predicates |
| 5549 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5550 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 5551 | // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm)) => (SSRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 5552 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSRAv16i8_shift, |
| 5553 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 5554 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 5555 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5556 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 5557 | GIR_EraseFromParent, /*InsnID*/0, |
| 5558 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5559 | // GIR_Coverage, 1883, |
| 5560 | GIR_Done, |
| 5561 | // Label 300: @11264 |
| 5562 | GIM_Try, /*On fail goto*//*Label 301*/ 11324, // Rule ID 1935 // |
| 5563 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5564 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 5565 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5566 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 5567 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 5568 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 5569 | // MIs[1] imm |
| 5570 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 5571 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 5572 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, |
| 5573 | // MIs[2] Operand 1 |
| 5574 | // No operand predicates |
| 5575 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5576 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 5577 | // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (AArch64vlshr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm)) => (USRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 5578 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USRAv16i8_shift, |
| 5579 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 5580 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 5581 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5582 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 5583 | GIR_EraseFromParent, /*InsnID*/0, |
| 5584 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5585 | // GIR_Coverage, 1935, |
| 5586 | GIR_Done, |
| 5587 | // Label 301: @11324 |
| 5588 | GIM_Try, /*On fail goto*//*Label 302*/ 11343, // Rule ID 891 // |
| 5589 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 5590 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 5591 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 5592 | // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (ADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 5593 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ADDv16i8, |
| 5594 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5595 | // GIR_Coverage, 891, |
| 5596 | GIR_Done, |
| 5597 | // Label 302: @11343 |
| 5598 | GIM_Reject, |
| 5599 | // Label 293: @11344 |
| 5600 | GIM_Reject, |
| 5601 | // Label 108: @11345 |
| 5602 | GIM_Reject, |
| 5603 | // Label 1: @11346 |
| 5604 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 312*/ 15191, |
| 5605 | /*GILLT_s32*//*Label 303*/ 11362, |
| 5606 | /*GILLT_s64*//*Label 304*/ 11593, 0, |
| 5607 | /*GILLT_v2s32*//*Label 305*/ 12651, |
| 5608 | /*GILLT_v2s64*//*Label 306*/ 12722, |
| 5609 | /*GILLT_v4s16*//*Label 307*/ 13538, |
| 5610 | /*GILLT_v4s32*//*Label 308*/ 13609, |
| 5611 | /*GILLT_v8s8*//*Label 309*/ 14425, |
| 5612 | /*GILLT_v8s16*//*Label 310*/ 14496, |
| 5613 | /*GILLT_v16s8*//*Label 311*/ 15120, |
| 5614 | // Label 303: @11362 |
| 5615 | GIM_Try, /*On fail goto*//*Label 313*/ 11592, |
| 5616 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 5617 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 5618 | GIM_Try, /*On fail goto*//*Label 314*/ 11431, // Rule ID 3499 // |
| 5619 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 5620 | GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, |
| 5621 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5622 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 5623 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5624 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5625 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 5626 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 5627 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5628 | // (sub:{ *:[i32] } 0:{ *:[i32] }, (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)) => (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] }) |
| 5629 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBWrrr, |
| 5630 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 5631 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5632 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 5633 | GIR_AddRegister, /*InsnID*/0, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 5634 | GIR_EraseFromParent, /*InsnID*/0, |
| 5635 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5636 | // GIR_Coverage, 3499, |
| 5637 | GIR_Done, |
| 5638 | // Label 314: @11431 |
| 5639 | GIM_Try, /*On fail goto*//*Label 315*/ 11465, // Rule ID 3465 // |
| 5640 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 5641 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID, |
| 5642 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_arith_extended_reg32_i32, |
| 5643 | // (sub:{ *:[i32] } GPR32sp:{ *:[i32] }:$R2, arith_extended_reg32_i32:{ *:[i32] }:$R3) => (SUBSWrx:{ *:[i32] }:{ *:[i32] } GPR32sp:{ *:[i32] }:$R2, arith_extended_reg32_i32:{ *:[i32] }:$R3) |
| 5644 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWrx, |
| 5645 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // R1 |
| 5646 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // R2 |
| 5647 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // R3 |
| 5648 | GIR_EraseFromParent, /*InsnID*/0, |
| 5649 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5650 | // GIR_Coverage, 3465, |
| 5651 | GIR_Done, |
| 5652 | // Label 315: @11465 |
| 5653 | GIM_Try, /*On fail goto*//*Label 316*/ 11499, // Rule ID 3469 // |
| 5654 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, |
| 5655 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 5656 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_neg_addsub_shifted_imm32, |
| 5657 | // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm) => (ADDWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm) |
| 5658 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDWri, |
| 5659 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 5660 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 5661 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm |
| 5662 | GIR_EraseFromParent, /*InsnID*/0, |
| 5663 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5664 | // GIR_Coverage, 3469, |
| 5665 | GIR_Done, |
| 5666 | // Label 316: @11499 |
| 5667 | GIM_Try, /*On fail goto*//*Label 317*/ 11533, // Rule ID 3459 // |
| 5668 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 5669 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID, |
| 5670 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm32, |
| 5671 | // (sub:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm) => (SUBSWri:{ *:[i32] }:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm) |
| 5672 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWri, |
| 5673 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 5674 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 5675 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm |
| 5676 | GIR_EraseFromParent, /*InsnID*/0, |
| 5677 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5678 | // GIR_Coverage, 3459, |
| 5679 | GIR_Done, |
| 5680 | // Label 317: @11533 |
| 5681 | GIM_Try, /*On fail goto*//*Label 318*/ 11567, // Rule ID 3463 // |
| 5682 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 5683 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 5684 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_arith_shifted_reg32, |
| 5685 | // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm) => (SUBSWrs:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm) |
| 5686 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWrs, |
| 5687 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 5688 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 5689 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 5690 | GIR_EraseFromParent, /*InsnID*/0, |
| 5691 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5692 | // GIR_Coverage, 3463, |
| 5693 | GIR_Done, |
| 5694 | // Label 318: @11567 |
| 5695 | GIM_Try, /*On fail goto*//*Label 319*/ 11591, // Rule ID 3461 // |
| 5696 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 5697 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 5698 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 5699 | // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (SUBSWrr:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 5700 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBSWrr, |
| 5701 | GIR_AddImplicitDef, /*InsnID*/0, AArch64::NZCV, |
| 5702 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5703 | // GIR_Coverage, 3461, |
| 5704 | GIR_Done, |
| 5705 | // Label 319: @11591 |
| 5706 | GIM_Reject, |
| 5707 | // Label 313: @11592 |
| 5708 | GIM_Reject, |
| 5709 | // Label 304: @11593 |
| 5710 | GIM_Try, /*On fail goto*//*Label 320*/ 12650, |
| 5711 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 5712 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 5713 | GIM_Try, /*On fail goto*//*Label 321*/ 11699, // Rule ID 3514 // |
| 5714 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 5715 | GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, |
| 5716 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5717 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 5718 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 5719 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 5720 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 5721 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, |
| 5722 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5723 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 5724 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 5725 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 5726 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit, |
| 5727 | // MIs[3] Operand 1 |
| 5728 | // No operand predicates |
| 5729 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5730 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 5731 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 5732 | // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C)) => (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] }) |
| 5733 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 5734 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, |
| 5735 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 5736 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C |
| 5737 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5738 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr, |
| 5739 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 5740 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 5741 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 5742 | GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, |
| 5743 | GIR_EraseFromParent, /*InsnID*/0, |
| 5744 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5745 | // GIR_Coverage, 3514, |
| 5746 | GIR_Done, |
| 5747 | // Label 321: @11699 |
| 5748 | GIM_Try, /*On fail goto*//*Label 322*/ 11795, // Rule ID 3515 // |
| 5749 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 5750 | GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, |
| 5751 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5752 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 5753 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 5754 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 5755 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 5756 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, |
| 5757 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5758 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 5759 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 5760 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 5761 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit, |
| 5762 | // MIs[3] Operand 1 |
| 5763 | // No operand predicates |
| 5764 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5765 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 5766 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 5767 | // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C)) => (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] }) |
| 5768 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 5769 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, |
| 5770 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 5771 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C |
| 5772 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5773 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr, |
| 5774 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 5775 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 5776 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 5777 | GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, |
| 5778 | GIR_EraseFromParent, /*InsnID*/0, |
| 5779 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5780 | // GIR_Coverage, 3515, |
| 5781 | GIR_Done, |
| 5782 | // Label 322: @11795 |
| 5783 | GIM_Try, /*On fail goto*//*Label 323*/ 11880, // Rule ID 3509 // |
| 5784 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 5785 | GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, |
| 5786 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5787 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 5788 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 5789 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 5790 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 5791 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, |
| 5792 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5793 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 5794 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 5795 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT, |
| 5796 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 5797 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 5798 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5799 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 5800 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 5801 | // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] }) |
| 5802 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr, |
| 5803 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 5804 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 5805 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 5806 | GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, |
| 5807 | GIR_EraseFromParent, /*InsnID*/0, |
| 5808 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5809 | // GIR_Coverage, 3509, |
| 5810 | GIR_Done, |
| 5811 | // Label 323: @11880 |
| 5812 | GIM_Try, /*On fail goto*//*Label 324*/ 11965, // Rule ID 3510 // |
| 5813 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 5814 | GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, |
| 5815 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5816 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 5817 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 5818 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 5819 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 5820 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, |
| 5821 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5822 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 5823 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 5824 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT, |
| 5825 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 5826 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 5827 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5828 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 5829 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 5830 | // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] }) |
| 5831 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr, |
| 5832 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 5833 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 5834 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 5835 | GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, |
| 5836 | GIR_EraseFromParent, /*InsnID*/0, |
| 5837 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5838 | // GIR_Coverage, 3510, |
| 5839 | GIR_Done, |
| 5840 | // Label 324: @11965 |
| 5841 | GIM_Try, /*On fail goto*//*Label 325*/ 12061, // Rule ID 3520 // |
| 5842 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 5843 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 5844 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5845 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 5846 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 5847 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 5848 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 5849 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, |
| 5850 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5851 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 5852 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 5853 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 5854 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit, |
| 5855 | // MIs[3] Operand 1 |
| 5856 | // No operand predicates |
| 5857 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5858 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 5859 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 5860 | // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C)) => (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra) |
| 5861 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 5862 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, |
| 5863 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 5864 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C |
| 5865 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5866 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr, |
| 5867 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 5868 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 5869 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 5870 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra |
| 5871 | GIR_EraseFromParent, /*InsnID*/0, |
| 5872 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5873 | // GIR_Coverage, 3520, |
| 5874 | GIR_Done, |
| 5875 | // Label 325: @12061 |
| 5876 | GIM_Try, /*On fail goto*//*Label 326*/ 12157, // Rule ID 3521 // |
| 5877 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 5878 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 5879 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5880 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 5881 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 5882 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 5883 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 5884 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, |
| 5885 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5886 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 5887 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 5888 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 5889 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit, |
| 5890 | // MIs[3] Operand 1 |
| 5891 | // No operand predicates |
| 5892 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5893 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 5894 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 5895 | // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C)) => (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra) |
| 5896 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 5897 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, |
| 5898 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 5899 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GICR_renderTruncImm, // C |
| 5900 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5901 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr, |
| 5902 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 5903 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 5904 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 5905 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra |
| 5906 | GIR_EraseFromParent, /*InsnID*/0, |
| 5907 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5908 | // GIR_Coverage, 3521, |
| 5909 | GIR_Done, |
| 5910 | // Label 326: @12157 |
| 5911 | GIM_Try, /*On fail goto*//*Label 327*/ 12242, // Rule ID 115 // |
| 5912 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 5913 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 5914 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5915 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 5916 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 5917 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 5918 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 5919 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, |
| 5920 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5921 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 5922 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 5923 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SEXT, |
| 5924 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 5925 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 5926 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5927 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 5928 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 5929 | // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra) |
| 5930 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMSUBLrrr, |
| 5931 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 5932 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 5933 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 5934 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra |
| 5935 | GIR_EraseFromParent, /*InsnID*/0, |
| 5936 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5937 | // GIR_Coverage, 115, |
| 5938 | GIR_Done, |
| 5939 | // Label 327: @12242 |
| 5940 | GIM_Try, /*On fail goto*//*Label 328*/ 12327, // Rule ID 117 // |
| 5941 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 5942 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 5943 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5944 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 5945 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 5946 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 5947 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 5948 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, |
| 5949 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5950 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 5951 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 5952 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT, |
| 5953 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 5954 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 5955 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5956 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 5957 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 5958 | // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra) |
| 5959 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMSUBLrrr, |
| 5960 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 5961 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 5962 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 5963 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra |
| 5964 | GIR_EraseFromParent, /*InsnID*/0, |
| 5965 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5966 | // GIR_Coverage, 117, |
| 5967 | GIR_Done, |
| 5968 | // Label 328: @12327 |
| 5969 | GIM_Try, /*On fail goto*//*Label 329*/ 12386, // Rule ID 3500 // |
| 5970 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 5971 | GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, |
| 5972 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5973 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 5974 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 5975 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 5976 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 5977 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 5978 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5979 | // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)) => (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] }) |
| 5980 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBXrrr, |
| 5981 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 5982 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5983 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 5984 | GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, |
| 5985 | GIR_EraseFromParent, /*InsnID*/0, |
| 5986 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5987 | // GIR_Coverage, 3500, |
| 5988 | GIR_Done, |
| 5989 | // Label 329: @12386 |
| 5990 | GIM_Try, /*On fail goto*//*Label 330*/ 12420, // Rule ID 3466 // |
| 5991 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 5992 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 5993 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_arith_extended_reg32to64_i64, |
| 5994 | // (sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$R2, arith_extended_reg32to64_i64:{ *:[i64] }:$R3) => (SUBSXrx:{ *:[i64] }:{ *:[i32] } GPR64sp:{ *:[i64] }:$R2, arith_extended_reg32to64_i64:{ *:[i64] }:$R3) |
| 5995 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXrx, |
| 5996 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // R1 |
| 5997 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // R2 |
| 5998 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // R3 |
| 5999 | GIR_EraseFromParent, /*InsnID*/0, |
| 6000 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6001 | // GIR_Coverage, 3466, |
| 6002 | GIR_Done, |
| 6003 | // Label 330: @12420 |
| 6004 | GIM_Try, /*On fail goto*//*Label 331*/ 12454, // Rule ID 3470 // |
| 6005 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, |
| 6006 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 6007 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_neg_addsub_shifted_imm64, |
| 6008 | // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm) => (ADDXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm) |
| 6009 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri, |
| 6010 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6011 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 6012 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm |
| 6013 | GIR_EraseFromParent, /*InsnID*/0, |
| 6014 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6015 | // GIR_Coverage, 3470, |
| 6016 | GIR_Done, |
| 6017 | // Label 331: @12454 |
| 6018 | GIM_Try, /*On fail goto*//*Label 332*/ 12488, // Rule ID 3460 // |
| 6019 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 6020 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 6021 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm64, |
| 6022 | // (sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm) => (SUBSXri:{ *:[i64] }:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm) |
| 6023 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXri, |
| 6024 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6025 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 6026 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // imm |
| 6027 | GIR_EraseFromParent, /*InsnID*/0, |
| 6028 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6029 | // GIR_Coverage, 3460, |
| 6030 | GIR_Done, |
| 6031 | // Label 332: @12488 |
| 6032 | GIM_Try, /*On fail goto*//*Label 333*/ 12522, // Rule ID 3464 // |
| 6033 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 6034 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 6035 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_arith_shifted_reg64, |
| 6036 | // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm) => (SUBSXrs:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm) |
| 6037 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSXrs, |
| 6038 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6039 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 6040 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 6041 | GIR_EraseFromParent, /*InsnID*/0, |
| 6042 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6043 | // GIR_Coverage, 3464, |
| 6044 | GIR_Done, |
| 6045 | // Label 333: @12522 |
| 6046 | GIM_Try, /*On fail goto*//*Label 334*/ 12562, // Rule ID 1374 // |
| 6047 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6048 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 6049 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6050 | GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 6051 | GIM_CheckIsBuildVectorAllZeros, /*MI*/1, |
| 6052 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 6053 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6054 | // (sub:{ *:[v1i64] } immAllZerosV:{ *:[v1i64] }, FPR64:{ *:[v1i64] }:$Rn) => (NEGv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn) |
| 6055 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NEGv1i64, |
| 6056 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6057 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 6058 | GIR_EraseFromParent, /*InsnID*/0, |
| 6059 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6060 | // GIR_Coverage, 1374, |
| 6061 | GIR_Done, |
| 6062 | // Label 334: @12562 |
| 6063 | GIM_Try, /*On fail goto*//*Label 335*/ 12602, // Rule ID 4142 // |
| 6064 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6065 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 6066 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6067 | GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 6068 | GIM_CheckIsBuildVectorAllZeros, /*MI*/1, |
| 6069 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 6070 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6071 | // (sub:{ *:[i64] } immAllZerosV:{ *:[i64] }, FPR64:{ *:[i64] }:$Rn) => (NEGv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn) |
| 6072 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NEGv1i64, |
| 6073 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6074 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 6075 | GIR_EraseFromParent, /*InsnID*/0, |
| 6076 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6077 | // GIR_Coverage, 4142, |
| 6078 | GIR_Done, |
| 6079 | // Label 335: @12602 |
| 6080 | GIM_Try, /*On fail goto*//*Label 336*/ 12625, // Rule ID 1364 // |
| 6081 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6082 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 6083 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6084 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 6085 | // (sub:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SUBv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) |
| 6086 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv1i64, |
| 6087 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6088 | // GIR_Coverage, 1364, |
| 6089 | GIR_Done, |
| 6090 | // Label 336: @12625 |
| 6091 | GIM_Try, /*On fail goto*//*Label 337*/ 12649, // Rule ID 3462 // |
| 6092 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 6093 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 6094 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 6095 | // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (SUBSXrr:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) |
| 6096 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBSXrr, |
| 6097 | GIR_AddImplicitDef, /*InsnID*/0, AArch64::NZCV, |
| 6098 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6099 | // GIR_Coverage, 3462, |
| 6100 | GIR_Done, |
| 6101 | // Label 337: @12649 |
| 6102 | GIM_Reject, |
| 6103 | // Label 320: @12650 |
| 6104 | GIM_Reject, |
| 6105 | // Label 305: @12651 |
| 6106 | GIM_Try, /*On fail goto*//*Label 338*/ 12721, |
| 6107 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 6108 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 6109 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 6110 | GIM_Try, /*On fail goto*//*Label 339*/ 12701, // Rule ID 793 // |
| 6111 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6112 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6113 | GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 6114 | GIM_CheckIsBuildVectorAllZeros, /*MI*/1, |
| 6115 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 6116 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6117 | // (sub:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$Rn) => (NEGv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) |
| 6118 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NEGv2i32, |
| 6119 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6120 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 6121 | GIR_EraseFromParent, /*InsnID*/0, |
| 6122 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6123 | // GIR_Coverage, 793, |
| 6124 | GIR_Done, |
| 6125 | // Label 339: @12701 |
| 6126 | GIM_Try, /*On fail goto*//*Label 340*/ 12720, // Rule ID 1194 // |
| 6127 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6128 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6129 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 6130 | // (sub:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 6131 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv2i32, |
| 6132 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6133 | // GIR_Coverage, 1194, |
| 6134 | GIR_Done, |
| 6135 | // Label 340: @12720 |
| 6136 | GIM_Reject, |
| 6137 | // Label 338: @12721 |
| 6138 | GIM_Reject, |
| 6139 | // Label 306: @12722 |
| 6140 | GIM_Try, /*On fail goto*//*Label 341*/ 13537, |
| 6141 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 6142 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 6143 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 6144 | GIM_Try, /*On fail goto*//*Label 342*/ 12832, // Rule ID 1724 // |
| 6145 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6146 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 6147 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6148 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 6149 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 6150 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, |
| 6151 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 6152 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 6153 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 6154 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 6155 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 6156 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 6157 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 6158 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 6159 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 6160 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 6161 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 6162 | // MIs[3] Operand 1 |
| 6163 | // No operand predicates |
| 6164 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6165 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 6166 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 6167 | // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 444:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (SMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 6168 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLSLv2i32_indexed, |
| 6169 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 6170 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 6171 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 6172 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6173 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 6174 | GIR_EraseFromParent, /*InsnID*/0, |
| 6175 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6176 | // GIR_Coverage, 1724, |
| 6177 | GIR_Done, |
| 6178 | // Label 342: @12832 |
| 6179 | GIM_Try, /*On fail goto*//*Label 343*/ 12928, // Rule ID 1760 // |
| 6180 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6181 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 6182 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6183 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 6184 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 6185 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, |
| 6186 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 6187 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 6188 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 6189 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 6190 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 6191 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 6192 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 6193 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 6194 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 6195 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 6196 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 6197 | // MIs[3] Operand 1 |
| 6198 | // No operand predicates |
| 6199 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6200 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 6201 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 6202 | // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 503:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (UMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 6203 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLSLv2i32_indexed, |
| 6204 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 6205 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 6206 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 6207 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6208 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 6209 | GIR_EraseFromParent, /*InsnID*/0, |
| 6210 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6211 | // GIR_Coverage, 1760, |
| 6212 | GIR_Done, |
| 6213 | // Label 343: @12928 |
| 6214 | GIM_Try, /*On fail goto*//*Label 344*/ 12992, // Rule ID 1451 // |
| 6215 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6216 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 6217 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6218 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 6219 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 6220 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, |
| 6221 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 6222 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 6223 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 6224 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 6225 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6226 | // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 444:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 6227 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLSLv2i32_v2i64, |
| 6228 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 6229 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 6230 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 6231 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 6232 | GIR_EraseFromParent, /*InsnID*/0, |
| 6233 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6234 | // GIR_Coverage, 1451, |
| 6235 | GIR_Done, |
| 6236 | // Label 344: @12992 |
| 6237 | GIM_Try, /*On fail goto*//*Label 345*/ 13056, // Rule ID 1541 // |
| 6238 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6239 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 6240 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6241 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 6242 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 6243 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, |
| 6244 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 6245 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 6246 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 6247 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 6248 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6249 | // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 503:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (UMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 6250 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLSLv2i32_v2i64, |
| 6251 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 6252 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 6253 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 6254 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 6255 | GIR_EraseFromParent, /*InsnID*/0, |
| 6256 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6257 | // GIR_Coverage, 1541, |
| 6258 | GIR_Done, |
| 6259 | // Label 345: @13056 |
| 6260 | GIM_Try, /*On fail goto*//*Label 346*/ 13114, // Rule ID 1568 // |
| 6261 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6262 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6263 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, |
| 6264 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 6265 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6266 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6267 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT, |
| 6268 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 6269 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6270 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6271 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 6272 | // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 6273 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv2i32_v2i64, |
| 6274 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6275 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6276 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6277 | GIR_EraseFromParent, /*InsnID*/0, |
| 6278 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6279 | // GIR_Coverage, 1568, |
| 6280 | GIR_Done, |
| 6281 | // Label 346: @13114 |
| 6282 | GIM_Try, /*On fail goto*//*Label 347*/ 13172, // Rule ID 1567 // |
| 6283 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6284 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6285 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, |
| 6286 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 6287 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6288 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6289 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, |
| 6290 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 6291 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6292 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6293 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 6294 | // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 6295 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv2i32_v2i64, |
| 6296 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6297 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6298 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6299 | GIR_EraseFromParent, /*InsnID*/0, |
| 6300 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6301 | // GIR_Coverage, 1567, |
| 6302 | GIR_Done, |
| 6303 | // Label 347: @13172 |
| 6304 | GIM_Try, /*On fail goto*//*Label 348*/ 13230, // Rule ID 1475 // |
| 6305 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6306 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6307 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, |
| 6308 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 6309 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6310 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6311 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, |
| 6312 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 6313 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6314 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6315 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 6316 | // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (SSUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 6317 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv2i32_v2i64, |
| 6318 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6319 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6320 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6321 | GIR_EraseFromParent, /*InsnID*/0, |
| 6322 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6323 | // GIR_Coverage, 1475, |
| 6324 | GIR_Done, |
| 6325 | // Label 348: @13230 |
| 6326 | GIM_Try, /*On fail goto*//*Label 349*/ 13288, // Rule ID 1566 // |
| 6327 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6328 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6329 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 6330 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 6331 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6332 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6333 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT, |
| 6334 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 6335 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6336 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6337 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 6338 | // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 6339 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv2i32_v2i64, |
| 6340 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6341 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6342 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6343 | GIR_EraseFromParent, /*InsnID*/0, |
| 6344 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6345 | // GIR_Coverage, 1566, |
| 6346 | GIR_Done, |
| 6347 | // Label 349: @13288 |
| 6348 | GIM_Try, /*On fail goto*//*Label 350*/ 13346, // Rule ID 1565 // |
| 6349 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6350 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6351 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 6352 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 6353 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6354 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6355 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, |
| 6356 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 6357 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6358 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6359 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 6360 | // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 6361 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv2i32_v2i64, |
| 6362 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6363 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6364 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6365 | GIR_EraseFromParent, /*InsnID*/0, |
| 6366 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6367 | // GIR_Coverage, 1565, |
| 6368 | GIR_Done, |
| 6369 | // Label 350: @13346 |
| 6370 | GIM_Try, /*On fail goto*//*Label 351*/ 13382, // Rule ID 795 // |
| 6371 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6372 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6373 | GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 6374 | GIM_CheckIsBuildVectorAllZeros, /*MI*/1, |
| 6375 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 6376 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6377 | // (sub:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$Rn) => (NEGv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn) |
| 6378 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NEGv2i64, |
| 6379 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6380 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 6381 | GIR_EraseFromParent, /*InsnID*/0, |
| 6382 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6383 | // GIR_Coverage, 795, |
| 6384 | GIR_Done, |
| 6385 | // Label 351: @13382 |
| 6386 | GIM_Try, /*On fail goto*//*Label 352*/ 13427, // Rule ID 1582 // |
| 6387 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6388 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 6389 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6390 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, |
| 6391 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 6392 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6393 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6394 | // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (USUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 6395 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv2i32_v2i64, |
| 6396 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6397 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 6398 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6399 | GIR_EraseFromParent, /*InsnID*/0, |
| 6400 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6401 | // GIR_Coverage, 1582, |
| 6402 | GIR_Done, |
| 6403 | // Label 352: @13427 |
| 6404 | GIM_Try, /*On fail goto*//*Label 353*/ 13472, // Rule ID 1481 // |
| 6405 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6406 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 6407 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6408 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, |
| 6409 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 6410 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6411 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6412 | // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (SSUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 6413 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv2i32_v2i64, |
| 6414 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6415 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 6416 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6417 | GIR_EraseFromParent, /*InsnID*/0, |
| 6418 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6419 | // GIR_Coverage, 1481, |
| 6420 | GIR_Done, |
| 6421 | // Label 353: @13472 |
| 6422 | GIM_Try, /*On fail goto*//*Label 354*/ 13517, // Rule ID 1581 // |
| 6423 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6424 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 6425 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6426 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 6427 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 6428 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6429 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6430 | // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (USUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 6431 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv2i32_v2i64, |
| 6432 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6433 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 6434 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6435 | GIR_EraseFromParent, /*InsnID*/0, |
| 6436 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6437 | // GIR_Coverage, 1581, |
| 6438 | GIR_Done, |
| 6439 | // Label 354: @13517 |
| 6440 | GIM_Try, /*On fail goto*//*Label 355*/ 13536, // Rule ID 1196 // |
| 6441 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6442 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 6443 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 6444 | // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 6445 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv2i64, |
| 6446 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6447 | // GIR_Coverage, 1196, |
| 6448 | GIR_Done, |
| 6449 | // Label 355: @13536 |
| 6450 | GIM_Reject, |
| 6451 | // Label 341: @13537 |
| 6452 | GIM_Reject, |
| 6453 | // Label 307: @13538 |
| 6454 | GIM_Try, /*On fail goto*//*Label 356*/ 13608, |
| 6455 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 6456 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 6457 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 6458 | GIM_Try, /*On fail goto*//*Label 357*/ 13588, // Rule ID 791 // |
| 6459 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6460 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6461 | GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 6462 | GIM_CheckIsBuildVectorAllZeros, /*MI*/1, |
| 6463 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 6464 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6465 | // (sub:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$Rn) => (NEGv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) |
| 6466 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NEGv4i16, |
| 6467 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6468 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 6469 | GIR_EraseFromParent, /*InsnID*/0, |
| 6470 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6471 | // GIR_Coverage, 791, |
| 6472 | GIR_Done, |
| 6473 | // Label 357: @13588 |
| 6474 | GIM_Try, /*On fail goto*//*Label 358*/ 13607, // Rule ID 1192 // |
| 6475 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6476 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6477 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 6478 | // (sub:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 6479 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv4i16, |
| 6480 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6481 | // GIR_Coverage, 1192, |
| 6482 | GIR_Done, |
| 6483 | // Label 358: @13607 |
| 6484 | GIM_Reject, |
| 6485 | // Label 356: @13608 |
| 6486 | GIM_Reject, |
| 6487 | // Label 308: @13609 |
| 6488 | GIM_Try, /*On fail goto*//*Label 359*/ 14424, |
| 6489 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 6490 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6491 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 6492 | GIM_Try, /*On fail goto*//*Label 360*/ 13719, // Rule ID 1722 // |
| 6493 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6494 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 6495 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6496 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 6497 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 6498 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, |
| 6499 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 6500 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 6501 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 6502 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 6503 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, |
| 6504 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 6505 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 6506 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 6507 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 6508 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 6509 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 6510 | // MIs[3] Operand 1 |
| 6511 | // No operand predicates |
| 6512 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6513 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 6514 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 6515 | // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 444:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))) => (SMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 6516 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLSLv4i16_indexed, |
| 6517 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 6518 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 6519 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 6520 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6521 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 6522 | GIR_EraseFromParent, /*InsnID*/0, |
| 6523 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6524 | // GIR_Coverage, 1722, |
| 6525 | GIR_Done, |
| 6526 | // Label 360: @13719 |
| 6527 | GIM_Try, /*On fail goto*//*Label 361*/ 13815, // Rule ID 1758 // |
| 6528 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6529 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 6530 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6531 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 6532 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 6533 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, |
| 6534 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 6535 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 6536 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 6537 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 6538 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, |
| 6539 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 6540 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 6541 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 6542 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 6543 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 6544 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 6545 | // MIs[3] Operand 1 |
| 6546 | // No operand predicates |
| 6547 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6548 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 6549 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 6550 | // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 503:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))) => (UMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 6551 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLSLv4i16_indexed, |
| 6552 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 6553 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 6554 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 6555 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6556 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 6557 | GIR_EraseFromParent, /*InsnID*/0, |
| 6558 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6559 | // GIR_Coverage, 1758, |
| 6560 | GIR_Done, |
| 6561 | // Label 361: @13815 |
| 6562 | GIM_Try, /*On fail goto*//*Label 362*/ 13879, // Rule ID 1449 // |
| 6563 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6564 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 6565 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6566 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 6567 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 6568 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, |
| 6569 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 6570 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 6571 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 6572 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 6573 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6574 | // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 444:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 6575 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLSLv4i16_v4i32, |
| 6576 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 6577 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 6578 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 6579 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 6580 | GIR_EraseFromParent, /*InsnID*/0, |
| 6581 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6582 | // GIR_Coverage, 1449, |
| 6583 | GIR_Done, |
| 6584 | // Label 362: @13879 |
| 6585 | GIM_Try, /*On fail goto*//*Label 363*/ 13943, // Rule ID 1539 // |
| 6586 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6587 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 6588 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6589 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 6590 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 6591 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, |
| 6592 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 6593 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 6594 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 6595 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 6596 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6597 | // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 503:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (UMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 6598 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLSLv4i16_v4i32, |
| 6599 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 6600 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 6601 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 6602 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 6603 | GIR_EraseFromParent, /*InsnID*/0, |
| 6604 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6605 | // GIR_Coverage, 1539, |
| 6606 | GIR_Done, |
| 6607 | // Label 363: @13943 |
| 6608 | GIM_Try, /*On fail goto*//*Label 364*/ 14001, // Rule ID 1560 // |
| 6609 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6610 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6611 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, |
| 6612 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 6613 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6614 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6615 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT, |
| 6616 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 6617 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6618 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6619 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 6620 | // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 6621 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv4i16_v4i32, |
| 6622 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6623 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6624 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6625 | GIR_EraseFromParent, /*InsnID*/0, |
| 6626 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6627 | // GIR_Coverage, 1560, |
| 6628 | GIR_Done, |
| 6629 | // Label 364: @14001 |
| 6630 | GIM_Try, /*On fail goto*//*Label 365*/ 14059, // Rule ID 1559 // |
| 6631 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6632 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6633 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, |
| 6634 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 6635 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6636 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6637 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, |
| 6638 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 6639 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6640 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6641 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 6642 | // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 6643 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv4i16_v4i32, |
| 6644 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6645 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6646 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6647 | GIR_EraseFromParent, /*InsnID*/0, |
| 6648 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6649 | // GIR_Coverage, 1559, |
| 6650 | GIR_Done, |
| 6651 | // Label 365: @14059 |
| 6652 | GIM_Try, /*On fail goto*//*Label 366*/ 14117, // Rule ID 1473 // |
| 6653 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6654 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6655 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, |
| 6656 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 6657 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6658 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6659 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, |
| 6660 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 6661 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6662 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6663 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 6664 | // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (SSUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 6665 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv4i16_v4i32, |
| 6666 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6667 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6668 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6669 | GIR_EraseFromParent, /*InsnID*/0, |
| 6670 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6671 | // GIR_Coverage, 1473, |
| 6672 | GIR_Done, |
| 6673 | // Label 366: @14117 |
| 6674 | GIM_Try, /*On fail goto*//*Label 367*/ 14175, // Rule ID 1558 // |
| 6675 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6676 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6677 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 6678 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 6679 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6680 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6681 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT, |
| 6682 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 6683 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6684 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6685 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 6686 | // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 6687 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv4i16_v4i32, |
| 6688 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6689 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6690 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6691 | GIR_EraseFromParent, /*InsnID*/0, |
| 6692 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6693 | // GIR_Coverage, 1558, |
| 6694 | GIR_Done, |
| 6695 | // Label 367: @14175 |
| 6696 | GIM_Try, /*On fail goto*//*Label 368*/ 14233, // Rule ID 1557 // |
| 6697 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6698 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6699 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 6700 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 6701 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6702 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6703 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, |
| 6704 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 6705 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6706 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6707 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 6708 | // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 6709 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv4i16_v4i32, |
| 6710 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6711 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6712 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6713 | GIR_EraseFromParent, /*InsnID*/0, |
| 6714 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6715 | // GIR_Coverage, 1557, |
| 6716 | GIR_Done, |
| 6717 | // Label 368: @14233 |
| 6718 | GIM_Try, /*On fail goto*//*Label 369*/ 14269, // Rule ID 794 // |
| 6719 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6720 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6721 | GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 6722 | GIM_CheckIsBuildVectorAllZeros, /*MI*/1, |
| 6723 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 6724 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6725 | // (sub:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$Rn) => (NEGv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) |
| 6726 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NEGv4i32, |
| 6727 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6728 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 6729 | GIR_EraseFromParent, /*InsnID*/0, |
| 6730 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6731 | // GIR_Coverage, 794, |
| 6732 | GIR_Done, |
| 6733 | // Label 369: @14269 |
| 6734 | GIM_Try, /*On fail goto*//*Label 370*/ 14314, // Rule ID 1578 // |
| 6735 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6736 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 6737 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6738 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, |
| 6739 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 6740 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6741 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6742 | // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (USUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 6743 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv4i16_v4i32, |
| 6744 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6745 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 6746 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6747 | GIR_EraseFromParent, /*InsnID*/0, |
| 6748 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6749 | // GIR_Coverage, 1578, |
| 6750 | GIR_Done, |
| 6751 | // Label 370: @14314 |
| 6752 | GIM_Try, /*On fail goto*//*Label 371*/ 14359, // Rule ID 1479 // |
| 6753 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6754 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 6755 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6756 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, |
| 6757 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 6758 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6759 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6760 | // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (SSUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 6761 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv4i16_v4i32, |
| 6762 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6763 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 6764 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6765 | GIR_EraseFromParent, /*InsnID*/0, |
| 6766 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6767 | // GIR_Coverage, 1479, |
| 6768 | GIR_Done, |
| 6769 | // Label 371: @14359 |
| 6770 | GIM_Try, /*On fail goto*//*Label 372*/ 14404, // Rule ID 1577 // |
| 6771 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6772 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 6773 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6774 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 6775 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 6776 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6777 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6778 | // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (USUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 6779 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv4i16_v4i32, |
| 6780 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6781 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 6782 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6783 | GIR_EraseFromParent, /*InsnID*/0, |
| 6784 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6785 | // GIR_Coverage, 1577, |
| 6786 | GIR_Done, |
| 6787 | // Label 372: @14404 |
| 6788 | GIM_Try, /*On fail goto*//*Label 373*/ 14423, // Rule ID 1195 // |
| 6789 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6790 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 6791 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 6792 | // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 6793 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv4i32, |
| 6794 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6795 | // GIR_Coverage, 1195, |
| 6796 | GIR_Done, |
| 6797 | // Label 373: @14423 |
| 6798 | GIM_Reject, |
| 6799 | // Label 359: @14424 |
| 6800 | GIM_Reject, |
| 6801 | // Label 309: @14425 |
| 6802 | GIM_Try, /*On fail goto*//*Label 374*/ 14495, |
| 6803 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 6804 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 6805 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 6806 | GIM_Try, /*On fail goto*//*Label 375*/ 14475, // Rule ID 789 // |
| 6807 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6808 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6809 | GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 6810 | GIM_CheckIsBuildVectorAllZeros, /*MI*/1, |
| 6811 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 6812 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6813 | // (sub:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rn) => (NEGv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) |
| 6814 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NEGv8i8, |
| 6815 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6816 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 6817 | GIR_EraseFromParent, /*InsnID*/0, |
| 6818 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6819 | // GIR_Coverage, 789, |
| 6820 | GIR_Done, |
| 6821 | // Label 375: @14475 |
| 6822 | GIM_Try, /*On fail goto*//*Label 376*/ 14494, // Rule ID 1190 // |
| 6823 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6824 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6825 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 6826 | // (sub:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 6827 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv8i8, |
| 6828 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6829 | // GIR_Coverage, 1190, |
| 6830 | GIR_Done, |
| 6831 | // Label 376: @14494 |
| 6832 | GIM_Reject, |
| 6833 | // Label 374: @14495 |
| 6834 | GIM_Reject, |
| 6835 | // Label 310: @14496 |
| 6836 | GIM_Try, /*On fail goto*//*Label 377*/ 15119, |
| 6837 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 6838 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 6839 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 6840 | GIM_Try, /*On fail goto*//*Label 378*/ 14574, // Rule ID 1447 // |
| 6841 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6842 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 6843 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6844 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 6845 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 6846 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_smull, |
| 6847 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 6848 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, |
| 6849 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 6850 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 6851 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6852 | // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 444:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (SMLSLv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 6853 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMLSLv8i8_v8i16, |
| 6854 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 6855 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 6856 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 6857 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 6858 | GIR_EraseFromParent, /*InsnID*/0, |
| 6859 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6860 | // GIR_Coverage, 1447, |
| 6861 | GIR_Done, |
| 6862 | // Label 378: @14574 |
| 6863 | GIM_Try, /*On fail goto*//*Label 379*/ 14638, // Rule ID 1537 // |
| 6864 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6865 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 6866 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6867 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 6868 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 6869 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_umull, |
| 6870 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 6871 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, |
| 6872 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 6873 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 6874 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6875 | // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 503:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (UMLSLv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 6876 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMLSLv8i8_v8i16, |
| 6877 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 6878 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 6879 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 6880 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 6881 | GIR_EraseFromParent, /*InsnID*/0, |
| 6882 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6883 | // GIR_Coverage, 1537, |
| 6884 | GIR_Done, |
| 6885 | // Label 379: @14638 |
| 6886 | GIM_Try, /*On fail goto*//*Label 380*/ 14696, // Rule ID 1552 // |
| 6887 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6888 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6889 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, |
| 6890 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 6891 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6892 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6893 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT, |
| 6894 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 6895 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6896 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6897 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 6898 | // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 6899 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv8i8_v8i16, |
| 6900 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6901 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6902 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6903 | GIR_EraseFromParent, /*InsnID*/0, |
| 6904 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6905 | // GIR_Coverage, 1552, |
| 6906 | GIR_Done, |
| 6907 | // Label 380: @14696 |
| 6908 | GIM_Try, /*On fail goto*//*Label 381*/ 14754, // Rule ID 1551 // |
| 6909 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6910 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6911 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, |
| 6912 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 6913 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6914 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6915 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, |
| 6916 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 6917 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6918 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6919 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 6920 | // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 6921 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv8i8_v8i16, |
| 6922 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6923 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6924 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6925 | GIR_EraseFromParent, /*InsnID*/0, |
| 6926 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6927 | // GIR_Coverage, 1551, |
| 6928 | GIR_Done, |
| 6929 | // Label 381: @14754 |
| 6930 | GIM_Try, /*On fail goto*//*Label 382*/ 14812, // Rule ID 1471 // |
| 6931 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6932 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6933 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, |
| 6934 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 6935 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6936 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6937 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, |
| 6938 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 6939 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6940 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6941 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 6942 | // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (SSUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 6943 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBLv8i8_v8i16, |
| 6944 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6945 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6946 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6947 | GIR_EraseFromParent, /*InsnID*/0, |
| 6948 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6949 | // GIR_Coverage, 1471, |
| 6950 | GIR_Done, |
| 6951 | // Label 382: @14812 |
| 6952 | GIM_Try, /*On fail goto*//*Label 383*/ 14870, // Rule ID 1550 // |
| 6953 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6954 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6955 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 6956 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 6957 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6958 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6959 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT, |
| 6960 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 6961 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6962 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6963 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 6964 | // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 6965 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv8i8_v8i16, |
| 6966 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6967 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6968 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6969 | GIR_EraseFromParent, /*InsnID*/0, |
| 6970 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6971 | // GIR_Coverage, 1550, |
| 6972 | GIR_Done, |
| 6973 | // Label 383: @14870 |
| 6974 | GIM_Try, /*On fail goto*//*Label 384*/ 14928, // Rule ID 1549 // |
| 6975 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6976 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6977 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 6978 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 6979 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6980 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6981 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, |
| 6982 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 6983 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 6984 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6985 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 6986 | // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 6987 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBLv8i8_v8i16, |
| 6988 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 6989 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6990 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6991 | GIR_EraseFromParent, /*InsnID*/0, |
| 6992 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6993 | // GIR_Coverage, 1549, |
| 6994 | GIR_Done, |
| 6995 | // Label 384: @14928 |
| 6996 | GIM_Try, /*On fail goto*//*Label 385*/ 14964, // Rule ID 792 // |
| 6997 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 6998 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6999 | GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 7000 | GIM_CheckIsBuildVectorAllZeros, /*MI*/1, |
| 7001 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 7002 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7003 | // (sub:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$Rn) => (NEGv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) |
| 7004 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NEGv8i16, |
| 7005 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7006 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 7007 | GIR_EraseFromParent, /*InsnID*/0, |
| 7008 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7009 | // GIR_Coverage, 792, |
| 7010 | GIR_Done, |
| 7011 | // Label 385: @14964 |
| 7012 | GIM_Try, /*On fail goto*//*Label 386*/ 15009, // Rule ID 1574 // |
| 7013 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 7014 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 7015 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7016 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, |
| 7017 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 7018 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 7019 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7020 | // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (USUBWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 7021 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv8i8_v8i16, |
| 7022 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7023 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 7024 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 7025 | GIR_EraseFromParent, /*InsnID*/0, |
| 7026 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7027 | // GIR_Coverage, 1574, |
| 7028 | GIR_Done, |
| 7029 | // Label 386: @15009 |
| 7030 | GIM_Try, /*On fail goto*//*Label 387*/ 15054, // Rule ID 1477 // |
| 7031 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 7032 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 7033 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7034 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, |
| 7035 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 7036 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 7037 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7038 | // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (SSUBWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 7039 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSUBWv8i8_v8i16, |
| 7040 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7041 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 7042 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 7043 | GIR_EraseFromParent, /*InsnID*/0, |
| 7044 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7045 | // GIR_Coverage, 1477, |
| 7046 | GIR_Done, |
| 7047 | // Label 387: @15054 |
| 7048 | GIM_Try, /*On fail goto*//*Label 388*/ 15099, // Rule ID 1573 // |
| 7049 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 7050 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 7051 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7052 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 7053 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 7054 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 7055 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7056 | // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (USUBWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 7057 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USUBWv8i8_v8i16, |
| 7058 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7059 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 7060 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 7061 | GIR_EraseFromParent, /*InsnID*/0, |
| 7062 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7063 | // GIR_Coverage, 1573, |
| 7064 | GIR_Done, |
| 7065 | // Label 388: @15099 |
| 7066 | GIM_Try, /*On fail goto*//*Label 389*/ 15118, // Rule ID 1193 // |
| 7067 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 7068 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 7069 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 7070 | // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 7071 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv8i16, |
| 7072 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7073 | // GIR_Coverage, 1193, |
| 7074 | GIR_Done, |
| 7075 | // Label 389: @15118 |
| 7076 | GIM_Reject, |
| 7077 | // Label 377: @15119 |
| 7078 | GIM_Reject, |
| 7079 | // Label 311: @15120 |
| 7080 | GIM_Try, /*On fail goto*//*Label 390*/ 15190, |
| 7081 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 7082 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7083 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 7084 | GIM_Try, /*On fail goto*//*Label 391*/ 15170, // Rule ID 790 // |
| 7085 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 7086 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7087 | GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 7088 | GIM_CheckIsBuildVectorAllZeros, /*MI*/1, |
| 7089 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 7090 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7091 | // (sub:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rn) => (NEGv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) |
| 7092 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NEGv16i8, |
| 7093 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7094 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 7095 | GIR_EraseFromParent, /*InsnID*/0, |
| 7096 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7097 | // GIR_Coverage, 790, |
| 7098 | GIR_Done, |
| 7099 | // Label 391: @15170 |
| 7100 | GIM_Try, /*On fail goto*//*Label 392*/ 15189, // Rule ID 1191 // |
| 7101 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 7102 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 7103 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 7104 | // (sub:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 7105 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SUBv16i8, |
| 7106 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7107 | // GIR_Coverage, 1191, |
| 7108 | GIR_Done, |
| 7109 | // Label 392: @15189 |
| 7110 | GIM_Reject, |
| 7111 | // Label 390: @15190 |
| 7112 | GIM_Reject, |
| 7113 | // Label 312: @15191 |
| 7114 | GIM_Reject, |
| 7115 | // Label 2: @15192 |
| 7116 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 401*/ 16506, |
| 7117 | /*GILLT_s32*//*Label 393*/ 15208, |
| 7118 | /*GILLT_s64*//*Label 394*/ 15368, 0, |
| 7119 | /*GILLT_v2s32*//*Label 395*/ 15790, 0, |
| 7120 | /*GILLT_v4s16*//*Label 396*/ 15953, |
| 7121 | /*GILLT_v4s32*//*Label 397*/ 16116, |
| 7122 | /*GILLT_v8s8*//*Label 398*/ 16279, |
| 7123 | /*GILLT_v8s16*//*Label 399*/ 16311, |
| 7124 | /*GILLT_v16s8*//*Label 400*/ 16474, |
| 7125 | // Label 393: @15208 |
| 7126 | GIM_Try, /*On fail goto*//*Label 402*/ 15367, |
| 7127 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 7128 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 7129 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 7130 | GIM_Try, /*On fail goto*//*Label 403*/ 15277, // Rule ID 3501 // |
| 7131 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7132 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, |
| 7133 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7134 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7135 | GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0, |
| 7136 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 7137 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 7138 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7139 | // (mul:{ *:[i32] } (sub:{ *:[i32] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rn), GPR32:{ *:[i32] }:$Rm) => (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] }) |
| 7140 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBWrrr, |
| 7141 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7142 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 7143 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 7144 | GIR_AddRegister, /*InsnID*/0, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 7145 | GIR_EraseFromParent, /*InsnID*/0, |
| 7146 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7147 | // GIR_Coverage, 3501, |
| 7148 | GIR_Done, |
| 7149 | // Label 403: @15277 |
| 7150 | GIM_Try, /*On fail goto*//*Label 404*/ 15332, // Rule ID 7922 // |
| 7151 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 7152 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7153 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, |
| 7154 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7155 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7156 | GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0, |
| 7157 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 7158 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7159 | // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, (sub:{ *:[i32] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rn)) => (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] }) |
| 7160 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBWrrr, |
| 7161 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7162 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 7163 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm |
| 7164 | GIR_AddRegister, /*InsnID*/0, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 7165 | GIR_EraseFromParent, /*InsnID*/0, |
| 7166 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7167 | // GIR_Coverage, 7922, |
| 7168 | GIR_Done, |
| 7169 | // Label 404: @15332 |
| 7170 | GIM_Try, /*On fail goto*//*Label 405*/ 15366, // Rule ID 3497 // |
| 7171 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 7172 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 7173 | // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (MADDWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] }) |
| 7174 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MADDWrrr, |
| 7175 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7176 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 7177 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 7178 | GIR_AddRegister, /*InsnID*/0, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 7179 | GIR_EraseFromParent, /*InsnID*/0, |
| 7180 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7181 | // GIR_Coverage, 3497, |
| 7182 | GIR_Done, |
| 7183 | // Label 405: @15366 |
| 7184 | GIM_Reject, |
| 7185 | // Label 402: @15367 |
| 7186 | GIM_Reject, |
| 7187 | // Label 394: @15368 |
| 7188 | GIM_Try, /*On fail goto*//*Label 406*/ 15789, |
| 7189 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 7190 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 7191 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 7192 | GIM_Try, /*On fail goto*//*Label 407*/ 15437, // Rule ID 3502 // |
| 7193 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7194 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, |
| 7195 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 7196 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 7197 | GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0, |
| 7198 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 7199 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 7200 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7201 | // (mul:{ *:[i64] } (sub:{ *:[i64] } 0:{ *:[i64] }, GPR64:{ *:[i64] }:$Rn), GPR64:{ *:[i64] }:$Rm) => (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] }) |
| 7202 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBXrrr, |
| 7203 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7204 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 7205 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 7206 | GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, |
| 7207 | GIR_EraseFromParent, /*InsnID*/0, |
| 7208 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7209 | // GIR_Coverage, 3502, |
| 7210 | GIR_Done, |
| 7211 | // Label 407: @15437 |
| 7212 | GIM_Try, /*On fail goto*//*Label 408*/ 15492, // Rule ID 7923 // |
| 7213 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 7214 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7215 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, |
| 7216 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 7217 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 7218 | GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0, |
| 7219 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 7220 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7221 | // (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, (sub:{ *:[i64] } 0:{ *:[i64] }, GPR64:{ *:[i64] }:$Rn)) => (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] }) |
| 7222 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MSUBXrrr, |
| 7223 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7224 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 7225 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm |
| 7226 | GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, |
| 7227 | GIR_EraseFromParent, /*InsnID*/0, |
| 7228 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7229 | // GIR_Coverage, 7923, |
| 7230 | GIR_Done, |
| 7231 | // Label 408: @15492 |
| 7232 | GIM_Try, /*On fail goto*//*Label 409*/ 15563, // Rule ID 3511 // |
| 7233 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7234 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, |
| 7235 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7236 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 7237 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7238 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 7239 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_s64imm_32bit, |
| 7240 | // MIs[2] Operand 1 |
| 7241 | // No operand predicates |
| 7242 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7243 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 7244 | // (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] }) |
| 7245 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 7246 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, |
| 7247 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 7248 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/2, /*Renderer*/GICR_renderTruncImm, // C |
| 7249 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7250 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr, |
| 7251 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7252 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 7253 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 7254 | GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, |
| 7255 | GIR_EraseFromParent, /*InsnID*/0, |
| 7256 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7257 | // GIR_Coverage, 3511, |
| 7258 | GIR_Done, |
| 7259 | // Label 409: @15563 |
| 7260 | GIM_Try, /*On fail goto*//*Label 410*/ 15634, // Rule ID 3512 // |
| 7261 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7262 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 7263 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7264 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 7265 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7266 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 7267 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit, |
| 7268 | // MIs[2] Operand 1 |
| 7269 | // No operand predicates |
| 7270 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7271 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 7272 | // (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] }) |
| 7273 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 7274 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, |
| 7275 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 7276 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/2, /*Renderer*/GICR_renderTruncImm, // C |
| 7277 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7278 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr, |
| 7279 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7280 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 7281 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 7282 | GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, |
| 7283 | GIR_EraseFromParent, /*InsnID*/0, |
| 7284 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7285 | // GIR_Coverage, 3512, |
| 7286 | GIR_Done, |
| 7287 | // Label 410: @15634 |
| 7288 | GIM_Try, /*On fail goto*//*Label 411*/ 15694, // Rule ID 3505 // |
| 7289 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7290 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, |
| 7291 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7292 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 7293 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7294 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, |
| 7295 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7296 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 7297 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7298 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 7299 | // (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] }) |
| 7300 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMADDLrrr, |
| 7301 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7302 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 7303 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7304 | GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, |
| 7305 | GIR_EraseFromParent, /*InsnID*/0, |
| 7306 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7307 | // GIR_Coverage, 3505, |
| 7308 | GIR_Done, |
| 7309 | // Label 411: @15694 |
| 7310 | GIM_Try, /*On fail goto*//*Label 412*/ 15754, // Rule ID 3508 // |
| 7311 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7312 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 7313 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7314 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 7315 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7316 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, |
| 7317 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7318 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 7319 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7320 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 7321 | // (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] }) |
| 7322 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMADDLrrr, |
| 7323 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7324 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 7325 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7326 | GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, |
| 7327 | GIR_EraseFromParent, /*InsnID*/0, |
| 7328 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7329 | // GIR_Coverage, 3508, |
| 7330 | GIR_Done, |
| 7331 | // Label 412: @15754 |
| 7332 | GIM_Try, /*On fail goto*//*Label 413*/ 15788, // Rule ID 3498 // |
| 7333 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 7334 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 7335 | // (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (MADDXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] }) |
| 7336 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MADDXrrr, |
| 7337 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7338 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 7339 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 7340 | GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, |
| 7341 | GIR_EraseFromParent, /*InsnID*/0, |
| 7342 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7343 | // GIR_Coverage, 3498, |
| 7344 | GIR_Done, |
| 7345 | // Label 413: @15788 |
| 7346 | GIM_Reject, |
| 7347 | // Label 406: @15789 |
| 7348 | GIM_Reject, |
| 7349 | // Label 395: @15790 |
| 7350 | GIM_Try, /*On fail goto*//*Label 414*/ 15952, |
| 7351 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 7352 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 7353 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 7354 | GIM_Try, /*On fail goto*//*Label 415*/ 15868, // Rule ID 7772 // |
| 7355 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 7356 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7357 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 7358 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 7359 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 7360 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 7361 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 7362 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 7363 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 7364 | // MIs[2] Operand 1 |
| 7365 | // No operand predicates |
| 7366 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 7367 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7368 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 7369 | // (mul:{ *:[v2i32] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn) => (MULv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 7370 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MULv2i32_indexed, |
| 7371 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7372 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 7373 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 7374 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 7375 | GIR_EraseFromParent, /*InsnID*/0, |
| 7376 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7377 | // GIR_Coverage, 7772, |
| 7378 | GIR_Done, |
| 7379 | // Label 415: @15868 |
| 7380 | GIM_Try, /*On fail goto*//*Label 416*/ 15932, // Rule ID 1716 // |
| 7381 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 7382 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 7383 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7384 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 7385 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 7386 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 7387 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 7388 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 7389 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 7390 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 7391 | // MIs[2] Operand 1 |
| 7392 | // No operand predicates |
| 7393 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7394 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 7395 | // (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (MULv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 7396 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MULv2i32_indexed, |
| 7397 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7398 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 7399 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 7400 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 7401 | GIR_EraseFromParent, /*InsnID*/0, |
| 7402 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7403 | // GIR_Coverage, 1716, |
| 7404 | GIR_Done, |
| 7405 | // Label 416: @15932 |
| 7406 | GIM_Try, /*On fail goto*//*Label 417*/ 15951, // Rule ID 1070 // |
| 7407 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 7408 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 7409 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 7410 | // (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (MULv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 7411 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::MULv2i32, |
| 7412 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7413 | // GIR_Coverage, 1070, |
| 7414 | GIR_Done, |
| 7415 | // Label 417: @15951 |
| 7416 | GIM_Reject, |
| 7417 | // Label 414: @15952 |
| 7418 | GIM_Reject, |
| 7419 | // Label 396: @15953 |
| 7420 | GIM_Try, /*On fail goto*//*Label 418*/ 16115, |
| 7421 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 7422 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 7423 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 7424 | GIM_Try, /*On fail goto*//*Label 419*/ 16031, // Rule ID 7770 // |
| 7425 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 7426 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7427 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 7428 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 7429 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 7430 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 7431 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 7432 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 7433 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 7434 | // MIs[2] Operand 1 |
| 7435 | // No operand predicates |
| 7436 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 7437 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7438 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 7439 | // (mul:{ *:[v4i16] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn) => (MULv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 7440 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MULv4i16_indexed, |
| 7441 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7442 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 7443 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 7444 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 7445 | GIR_EraseFromParent, /*InsnID*/0, |
| 7446 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7447 | // GIR_Coverage, 7770, |
| 7448 | GIR_Done, |
| 7449 | // Label 419: @16031 |
| 7450 | GIM_Try, /*On fail goto*//*Label 420*/ 16095, // Rule ID 1714 // |
| 7451 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 7452 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 7453 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7454 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 7455 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 7456 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 7457 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 7458 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 7459 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 7460 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 7461 | // MIs[2] Operand 1 |
| 7462 | // No operand predicates |
| 7463 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7464 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 7465 | // (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (MULv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 7466 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MULv4i16_indexed, |
| 7467 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7468 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 7469 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 7470 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 7471 | GIR_EraseFromParent, /*InsnID*/0, |
| 7472 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7473 | // GIR_Coverage, 1714, |
| 7474 | GIR_Done, |
| 7475 | // Label 420: @16095 |
| 7476 | GIM_Try, /*On fail goto*//*Label 421*/ 16114, // Rule ID 1068 // |
| 7477 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 7478 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 7479 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 7480 | // (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (MULv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 7481 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::MULv4i16, |
| 7482 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7483 | // GIR_Coverage, 1068, |
| 7484 | GIR_Done, |
| 7485 | // Label 421: @16114 |
| 7486 | GIM_Reject, |
| 7487 | // Label 418: @16115 |
| 7488 | GIM_Reject, |
| 7489 | // Label 397: @16116 |
| 7490 | GIM_Try, /*On fail goto*//*Label 422*/ 16278, |
| 7491 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 7492 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7493 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 7494 | GIM_Try, /*On fail goto*//*Label 423*/ 16194, // Rule ID 7773 // |
| 7495 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 7496 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7497 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 7498 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 7499 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 7500 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 7501 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 7502 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 7503 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 7504 | // MIs[2] Operand 1 |
| 7505 | // No operand predicates |
| 7506 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 7507 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7508 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 7509 | // (mul:{ *:[v4i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4i32] }:$Rn) => (MULv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 7510 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MULv4i32_indexed, |
| 7511 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7512 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 7513 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 7514 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 7515 | GIR_EraseFromParent, /*InsnID*/0, |
| 7516 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7517 | // GIR_Coverage, 7773, |
| 7518 | GIR_Done, |
| 7519 | // Label 423: @16194 |
| 7520 | GIM_Try, /*On fail goto*//*Label 424*/ 16258, // Rule ID 1717 // |
| 7521 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 7522 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 7523 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7524 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 7525 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 7526 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 7527 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 7528 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 7529 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 7530 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 7531 | // MIs[2] Operand 1 |
| 7532 | // No operand predicates |
| 7533 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7534 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 7535 | // (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (MULv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 7536 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MULv4i32_indexed, |
| 7537 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7538 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 7539 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 7540 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 7541 | GIR_EraseFromParent, /*InsnID*/0, |
| 7542 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7543 | // GIR_Coverage, 1717, |
| 7544 | GIR_Done, |
| 7545 | // Label 424: @16258 |
| 7546 | GIM_Try, /*On fail goto*//*Label 425*/ 16277, // Rule ID 1071 // |
| 7547 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 7548 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 7549 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 7550 | // (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (MULv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 7551 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::MULv4i32, |
| 7552 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7553 | // GIR_Coverage, 1071, |
| 7554 | GIR_Done, |
| 7555 | // Label 425: @16277 |
| 7556 | GIM_Reject, |
| 7557 | // Label 422: @16278 |
| 7558 | GIM_Reject, |
| 7559 | // Label 398: @16279 |
| 7560 | GIM_Try, /*On fail goto*//*Label 426*/ 16310, // Rule ID 1066 // |
| 7561 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 7562 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 7563 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 7564 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 7565 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 7566 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 7567 | // (mul:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (MULv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 7568 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::MULv8i8, |
| 7569 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7570 | // GIR_Coverage, 1066, |
| 7571 | GIR_Done, |
| 7572 | // Label 426: @16310 |
| 7573 | GIM_Reject, |
| 7574 | // Label 399: @16311 |
| 7575 | GIM_Try, /*On fail goto*//*Label 427*/ 16473, |
| 7576 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 7577 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 7578 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 7579 | GIM_Try, /*On fail goto*//*Label 428*/ 16389, // Rule ID 7771 // |
| 7580 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 7581 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7582 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 7583 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 7584 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 7585 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 7586 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 7587 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 7588 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 7589 | // MIs[2] Operand 1 |
| 7590 | // No operand predicates |
| 7591 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 7592 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7593 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 7594 | // (mul:{ *:[v8i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8i16] }:$Rn) => (MULv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 7595 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MULv8i16_indexed, |
| 7596 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7597 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 7598 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 7599 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 7600 | GIR_EraseFromParent, /*InsnID*/0, |
| 7601 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7602 | // GIR_Coverage, 7771, |
| 7603 | GIR_Done, |
| 7604 | // Label 428: @16389 |
| 7605 | GIM_Try, /*On fail goto*//*Label 429*/ 16453, // Rule ID 1715 // |
| 7606 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 7607 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 7608 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7609 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 7610 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 7611 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 7612 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 7613 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 7614 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 7615 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 7616 | // MIs[2] Operand 1 |
| 7617 | // No operand predicates |
| 7618 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7619 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 7620 | // (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (MULv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 7621 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MULv8i16_indexed, |
| 7622 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7623 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 7624 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 7625 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 7626 | GIR_EraseFromParent, /*InsnID*/0, |
| 7627 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7628 | // GIR_Coverage, 1715, |
| 7629 | GIR_Done, |
| 7630 | // Label 429: @16453 |
| 7631 | GIM_Try, /*On fail goto*//*Label 430*/ 16472, // Rule ID 1069 // |
| 7632 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 7633 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 7634 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 7635 | // (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (MULv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 7636 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::MULv8i16, |
| 7637 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7638 | // GIR_Coverage, 1069, |
| 7639 | GIR_Done, |
| 7640 | // Label 430: @16472 |
| 7641 | GIM_Reject, |
| 7642 | // Label 427: @16473 |
| 7643 | GIM_Reject, |
| 7644 | // Label 400: @16474 |
| 7645 | GIM_Try, /*On fail goto*//*Label 431*/ 16505, // Rule ID 1067 // |
| 7646 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 7647 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 7648 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7649 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 7650 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 7651 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 7652 | // (mul:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (MULv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 7653 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::MULv16i8, |
| 7654 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7655 | // GIR_Coverage, 1067, |
| 7656 | GIR_Done, |
| 7657 | // Label 431: @16505 |
| 7658 | GIM_Reject, |
| 7659 | // Label 401: @16506 |
| 7660 | GIM_Reject, |
| 7661 | // Label 3: @16507 |
| 7662 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 434*/ 16575, |
| 7663 | /*GILLT_s32*//*Label 432*/ 16515, |
| 7664 | /*GILLT_s64*//*Label 433*/ 16545, |
| 7665 | // Label 432: @16515 |
| 7666 | GIM_Try, /*On fail goto*//*Label 435*/ 16544, // Rule ID 108 // |
| 7667 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 7668 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 7669 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 7670 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 7671 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 7672 | // (sdiv:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (SDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 7673 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SDIVWr, |
| 7674 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7675 | // GIR_Coverage, 108, |
| 7676 | GIR_Done, |
| 7677 | // Label 435: @16544 |
| 7678 | GIM_Reject, |
| 7679 | // Label 433: @16545 |
| 7680 | GIM_Try, /*On fail goto*//*Label 436*/ 16574, // Rule ID 109 // |
| 7681 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 7682 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 7683 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 7684 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 7685 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 7686 | // (sdiv:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (SDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) |
| 7687 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SDIVXr, |
| 7688 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7689 | // GIR_Coverage, 109, |
| 7690 | GIR_Done, |
| 7691 | // Label 436: @16574 |
| 7692 | GIM_Reject, |
| 7693 | // Label 434: @16575 |
| 7694 | GIM_Reject, |
| 7695 | // Label 4: @16576 |
| 7696 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 439*/ 16644, |
| 7697 | /*GILLT_s32*//*Label 437*/ 16584, |
| 7698 | /*GILLT_s64*//*Label 438*/ 16614, |
| 7699 | // Label 437: @16584 |
| 7700 | GIM_Try, /*On fail goto*//*Label 440*/ 16613, // Rule ID 106 // |
| 7701 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 7702 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 7703 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 7704 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 7705 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 7706 | // (udiv:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (UDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 7707 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UDIVWr, |
| 7708 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7709 | // GIR_Coverage, 106, |
| 7710 | GIR_Done, |
| 7711 | // Label 440: @16613 |
| 7712 | GIM_Reject, |
| 7713 | // Label 438: @16614 |
| 7714 | GIM_Try, /*On fail goto*//*Label 441*/ 16643, // Rule ID 107 // |
| 7715 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 7716 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 7717 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 7718 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 7719 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 7720 | // (udiv:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (UDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) |
| 7721 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UDIVXr, |
| 7722 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7723 | // GIR_Coverage, 107, |
| 7724 | GIR_Done, |
| 7725 | // Label 441: @16643 |
| 7726 | GIM_Reject, |
| 7727 | // Label 439: @16644 |
| 7728 | GIM_Reject, |
| 7729 | // Label 5: @16645 |
| 7730 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 451*/ 20263, |
| 7731 | /*GILLT_s32*//*Label 442*/ 16661, |
| 7732 | /*GILLT_s64*//*Label 443*/ 17148, 0, |
| 7733 | /*GILLT_v2s32*//*Label 444*/ 18310, |
| 7734 | /*GILLT_v2s64*//*Label 445*/ 18589, |
| 7735 | /*GILLT_v4s16*//*Label 446*/ 18868, |
| 7736 | /*GILLT_v4s32*//*Label 447*/ 19147, |
| 7737 | /*GILLT_v8s8*//*Label 448*/ 19426, |
| 7738 | /*GILLT_v8s16*//*Label 449*/ 19705, |
| 7739 | /*GILLT_v16s8*//*Label 450*/ 19984, |
| 7740 | // Label 442: @16661 |
| 7741 | GIM_Try, /*On fail goto*//*Label 452*/ 17147, |
| 7742 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 7743 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 7744 | GIM_Try, /*On fail goto*//*Label 453*/ 16726, // Rule ID 7556 // |
| 7745 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 7746 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7747 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 7748 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7749 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7750 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 7751 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 7752 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7753 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, |
| 7754 | // (and:{ *:[i32] } (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn) => (BICWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) |
| 7755 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICWrs, |
| 7756 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7757 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 7758 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 7759 | GIR_EraseFromParent, /*InsnID*/0, |
| 7760 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7761 | // GIR_Coverage, 7556, |
| 7762 | GIR_Done, |
| 7763 | // Label 453: @16726 |
| 7764 | GIM_Try, /*On fail goto*//*Label 454*/ 16781, // Rule ID 153 // |
| 7765 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 7766 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 7767 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7768 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 7769 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7770 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7771 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 7772 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7773 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, |
| 7774 | // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (BICWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) |
| 7775 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICWrs, |
| 7776 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7777 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 7778 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 7779 | GIR_EraseFromParent, /*InsnID*/0, |
| 7780 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7781 | // GIR_Coverage, 153, |
| 7782 | GIR_Done, |
| 7783 | // Label 454: @16781 |
| 7784 | GIM_Try, /*On fail goto*//*Label 455*/ 16843, // Rule ID 4403 // |
| 7785 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 7786 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7787 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 7788 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 7789 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 7790 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 7791 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 7792 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 7793 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexB, |
| 7794 | // MIs[2] Operand 1 |
| 7795 | // No operand predicates |
| 7796 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255, |
| 7797 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7798 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 7799 | // (and:{ *:[i32] } (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx), 255:{ *:[i32] }) => (UMOVvi8:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx) |
| 7800 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi8, |
| 7801 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7802 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 7803 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 7804 | GIR_EraseFromParent, /*InsnID*/0, |
| 7805 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7806 | // GIR_Coverage, 4403, |
| 7807 | GIR_Done, |
| 7808 | // Label 455: @16843 |
| 7809 | GIM_Try, /*On fail goto*//*Label 456*/ 16905, // Rule ID 4404 // |
| 7810 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 7811 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7812 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 7813 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 7814 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 7815 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 7816 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 7817 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 7818 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 7819 | // MIs[2] Operand 1 |
| 7820 | // No operand predicates |
| 7821 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535, |
| 7822 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7823 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 7824 | // (and:{ *:[i32] } (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 65535:{ *:[i32] }) => (UMOVvi16:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) |
| 7825 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi16, |
| 7826 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7827 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 7828 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 7829 | GIR_EraseFromParent, /*InsnID*/0, |
| 7830 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7831 | // GIR_Coverage, 4404, |
| 7832 | GIR_Done, |
| 7833 | // Label 456: @16905 |
| 7834 | GIM_Try, /*On fail goto*//*Label 457*/ 16947, // Rule ID 133 // |
| 7835 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, |
| 7836 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 7837 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7838 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 7839 | GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_logical_imm32, |
| 7840 | // MIs[1] Operand 1 |
| 7841 | // No operand predicates |
| 7842 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7843 | // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_logical_imm32>><<X:logical_imm32_XFORM>>:$imm) => (ANDWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (logical_imm32_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm)) |
| 7844 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ANDWri, |
| 7845 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7846 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 7847 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GICR_renderLogicalImm32, // imm |
| 7848 | GIR_EraseFromParent, /*InsnID*/0, |
| 7849 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7850 | // GIR_Coverage, 133, |
| 7851 | GIR_Done, |
| 7852 | // Label 457: @16947 |
| 7853 | GIM_Try, /*On fail goto*//*Label 458*/ 16981, // Rule ID 7552 // |
| 7854 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 7855 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 7856 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, |
| 7857 | // (and:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm, GPR32:{ *:[i32] }:$Rn) => (ANDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) |
| 7858 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ANDWrs, |
| 7859 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7860 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 7861 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 7862 | GIR_EraseFromParent, /*InsnID*/0, |
| 7863 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7864 | // GIR_Coverage, 7552, |
| 7865 | GIR_Done, |
| 7866 | // Label 458: @16981 |
| 7867 | GIM_Try, /*On fail goto*//*Label 459*/ 17015, // Rule ID 149 // |
| 7868 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 7869 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 7870 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg32, |
| 7871 | // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) => (ANDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) |
| 7872 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ANDWrs, |
| 7873 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7874 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 7875 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 7876 | GIR_EraseFromParent, /*InsnID*/0, |
| 7877 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7878 | // GIR_Coverage, 149, |
| 7879 | GIR_Done, |
| 7880 | // Label 459: @17015 |
| 7881 | GIM_Try, /*On fail goto*//*Label 460*/ 17070, // Rule ID 7554 // |
| 7882 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 7883 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7884 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 7885 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7886 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7887 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 7888 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 7889 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 7890 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7891 | // (and:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn) => (BICWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 7892 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICWrr, |
| 7893 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7894 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 7895 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 7896 | GIR_EraseFromParent, /*InsnID*/0, |
| 7897 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7898 | // GIR_Coverage, 7554, |
| 7899 | GIR_Done, |
| 7900 | // Label 460: @17070 |
| 7901 | GIM_Try, /*On fail goto*//*Label 461*/ 17125, // Rule ID 151 // |
| 7902 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 7903 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 7904 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7905 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 7906 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7907 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7908 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 7909 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 7910 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7911 | // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (BICWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 7912 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICWrr, |
| 7913 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7914 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 7915 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 7916 | GIR_EraseFromParent, /*InsnID*/0, |
| 7917 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7918 | // GIR_Coverage, 151, |
| 7919 | GIR_Done, |
| 7920 | // Label 461: @17125 |
| 7921 | GIM_Try, /*On fail goto*//*Label 462*/ 17146, // Rule ID 147 // |
| 7922 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 7923 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 7924 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 7925 | // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (ANDWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 7926 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDWrr, |
| 7927 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7928 | // GIR_Coverage, 147, |
| 7929 | GIR_Done, |
| 7930 | // Label 462: @17146 |
| 7931 | GIM_Reject, |
| 7932 | // Label 452: @17147 |
| 7933 | GIM_Reject, |
| 7934 | // Label 443: @17148 |
| 7935 | GIM_Try, /*On fail goto*//*Label 463*/ 18309, |
| 7936 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 7937 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 7938 | GIM_Try, /*On fail goto*//*Label 464*/ 17213, // Rule ID 7557 // |
| 7939 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 7940 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7941 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 7942 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 7943 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 7944 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 7945 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 7946 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7947 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, |
| 7948 | // (and:{ *:[i64] } (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn) => (BICXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) |
| 7949 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICXrs, |
| 7950 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7951 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 7952 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 7953 | GIR_EraseFromParent, /*InsnID*/0, |
| 7954 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7955 | // GIR_Coverage, 7557, |
| 7956 | GIR_Done, |
| 7957 | // Label 464: @17213 |
| 7958 | GIM_Try, /*On fail goto*//*Label 465*/ 17268, // Rule ID 154 // |
| 7959 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 7960 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 7961 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7962 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 7963 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 7964 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 7965 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 7966 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7967 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, |
| 7968 | // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm, -1:{ *:[i64] })) => (BICXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) |
| 7969 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICXrs, |
| 7970 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 7971 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 7972 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 7973 | GIR_EraseFromParent, /*InsnID*/0, |
| 7974 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7975 | // GIR_Coverage, 154, |
| 7976 | GIR_Done, |
| 7977 | // Label 465: @17268 |
| 7978 | GIM_Try, /*On fail goto*//*Label 466*/ 17354, // Rule ID 5412 // |
| 7979 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 7980 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7981 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, |
| 7982 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 7983 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_ldxr, |
| 7984 | // MIs[1] addr |
| 7985 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64, |
| 7986 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, |
| 7987 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_ldxr_1, |
| 7988 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255, |
| 7989 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 7990 | // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 356:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_1>>, 255:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) |
| 7991 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 7992 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDXRB, |
| 7993 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 7994 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr |
| 7995 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 7996 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7997 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 7998 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 7999 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 8000 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 8001 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 8002 | GIR_EraseFromParent, /*InsnID*/0, |
| 8003 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 8004 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 8005 | // GIR_Coverage, 5412, |
| 8006 | GIR_Done, |
| 8007 | // Label 466: @17354 |
| 8008 | GIM_Try, /*On fail goto*//*Label 467*/ 17440, // Rule ID 5413 // |
| 8009 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 8010 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8011 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, |
| 8012 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 8013 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_ldxr, |
| 8014 | // MIs[1] addr |
| 8015 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64, |
| 8016 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, |
| 8017 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_ldxr_2, |
| 8018 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535, |
| 8019 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8020 | // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 356:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_2>>, 65535:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) |
| 8021 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 8022 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDXRH, |
| 8023 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 8024 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr |
| 8025 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 8026 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8027 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 8028 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 8029 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 8030 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 8031 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 8032 | GIR_EraseFromParent, /*InsnID*/0, |
| 8033 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 8034 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 8035 | // GIR_Coverage, 5413, |
| 8036 | GIR_Done, |
| 8037 | // Label 467: @17440 |
| 8038 | GIM_Try, /*On fail goto*//*Label 468*/ 17526, // Rule ID 5414 // |
| 8039 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 8040 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8041 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, |
| 8042 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 8043 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_ldxr, |
| 8044 | // MIs[1] addr |
| 8045 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64, |
| 8046 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, |
| 8047 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_ldxr_4, |
| 8048 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 4294967295, |
| 8049 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8050 | // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 356:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_4>>, 4294967295:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) |
| 8051 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 8052 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDXRW, |
| 8053 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 8054 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr |
| 8055 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 8056 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8057 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 8058 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 8059 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 8060 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 8061 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 8062 | GIR_EraseFromParent, /*InsnID*/0, |
| 8063 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 8064 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 8065 | // GIR_Coverage, 5414, |
| 8066 | GIR_Done, |
| 8067 | // Label 468: @17526 |
| 8068 | GIM_Try, /*On fail goto*//*Label 469*/ 17612, // Rule ID 5419 // |
| 8069 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 8070 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8071 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, |
| 8072 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 8073 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_ldaxr, |
| 8074 | // MIs[1] addr |
| 8075 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64, |
| 8076 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, |
| 8077 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_ldaxr_1, |
| 8078 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255, |
| 8079 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8080 | // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 353:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_1>>, 255:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) |
| 8081 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 8082 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDAXRB, |
| 8083 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 8084 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr |
| 8085 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 8086 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8087 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 8088 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 8089 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 8090 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 8091 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 8092 | GIR_EraseFromParent, /*InsnID*/0, |
| 8093 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 8094 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 8095 | // GIR_Coverage, 5419, |
| 8096 | GIR_Done, |
| 8097 | // Label 469: @17612 |
| 8098 | GIM_Try, /*On fail goto*//*Label 470*/ 17698, // Rule ID 5420 // |
| 8099 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 8100 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8101 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, |
| 8102 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 8103 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_ldaxr, |
| 8104 | // MIs[1] addr |
| 8105 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64, |
| 8106 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, |
| 8107 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_ldaxr_2, |
| 8108 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535, |
| 8109 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8110 | // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 353:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_2>>, 65535:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) |
| 8111 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 8112 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDAXRH, |
| 8113 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 8114 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr |
| 8115 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 8116 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8117 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 8118 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 8119 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 8120 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 8121 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 8122 | GIR_EraseFromParent, /*InsnID*/0, |
| 8123 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 8124 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 8125 | // GIR_Coverage, 5420, |
| 8126 | GIR_Done, |
| 8127 | // Label 470: @17698 |
| 8128 | GIM_Try, /*On fail goto*//*Label 471*/ 17784, // Rule ID 5421 // |
| 8129 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 8130 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8131 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, |
| 8132 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 8133 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_ldaxr, |
| 8134 | // MIs[1] addr |
| 8135 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64, |
| 8136 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, |
| 8137 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_ldaxr_4, |
| 8138 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 4294967295, |
| 8139 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8140 | // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 353:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_4>>, 4294967295:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) |
| 8141 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 8142 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDAXRW, |
| 8143 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 8144 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr |
| 8145 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 8146 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8147 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 8148 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 8149 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 8150 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 8151 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 8152 | GIR_EraseFromParent, /*InsnID*/0, |
| 8153 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 8154 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 8155 | // GIR_Coverage, 5421, |
| 8156 | GIR_Done, |
| 8157 | // Label 471: @17784 |
| 8158 | GIM_Try, /*On fail goto*//*Label 472*/ 17826, // Rule ID 134 // |
| 8159 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, |
| 8160 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 8161 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8162 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 8163 | GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_logical_imm64, |
| 8164 | // MIs[1] Operand 1 |
| 8165 | // No operand predicates |
| 8166 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8167 | // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_logical_imm64>><<X:logical_imm64_XFORM>>:$imm) => (ANDXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (logical_imm64_XFORM:{ *:[i64] } (imm:{ *:[i64] }):$imm)) |
| 8168 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ANDXri, |
| 8169 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8170 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 8171 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GICR_renderLogicalImm64, // imm |
| 8172 | GIR_EraseFromParent, /*InsnID*/0, |
| 8173 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8174 | // GIR_Coverage, 134, |
| 8175 | GIR_Done, |
| 8176 | // Label 472: @17826 |
| 8177 | GIM_Try, /*On fail goto*//*Label 473*/ 17860, // Rule ID 7553 // |
| 8178 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 8179 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 8180 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, |
| 8181 | // (and:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm, GPR64:{ *:[i64] }:$Rn) => (ANDXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) |
| 8182 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ANDXrs, |
| 8183 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8184 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 8185 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 8186 | GIR_EraseFromParent, /*InsnID*/0, |
| 8187 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8188 | // GIR_Coverage, 7553, |
| 8189 | GIR_Done, |
| 8190 | // Label 473: @17860 |
| 8191 | GIM_Try, /*On fail goto*//*Label 474*/ 17894, // Rule ID 150 // |
| 8192 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 8193 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 8194 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg64, |
| 8195 | // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) => (ANDXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) |
| 8196 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ANDXrs, |
| 8197 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8198 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 8199 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 8200 | GIR_EraseFromParent, /*InsnID*/0, |
| 8201 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8202 | // GIR_Coverage, 150, |
| 8203 | GIR_Done, |
| 8204 | // Label 474: @17894 |
| 8205 | GIM_Try, /*On fail goto*//*Label 475*/ 17949, // Rule ID 7555 // |
| 8206 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 8207 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8208 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8209 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 8210 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 8211 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 8212 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 8213 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 8214 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8215 | // (and:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn) => (BICXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) |
| 8216 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICXrr, |
| 8217 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8218 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 8219 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 8220 | GIR_EraseFromParent, /*InsnID*/0, |
| 8221 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8222 | // GIR_Coverage, 7555, |
| 8223 | GIR_Done, |
| 8224 | // Label 475: @17949 |
| 8225 | GIM_Try, /*On fail goto*//*Label 476*/ 18004, // Rule ID 152 // |
| 8226 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 8227 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 8228 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8229 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8230 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 8231 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 8232 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 8233 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 8234 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8235 | // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] })) => (BICXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) |
| 8236 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICXrr, |
| 8237 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8238 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 8239 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 8240 | GIR_EraseFromParent, /*InsnID*/0, |
| 8241 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8242 | // GIR_Coverage, 152, |
| 8243 | GIR_Done, |
| 8244 | // Label 476: @18004 |
| 8245 | GIM_Try, /*On fail goto*//*Label 477*/ 18069, // Rule ID 7969 // |
| 8246 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8247 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 8248 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8249 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8250 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 8251 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 8252 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8253 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8254 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8255 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 8256 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 8257 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8258 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8259 | // (and:{ *:[v1i64] } (xor:{ *:[v1i64] } immAllOnesV:{ *:[v1i64] }, V64:{ *:[v1i64] }:$RHS), V64:{ *:[v1i64] }:$LHS) => (BICv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) |
| 8260 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv8i8, |
| 8261 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8262 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS |
| 8263 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 8264 | GIR_EraseFromParent, /*InsnID*/0, |
| 8265 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8266 | // GIR_Coverage, 7969, |
| 8267 | GIR_Done, |
| 8268 | // Label 477: @18069 |
| 8269 | GIM_Try, /*On fail goto*//*Label 478*/ 18134, // Rule ID 7968 // |
| 8270 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8271 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 8272 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8273 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8274 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 8275 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 8276 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 8277 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8278 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8279 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8280 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 8281 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8282 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8283 | // (and:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$LHS) => (BICv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) |
| 8284 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv8i8, |
| 8285 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8286 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS |
| 8287 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 8288 | GIR_EraseFromParent, /*InsnID*/0, |
| 8289 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8290 | // GIR_Coverage, 7968, |
| 8291 | GIR_Done, |
| 8292 | // Label 478: @18134 |
| 8293 | GIM_Try, /*On fail goto*//*Label 479*/ 18199, // Rule ID 7967 // |
| 8294 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8295 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 8296 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 8297 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8298 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8299 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 8300 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 8301 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8302 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8303 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8304 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 8305 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8306 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8307 | // (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, (xor:{ *:[v1i64] } immAllOnesV:{ *:[v1i64] }, V64:{ *:[v1i64] }:$RHS)) => (BICv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) |
| 8308 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv8i8, |
| 8309 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8310 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS |
| 8311 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 8312 | GIR_EraseFromParent, /*InsnID*/0, |
| 8313 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8314 | // GIR_Coverage, 7967, |
| 8315 | GIR_Done, |
| 8316 | // Label 479: @18199 |
| 8317 | GIM_Try, /*On fail goto*//*Label 480*/ 18264, // Rule ID 4069 // |
| 8318 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8319 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 8320 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 8321 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8322 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8323 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 8324 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 8325 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 8326 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8327 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8328 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8329 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8330 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8331 | // (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, immAllOnesV:{ *:[v1i64] })) => (BICv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) |
| 8332 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv8i8, |
| 8333 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8334 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS |
| 8335 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 8336 | GIR_EraseFromParent, /*InsnID*/0, |
| 8337 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8338 | // GIR_Coverage, 4069, |
| 8339 | GIR_Done, |
| 8340 | // Label 480: @18264 |
| 8341 | GIM_Try, /*On fail goto*//*Label 481*/ 18285, // Rule ID 148 // |
| 8342 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 8343 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 8344 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 8345 | // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (ANDXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) |
| 8346 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDXrr, |
| 8347 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8348 | // GIR_Coverage, 148, |
| 8349 | GIR_Done, |
| 8350 | // Label 481: @18285 |
| 8351 | GIM_Try, /*On fail goto*//*Label 482*/ 18308, // Rule ID 2686 // |
| 8352 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8353 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 8354 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 8355 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 8356 | // (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) => (ANDv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) |
| 8357 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv8i8, |
| 8358 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8359 | // GIR_Coverage, 2686, |
| 8360 | GIR_Done, |
| 8361 | // Label 482: @18308 |
| 8362 | GIM_Reject, |
| 8363 | // Label 463: @18309 |
| 8364 | GIM_Reject, |
| 8365 | // Label 444: @18310 |
| 8366 | GIM_Try, /*On fail goto*//*Label 483*/ 18588, |
| 8367 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 8368 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 8369 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 8370 | GIM_Try, /*On fail goto*//*Label 484*/ 18385, // Rule ID 7966 // |
| 8371 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8372 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8373 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8374 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 8375 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 8376 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8377 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8378 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8379 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 8380 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 8381 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8382 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8383 | // (and:{ *:[v2i32] } (xor:{ *:[v2i32] } immAllOnesV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$RHS), V64:{ *:[v2i32] }:$LHS) => (BICv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) |
| 8384 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv8i8, |
| 8385 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8386 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS |
| 8387 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 8388 | GIR_EraseFromParent, /*InsnID*/0, |
| 8389 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8390 | // GIR_Coverage, 7966, |
| 8391 | GIR_Done, |
| 8392 | // Label 484: @18385 |
| 8393 | GIM_Try, /*On fail goto*//*Label 485*/ 18446, // Rule ID 7965 // |
| 8394 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8395 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8396 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8397 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 8398 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 8399 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 8400 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8401 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8402 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8403 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 8404 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8405 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8406 | // (and:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$LHS) => (BICv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) |
| 8407 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv8i8, |
| 8408 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8409 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS |
| 8410 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 8411 | GIR_EraseFromParent, /*InsnID*/0, |
| 8412 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8413 | // GIR_Coverage, 7965, |
| 8414 | GIR_Done, |
| 8415 | // Label 485: @18446 |
| 8416 | GIM_Try, /*On fail goto*//*Label 486*/ 18507, // Rule ID 7964 // |
| 8417 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8418 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 8419 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8420 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8421 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 8422 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 8423 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8424 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8425 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8426 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 8427 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8428 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8429 | // (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, (xor:{ *:[v2i32] } immAllOnesV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$RHS)) => (BICv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) |
| 8430 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv8i8, |
| 8431 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8432 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS |
| 8433 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 8434 | GIR_EraseFromParent, /*InsnID*/0, |
| 8435 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8436 | // GIR_Coverage, 7964, |
| 8437 | GIR_Done, |
| 8438 | // Label 486: @18507 |
| 8439 | GIM_Try, /*On fail goto*//*Label 487*/ 18568, // Rule ID 4068 // |
| 8440 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8441 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 8442 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8443 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8444 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 8445 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 8446 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 8447 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8448 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8449 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8450 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8451 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8452 | // (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, immAllOnesV:{ *:[v2i32] })) => (BICv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) |
| 8453 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv8i8, |
| 8454 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8455 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS |
| 8456 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 8457 | GIR_EraseFromParent, /*InsnID*/0, |
| 8458 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8459 | // GIR_Coverage, 4068, |
| 8460 | GIR_Done, |
| 8461 | // Label 487: @18568 |
| 8462 | GIM_Try, /*On fail goto*//*Label 488*/ 18587, // Rule ID 2685 // |
| 8463 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8464 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 8465 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 8466 | // (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (ANDv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) |
| 8467 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv8i8, |
| 8468 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8469 | // GIR_Coverage, 2685, |
| 8470 | GIR_Done, |
| 8471 | // Label 488: @18587 |
| 8472 | GIM_Reject, |
| 8473 | // Label 483: @18588 |
| 8474 | GIM_Reject, |
| 8475 | // Label 445: @18589 |
| 8476 | GIM_Try, /*On fail goto*//*Label 489*/ 18867, |
| 8477 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 8478 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8479 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 8480 | GIM_Try, /*On fail goto*//*Label 490*/ 18664, // Rule ID 7978 // |
| 8481 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8482 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8483 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8484 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 8485 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8486 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8487 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8488 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8489 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 8490 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 8491 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8492 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8493 | // (and:{ *:[v2i64] } (xor:{ *:[v2i64] } immAllOnesV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$RHS), V128:{ *:[v2i64] }:$LHS) => (BICv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) |
| 8494 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv16i8, |
| 8495 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8496 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS |
| 8497 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 8498 | GIR_EraseFromParent, /*InsnID*/0, |
| 8499 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8500 | // GIR_Coverage, 7978, |
| 8501 | GIR_Done, |
| 8502 | // Label 490: @18664 |
| 8503 | GIM_Try, /*On fail goto*//*Label 491*/ 18725, // Rule ID 7977 // |
| 8504 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8505 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8506 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8507 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 8508 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8509 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 8510 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8511 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8512 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8513 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 8514 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8515 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8516 | // (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$LHS) => (BICv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) |
| 8517 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv16i8, |
| 8518 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8519 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS |
| 8520 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 8521 | GIR_EraseFromParent, /*InsnID*/0, |
| 8522 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8523 | // GIR_Coverage, 7977, |
| 8524 | GIR_Done, |
| 8525 | // Label 491: @18725 |
| 8526 | GIM_Try, /*On fail goto*//*Label 492*/ 18786, // Rule ID 7976 // |
| 8527 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8528 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 8529 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8530 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8531 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 8532 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8533 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8534 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8535 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8536 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 8537 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8538 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8539 | // (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, (xor:{ *:[v2i64] } immAllOnesV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$RHS)) => (BICv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) |
| 8540 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv16i8, |
| 8541 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8542 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS |
| 8543 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 8544 | GIR_EraseFromParent, /*InsnID*/0, |
| 8545 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8546 | // GIR_Coverage, 7976, |
| 8547 | GIR_Done, |
| 8548 | // Label 492: @18786 |
| 8549 | GIM_Try, /*On fail goto*//*Label 493*/ 18847, // Rule ID 4072 // |
| 8550 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8551 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 8552 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8553 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8554 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 8555 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8556 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 8557 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8558 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8559 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8560 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8561 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8562 | // (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, immAllOnesV:{ *:[v2i64] })) => (BICv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) |
| 8563 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv16i8, |
| 8564 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8565 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS |
| 8566 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 8567 | GIR_EraseFromParent, /*InsnID*/0, |
| 8568 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8569 | // GIR_Coverage, 4072, |
| 8570 | GIR_Done, |
| 8571 | // Label 493: @18847 |
| 8572 | GIM_Try, /*On fail goto*//*Label 494*/ 18866, // Rule ID 2689 // |
| 8573 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8574 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 8575 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 8576 | // (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (ANDv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) |
| 8577 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv16i8, |
| 8578 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8579 | // GIR_Coverage, 2689, |
| 8580 | GIR_Done, |
| 8581 | // Label 494: @18866 |
| 8582 | GIM_Reject, |
| 8583 | // Label 489: @18867 |
| 8584 | GIM_Reject, |
| 8585 | // Label 446: @18868 |
| 8586 | GIM_Try, /*On fail goto*//*Label 495*/ 19146, |
| 8587 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8588 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 8589 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 8590 | GIM_Try, /*On fail goto*//*Label 496*/ 18943, // Rule ID 7963 // |
| 8591 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8592 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8593 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8594 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8595 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 8596 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8597 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8598 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8599 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 8600 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 8601 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8602 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8603 | // (and:{ *:[v4i16] } (xor:{ *:[v4i16] } immAllOnesV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$RHS), V64:{ *:[v4i16] }:$LHS) => (BICv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) |
| 8604 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv8i8, |
| 8605 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8606 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS |
| 8607 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 8608 | GIR_EraseFromParent, /*InsnID*/0, |
| 8609 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8610 | // GIR_Coverage, 7963, |
| 8611 | GIR_Done, |
| 8612 | // Label 496: @18943 |
| 8613 | GIM_Try, /*On fail goto*//*Label 497*/ 19004, // Rule ID 7962 // |
| 8614 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8615 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8616 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8617 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8618 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 8619 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 8620 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8621 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8622 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8623 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 8624 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8625 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8626 | // (and:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$LHS) => (BICv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) |
| 8627 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv8i8, |
| 8628 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8629 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS |
| 8630 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 8631 | GIR_EraseFromParent, /*InsnID*/0, |
| 8632 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8633 | // GIR_Coverage, 7962, |
| 8634 | GIR_Done, |
| 8635 | // Label 497: @19004 |
| 8636 | GIM_Try, /*On fail goto*//*Label 498*/ 19065, // Rule ID 7961 // |
| 8637 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8638 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 8639 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8640 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8641 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8642 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 8643 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8644 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8645 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8646 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 8647 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8648 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8649 | // (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, (xor:{ *:[v4i16] } immAllOnesV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$RHS)) => (BICv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) |
| 8650 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv8i8, |
| 8651 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8652 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS |
| 8653 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 8654 | GIR_EraseFromParent, /*InsnID*/0, |
| 8655 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8656 | // GIR_Coverage, 7961, |
| 8657 | GIR_Done, |
| 8658 | // Label 498: @19065 |
| 8659 | GIM_Try, /*On fail goto*//*Label 499*/ 19126, // Rule ID 4067 // |
| 8660 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8661 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 8662 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8663 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8664 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8665 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 8666 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 8667 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8668 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8669 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8670 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8671 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8672 | // (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, immAllOnesV:{ *:[v4i16] })) => (BICv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) |
| 8673 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv8i8, |
| 8674 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8675 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS |
| 8676 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 8677 | GIR_EraseFromParent, /*InsnID*/0, |
| 8678 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8679 | // GIR_Coverage, 4067, |
| 8680 | GIR_Done, |
| 8681 | // Label 499: @19126 |
| 8682 | GIM_Try, /*On fail goto*//*Label 500*/ 19145, // Rule ID 2684 // |
| 8683 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8684 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 8685 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 8686 | // (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (ANDv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) |
| 8687 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv8i8, |
| 8688 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8689 | // GIR_Coverage, 2684, |
| 8690 | GIR_Done, |
| 8691 | // Label 500: @19145 |
| 8692 | GIM_Reject, |
| 8693 | // Label 495: @19146 |
| 8694 | GIM_Reject, |
| 8695 | // Label 447: @19147 |
| 8696 | GIM_Try, /*On fail goto*//*Label 501*/ 19425, |
| 8697 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 8698 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8699 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 8700 | GIM_Try, /*On fail goto*//*Label 502*/ 19222, // Rule ID 7975 // |
| 8701 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8702 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8703 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8704 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 8705 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8706 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8707 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8708 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8709 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 8710 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 8711 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8712 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8713 | // (and:{ *:[v4i32] } (xor:{ *:[v4i32] } immAllOnesV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$RHS), V128:{ *:[v4i32] }:$LHS) => (BICv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) |
| 8714 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv16i8, |
| 8715 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8716 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS |
| 8717 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 8718 | GIR_EraseFromParent, /*InsnID*/0, |
| 8719 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8720 | // GIR_Coverage, 7975, |
| 8721 | GIR_Done, |
| 8722 | // Label 502: @19222 |
| 8723 | GIM_Try, /*On fail goto*//*Label 503*/ 19283, // Rule ID 7974 // |
| 8724 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8725 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8726 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8727 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 8728 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8729 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 8730 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8731 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8732 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8733 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 8734 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8735 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8736 | // (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$LHS) => (BICv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) |
| 8737 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv16i8, |
| 8738 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8739 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS |
| 8740 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 8741 | GIR_EraseFromParent, /*InsnID*/0, |
| 8742 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8743 | // GIR_Coverage, 7974, |
| 8744 | GIR_Done, |
| 8745 | // Label 503: @19283 |
| 8746 | GIM_Try, /*On fail goto*//*Label 504*/ 19344, // Rule ID 7973 // |
| 8747 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8748 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 8749 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8750 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8751 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 8752 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8753 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8754 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8755 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8756 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 8757 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8758 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8759 | // (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, (xor:{ *:[v4i32] } immAllOnesV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$RHS)) => (BICv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) |
| 8760 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv16i8, |
| 8761 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8762 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS |
| 8763 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 8764 | GIR_EraseFromParent, /*InsnID*/0, |
| 8765 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8766 | // GIR_Coverage, 7973, |
| 8767 | GIR_Done, |
| 8768 | // Label 504: @19344 |
| 8769 | GIM_Try, /*On fail goto*//*Label 505*/ 19405, // Rule ID 4071 // |
| 8770 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8771 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 8772 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8773 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8774 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 8775 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8776 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 8777 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8778 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8779 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8780 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8781 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8782 | // (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, immAllOnesV:{ *:[v4i32] })) => (BICv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) |
| 8783 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv16i8, |
| 8784 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8785 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS |
| 8786 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 8787 | GIR_EraseFromParent, /*InsnID*/0, |
| 8788 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8789 | // GIR_Coverage, 4071, |
| 8790 | GIR_Done, |
| 8791 | // Label 505: @19405 |
| 8792 | GIM_Try, /*On fail goto*//*Label 506*/ 19424, // Rule ID 2688 // |
| 8793 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8794 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 8795 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 8796 | // (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (ANDv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) |
| 8797 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv16i8, |
| 8798 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8799 | // GIR_Coverage, 2688, |
| 8800 | GIR_Done, |
| 8801 | // Label 506: @19424 |
| 8802 | GIM_Reject, |
| 8803 | // Label 501: @19425 |
| 8804 | GIM_Reject, |
| 8805 | // Label 448: @19426 |
| 8806 | GIM_Try, /*On fail goto*//*Label 507*/ 19704, |
| 8807 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 8808 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 8809 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 8810 | GIM_Try, /*On fail goto*//*Label 508*/ 19501, // Rule ID 7659 // |
| 8811 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8812 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8813 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8814 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 8815 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 8816 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8817 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8818 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8819 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 8820 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 8821 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8822 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8823 | // (and:{ *:[v8i8] } (xor:{ *:[v8i8] } immAllOnesV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rn) => (BICv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 8824 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv8i8, |
| 8825 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8826 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 8827 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 8828 | GIR_EraseFromParent, /*InsnID*/0, |
| 8829 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8830 | // GIR_Coverage, 7659, |
| 8831 | GIR_Done, |
| 8832 | // Label 508: @19501 |
| 8833 | GIM_Try, /*On fail goto*//*Label 509*/ 19562, // Rule ID 7658 // |
| 8834 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8835 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8836 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8837 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 8838 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 8839 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 8840 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8841 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8842 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8843 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 8844 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8845 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8846 | // (and:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rn) => (BICv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 8847 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv8i8, |
| 8848 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8849 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 8850 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 8851 | GIR_EraseFromParent, /*InsnID*/0, |
| 8852 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8853 | // GIR_Coverage, 7658, |
| 8854 | GIR_Done, |
| 8855 | // Label 509: @19562 |
| 8856 | GIM_Try, /*On fail goto*//*Label 510*/ 19623, // Rule ID 7657 // |
| 8857 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8858 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 8859 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8860 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8861 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 8862 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 8863 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8864 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8865 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8866 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 8867 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8868 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8869 | // (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (xor:{ *:[v8i8] } immAllOnesV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rm)) => (BICv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 8870 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv8i8, |
| 8871 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8872 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 8873 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 8874 | GIR_EraseFromParent, /*InsnID*/0, |
| 8875 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8876 | // GIR_Coverage, 7657, |
| 8877 | GIR_Done, |
| 8878 | // Label 510: @19623 |
| 8879 | GIM_Try, /*On fail goto*//*Label 511*/ 19684, // Rule ID 1315 // |
| 8880 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8881 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 8882 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8883 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8884 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 8885 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 8886 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 8887 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8888 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8889 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8890 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8891 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8892 | // (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, immAllOnesV:{ *:[v8i8] })) => (BICv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 8893 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv8i8, |
| 8894 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8895 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 8896 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 8897 | GIR_EraseFromParent, /*InsnID*/0, |
| 8898 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8899 | // GIR_Coverage, 1315, |
| 8900 | GIR_Done, |
| 8901 | // Label 511: @19684 |
| 8902 | GIM_Try, /*On fail goto*//*Label 512*/ 19703, // Rule ID 1313 // |
| 8903 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8904 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 8905 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 8906 | // (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (ANDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 8907 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv8i8, |
| 8908 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8909 | // GIR_Coverage, 1313, |
| 8910 | GIR_Done, |
| 8911 | // Label 512: @19703 |
| 8912 | GIM_Reject, |
| 8913 | // Label 507: @19704 |
| 8914 | GIM_Reject, |
| 8915 | // Label 449: @19705 |
| 8916 | GIM_Try, /*On fail goto*//*Label 513*/ 19983, |
| 8917 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 8918 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 8919 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 8920 | GIM_Try, /*On fail goto*//*Label 514*/ 19780, // Rule ID 7972 // |
| 8921 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8922 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8923 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8924 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 8925 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 8926 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8927 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8928 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8929 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 8930 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 8931 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8932 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8933 | // (and:{ *:[v8i16] } (xor:{ *:[v8i16] } immAllOnesV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$RHS), V128:{ *:[v8i16] }:$LHS) => (BICv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) |
| 8934 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv16i8, |
| 8935 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8936 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS |
| 8937 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 8938 | GIR_EraseFromParent, /*InsnID*/0, |
| 8939 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8940 | // GIR_Coverage, 7972, |
| 8941 | GIR_Done, |
| 8942 | // Label 514: @19780 |
| 8943 | GIM_Try, /*On fail goto*//*Label 515*/ 19841, // Rule ID 7971 // |
| 8944 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8945 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8946 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8947 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 8948 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 8949 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 8950 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8951 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8952 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8953 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 8954 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8955 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8956 | // (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$LHS) => (BICv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) |
| 8957 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv16i8, |
| 8958 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8959 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS |
| 8960 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 8961 | GIR_EraseFromParent, /*InsnID*/0, |
| 8962 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8963 | // GIR_Coverage, 7971, |
| 8964 | GIR_Done, |
| 8965 | // Label 515: @19841 |
| 8966 | GIM_Try, /*On fail goto*//*Label 516*/ 19902, // Rule ID 7970 // |
| 8967 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8968 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 8969 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8970 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8971 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 8972 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 8973 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8974 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8975 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8976 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 8977 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 8978 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 8979 | // (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, (xor:{ *:[v8i16] } immAllOnesV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$RHS)) => (BICv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) |
| 8980 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv16i8, |
| 8981 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 8982 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS |
| 8983 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 8984 | GIR_EraseFromParent, /*InsnID*/0, |
| 8985 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8986 | // GIR_Coverage, 7970, |
| 8987 | GIR_Done, |
| 8988 | // Label 516: @19902 |
| 8989 | GIM_Try, /*On fail goto*//*Label 517*/ 19963, // Rule ID 4070 // |
| 8990 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 8991 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 8992 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8993 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 8994 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 8995 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 8996 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 8997 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8998 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 8999 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 9000 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9001 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 9002 | // (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, immAllOnesV:{ *:[v8i16] })) => (BICv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) |
| 9003 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv16i8, |
| 9004 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 9005 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS |
| 9006 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 9007 | GIR_EraseFromParent, /*InsnID*/0, |
| 9008 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9009 | // GIR_Coverage, 4070, |
| 9010 | GIR_Done, |
| 9011 | // Label 517: @19963 |
| 9012 | GIM_Try, /*On fail goto*//*Label 518*/ 19982, // Rule ID 2687 // |
| 9013 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 9014 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 9015 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 9016 | // (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (ANDv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) |
| 9017 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv16i8, |
| 9018 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9019 | // GIR_Coverage, 2687, |
| 9020 | GIR_Done, |
| 9021 | // Label 518: @19982 |
| 9022 | GIM_Reject, |
| 9023 | // Label 513: @19983 |
| 9024 | GIM_Reject, |
| 9025 | // Label 450: @19984 |
| 9026 | GIM_Try, /*On fail goto*//*Label 519*/ 20262, |
| 9027 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 9028 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9029 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 9030 | GIM_Try, /*On fail goto*//*Label 520*/ 20059, // Rule ID 7662 // |
| 9031 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 9032 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9033 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 9034 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 9035 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9036 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 9037 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 9038 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 9039 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 9040 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 9041 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9042 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 9043 | // (and:{ *:[v16i8] } (xor:{ *:[v16i8] } immAllOnesV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rn) => (BICv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 9044 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv16i8, |
| 9045 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 9046 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 9047 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 9048 | GIR_EraseFromParent, /*InsnID*/0, |
| 9049 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9050 | // GIR_Coverage, 7662, |
| 9051 | GIR_Done, |
| 9052 | // Label 520: @20059 |
| 9053 | GIM_Try, /*On fail goto*//*Label 521*/ 20120, // Rule ID 7661 // |
| 9054 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 9055 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9056 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 9057 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 9058 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9059 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 9060 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 9061 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 9062 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 9063 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 9064 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9065 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 9066 | // (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rn) => (BICv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 9067 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv16i8, |
| 9068 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 9069 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 9070 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 9071 | GIR_EraseFromParent, /*InsnID*/0, |
| 9072 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9073 | // GIR_Coverage, 7661, |
| 9074 | GIR_Done, |
| 9075 | // Label 521: @20120 |
| 9076 | GIM_Try, /*On fail goto*//*Label 522*/ 20181, // Rule ID 7660 // |
| 9077 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 9078 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 9079 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9080 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 9081 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 9082 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9083 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 9084 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 9085 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 9086 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 9087 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9088 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 9089 | // (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (xor:{ *:[v16i8] } immAllOnesV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rm)) => (BICv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 9090 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv16i8, |
| 9091 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 9092 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 9093 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 9094 | GIR_EraseFromParent, /*InsnID*/0, |
| 9095 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9096 | // GIR_Coverage, 7660, |
| 9097 | GIR_Done, |
| 9098 | // Label 522: @20181 |
| 9099 | GIM_Try, /*On fail goto*//*Label 523*/ 20242, // Rule ID 1316 // |
| 9100 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 9101 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 9102 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9103 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 9104 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 9105 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9106 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 9107 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 9108 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 9109 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 9110 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9111 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 9112 | // (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, immAllOnesV:{ *:[v16i8] })) => (BICv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 9113 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BICv16i8, |
| 9114 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 9115 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 9116 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 9117 | GIR_EraseFromParent, /*InsnID*/0, |
| 9118 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9119 | // GIR_Coverage, 1316, |
| 9120 | GIR_Done, |
| 9121 | // Label 523: @20242 |
| 9122 | GIM_Try, /*On fail goto*//*Label 524*/ 20261, // Rule ID 1314 // |
| 9123 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 9124 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 9125 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 9126 | // (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (ANDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 9127 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ANDv16i8, |
| 9128 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9129 | // GIR_Coverage, 1314, |
| 9130 | GIR_Done, |
| 9131 | // Label 524: @20261 |
| 9132 | GIM_Reject, |
| 9133 | // Label 519: @20262 |
| 9134 | GIM_Reject, |
| 9135 | // Label 451: @20263 |
| 9136 | GIM_Reject, |
| 9137 | // Label 6: @20264 |
| 9138 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 534*/ 36618, |
| 9139 | /*GILLT_s32*//*Label 525*/ 20280, |
| 9140 | /*GILLT_s64*//*Label 526*/ 20643, 0, |
| 9141 | /*GILLT_v2s32*//*Label 527*/ 23017, |
| 9142 | /*GILLT_v2s64*//*Label 528*/ 24960, |
| 9143 | /*GILLT_v4s16*//*Label 529*/ 26903, |
| 9144 | /*GILLT_v4s32*//*Label 530*/ 28846, |
| 9145 | /*GILLT_v8s8*//*Label 531*/ 30789, |
| 9146 | /*GILLT_v8s16*//*Label 532*/ 32732, |
| 9147 | /*GILLT_v16s8*//*Label 533*/ 34675, |
| 9148 | // Label 525: @20280 |
| 9149 | GIM_Try, /*On fail goto*//*Label 535*/ 20642, |
| 9150 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 9151 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 9152 | GIM_Try, /*On fail goto*//*Label 536*/ 20345, // Rule ID 7576 // |
| 9153 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 9154 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9155 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 9156 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 9157 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 9158 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 9159 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 9160 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9161 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, |
| 9162 | // (or:{ *:[i32] } (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn) => (ORNWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) |
| 9163 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrs, |
| 9164 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 9165 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 9166 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 9167 | GIR_EraseFromParent, /*InsnID*/0, |
| 9168 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9169 | // GIR_Coverage, 7576, |
| 9170 | GIR_Done, |
| 9171 | // Label 536: @20345 |
| 9172 | GIM_Try, /*On fail goto*//*Label 537*/ 20400, // Rule ID 165 // |
| 9173 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 9174 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 9175 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9176 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 9177 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 9178 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 9179 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 9180 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9181 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, |
| 9182 | // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (ORNWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) |
| 9183 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrs, |
| 9184 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 9185 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 9186 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 9187 | GIR_EraseFromParent, /*InsnID*/0, |
| 9188 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9189 | // GIR_Coverage, 165, |
| 9190 | GIR_Done, |
| 9191 | // Label 537: @20400 |
| 9192 | GIM_Try, /*On fail goto*//*Label 538*/ 20442, // Rule ID 137 // |
| 9193 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, |
| 9194 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 9195 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9196 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 9197 | GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_logical_imm32, |
| 9198 | // MIs[1] Operand 1 |
| 9199 | // No operand predicates |
| 9200 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9201 | // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_logical_imm32>><<X:logical_imm32_XFORM>>:$imm) => (ORRWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (logical_imm32_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm)) |
| 9202 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRWri, |
| 9203 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 9204 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 9205 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GICR_renderLogicalImm32, // imm |
| 9206 | GIR_EraseFromParent, /*InsnID*/0, |
| 9207 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9208 | // GIR_Coverage, 137, |
| 9209 | GIR_Done, |
| 9210 | // Label 538: @20442 |
| 9211 | GIM_Try, /*On fail goto*//*Label 539*/ 20476, // Rule ID 7578 // |
| 9212 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 9213 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 9214 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, |
| 9215 | // (or:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm, GPR32:{ *:[i32] }:$Rn) => (ORRWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) |
| 9216 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRWrs, |
| 9217 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 9218 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 9219 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 9220 | GIR_EraseFromParent, /*InsnID*/0, |
| 9221 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9222 | // GIR_Coverage, 7578, |
| 9223 | GIR_Done, |
| 9224 | // Label 539: @20476 |
| 9225 | GIM_Try, /*On fail goto*//*Label 540*/ 20510, // Rule ID 169 // |
| 9226 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 9227 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 9228 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg32, |
| 9229 | // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) => (ORRWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) |
| 9230 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRWrs, |
| 9231 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 9232 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 9233 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 9234 | GIR_EraseFromParent, /*InsnID*/0, |
| 9235 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9236 | // GIR_Coverage, 169, |
| 9237 | GIR_Done, |
| 9238 | // Label 540: @20510 |
| 9239 | GIM_Try, /*On fail goto*//*Label 541*/ 20565, // Rule ID 7574 // |
| 9240 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 9241 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9242 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 9243 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 9244 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 9245 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 9246 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 9247 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 9248 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9249 | // (or:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn) => (ORNWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 9250 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrr, |
| 9251 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 9252 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 9253 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 9254 | GIR_EraseFromParent, /*InsnID*/0, |
| 9255 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9256 | // GIR_Coverage, 7574, |
| 9257 | GIR_Done, |
| 9258 | // Label 541: @20565 |
| 9259 | GIM_Try, /*On fail goto*//*Label 542*/ 20620, // Rule ID 163 // |
| 9260 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 9261 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 9262 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9263 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 9264 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 9265 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 9266 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 9267 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 9268 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9269 | // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (ORNWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 9270 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrr, |
| 9271 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 9272 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 9273 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 9274 | GIR_EraseFromParent, /*InsnID*/0, |
| 9275 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9276 | // GIR_Coverage, 163, |
| 9277 | GIR_Done, |
| 9278 | // Label 542: @20620 |
| 9279 | GIM_Try, /*On fail goto*//*Label 543*/ 20641, // Rule ID 167 // |
| 9280 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 9281 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 9282 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 9283 | // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (ORRWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 9284 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRWrr, |
| 9285 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9286 | // GIR_Coverage, 167, |
| 9287 | GIR_Done, |
| 9288 | // Label 543: @20641 |
| 9289 | GIM_Reject, |
| 9290 | // Label 535: @20642 |
| 9291 | GIM_Reject, |
| 9292 | // Label 526: @20643 |
| 9293 | GIM_Try, /*On fail goto*//*Label 544*/ 23016, |
| 9294 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 9295 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 9296 | GIM_Try, /*On fail goto*//*Label 545*/ 20708, // Rule ID 7577 // |
| 9297 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 9298 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9299 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 9300 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9301 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9302 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 9303 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 9304 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9305 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, |
| 9306 | // (or:{ *:[i64] } (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn) => (ORNXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) |
| 9307 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNXrs, |
| 9308 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 9309 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 9310 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 9311 | GIR_EraseFromParent, /*InsnID*/0, |
| 9312 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9313 | // GIR_Coverage, 7577, |
| 9314 | GIR_Done, |
| 9315 | // Label 545: @20708 |
| 9316 | GIM_Try, /*On fail goto*//*Label 546*/ 20763, // Rule ID 166 // |
| 9317 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 9318 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 9319 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9320 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 9321 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9322 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9323 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 9324 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9325 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, |
| 9326 | // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm, -1:{ *:[i64] })) => (ORNXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) |
| 9327 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNXrs, |
| 9328 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 9329 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 9330 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 9331 | GIR_EraseFromParent, /*InsnID*/0, |
| 9332 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9333 | // GIR_Coverage, 166, |
| 9334 | GIR_Done, |
| 9335 | // Label 546: @20763 |
| 9336 | GIM_Try, /*On fail goto*//*Label 547*/ 20871, // Rule ID 7855 // |
| 9337 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 9338 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 9339 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9340 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 9341 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9342 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9343 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 9344 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 9345 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 9346 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 9347 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 9348 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 9349 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 9350 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 9351 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 9352 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 9353 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 9354 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s64, |
| 9355 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 9356 | // MIs[4] LHS |
| 9357 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 9358 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9359 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 9360 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 9361 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 9362 | // (or:{ *:[v1i64] } (and:{ *:[v1i64] } (xor:{ *:[v1i64] } immAllOnesV:{ *:[v1i64] }, V64:{ *:[v1i64] }:$LHS), V64:{ *:[v1i64] }:$RHS), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$LHS)) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS) |
| 9363 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 9364 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 9365 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // LHS |
| 9366 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS |
| 9367 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 9368 | GIR_EraseFromParent, /*InsnID*/0, |
| 9369 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9370 | // GIR_Coverage, 7855, |
| 9371 | GIR_Done, |
| 9372 | // Label 547: @20871 |
| 9373 | GIM_Try, /*On fail goto*//*Label 548*/ 20979, // Rule ID 7854 // |
| 9374 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 9375 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 9376 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9377 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 9378 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9379 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9380 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 9381 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 9382 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 9383 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 9384 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 9385 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 9386 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 9387 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 9388 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 9389 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 9390 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 9391 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64, |
| 9392 | // MIs[4] LHS |
| 9393 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 9394 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 9395 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9396 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 9397 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 9398 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 9399 | // (or:{ *:[v1i64] } (and:{ *:[v1i64] } (xor:{ *:[v1i64] } immAllOnesV:{ *:[v1i64] }, V64:{ *:[v1i64] }:$LHS), V64:{ *:[v1i64] }:$RHS), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS)) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS) |
| 9400 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 9401 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 9402 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // LHS |
| 9403 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS |
| 9404 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 9405 | GIR_EraseFromParent, /*InsnID*/0, |
| 9406 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9407 | // GIR_Coverage, 7854, |
| 9408 | GIR_Done, |
| 9409 | // Label 548: @20979 |
| 9410 | GIM_Try, /*On fail goto*//*Label 549*/ 21087, // Rule ID 7853 // |
| 9411 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 9412 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 9413 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9414 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 9415 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9416 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9417 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 9418 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 9419 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 9420 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 9421 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 9422 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 9423 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 9424 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 9425 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 9426 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 9427 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 9428 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s64, |
| 9429 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 9430 | // MIs[4] LHS |
| 9431 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 9432 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9433 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 9434 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 9435 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 9436 | // (or:{ *:[v1i64] } (and:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$RHS), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$LHS)) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS) |
| 9437 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 9438 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 9439 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS |
| 9440 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS |
| 9441 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 9442 | GIR_EraseFromParent, /*InsnID*/0, |
| 9443 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9444 | // GIR_Coverage, 7853, |
| 9445 | GIR_Done, |
| 9446 | // Label 549: @21087 |
| 9447 | GIM_Try, /*On fail goto*//*Label 550*/ 21195, // Rule ID 7852 // |
| 9448 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 9449 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 9450 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9451 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 9452 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9453 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9454 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 9455 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 9456 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 9457 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 9458 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 9459 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 9460 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 9461 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 9462 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 9463 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 9464 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 9465 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64, |
| 9466 | // MIs[4] LHS |
| 9467 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 9468 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 9469 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9470 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 9471 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 9472 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 9473 | // (or:{ *:[v1i64] } (and:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$RHS), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS)) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS) |
| 9474 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 9475 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 9476 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS |
| 9477 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS |
| 9478 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 9479 | GIR_EraseFromParent, /*InsnID*/0, |
| 9480 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9481 | // GIR_Coverage, 7852, |
| 9482 | GIR_Done, |
| 9483 | // Label 550: @21195 |
| 9484 | GIM_Try, /*On fail goto*//*Label 551*/ 21303, // Rule ID 7859 // |
| 9485 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 9486 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 9487 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9488 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 9489 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9490 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9491 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 9492 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 9493 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 9494 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 9495 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 9496 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 9497 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 9498 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 9499 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 9500 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 9501 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 9502 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s64, |
| 9503 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 9504 | // MIs[4] LHS |
| 9505 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 9506 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9507 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 9508 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 9509 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 9510 | // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, (xor:{ *:[v1i64] } immAllOnesV:{ *:[v1i64] }, V64:{ *:[v1i64] }:$LHS)), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$LHS)) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS) |
| 9511 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 9512 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 9513 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // LHS |
| 9514 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS |
| 9515 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 9516 | GIR_EraseFromParent, /*InsnID*/0, |
| 9517 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9518 | // GIR_Coverage, 7859, |
| 9519 | GIR_Done, |
| 9520 | // Label 551: @21303 |
| 9521 | GIM_Try, /*On fail goto*//*Label 552*/ 21411, // Rule ID 7858 // |
| 9522 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 9523 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 9524 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9525 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 9526 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9527 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9528 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 9529 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 9530 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 9531 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 9532 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 9533 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 9534 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 9535 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 9536 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 9537 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 9538 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 9539 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64, |
| 9540 | // MIs[4] LHS |
| 9541 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 9542 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 9543 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9544 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 9545 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 9546 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 9547 | // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, (xor:{ *:[v1i64] } immAllOnesV:{ *:[v1i64] }, V64:{ *:[v1i64] }:$LHS)), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS)) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS) |
| 9548 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 9549 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 9550 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // LHS |
| 9551 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS |
| 9552 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 9553 | GIR_EraseFromParent, /*InsnID*/0, |
| 9554 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9555 | // GIR_Coverage, 7858, |
| 9556 | GIR_Done, |
| 9557 | // Label 552: @21411 |
| 9558 | GIM_Try, /*On fail goto*//*Label 553*/ 21519, // Rule ID 7857 // |
| 9559 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 9560 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 9561 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9562 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 9563 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9564 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9565 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 9566 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 9567 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 9568 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 9569 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 9570 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 9571 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 9572 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 9573 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 9574 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 9575 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 9576 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s64, |
| 9577 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 9578 | // MIs[4] LHS |
| 9579 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 9580 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9581 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 9582 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 9583 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 9584 | // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] })), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$LHS)) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS) |
| 9585 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 9586 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 9587 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS |
| 9588 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS |
| 9589 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 9590 | GIR_EraseFromParent, /*InsnID*/0, |
| 9591 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9592 | // GIR_Coverage, 7857, |
| 9593 | GIR_Done, |
| 9594 | // Label 553: @21519 |
| 9595 | GIM_Try, /*On fail goto*//*Label 554*/ 21627, // Rule ID 7856 // |
| 9596 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 9597 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 9598 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9599 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 9600 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9601 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9602 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 9603 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 9604 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 9605 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 9606 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 9607 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 9608 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 9609 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 9610 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 9611 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 9612 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 9613 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64, |
| 9614 | // MIs[4] LHS |
| 9615 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 9616 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 9617 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9618 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 9619 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 9620 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 9621 | // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] })), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS)) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS) |
| 9622 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 9623 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 9624 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS |
| 9625 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS |
| 9626 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 9627 | GIR_EraseFromParent, /*InsnID*/0, |
| 9628 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9629 | // GIR_Coverage, 7856, |
| 9630 | GIR_Done, |
| 9631 | // Label 554: @21627 |
| 9632 | GIM_Try, /*On fail goto*//*Label 555*/ 21735, // Rule ID 7845 // |
| 9633 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 9634 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 9635 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9636 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 9637 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9638 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9639 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 9640 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 9641 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 9642 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 9643 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 9644 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 9645 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 9646 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 9647 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64, |
| 9648 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 9649 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 9650 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 9651 | // MIs[3] LHS |
| 9652 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 9653 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 9654 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9655 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 9656 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 9657 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 9658 | // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS), (and:{ *:[v1i64] } (xor:{ *:[v1i64] } immAllOnesV:{ *:[v1i64] }, V64:{ *:[v1i64] }:$LHS), V64:{ *:[v1i64] }:$RHS)) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS) |
| 9659 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 9660 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 9661 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS |
| 9662 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS |
| 9663 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS |
| 9664 | GIR_EraseFromParent, /*InsnID*/0, |
| 9665 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9666 | // GIR_Coverage, 7845, |
| 9667 | GIR_Done, |
| 9668 | // Label 555: @21735 |
| 9669 | GIM_Try, /*On fail goto*//*Label 556*/ 21843, // Rule ID 7849 // |
| 9670 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 9671 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 9672 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9673 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 9674 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9675 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9676 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 9677 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 9678 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 9679 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 9680 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 9681 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 9682 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 9683 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 9684 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64, |
| 9685 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 9686 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 9687 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 9688 | // MIs[3] LHS |
| 9689 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 9690 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 9691 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9692 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 9693 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 9694 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 9695 | // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$LHS), (and:{ *:[v1i64] } (xor:{ *:[v1i64] } immAllOnesV:{ *:[v1i64] }, V64:{ *:[v1i64] }:$LHS), V64:{ *:[v1i64] }:$RHS)) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS) |
| 9696 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 9697 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 9698 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS |
| 9699 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS |
| 9700 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS |
| 9701 | GIR_EraseFromParent, /*InsnID*/0, |
| 9702 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9703 | // GIR_Coverage, 7849, |
| 9704 | GIR_Done, |
| 9705 | // Label 556: @21843 |
| 9706 | GIM_Try, /*On fail goto*//*Label 557*/ 21951, // Rule ID 2673 // |
| 9707 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 9708 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 9709 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9710 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 9711 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9712 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9713 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 9714 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 9715 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 9716 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 9717 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 9718 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 9719 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 9720 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 9721 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64, |
| 9722 | // MIs[3] LHS |
| 9723 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 9724 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 9725 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 9726 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 9727 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 9728 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9729 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 9730 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 9731 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 9732 | // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS), (and:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$RHS)) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS) |
| 9733 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 9734 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 9735 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS |
| 9736 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS |
| 9737 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS |
| 9738 | GIR_EraseFromParent, /*InsnID*/0, |
| 9739 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9740 | // GIR_Coverage, 2673, |
| 9741 | GIR_Done, |
| 9742 | // Label 557: @21951 |
| 9743 | GIM_Try, /*On fail goto*//*Label 558*/ 22059, // Rule ID 7848 // |
| 9744 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 9745 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 9746 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9747 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 9748 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9749 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9750 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 9751 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 9752 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 9753 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 9754 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 9755 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 9756 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 9757 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 9758 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64, |
| 9759 | // MIs[3] LHS |
| 9760 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 9761 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 9762 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 9763 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 9764 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 9765 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9766 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 9767 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 9768 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 9769 | // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$LHS), (and:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$RHS)) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS) |
| 9770 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 9771 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 9772 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS |
| 9773 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS |
| 9774 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS |
| 9775 | GIR_EraseFromParent, /*InsnID*/0, |
| 9776 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9777 | // GIR_Coverage, 7848, |
| 9778 | GIR_Done, |
| 9779 | // Label 558: @22059 |
| 9780 | GIM_Try, /*On fail goto*//*Label 559*/ 22167, // Rule ID 7847 // |
| 9781 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 9782 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 9783 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9784 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 9785 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9786 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9787 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 9788 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 9789 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 9790 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 9791 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 9792 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 9793 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 9794 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 9795 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 9796 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64, |
| 9797 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 9798 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 9799 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 9800 | // MIs[3] LHS |
| 9801 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 9802 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9803 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 9804 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 9805 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 9806 | // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, (xor:{ *:[v1i64] } immAllOnesV:{ *:[v1i64] }, V64:{ *:[v1i64] }:$LHS))) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS) |
| 9807 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 9808 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 9809 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS |
| 9810 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS |
| 9811 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS |
| 9812 | GIR_EraseFromParent, /*InsnID*/0, |
| 9813 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9814 | // GIR_Coverage, 7847, |
| 9815 | GIR_Done, |
| 9816 | // Label 559: @22167 |
| 9817 | GIM_Try, /*On fail goto*//*Label 560*/ 22275, // Rule ID 7851 // |
| 9818 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 9819 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 9820 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9821 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 9822 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9823 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9824 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 9825 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 9826 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 9827 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 9828 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 9829 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 9830 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 9831 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 9832 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 9833 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64, |
| 9834 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 9835 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 9836 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 9837 | // MIs[3] LHS |
| 9838 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 9839 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9840 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 9841 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 9842 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 9843 | // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$LHS), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, (xor:{ *:[v1i64] } immAllOnesV:{ *:[v1i64] }, V64:{ *:[v1i64] }:$LHS))) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS) |
| 9844 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 9845 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 9846 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS |
| 9847 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS |
| 9848 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS |
| 9849 | GIR_EraseFromParent, /*InsnID*/0, |
| 9850 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9851 | // GIR_Coverage, 7851, |
| 9852 | GIR_Done, |
| 9853 | // Label 560: @22275 |
| 9854 | GIM_Try, /*On fail goto*//*Label 561*/ 22383, // Rule ID 7846 // |
| 9855 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 9856 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 9857 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9858 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 9859 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9860 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9861 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 9862 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 9863 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 9864 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 9865 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 9866 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 9867 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 9868 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 9869 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 9870 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64, |
| 9871 | // MIs[3] LHS |
| 9872 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 9873 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 9874 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 9875 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 9876 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9877 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 9878 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 9879 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 9880 | // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] }))) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS) |
| 9881 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 9882 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 9883 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS |
| 9884 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS |
| 9885 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS |
| 9886 | GIR_EraseFromParent, /*InsnID*/0, |
| 9887 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9888 | // GIR_Coverage, 7846, |
| 9889 | GIR_Done, |
| 9890 | // Label 561: @22383 |
| 9891 | GIM_Try, /*On fail goto*//*Label 562*/ 22491, // Rule ID 7850 // |
| 9892 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 9893 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 9894 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9895 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 9896 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9897 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9898 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 9899 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 9900 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 9901 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 9902 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 9903 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 9904 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 9905 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 9906 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 9907 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64, |
| 9908 | // MIs[3] LHS |
| 9909 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 9910 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 9911 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 9912 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 9913 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9914 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 9915 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 9916 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 9917 | // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$LHS), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] }))) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS) |
| 9918 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 9919 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 9920 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS |
| 9921 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS |
| 9922 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS |
| 9923 | GIR_EraseFromParent, /*InsnID*/0, |
| 9924 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9925 | // GIR_Coverage, 7850, |
| 9926 | GIR_Done, |
| 9927 | // Label 562: @22491 |
| 9928 | GIM_Try, /*On fail goto*//*Label 563*/ 22533, // Rule ID 138 // |
| 9929 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, |
| 9930 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 9931 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9932 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 9933 | GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_logical_imm64, |
| 9934 | // MIs[1] Operand 1 |
| 9935 | // No operand predicates |
| 9936 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9937 | // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_logical_imm64>><<X:logical_imm64_XFORM>>:$imm) => (ORRXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (logical_imm64_XFORM:{ *:[i64] } (imm:{ *:[i64] }):$imm)) |
| 9938 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRXri, |
| 9939 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 9940 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 9941 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GICR_renderLogicalImm64, // imm |
| 9942 | GIR_EraseFromParent, /*InsnID*/0, |
| 9943 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9944 | // GIR_Coverage, 138, |
| 9945 | GIR_Done, |
| 9946 | // Label 563: @22533 |
| 9947 | GIM_Try, /*On fail goto*//*Label 564*/ 22567, // Rule ID 7579 // |
| 9948 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 9949 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 9950 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, |
| 9951 | // (or:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm, GPR64:{ *:[i64] }:$Rn) => (ORRXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) |
| 9952 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRXrs, |
| 9953 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 9954 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 9955 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 9956 | GIR_EraseFromParent, /*InsnID*/0, |
| 9957 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9958 | // GIR_Coverage, 7579, |
| 9959 | GIR_Done, |
| 9960 | // Label 564: @22567 |
| 9961 | GIM_Try, /*On fail goto*//*Label 565*/ 22601, // Rule ID 170 // |
| 9962 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 9963 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 9964 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg64, |
| 9965 | // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) => (ORRXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) |
| 9966 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRXrs, |
| 9967 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 9968 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 9969 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 9970 | GIR_EraseFromParent, /*InsnID*/0, |
| 9971 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9972 | // GIR_Coverage, 170, |
| 9973 | GIR_Done, |
| 9974 | // Label 565: @22601 |
| 9975 | GIM_Try, /*On fail goto*//*Label 566*/ 22656, // Rule ID 7575 // |
| 9976 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 9977 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9978 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 9979 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9980 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9981 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 9982 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 9983 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 9984 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9985 | // (or:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn) => (ORNXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) |
| 9986 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNXrr, |
| 9987 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 9988 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 9989 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 9990 | GIR_EraseFromParent, /*InsnID*/0, |
| 9991 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9992 | // GIR_Coverage, 7575, |
| 9993 | GIR_Done, |
| 9994 | // Label 566: @22656 |
| 9995 | GIM_Try, /*On fail goto*//*Label 567*/ 22711, // Rule ID 164 // |
| 9996 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 9997 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 9998 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9999 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 10000 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 10001 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 10002 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 10003 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 10004 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10005 | // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] })) => (ORNXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) |
| 10006 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNXrr, |
| 10007 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 10008 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 10009 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 10010 | GIR_EraseFromParent, /*InsnID*/0, |
| 10011 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10012 | // GIR_Coverage, 164, |
| 10013 | GIR_Done, |
| 10014 | // Label 567: @22711 |
| 10015 | GIM_Try, /*On fail goto*//*Label 568*/ 22776, // Rule ID 7987 // |
| 10016 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10017 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 10018 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10019 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 10020 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 10021 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 10022 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10023 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10024 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 10025 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10026 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10027 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10028 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10029 | // (or:{ *:[v1i64] } (xor:{ *:[v1i64] } immAllOnesV:{ *:[v1i64] }, V64:{ *:[v1i64] }:$RHS), V64:{ *:[v1i64] }:$LHS) => (ORNv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) |
| 10030 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv8i8, |
| 10031 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 10032 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS |
| 10033 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 10034 | GIR_EraseFromParent, /*InsnID*/0, |
| 10035 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10036 | // GIR_Coverage, 7987, |
| 10037 | GIR_Done, |
| 10038 | // Label 568: @22776 |
| 10039 | GIM_Try, /*On fail goto*//*Label 569*/ 22841, // Rule ID 7986 // |
| 10040 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10041 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 10042 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10043 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 10044 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 10045 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 10046 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10047 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 10048 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10049 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 10050 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10051 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10052 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10053 | // (or:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$LHS) => (ORNv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) |
| 10054 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv8i8, |
| 10055 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 10056 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS |
| 10057 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 10058 | GIR_EraseFromParent, /*InsnID*/0, |
| 10059 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10060 | // GIR_Coverage, 7986, |
| 10061 | GIR_Done, |
| 10062 | // Label 569: @22841 |
| 10063 | GIM_Try, /*On fail goto*//*Label 570*/ 22906, // Rule ID 7985 // |
| 10064 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10065 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 10066 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10067 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 10068 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 10069 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 10070 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 10071 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10072 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10073 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 10074 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10075 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10076 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10077 | // (or:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, (xor:{ *:[v1i64] } immAllOnesV:{ *:[v1i64] }, V64:{ *:[v1i64] }:$RHS)) => (ORNv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) |
| 10078 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv8i8, |
| 10079 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 10080 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS |
| 10081 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 10082 | GIR_EraseFromParent, /*InsnID*/0, |
| 10083 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10084 | // GIR_Coverage, 7985, |
| 10085 | GIR_Done, |
| 10086 | // Label 570: @22906 |
| 10087 | GIM_Try, /*On fail goto*//*Label 571*/ 22971, // Rule ID 4081 // |
| 10088 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10089 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 10090 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10091 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 10092 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 10093 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 10094 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 10095 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10096 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 10097 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10098 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 10099 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10100 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10101 | // (or:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, immAllOnesV:{ *:[v1i64] })) => (ORNv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) |
| 10102 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv8i8, |
| 10103 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 10104 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS |
| 10105 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 10106 | GIR_EraseFromParent, /*InsnID*/0, |
| 10107 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10108 | // GIR_Coverage, 4081, |
| 10109 | GIR_Done, |
| 10110 | // Label 571: @22971 |
| 10111 | GIM_Try, /*On fail goto*//*Label 572*/ 22992, // Rule ID 168 // |
| 10112 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 10113 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 10114 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 10115 | // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (ORRXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) |
| 10116 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRXrr, |
| 10117 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10118 | // GIR_Coverage, 168, |
| 10119 | GIR_Done, |
| 10120 | // Label 572: @22992 |
| 10121 | GIM_Try, /*On fail goto*//*Label 573*/ 23015, // Rule ID 4087 // |
| 10122 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10123 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 10124 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10125 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10126 | // (or:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) => (ORRv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) |
| 10127 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv8i8, |
| 10128 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10129 | // GIR_Coverage, 4087, |
| 10130 | GIR_Done, |
| 10131 | // Label 573: @23015 |
| 10132 | GIM_Reject, |
| 10133 | // Label 544: @23016 |
| 10134 | GIM_Reject, |
| 10135 | // Label 527: @23017 |
| 10136 | GIM_Try, /*On fail goto*//*Label 574*/ 24959, |
| 10137 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10138 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10139 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 10140 | GIM_Try, /*On fail goto*//*Label 575*/ 23135, // Rule ID 7840 // |
| 10141 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10142 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10143 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 10144 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10145 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10146 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10147 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 10148 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10149 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10150 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 10151 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10152 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 10153 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10154 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10155 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 10156 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 10157 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10158 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10159 | // MIs[4] LHS |
| 10160 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 10161 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10162 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10163 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 10164 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 10165 | // (or:{ *:[v2i32] } (and:{ *:[v2i32] } (xor:{ *:[v2i32] } immAllOnesV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$LHS), V64:{ *:[v2i32] }:$RHS), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$LHS)) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS) |
| 10166 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 10167 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 10168 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // LHS |
| 10169 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS |
| 10170 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 10171 | GIR_EraseFromParent, /*InsnID*/0, |
| 10172 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10173 | // GIR_Coverage, 7840, |
| 10174 | GIR_Done, |
| 10175 | // Label 575: @23135 |
| 10176 | GIM_Try, /*On fail goto*//*Label 576*/ 23239, // Rule ID 7839 // |
| 10177 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10178 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10179 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 10180 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10181 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10182 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10183 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 10184 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10185 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10186 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 10187 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10188 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 10189 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10190 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10191 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 10192 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 10193 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10194 | // MIs[4] LHS |
| 10195 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 10196 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10197 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10198 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10199 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 10200 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 10201 | // (or:{ *:[v2i32] } (and:{ *:[v2i32] } (xor:{ *:[v2i32] } immAllOnesV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$LHS), V64:{ *:[v2i32] }:$RHS), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS)) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS) |
| 10202 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 10203 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 10204 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // LHS |
| 10205 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS |
| 10206 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 10207 | GIR_EraseFromParent, /*InsnID*/0, |
| 10208 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10209 | // GIR_Coverage, 7839, |
| 10210 | GIR_Done, |
| 10211 | // Label 576: @23239 |
| 10212 | GIM_Try, /*On fail goto*//*Label 577*/ 23343, // Rule ID 7838 // |
| 10213 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10214 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10215 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 10216 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10217 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10218 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10219 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 10220 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10221 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10222 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10223 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 10224 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10225 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 10226 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10227 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 10228 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 10229 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10230 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10231 | // MIs[4] LHS |
| 10232 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 10233 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10234 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10235 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 10236 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 10237 | // (or:{ *:[v2i32] } (and:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$RHS), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$LHS)) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS) |
| 10238 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 10239 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 10240 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS |
| 10241 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS |
| 10242 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 10243 | GIR_EraseFromParent, /*InsnID*/0, |
| 10244 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10245 | // GIR_Coverage, 7838, |
| 10246 | GIR_Done, |
| 10247 | // Label 577: @23343 |
| 10248 | GIM_Try, /*On fail goto*//*Label 578*/ 23447, // Rule ID 7837 // |
| 10249 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10250 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10251 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 10252 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10253 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10254 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10255 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 10256 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10257 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10258 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10259 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 10260 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10261 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 10262 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10263 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 10264 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 10265 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10266 | // MIs[4] LHS |
| 10267 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 10268 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10269 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10270 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10271 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 10272 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 10273 | // (or:{ *:[v2i32] } (and:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$RHS), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS)) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS) |
| 10274 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 10275 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 10276 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS |
| 10277 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS |
| 10278 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 10279 | GIR_EraseFromParent, /*InsnID*/0, |
| 10280 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10281 | // GIR_Coverage, 7837, |
| 10282 | GIR_Done, |
| 10283 | // Label 578: @23447 |
| 10284 | GIM_Try, /*On fail goto*//*Label 579*/ 23551, // Rule ID 7844 // |
| 10285 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10286 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10287 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 10288 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10289 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10290 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10291 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 10292 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 10293 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10294 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10295 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 10296 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10297 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 10298 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10299 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 10300 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 10301 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10302 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10303 | // MIs[4] LHS |
| 10304 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 10305 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10306 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10307 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 10308 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 10309 | // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, (xor:{ *:[v2i32] } immAllOnesV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$LHS)), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$LHS)) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS) |
| 10310 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 10311 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 10312 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // LHS |
| 10313 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS |
| 10314 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 10315 | GIR_EraseFromParent, /*InsnID*/0, |
| 10316 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10317 | // GIR_Coverage, 7844, |
| 10318 | GIR_Done, |
| 10319 | // Label 579: @23551 |
| 10320 | GIM_Try, /*On fail goto*//*Label 580*/ 23655, // Rule ID 7843 // |
| 10321 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10322 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10323 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 10324 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10325 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10326 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10327 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 10328 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 10329 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10330 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10331 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 10332 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10333 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 10334 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10335 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 10336 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 10337 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10338 | // MIs[4] LHS |
| 10339 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 10340 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10341 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10342 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10343 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 10344 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 10345 | // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, (xor:{ *:[v2i32] } immAllOnesV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$LHS)), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS)) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS) |
| 10346 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 10347 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 10348 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // LHS |
| 10349 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS |
| 10350 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 10351 | GIR_EraseFromParent, /*InsnID*/0, |
| 10352 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10353 | // GIR_Coverage, 7843, |
| 10354 | GIR_Done, |
| 10355 | // Label 580: @23655 |
| 10356 | GIM_Try, /*On fail goto*//*Label 581*/ 23759, // Rule ID 7842 // |
| 10357 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10358 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10359 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 10360 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10361 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10362 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10363 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 10364 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 10365 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10366 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10367 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10368 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 10369 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10370 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 10371 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 10372 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 10373 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10374 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10375 | // MIs[4] LHS |
| 10376 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 10377 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10378 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10379 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 10380 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 10381 | // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] })), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$LHS)) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS) |
| 10382 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 10383 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 10384 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS |
| 10385 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS |
| 10386 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 10387 | GIR_EraseFromParent, /*InsnID*/0, |
| 10388 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10389 | // GIR_Coverage, 7842, |
| 10390 | GIR_Done, |
| 10391 | // Label 581: @23759 |
| 10392 | GIM_Try, /*On fail goto*//*Label 582*/ 23863, // Rule ID 7841 // |
| 10393 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10394 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10395 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 10396 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10397 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10398 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10399 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 10400 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 10401 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10402 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10403 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10404 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 10405 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10406 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 10407 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 10408 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 10409 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10410 | // MIs[4] LHS |
| 10411 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 10412 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10413 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10414 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10415 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 10416 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 10417 | // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] })), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS)) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS) |
| 10418 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 10419 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 10420 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS |
| 10421 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS |
| 10422 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 10423 | GIR_EraseFromParent, /*InsnID*/0, |
| 10424 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10425 | // GIR_Coverage, 7841, |
| 10426 | GIR_Done, |
| 10427 | // Label 582: @23863 |
| 10428 | GIM_Try, /*On fail goto*//*Label 583*/ 23967, // Rule ID 7830 // |
| 10429 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10430 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10431 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 10432 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10433 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10434 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10435 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10436 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 10437 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 10438 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10439 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10440 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 10441 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 10442 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10443 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 10444 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10445 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 10446 | // MIs[3] LHS |
| 10447 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 10448 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10449 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10450 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10451 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 10452 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 10453 | // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS), (and:{ *:[v2i32] } (xor:{ *:[v2i32] } immAllOnesV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$LHS), V64:{ *:[v2i32] }:$RHS)) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS) |
| 10454 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 10455 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 10456 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS |
| 10457 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS |
| 10458 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS |
| 10459 | GIR_EraseFromParent, /*InsnID*/0, |
| 10460 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10461 | // GIR_Coverage, 7830, |
| 10462 | GIR_Done, |
| 10463 | // Label 583: @23967 |
| 10464 | GIM_Try, /*On fail goto*//*Label 584*/ 24071, // Rule ID 7834 // |
| 10465 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10466 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10467 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 10468 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10469 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10470 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10471 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10472 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 10473 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 10474 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10475 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10476 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 10477 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 10478 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10479 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 10480 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10481 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 10482 | // MIs[3] LHS |
| 10483 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 10484 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10485 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10486 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10487 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 10488 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 10489 | // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$LHS), (and:{ *:[v2i32] } (xor:{ *:[v2i32] } immAllOnesV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$LHS), V64:{ *:[v2i32] }:$RHS)) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS) |
| 10490 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 10491 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 10492 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS |
| 10493 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS |
| 10494 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS |
| 10495 | GIR_EraseFromParent, /*InsnID*/0, |
| 10496 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10497 | // GIR_Coverage, 7834, |
| 10498 | GIR_Done, |
| 10499 | // Label 584: @24071 |
| 10500 | GIM_Try, /*On fail goto*//*Label 585*/ 24175, // Rule ID 2672 // |
| 10501 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10502 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10503 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 10504 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10505 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10506 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10507 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10508 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 10509 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 10510 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10511 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10512 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 10513 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 10514 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10515 | // MIs[3] LHS |
| 10516 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 10517 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 10518 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10519 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 10520 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10521 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10522 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10523 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 10524 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 10525 | // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS), (and:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$RHS)) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS) |
| 10526 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 10527 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 10528 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS |
| 10529 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS |
| 10530 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS |
| 10531 | GIR_EraseFromParent, /*InsnID*/0, |
| 10532 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10533 | // GIR_Coverage, 2672, |
| 10534 | GIR_Done, |
| 10535 | // Label 585: @24175 |
| 10536 | GIM_Try, /*On fail goto*//*Label 586*/ 24279, // Rule ID 7833 // |
| 10537 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10538 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10539 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 10540 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10541 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10542 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10543 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10544 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 10545 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 10546 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10547 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10548 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 10549 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 10550 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10551 | // MIs[3] LHS |
| 10552 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 10553 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 10554 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10555 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 10556 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10557 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10558 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10559 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 10560 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 10561 | // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$LHS), (and:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$RHS)) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS) |
| 10562 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 10563 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 10564 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS |
| 10565 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS |
| 10566 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS |
| 10567 | GIR_EraseFromParent, /*InsnID*/0, |
| 10568 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10569 | // GIR_Coverage, 7833, |
| 10570 | GIR_Done, |
| 10571 | // Label 586: @24279 |
| 10572 | GIM_Try, /*On fail goto*//*Label 587*/ 24383, // Rule ID 7832 // |
| 10573 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10574 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10575 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 10576 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10577 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10578 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10579 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10580 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 10581 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 10582 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10583 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10584 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10585 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 10586 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 10587 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10588 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 10589 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10590 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 10591 | // MIs[3] LHS |
| 10592 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 10593 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10594 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10595 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 10596 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 10597 | // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, (xor:{ *:[v2i32] } immAllOnesV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$LHS))) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS) |
| 10598 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 10599 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 10600 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS |
| 10601 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS |
| 10602 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS |
| 10603 | GIR_EraseFromParent, /*InsnID*/0, |
| 10604 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10605 | // GIR_Coverage, 7832, |
| 10606 | GIR_Done, |
| 10607 | // Label 587: @24383 |
| 10608 | GIM_Try, /*On fail goto*//*Label 588*/ 24487, // Rule ID 7836 // |
| 10609 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10610 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10611 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 10612 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10613 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10614 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10615 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10616 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 10617 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 10618 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10619 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10620 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10621 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 10622 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 10623 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10624 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 10625 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10626 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 10627 | // MIs[3] LHS |
| 10628 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 10629 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10630 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10631 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 10632 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 10633 | // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$LHS), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, (xor:{ *:[v2i32] } immAllOnesV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$LHS))) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS) |
| 10634 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 10635 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 10636 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS |
| 10637 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS |
| 10638 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS |
| 10639 | GIR_EraseFromParent, /*InsnID*/0, |
| 10640 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10641 | // GIR_Coverage, 7836, |
| 10642 | GIR_Done, |
| 10643 | // Label 588: @24487 |
| 10644 | GIM_Try, /*On fail goto*//*Label 589*/ 24591, // Rule ID 7831 // |
| 10645 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10646 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10647 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 10648 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10649 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10650 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10651 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10652 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 10653 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 10654 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10655 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10656 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10657 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 10658 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 10659 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10660 | // MIs[3] LHS |
| 10661 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 10662 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 10663 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10664 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 10665 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10666 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10667 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 10668 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 10669 | // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] }))) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS) |
| 10670 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 10671 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 10672 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS |
| 10673 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS |
| 10674 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS |
| 10675 | GIR_EraseFromParent, /*InsnID*/0, |
| 10676 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10677 | // GIR_Coverage, 7831, |
| 10678 | GIR_Done, |
| 10679 | // Label 589: @24591 |
| 10680 | GIM_Try, /*On fail goto*//*Label 590*/ 24695, // Rule ID 7835 // |
| 10681 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10682 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10683 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 10684 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10685 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10686 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10687 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10688 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 10689 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 10690 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10691 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10692 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10693 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 10694 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 10695 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10696 | // MIs[3] LHS |
| 10697 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 10698 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 10699 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10700 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 10701 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10702 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10703 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 10704 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 10705 | // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$LHS), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] }))) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS) |
| 10706 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 10707 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 10708 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS |
| 10709 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS |
| 10710 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS |
| 10711 | GIR_EraseFromParent, /*InsnID*/0, |
| 10712 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10713 | // GIR_Coverage, 7835, |
| 10714 | GIR_Done, |
| 10715 | // Label 590: @24695 |
| 10716 | GIM_Try, /*On fail goto*//*Label 591*/ 24756, // Rule ID 7984 // |
| 10717 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10718 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10719 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 10720 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10721 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10722 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10723 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10724 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 10725 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10726 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10727 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10728 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10729 | // (or:{ *:[v2i32] } (xor:{ *:[v2i32] } immAllOnesV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$RHS), V64:{ *:[v2i32] }:$LHS) => (ORNv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) |
| 10730 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv8i8, |
| 10731 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 10732 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS |
| 10733 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 10734 | GIR_EraseFromParent, /*InsnID*/0, |
| 10735 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10736 | // GIR_Coverage, 7984, |
| 10737 | GIR_Done, |
| 10738 | // Label 591: @24756 |
| 10739 | GIM_Try, /*On fail goto*//*Label 592*/ 24817, // Rule ID 7983 // |
| 10740 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10741 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10742 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 10743 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10744 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10745 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10746 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 10747 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10748 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 10749 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10750 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10751 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10752 | // (or:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$LHS) => (ORNv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) |
| 10753 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv8i8, |
| 10754 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 10755 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS |
| 10756 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 10757 | GIR_EraseFromParent, /*InsnID*/0, |
| 10758 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10759 | // GIR_Coverage, 7983, |
| 10760 | GIR_Done, |
| 10761 | // Label 592: @24817 |
| 10762 | GIM_Try, /*On fail goto*//*Label 593*/ 24878, // Rule ID 7982 // |
| 10763 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10764 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10765 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 10766 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 10767 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10768 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10769 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10770 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10771 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 10772 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10773 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10774 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10775 | // (or:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, (xor:{ *:[v2i32] } immAllOnesV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$RHS)) => (ORNv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) |
| 10776 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv8i8, |
| 10777 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 10778 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS |
| 10779 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 10780 | GIR_EraseFromParent, /*InsnID*/0, |
| 10781 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10782 | // GIR_Coverage, 7982, |
| 10783 | GIR_Done, |
| 10784 | // Label 593: @24878 |
| 10785 | GIM_Try, /*On fail goto*//*Label 594*/ 24939, // Rule ID 4080 // |
| 10786 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10787 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10788 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 10789 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 10790 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10791 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10792 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10793 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 10794 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10795 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 10796 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10797 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10798 | // (or:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, immAllOnesV:{ *:[v2i32] })) => (ORNv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) |
| 10799 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv8i8, |
| 10800 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 10801 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS |
| 10802 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 10803 | GIR_EraseFromParent, /*InsnID*/0, |
| 10804 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10805 | // GIR_Coverage, 4080, |
| 10806 | GIR_Done, |
| 10807 | // Label 594: @24939 |
| 10808 | GIM_Try, /*On fail goto*//*Label 595*/ 24958, // Rule ID 4086 // |
| 10809 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10810 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 10811 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 10812 | // (or:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (ORRv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) |
| 10813 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv8i8, |
| 10814 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10815 | // GIR_Coverage, 4086, |
| 10816 | GIR_Done, |
| 10817 | // Label 595: @24958 |
| 10818 | GIM_Reject, |
| 10819 | // Label 574: @24959 |
| 10820 | GIM_Reject, |
| 10821 | // Label 528: @24960 |
| 10822 | GIM_Try, /*On fail goto*//*Label 596*/ 26902, |
| 10823 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10824 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 10825 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 10826 | GIM_Try, /*On fail goto*//*Label 597*/ 25078, // Rule ID 7900 // |
| 10827 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10828 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10829 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 10830 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10831 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 10832 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10833 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 10834 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10835 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, |
| 10836 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 10837 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10838 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 10839 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 10840 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 10841 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 10842 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 10843 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10844 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 10845 | // MIs[4] LHS |
| 10846 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 10847 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10848 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10849 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 10850 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 10851 | // (or:{ *:[v2i64] } (and:{ *:[v2i64] } (xor:{ *:[v2i64] } immAllOnesV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$LHS), V128:{ *:[v2i64] }:$RHS), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$LHS)) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS) |
| 10852 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 10853 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 10854 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // LHS |
| 10855 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS |
| 10856 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 10857 | GIR_EraseFromParent, /*InsnID*/0, |
| 10858 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10859 | // GIR_Coverage, 7900, |
| 10860 | GIR_Done, |
| 10861 | // Label 597: @25078 |
| 10862 | GIM_Try, /*On fail goto*//*Label 598*/ 25182, // Rule ID 7899 // |
| 10863 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10864 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10865 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 10866 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10867 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 10868 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10869 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 10870 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10871 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, |
| 10872 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 10873 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10874 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 10875 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 10876 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 10877 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 10878 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 10879 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s64, |
| 10880 | // MIs[4] LHS |
| 10881 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 10882 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 10883 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10884 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10885 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 10886 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 10887 | // (or:{ *:[v2i64] } (and:{ *:[v2i64] } (xor:{ *:[v2i64] } immAllOnesV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$LHS), V128:{ *:[v2i64] }:$RHS), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS)) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS) |
| 10888 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 10889 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 10890 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // LHS |
| 10891 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS |
| 10892 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 10893 | GIR_EraseFromParent, /*InsnID*/0, |
| 10894 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10895 | // GIR_Coverage, 7899, |
| 10896 | GIR_Done, |
| 10897 | // Label 598: @25182 |
| 10898 | GIM_Try, /*On fail goto*//*Label 599*/ 25286, // Rule ID 7898 // |
| 10899 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10900 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10901 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 10902 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10903 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 10904 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10905 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 10906 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10907 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, |
| 10908 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 10909 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 10910 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10911 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 10912 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 10913 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 10914 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 10915 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10916 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 10917 | // MIs[4] LHS |
| 10918 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 10919 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10920 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10921 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 10922 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 10923 | // (or:{ *:[v2i64] } (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$RHS), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$LHS)) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS) |
| 10924 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 10925 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 10926 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS |
| 10927 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS |
| 10928 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 10929 | GIR_EraseFromParent, /*InsnID*/0, |
| 10930 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10931 | // GIR_Coverage, 7898, |
| 10932 | GIR_Done, |
| 10933 | // Label 599: @25286 |
| 10934 | GIM_Try, /*On fail goto*//*Label 600*/ 25390, // Rule ID 7897 // |
| 10935 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10936 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10937 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 10938 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10939 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 10940 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10941 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 10942 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10943 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, |
| 10944 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 10945 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 10946 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10947 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 10948 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 10949 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 10950 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 10951 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s64, |
| 10952 | // MIs[4] LHS |
| 10953 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 10954 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 10955 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10956 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10957 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 10958 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 10959 | // (or:{ *:[v2i64] } (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$RHS), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS)) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS) |
| 10960 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 10961 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 10962 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS |
| 10963 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS |
| 10964 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 10965 | GIR_EraseFromParent, /*InsnID*/0, |
| 10966 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10967 | // GIR_Coverage, 7897, |
| 10968 | GIR_Done, |
| 10969 | // Label 600: @25390 |
| 10970 | GIM_Try, /*On fail goto*//*Label 601*/ 25494, // Rule ID 7904 // |
| 10971 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 10972 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10973 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 10974 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10975 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 10976 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 10977 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 10978 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 10979 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10980 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, |
| 10981 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 10982 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 10983 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 10984 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 10985 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 10986 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 10987 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s64, |
| 10988 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 10989 | // MIs[4] LHS |
| 10990 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 10991 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 10992 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 10993 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 10994 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 10995 | // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, (xor:{ *:[v2i64] } immAllOnesV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$LHS)), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$LHS)) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS) |
| 10996 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 10997 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 10998 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // LHS |
| 10999 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS |
| 11000 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 11001 | GIR_EraseFromParent, /*InsnID*/0, |
| 11002 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11003 | // GIR_Coverage, 7904, |
| 11004 | GIR_Done, |
| 11005 | // Label 601: @25494 |
| 11006 | GIM_Try, /*On fail goto*//*Label 602*/ 25598, // Rule ID 7903 // |
| 11007 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11008 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11009 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 11010 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11011 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11012 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 11013 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 11014 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 11015 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11016 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11017 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 11018 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11019 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 11020 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 11021 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 11022 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 11023 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11024 | // MIs[4] LHS |
| 11025 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 11026 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 11027 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11028 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11029 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 11030 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 11031 | // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, (xor:{ *:[v2i64] } immAllOnesV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$LHS)), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS)) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS) |
| 11032 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 11033 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 11034 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // LHS |
| 11035 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS |
| 11036 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 11037 | GIR_EraseFromParent, /*InsnID*/0, |
| 11038 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11039 | // GIR_Coverage, 7903, |
| 11040 | GIR_Done, |
| 11041 | // Label 602: @25598 |
| 11042 | GIM_Try, /*On fail goto*//*Label 603*/ 25702, // Rule ID 7902 // |
| 11043 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11044 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11045 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 11046 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11047 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11048 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 11049 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 11050 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 11051 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11052 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11053 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 11054 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 11055 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11056 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 11057 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 11058 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 11059 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11060 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 11061 | // MIs[4] LHS |
| 11062 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 11063 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11064 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11065 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 11066 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 11067 | // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] })), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$LHS)) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS) |
| 11068 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 11069 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 11070 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS |
| 11071 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS |
| 11072 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 11073 | GIR_EraseFromParent, /*InsnID*/0, |
| 11074 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11075 | // GIR_Coverage, 7902, |
| 11076 | GIR_Done, |
| 11077 | // Label 603: @25702 |
| 11078 | GIM_Try, /*On fail goto*//*Label 604*/ 25806, // Rule ID 7901 // |
| 11079 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11080 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11081 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 11082 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11083 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11084 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 11085 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 11086 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 11087 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11088 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11089 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 11090 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 11091 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11092 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 11093 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 11094 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 11095 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11096 | // MIs[4] LHS |
| 11097 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 11098 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 11099 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11100 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11101 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 11102 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 11103 | // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] })), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS)) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS) |
| 11104 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 11105 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 11106 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS |
| 11107 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS |
| 11108 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 11109 | GIR_EraseFromParent, /*InsnID*/0, |
| 11110 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11111 | // GIR_Coverage, 7901, |
| 11112 | GIR_Done, |
| 11113 | // Label 604: @25806 |
| 11114 | GIM_Try, /*On fail goto*//*Label 605*/ 25910, // Rule ID 7890 // |
| 11115 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11116 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11117 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 11118 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11119 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11120 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 11121 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 11122 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 11123 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 11124 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11125 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11126 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 11127 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 11128 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11129 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 11130 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11131 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 11132 | // MIs[3] LHS |
| 11133 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 11134 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 11135 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11136 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11137 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 11138 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 11139 | // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS), (and:{ *:[v2i64] } (xor:{ *:[v2i64] } immAllOnesV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$LHS), V128:{ *:[v2i64] }:$RHS)) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS) |
| 11140 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 11141 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 11142 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS |
| 11143 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS |
| 11144 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS |
| 11145 | GIR_EraseFromParent, /*InsnID*/0, |
| 11146 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11147 | // GIR_Coverage, 7890, |
| 11148 | GIR_Done, |
| 11149 | // Label 605: @25910 |
| 11150 | GIM_Try, /*On fail goto*//*Label 606*/ 26014, // Rule ID 7894 // |
| 11151 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11152 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11153 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 11154 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11155 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11156 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 11157 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 11158 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 11159 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 11160 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11161 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11162 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 11163 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 11164 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11165 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 11166 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11167 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 11168 | // MIs[3] LHS |
| 11169 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 11170 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 11171 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11172 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11173 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 11174 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 11175 | // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$LHS), (and:{ *:[v2i64] } (xor:{ *:[v2i64] } immAllOnesV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$LHS), V128:{ *:[v2i64] }:$RHS)) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS) |
| 11176 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 11177 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 11178 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS |
| 11179 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS |
| 11180 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS |
| 11181 | GIR_EraseFromParent, /*InsnID*/0, |
| 11182 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11183 | // GIR_Coverage, 7894, |
| 11184 | GIR_Done, |
| 11185 | // Label 606: @26014 |
| 11186 | GIM_Try, /*On fail goto*//*Label 607*/ 26118, // Rule ID 2676 // |
| 11187 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11188 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11189 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 11190 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11191 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11192 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 11193 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 11194 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 11195 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 11196 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11197 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11198 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 11199 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 11200 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11201 | // MIs[3] LHS |
| 11202 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 11203 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 11204 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11205 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 11206 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 11207 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11208 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11209 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 11210 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 11211 | // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS), (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$RHS)) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS) |
| 11212 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 11213 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 11214 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS |
| 11215 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS |
| 11216 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS |
| 11217 | GIR_EraseFromParent, /*InsnID*/0, |
| 11218 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11219 | // GIR_Coverage, 2676, |
| 11220 | GIR_Done, |
| 11221 | // Label 607: @26118 |
| 11222 | GIM_Try, /*On fail goto*//*Label 608*/ 26222, // Rule ID 7893 // |
| 11223 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11224 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11225 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 11226 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11227 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11228 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 11229 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 11230 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 11231 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 11232 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11233 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11234 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 11235 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 11236 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11237 | // MIs[3] LHS |
| 11238 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 11239 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 11240 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11241 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 11242 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 11243 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11244 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11245 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 11246 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 11247 | // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$LHS), (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$RHS)) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS) |
| 11248 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 11249 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 11250 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS |
| 11251 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS |
| 11252 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS |
| 11253 | GIR_EraseFromParent, /*InsnID*/0, |
| 11254 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11255 | // GIR_Coverage, 7893, |
| 11256 | GIR_Done, |
| 11257 | // Label 608: @26222 |
| 11258 | GIM_Try, /*On fail goto*//*Label 609*/ 26326, // Rule ID 7892 // |
| 11259 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11260 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11261 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 11262 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11263 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11264 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 11265 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 11266 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 11267 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 11268 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11269 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11270 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 11271 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 11272 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 11273 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11274 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 11275 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11276 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 11277 | // MIs[3] LHS |
| 11278 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 11279 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11280 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11281 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 11282 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 11283 | // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, (xor:{ *:[v2i64] } immAllOnesV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$LHS))) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS) |
| 11284 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 11285 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 11286 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS |
| 11287 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS |
| 11288 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS |
| 11289 | GIR_EraseFromParent, /*InsnID*/0, |
| 11290 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11291 | // GIR_Coverage, 7892, |
| 11292 | GIR_Done, |
| 11293 | // Label 609: @26326 |
| 11294 | GIM_Try, /*On fail goto*//*Label 610*/ 26430, // Rule ID 7896 // |
| 11295 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11296 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11297 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 11298 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11299 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11300 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 11301 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 11302 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 11303 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 11304 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11305 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11306 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 11307 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 11308 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 11309 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11310 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 11311 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11312 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 11313 | // MIs[3] LHS |
| 11314 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 11315 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11316 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11317 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 11318 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 11319 | // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$LHS), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, (xor:{ *:[v2i64] } immAllOnesV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$LHS))) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS) |
| 11320 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 11321 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 11322 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS |
| 11323 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS |
| 11324 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS |
| 11325 | GIR_EraseFromParent, /*InsnID*/0, |
| 11326 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11327 | // GIR_Coverage, 7896, |
| 11328 | GIR_Done, |
| 11329 | // Label 610: @26430 |
| 11330 | GIM_Try, /*On fail goto*//*Label 611*/ 26534, // Rule ID 7891 // |
| 11331 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11332 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11333 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 11334 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11335 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11336 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 11337 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 11338 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 11339 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 11340 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11341 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11342 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 11343 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 11344 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 11345 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11346 | // MIs[3] LHS |
| 11347 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 11348 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 11349 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11350 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 11351 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11352 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11353 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 11354 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 11355 | // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] }))) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS) |
| 11356 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 11357 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 11358 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS |
| 11359 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS |
| 11360 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS |
| 11361 | GIR_EraseFromParent, /*InsnID*/0, |
| 11362 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11363 | // GIR_Coverage, 7891, |
| 11364 | GIR_Done, |
| 11365 | // Label 611: @26534 |
| 11366 | GIM_Try, /*On fail goto*//*Label 612*/ 26638, // Rule ID 7895 // |
| 11367 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11368 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11369 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 11370 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11371 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11372 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 11373 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 11374 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 11375 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 11376 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11377 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11378 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 11379 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 11380 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 11381 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11382 | // MIs[3] LHS |
| 11383 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 11384 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 11385 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11386 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 11387 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11388 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11389 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 11390 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 11391 | // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$LHS), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] }))) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS) |
| 11392 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 11393 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 11394 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS |
| 11395 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS |
| 11396 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS |
| 11397 | GIR_EraseFromParent, /*InsnID*/0, |
| 11398 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11399 | // GIR_Coverage, 7895, |
| 11400 | GIR_Done, |
| 11401 | // Label 612: @26638 |
| 11402 | GIM_Try, /*On fail goto*//*Label 613*/ 26699, // Rule ID 7996 // |
| 11403 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11404 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11405 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 11406 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11407 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11408 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 11409 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11410 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 11411 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 11412 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 11413 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11414 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11415 | // (or:{ *:[v2i64] } (xor:{ *:[v2i64] } immAllOnesV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$RHS), V128:{ *:[v2i64] }:$LHS) => (ORNv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) |
| 11416 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv16i8, |
| 11417 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 11418 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS |
| 11419 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 11420 | GIR_EraseFromParent, /*InsnID*/0, |
| 11421 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11422 | // GIR_Coverage, 7996, |
| 11423 | GIR_Done, |
| 11424 | // Label 613: @26699 |
| 11425 | GIM_Try, /*On fail goto*//*Label 614*/ 26760, // Rule ID 7995 // |
| 11426 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11427 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11428 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 11429 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11430 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11431 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 11432 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 11433 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11434 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 11435 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 11436 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11437 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11438 | // (or:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$LHS) => (ORNv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) |
| 11439 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv16i8, |
| 11440 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 11441 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS |
| 11442 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 11443 | GIR_EraseFromParent, /*InsnID*/0, |
| 11444 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11445 | // GIR_Coverage, 7995, |
| 11446 | GIR_Done, |
| 11447 | // Label 614: @26760 |
| 11448 | GIM_Try, /*On fail goto*//*Label 615*/ 26821, // Rule ID 7994 // |
| 11449 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11450 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 11451 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 11452 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 11453 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11454 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11455 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 11456 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11457 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 11458 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 11459 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11460 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11461 | // (or:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, (xor:{ *:[v2i64] } immAllOnesV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$RHS)) => (ORNv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) |
| 11462 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv16i8, |
| 11463 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 11464 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS |
| 11465 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 11466 | GIR_EraseFromParent, /*InsnID*/0, |
| 11467 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11468 | // GIR_Coverage, 7994, |
| 11469 | GIR_Done, |
| 11470 | // Label 615: @26821 |
| 11471 | GIM_Try, /*On fail goto*//*Label 616*/ 26882, // Rule ID 4084 // |
| 11472 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11473 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 11474 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 11475 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 11476 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11477 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11478 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 11479 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 11480 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11481 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 11482 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11483 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11484 | // (or:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, immAllOnesV:{ *:[v2i64] })) => (ORNv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) |
| 11485 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv16i8, |
| 11486 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 11487 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS |
| 11488 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 11489 | GIR_EraseFromParent, /*InsnID*/0, |
| 11490 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11491 | // GIR_Coverage, 4084, |
| 11492 | GIR_Done, |
| 11493 | // Label 616: @26882 |
| 11494 | GIM_Try, /*On fail goto*//*Label 617*/ 26901, // Rule ID 4090 // |
| 11495 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11496 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 11497 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 11498 | // (or:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (ORRv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) |
| 11499 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv16i8, |
| 11500 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11501 | // GIR_Coverage, 4090, |
| 11502 | GIR_Done, |
| 11503 | // Label 617: @26901 |
| 11504 | GIM_Reject, |
| 11505 | // Label 596: @26902 |
| 11506 | GIM_Reject, |
| 11507 | // Label 529: @26903 |
| 11508 | GIM_Try, /*On fail goto*//*Label 618*/ 28845, |
| 11509 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11510 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11511 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 11512 | GIM_Try, /*On fail goto*//*Label 619*/ 27021, // Rule ID 7825 // |
| 11513 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11514 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11515 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 11516 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11517 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11518 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 11519 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 11520 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11521 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11522 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 11523 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11524 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 11525 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 11526 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 11527 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 11528 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 11529 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11530 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 11531 | // MIs[4] LHS |
| 11532 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 11533 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11534 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11535 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 11536 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 11537 | // (or:{ *:[v4i16] } (and:{ *:[v4i16] } (xor:{ *:[v4i16] } immAllOnesV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$LHS), V64:{ *:[v4i16] }:$RHS), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$LHS)) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS) |
| 11538 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 11539 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 11540 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // LHS |
| 11541 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS |
| 11542 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 11543 | GIR_EraseFromParent, /*InsnID*/0, |
| 11544 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11545 | // GIR_Coverage, 7825, |
| 11546 | GIR_Done, |
| 11547 | // Label 619: @27021 |
| 11548 | GIM_Try, /*On fail goto*//*Label 620*/ 27125, // Rule ID 7824 // |
| 11549 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11550 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11551 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 11552 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11553 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11554 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 11555 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 11556 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11557 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11558 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 11559 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11560 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 11561 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 11562 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 11563 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 11564 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 11565 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11566 | // MIs[4] LHS |
| 11567 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 11568 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 11569 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11570 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11571 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 11572 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 11573 | // (or:{ *:[v4i16] } (and:{ *:[v4i16] } (xor:{ *:[v4i16] } immAllOnesV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$LHS), V64:{ *:[v4i16] }:$RHS), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS)) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS) |
| 11574 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 11575 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 11576 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // LHS |
| 11577 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS |
| 11578 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 11579 | GIR_EraseFromParent, /*InsnID*/0, |
| 11580 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11581 | // GIR_Coverage, 7824, |
| 11582 | GIR_Done, |
| 11583 | // Label 620: @27125 |
| 11584 | GIM_Try, /*On fail goto*//*Label 621*/ 27229, // Rule ID 7823 // |
| 11585 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11586 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11587 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 11588 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11589 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11590 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 11591 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 11592 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11593 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11594 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 11595 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 11596 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11597 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 11598 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 11599 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 11600 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 11601 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11602 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 11603 | // MIs[4] LHS |
| 11604 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 11605 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11606 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11607 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 11608 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 11609 | // (or:{ *:[v4i16] } (and:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$RHS), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$LHS)) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS) |
| 11610 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 11611 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 11612 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS |
| 11613 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS |
| 11614 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 11615 | GIR_EraseFromParent, /*InsnID*/0, |
| 11616 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11617 | // GIR_Coverage, 7823, |
| 11618 | GIR_Done, |
| 11619 | // Label 621: @27229 |
| 11620 | GIM_Try, /*On fail goto*//*Label 622*/ 27333, // Rule ID 7822 // |
| 11621 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11622 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11623 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 11624 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11625 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11626 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 11627 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 11628 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11629 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11630 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 11631 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 11632 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11633 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 11634 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 11635 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 11636 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 11637 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11638 | // MIs[4] LHS |
| 11639 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 11640 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 11641 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11642 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11643 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 11644 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 11645 | // (or:{ *:[v4i16] } (and:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$RHS), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS)) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS) |
| 11646 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 11647 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 11648 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS |
| 11649 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS |
| 11650 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 11651 | GIR_EraseFromParent, /*InsnID*/0, |
| 11652 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11653 | // GIR_Coverage, 7822, |
| 11654 | GIR_Done, |
| 11655 | // Label 622: @27333 |
| 11656 | GIM_Try, /*On fail goto*//*Label 623*/ 27437, // Rule ID 7829 // |
| 11657 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11658 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11659 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 11660 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11661 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11662 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 11663 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 11664 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 11665 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11666 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11667 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 11668 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11669 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 11670 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 11671 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 11672 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 11673 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11674 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 11675 | // MIs[4] LHS |
| 11676 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 11677 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11678 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11679 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 11680 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 11681 | // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, (xor:{ *:[v4i16] } immAllOnesV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$LHS)), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$LHS)) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS) |
| 11682 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 11683 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 11684 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // LHS |
| 11685 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS |
| 11686 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 11687 | GIR_EraseFromParent, /*InsnID*/0, |
| 11688 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11689 | // GIR_Coverage, 7829, |
| 11690 | GIR_Done, |
| 11691 | // Label 623: @27437 |
| 11692 | GIM_Try, /*On fail goto*//*Label 624*/ 27541, // Rule ID 7828 // |
| 11693 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11694 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11695 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 11696 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11697 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11698 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 11699 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 11700 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 11701 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11702 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11703 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 11704 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11705 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 11706 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 11707 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 11708 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 11709 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11710 | // MIs[4] LHS |
| 11711 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 11712 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 11713 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11714 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11715 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 11716 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 11717 | // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, (xor:{ *:[v4i16] } immAllOnesV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$LHS)), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS)) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS) |
| 11718 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 11719 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 11720 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // LHS |
| 11721 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS |
| 11722 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 11723 | GIR_EraseFromParent, /*InsnID*/0, |
| 11724 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11725 | // GIR_Coverage, 7828, |
| 11726 | GIR_Done, |
| 11727 | // Label 624: @27541 |
| 11728 | GIM_Try, /*On fail goto*//*Label 625*/ 27645, // Rule ID 7827 // |
| 11729 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11730 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11731 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 11732 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11733 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11734 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 11735 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 11736 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 11737 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11738 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11739 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 11740 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 11741 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11742 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 11743 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 11744 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 11745 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11746 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 11747 | // MIs[4] LHS |
| 11748 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 11749 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11750 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11751 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 11752 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 11753 | // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] })), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$LHS)) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS) |
| 11754 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 11755 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 11756 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS |
| 11757 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS |
| 11758 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 11759 | GIR_EraseFromParent, /*InsnID*/0, |
| 11760 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11761 | // GIR_Coverage, 7827, |
| 11762 | GIR_Done, |
| 11763 | // Label 625: @27645 |
| 11764 | GIM_Try, /*On fail goto*//*Label 626*/ 27749, // Rule ID 7826 // |
| 11765 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11766 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11767 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 11768 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11769 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11770 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 11771 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 11772 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 11773 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11774 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11775 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 11776 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 11777 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11778 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 11779 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 11780 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 11781 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11782 | // MIs[4] LHS |
| 11783 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 11784 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 11785 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11786 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11787 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 11788 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 11789 | // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] })), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS)) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS) |
| 11790 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 11791 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 11792 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS |
| 11793 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS |
| 11794 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 11795 | GIR_EraseFromParent, /*InsnID*/0, |
| 11796 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11797 | // GIR_Coverage, 7826, |
| 11798 | GIR_Done, |
| 11799 | // Label 626: @27749 |
| 11800 | GIM_Try, /*On fail goto*//*Label 627*/ 27853, // Rule ID 7815 // |
| 11801 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11802 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11803 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 11804 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11805 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11806 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 11807 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 11808 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 11809 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 11810 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11811 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11812 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 11813 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 11814 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11815 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 11816 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11817 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 11818 | // MIs[3] LHS |
| 11819 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 11820 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 11821 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11822 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11823 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 11824 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 11825 | // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS), (and:{ *:[v4i16] } (xor:{ *:[v4i16] } immAllOnesV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$LHS), V64:{ *:[v4i16] }:$RHS)) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS) |
| 11826 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 11827 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 11828 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS |
| 11829 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS |
| 11830 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS |
| 11831 | GIR_EraseFromParent, /*InsnID*/0, |
| 11832 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11833 | // GIR_Coverage, 7815, |
| 11834 | GIR_Done, |
| 11835 | // Label 627: @27853 |
| 11836 | GIM_Try, /*On fail goto*//*Label 628*/ 27957, // Rule ID 7819 // |
| 11837 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11838 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11839 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 11840 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11841 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11842 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 11843 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 11844 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 11845 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 11846 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11847 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11848 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 11849 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 11850 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11851 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 11852 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11853 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 11854 | // MIs[3] LHS |
| 11855 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 11856 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 11857 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11858 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11859 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 11860 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 11861 | // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$LHS), (and:{ *:[v4i16] } (xor:{ *:[v4i16] } immAllOnesV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$LHS), V64:{ *:[v4i16] }:$RHS)) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS) |
| 11862 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 11863 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 11864 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS |
| 11865 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS |
| 11866 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS |
| 11867 | GIR_EraseFromParent, /*InsnID*/0, |
| 11868 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11869 | // GIR_Coverage, 7819, |
| 11870 | GIR_Done, |
| 11871 | // Label 628: @27957 |
| 11872 | GIM_Try, /*On fail goto*//*Label 629*/ 28061, // Rule ID 2671 // |
| 11873 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11874 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11875 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 11876 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11877 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11878 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 11879 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 11880 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 11881 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 11882 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11883 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11884 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 11885 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 11886 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11887 | // MIs[3] LHS |
| 11888 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 11889 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 11890 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11891 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 11892 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 11893 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11894 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11895 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 11896 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 11897 | // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS), (and:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$RHS)) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS) |
| 11898 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 11899 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 11900 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS |
| 11901 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS |
| 11902 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS |
| 11903 | GIR_EraseFromParent, /*InsnID*/0, |
| 11904 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11905 | // GIR_Coverage, 2671, |
| 11906 | GIR_Done, |
| 11907 | // Label 629: @28061 |
| 11908 | GIM_Try, /*On fail goto*//*Label 630*/ 28165, // Rule ID 7818 // |
| 11909 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11910 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11911 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 11912 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11913 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11914 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 11915 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 11916 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 11917 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 11918 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11919 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11920 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 11921 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 11922 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11923 | // MIs[3] LHS |
| 11924 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 11925 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 11926 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11927 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 11928 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 11929 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11930 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11931 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 11932 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 11933 | // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$LHS), (and:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$RHS)) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS) |
| 11934 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 11935 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 11936 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS |
| 11937 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS |
| 11938 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS |
| 11939 | GIR_EraseFromParent, /*InsnID*/0, |
| 11940 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11941 | // GIR_Coverage, 7818, |
| 11942 | GIR_Done, |
| 11943 | // Label 630: @28165 |
| 11944 | GIM_Try, /*On fail goto*//*Label 631*/ 28269, // Rule ID 7817 // |
| 11945 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11946 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11947 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 11948 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11949 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11950 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 11951 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 11952 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 11953 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 11954 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11955 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11956 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 11957 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 11958 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 11959 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11960 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 11961 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11962 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 11963 | // MIs[3] LHS |
| 11964 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 11965 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11966 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 11967 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 11968 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 11969 | // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, (xor:{ *:[v4i16] } immAllOnesV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$LHS))) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS) |
| 11970 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 11971 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 11972 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS |
| 11973 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS |
| 11974 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS |
| 11975 | GIR_EraseFromParent, /*InsnID*/0, |
| 11976 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11977 | // GIR_Coverage, 7817, |
| 11978 | GIR_Done, |
| 11979 | // Label 631: @28269 |
| 11980 | GIM_Try, /*On fail goto*//*Label 632*/ 28373, // Rule ID 7821 // |
| 11981 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 11982 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 11983 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 11984 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11985 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11986 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 11987 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 11988 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 11989 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 11990 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11991 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 11992 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 11993 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 11994 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 11995 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11996 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 11997 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 11998 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 11999 | // MIs[3] LHS |
| 12000 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 12001 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12002 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12003 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 12004 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 12005 | // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$LHS), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, (xor:{ *:[v4i16] } immAllOnesV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$LHS))) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS) |
| 12006 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 12007 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12008 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS |
| 12009 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS |
| 12010 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS |
| 12011 | GIR_EraseFromParent, /*InsnID*/0, |
| 12012 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12013 | // GIR_Coverage, 7821, |
| 12014 | GIR_Done, |
| 12015 | // Label 632: @28373 |
| 12016 | GIM_Try, /*On fail goto*//*Label 633*/ 28477, // Rule ID 7816 // |
| 12017 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12018 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12019 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 12020 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 12021 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 12022 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 12023 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 12024 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 12025 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 12026 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 12027 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 12028 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 12029 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 12030 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 12031 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s16, |
| 12032 | // MIs[3] LHS |
| 12033 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 12034 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 12035 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12036 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 12037 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12038 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12039 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 12040 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 12041 | // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] }))) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS) |
| 12042 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 12043 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12044 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS |
| 12045 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS |
| 12046 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS |
| 12047 | GIR_EraseFromParent, /*InsnID*/0, |
| 12048 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12049 | // GIR_Coverage, 7816, |
| 12050 | GIR_Done, |
| 12051 | // Label 633: @28477 |
| 12052 | GIM_Try, /*On fail goto*//*Label 634*/ 28581, // Rule ID 7820 // |
| 12053 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12054 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12055 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 12056 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 12057 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 12058 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 12059 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 12060 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 12061 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 12062 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 12063 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 12064 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 12065 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 12066 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 12067 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s16, |
| 12068 | // MIs[3] LHS |
| 12069 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 12070 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 12071 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12072 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 12073 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12074 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12075 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 12076 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 12077 | // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$LHS), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] }))) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS) |
| 12078 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 12079 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12080 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS |
| 12081 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS |
| 12082 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS |
| 12083 | GIR_EraseFromParent, /*InsnID*/0, |
| 12084 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12085 | // GIR_Coverage, 7820, |
| 12086 | GIR_Done, |
| 12087 | // Label 634: @28581 |
| 12088 | GIM_Try, /*On fail goto*//*Label 635*/ 28642, // Rule ID 7981 // |
| 12089 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12090 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12091 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 12092 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 12093 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 12094 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 12095 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12096 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 12097 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 12098 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 12099 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12100 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12101 | // (or:{ *:[v4i16] } (xor:{ *:[v4i16] } immAllOnesV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$RHS), V64:{ *:[v4i16] }:$LHS) => (ORNv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) |
| 12102 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv8i8, |
| 12103 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 12104 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS |
| 12105 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 12106 | GIR_EraseFromParent, /*InsnID*/0, |
| 12107 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12108 | // GIR_Coverage, 7981, |
| 12109 | GIR_Done, |
| 12110 | // Label 635: @28642 |
| 12111 | GIM_Try, /*On fail goto*//*Label 636*/ 28703, // Rule ID 7980 // |
| 12112 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12113 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12114 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 12115 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 12116 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 12117 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 12118 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 12119 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12120 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 12121 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 12122 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12123 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12124 | // (or:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$LHS) => (ORNv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) |
| 12125 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv8i8, |
| 12126 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 12127 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS |
| 12128 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 12129 | GIR_EraseFromParent, /*InsnID*/0, |
| 12130 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12131 | // GIR_Coverage, 7980, |
| 12132 | GIR_Done, |
| 12133 | // Label 636: @28703 |
| 12134 | GIM_Try, /*On fail goto*//*Label 637*/ 28764, // Rule ID 7979 // |
| 12135 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12136 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 12137 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 12138 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 12139 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 12140 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 12141 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 12142 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12143 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 12144 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 12145 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12146 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12147 | // (or:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, (xor:{ *:[v4i16] } immAllOnesV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$RHS)) => (ORNv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) |
| 12148 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv8i8, |
| 12149 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 12150 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS |
| 12151 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 12152 | GIR_EraseFromParent, /*InsnID*/0, |
| 12153 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12154 | // GIR_Coverage, 7979, |
| 12155 | GIR_Done, |
| 12156 | // Label 637: @28764 |
| 12157 | GIM_Try, /*On fail goto*//*Label 638*/ 28825, // Rule ID 4079 // |
| 12158 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12159 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 12160 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 12161 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 12162 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 12163 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 12164 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 12165 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 12166 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12167 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 12168 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12169 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12170 | // (or:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, immAllOnesV:{ *:[v4i16] })) => (ORNv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) |
| 12171 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv8i8, |
| 12172 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 12173 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS |
| 12174 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 12175 | GIR_EraseFromParent, /*InsnID*/0, |
| 12176 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12177 | // GIR_Coverage, 4079, |
| 12178 | GIR_Done, |
| 12179 | // Label 638: @28825 |
| 12180 | GIM_Try, /*On fail goto*//*Label 639*/ 28844, // Rule ID 4085 // |
| 12181 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12182 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 12183 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 12184 | // (or:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (ORRv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) |
| 12185 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv8i8, |
| 12186 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12187 | // GIR_Coverage, 4085, |
| 12188 | GIR_Done, |
| 12189 | // Label 639: @28844 |
| 12190 | GIM_Reject, |
| 12191 | // Label 618: @28845 |
| 12192 | GIM_Reject, |
| 12193 | // Label 530: @28846 |
| 12194 | GIM_Try, /*On fail goto*//*Label 640*/ 30788, |
| 12195 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12196 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12197 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 12198 | GIM_Try, /*On fail goto*//*Label 641*/ 28964, // Rule ID 7885 // |
| 12199 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12200 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12201 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 12202 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12203 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12204 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 12205 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 12206 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12207 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12208 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 12209 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12210 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 12211 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12212 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12213 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 12214 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 12215 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12216 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12217 | // MIs[4] LHS |
| 12218 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 12219 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12220 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12221 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 12222 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 12223 | // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (xor:{ *:[v4i32] } immAllOnesV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$LHS), V128:{ *:[v4i32] }:$RHS), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$LHS)) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS) |
| 12224 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 12225 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12226 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // LHS |
| 12227 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS |
| 12228 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 12229 | GIR_EraseFromParent, /*InsnID*/0, |
| 12230 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12231 | // GIR_Coverage, 7885, |
| 12232 | GIR_Done, |
| 12233 | // Label 641: @28964 |
| 12234 | GIM_Try, /*On fail goto*//*Label 642*/ 29068, // Rule ID 7884 // |
| 12235 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12236 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12237 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 12238 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12239 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12240 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 12241 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 12242 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12243 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12244 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 12245 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12246 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 12247 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12248 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12249 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 12250 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 12251 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12252 | // MIs[4] LHS |
| 12253 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 12254 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12255 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12256 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12257 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 12258 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 12259 | // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (xor:{ *:[v4i32] } immAllOnesV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$LHS), V128:{ *:[v4i32] }:$RHS), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS)) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS) |
| 12260 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 12261 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12262 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // LHS |
| 12263 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS |
| 12264 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 12265 | GIR_EraseFromParent, /*InsnID*/0, |
| 12266 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12267 | // GIR_Coverage, 7884, |
| 12268 | GIR_Done, |
| 12269 | // Label 642: @29068 |
| 12270 | GIM_Try, /*On fail goto*//*Label 643*/ 29172, // Rule ID 7883 // |
| 12271 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12272 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12273 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 12274 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12275 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12276 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 12277 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 12278 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12279 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12280 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12281 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 12282 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12283 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 12284 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12285 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 12286 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 12287 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12288 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12289 | // MIs[4] LHS |
| 12290 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 12291 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12292 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12293 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 12294 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 12295 | // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$RHS), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$LHS)) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS) |
| 12296 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 12297 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12298 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS |
| 12299 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS |
| 12300 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 12301 | GIR_EraseFromParent, /*InsnID*/0, |
| 12302 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12303 | // GIR_Coverage, 7883, |
| 12304 | GIR_Done, |
| 12305 | // Label 643: @29172 |
| 12306 | GIM_Try, /*On fail goto*//*Label 644*/ 29276, // Rule ID 7882 // |
| 12307 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12308 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12309 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 12310 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12311 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12312 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 12313 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 12314 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12315 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12316 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12317 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 12318 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12319 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 12320 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12321 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 12322 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 12323 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12324 | // MIs[4] LHS |
| 12325 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 12326 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12327 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12328 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12329 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 12330 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 12331 | // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$RHS), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS)) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS) |
| 12332 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 12333 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12334 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS |
| 12335 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS |
| 12336 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 12337 | GIR_EraseFromParent, /*InsnID*/0, |
| 12338 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12339 | // GIR_Coverage, 7882, |
| 12340 | GIR_Done, |
| 12341 | // Label 644: @29276 |
| 12342 | GIM_Try, /*On fail goto*//*Label 645*/ 29380, // Rule ID 7889 // |
| 12343 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12344 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12345 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 12346 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12347 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12348 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12349 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 12350 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 12351 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12352 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12353 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 12354 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12355 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 12356 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12357 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 12358 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 12359 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12360 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12361 | // MIs[4] LHS |
| 12362 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 12363 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12364 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12365 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 12366 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 12367 | // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, (xor:{ *:[v4i32] } immAllOnesV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$LHS)), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$LHS)) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS) |
| 12368 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 12369 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12370 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // LHS |
| 12371 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS |
| 12372 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 12373 | GIR_EraseFromParent, /*InsnID*/0, |
| 12374 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12375 | // GIR_Coverage, 7889, |
| 12376 | GIR_Done, |
| 12377 | // Label 645: @29380 |
| 12378 | GIM_Try, /*On fail goto*//*Label 646*/ 29484, // Rule ID 7888 // |
| 12379 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12380 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12381 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 12382 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12383 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12384 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12385 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 12386 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 12387 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12388 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12389 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 12390 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12391 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 12392 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12393 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 12394 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 12395 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12396 | // MIs[4] LHS |
| 12397 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 12398 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12399 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12400 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12401 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 12402 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 12403 | // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, (xor:{ *:[v4i32] } immAllOnesV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$LHS)), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS)) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS) |
| 12404 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 12405 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12406 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // LHS |
| 12407 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS |
| 12408 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 12409 | GIR_EraseFromParent, /*InsnID*/0, |
| 12410 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12411 | // GIR_Coverage, 7888, |
| 12412 | GIR_Done, |
| 12413 | // Label 646: @29484 |
| 12414 | GIM_Try, /*On fail goto*//*Label 647*/ 29588, // Rule ID 7887 // |
| 12415 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12416 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12417 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 12418 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12419 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12420 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12421 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 12422 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 12423 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12424 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12425 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12426 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 12427 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12428 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 12429 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 12430 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 12431 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12432 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12433 | // MIs[4] LHS |
| 12434 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 12435 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12436 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12437 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 12438 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 12439 | // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] })), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$LHS)) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS) |
| 12440 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 12441 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12442 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS |
| 12443 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS |
| 12444 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 12445 | GIR_EraseFromParent, /*InsnID*/0, |
| 12446 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12447 | // GIR_Coverage, 7887, |
| 12448 | GIR_Done, |
| 12449 | // Label 647: @29588 |
| 12450 | GIM_Try, /*On fail goto*//*Label 648*/ 29692, // Rule ID 7886 // |
| 12451 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12452 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12453 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 12454 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12455 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12456 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12457 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 12458 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 12459 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12460 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12461 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12462 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 12463 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12464 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 12465 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 12466 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 12467 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12468 | // MIs[4] LHS |
| 12469 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 12470 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12471 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12472 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12473 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 12474 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 12475 | // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] })), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS)) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS) |
| 12476 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 12477 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12478 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS |
| 12479 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS |
| 12480 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 12481 | GIR_EraseFromParent, /*InsnID*/0, |
| 12482 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12483 | // GIR_Coverage, 7886, |
| 12484 | GIR_Done, |
| 12485 | // Label 648: @29692 |
| 12486 | GIM_Try, /*On fail goto*//*Label 649*/ 29796, // Rule ID 7875 // |
| 12487 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12488 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12489 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 12490 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12491 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12492 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12493 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12494 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 12495 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 12496 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12497 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12498 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 12499 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 12500 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12501 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 12502 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12503 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 12504 | // MIs[3] LHS |
| 12505 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 12506 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12507 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12508 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12509 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 12510 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 12511 | // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS), (and:{ *:[v4i32] } (xor:{ *:[v4i32] } immAllOnesV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$LHS), V128:{ *:[v4i32] }:$RHS)) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS) |
| 12512 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 12513 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12514 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS |
| 12515 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS |
| 12516 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS |
| 12517 | GIR_EraseFromParent, /*InsnID*/0, |
| 12518 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12519 | // GIR_Coverage, 7875, |
| 12520 | GIR_Done, |
| 12521 | // Label 649: @29796 |
| 12522 | GIM_Try, /*On fail goto*//*Label 650*/ 29900, // Rule ID 7879 // |
| 12523 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12524 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12525 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 12526 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12527 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12528 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12529 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12530 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 12531 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 12532 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12533 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12534 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 12535 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 12536 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12537 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 12538 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12539 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 12540 | // MIs[3] LHS |
| 12541 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 12542 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12543 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12544 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12545 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 12546 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 12547 | // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$LHS), (and:{ *:[v4i32] } (xor:{ *:[v4i32] } immAllOnesV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$LHS), V128:{ *:[v4i32] }:$RHS)) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS) |
| 12548 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 12549 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12550 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS |
| 12551 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS |
| 12552 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS |
| 12553 | GIR_EraseFromParent, /*InsnID*/0, |
| 12554 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12555 | // GIR_Coverage, 7879, |
| 12556 | GIR_Done, |
| 12557 | // Label 650: @29900 |
| 12558 | GIM_Try, /*On fail goto*//*Label 651*/ 30004, // Rule ID 2675 // |
| 12559 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12560 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12561 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 12562 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12563 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12564 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12565 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12566 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 12567 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 12568 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12569 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12570 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 12571 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 12572 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12573 | // MIs[3] LHS |
| 12574 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 12575 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 12576 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12577 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 12578 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12579 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12580 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12581 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 12582 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 12583 | // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS), (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$RHS)) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS) |
| 12584 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 12585 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12586 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS |
| 12587 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS |
| 12588 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS |
| 12589 | GIR_EraseFromParent, /*InsnID*/0, |
| 12590 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12591 | // GIR_Coverage, 2675, |
| 12592 | GIR_Done, |
| 12593 | // Label 651: @30004 |
| 12594 | GIM_Try, /*On fail goto*//*Label 652*/ 30108, // Rule ID 7878 // |
| 12595 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12596 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12597 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 12598 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12599 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12600 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12601 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12602 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 12603 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 12604 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12605 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12606 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 12607 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 12608 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12609 | // MIs[3] LHS |
| 12610 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 12611 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 12612 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12613 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 12614 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12615 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12616 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12617 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 12618 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 12619 | // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$LHS), (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$RHS)) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS) |
| 12620 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 12621 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12622 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS |
| 12623 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS |
| 12624 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS |
| 12625 | GIR_EraseFromParent, /*InsnID*/0, |
| 12626 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12627 | // GIR_Coverage, 7878, |
| 12628 | GIR_Done, |
| 12629 | // Label 652: @30108 |
| 12630 | GIM_Try, /*On fail goto*//*Label 653*/ 30212, // Rule ID 7877 // |
| 12631 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12632 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12633 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 12634 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12635 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12636 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12637 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12638 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 12639 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 12640 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12641 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12642 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12643 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 12644 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 12645 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12646 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 12647 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12648 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 12649 | // MIs[3] LHS |
| 12650 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 12651 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12652 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12653 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 12654 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 12655 | // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, (xor:{ *:[v4i32] } immAllOnesV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$LHS))) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS) |
| 12656 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 12657 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12658 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS |
| 12659 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS |
| 12660 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS |
| 12661 | GIR_EraseFromParent, /*InsnID*/0, |
| 12662 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12663 | // GIR_Coverage, 7877, |
| 12664 | GIR_Done, |
| 12665 | // Label 653: @30212 |
| 12666 | GIM_Try, /*On fail goto*//*Label 654*/ 30316, // Rule ID 7881 // |
| 12667 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12668 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12669 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 12670 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12671 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12672 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12673 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12674 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 12675 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 12676 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12677 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12678 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12679 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 12680 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 12681 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12682 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 12683 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12684 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 12685 | // MIs[3] LHS |
| 12686 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 12687 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12688 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12689 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 12690 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 12691 | // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$LHS), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, (xor:{ *:[v4i32] } immAllOnesV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$LHS))) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS) |
| 12692 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 12693 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12694 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS |
| 12695 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS |
| 12696 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS |
| 12697 | GIR_EraseFromParent, /*InsnID*/0, |
| 12698 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12699 | // GIR_Coverage, 7881, |
| 12700 | GIR_Done, |
| 12701 | // Label 654: @30316 |
| 12702 | GIM_Try, /*On fail goto*//*Label 655*/ 30420, // Rule ID 7876 // |
| 12703 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12704 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12705 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 12706 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12707 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12708 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12709 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12710 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 12711 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 12712 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12713 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12714 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12715 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 12716 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 12717 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12718 | // MIs[3] LHS |
| 12719 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 12720 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 12721 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12722 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 12723 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12724 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12725 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 12726 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 12727 | // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] }))) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS) |
| 12728 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 12729 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12730 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS |
| 12731 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS |
| 12732 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS |
| 12733 | GIR_EraseFromParent, /*InsnID*/0, |
| 12734 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12735 | // GIR_Coverage, 7876, |
| 12736 | GIR_Done, |
| 12737 | // Label 655: @30420 |
| 12738 | GIM_Try, /*On fail goto*//*Label 656*/ 30524, // Rule ID 7880 // |
| 12739 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12740 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12741 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 12742 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12743 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12744 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12745 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12746 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 12747 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 12748 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12749 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12750 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12751 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 12752 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 12753 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12754 | // MIs[3] LHS |
| 12755 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 12756 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 12757 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12758 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 12759 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12760 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12761 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 12762 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 12763 | // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$LHS), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] }))) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS) |
| 12764 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 12765 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12766 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS |
| 12767 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS |
| 12768 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS |
| 12769 | GIR_EraseFromParent, /*InsnID*/0, |
| 12770 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12771 | // GIR_Coverage, 7880, |
| 12772 | GIR_Done, |
| 12773 | // Label 656: @30524 |
| 12774 | GIM_Try, /*On fail goto*//*Label 657*/ 30585, // Rule ID 7993 // |
| 12775 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12776 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12777 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 12778 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12779 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12780 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 12781 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12782 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 12783 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12784 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12785 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12786 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12787 | // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } immAllOnesV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$RHS), V128:{ *:[v4i32] }:$LHS) => (ORNv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) |
| 12788 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv16i8, |
| 12789 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 12790 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS |
| 12791 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 12792 | GIR_EraseFromParent, /*InsnID*/0, |
| 12793 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12794 | // GIR_Coverage, 7993, |
| 12795 | GIR_Done, |
| 12796 | // Label 657: @30585 |
| 12797 | GIM_Try, /*On fail goto*//*Label 658*/ 30646, // Rule ID 7992 // |
| 12798 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12799 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12800 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 12801 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12802 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12803 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12804 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 12805 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12806 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 12807 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12808 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12809 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12810 | // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$LHS) => (ORNv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) |
| 12811 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv16i8, |
| 12812 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 12813 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS |
| 12814 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 12815 | GIR_EraseFromParent, /*InsnID*/0, |
| 12816 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12817 | // GIR_Coverage, 7992, |
| 12818 | GIR_Done, |
| 12819 | // Label 658: @30646 |
| 12820 | GIM_Try, /*On fail goto*//*Label 659*/ 30707, // Rule ID 7991 // |
| 12821 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12822 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12823 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 12824 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 12825 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12826 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12827 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 12828 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12829 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 12830 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12831 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12832 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12833 | // (or:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, (xor:{ *:[v4i32] } immAllOnesV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$RHS)) => (ORNv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) |
| 12834 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv16i8, |
| 12835 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 12836 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS |
| 12837 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 12838 | GIR_EraseFromParent, /*InsnID*/0, |
| 12839 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12840 | // GIR_Coverage, 7991, |
| 12841 | GIR_Done, |
| 12842 | // Label 659: @30707 |
| 12843 | GIM_Try, /*On fail goto*//*Label 660*/ 30768, // Rule ID 4083 // |
| 12844 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12845 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12846 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 12847 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 12848 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12849 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 12850 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12851 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 12852 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12853 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 12854 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12855 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12856 | // (or:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, immAllOnesV:{ *:[v4i32] })) => (ORNv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) |
| 12857 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv16i8, |
| 12858 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 12859 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS |
| 12860 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 12861 | GIR_EraseFromParent, /*InsnID*/0, |
| 12862 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12863 | // GIR_Coverage, 4083, |
| 12864 | GIR_Done, |
| 12865 | // Label 660: @30768 |
| 12866 | GIM_Try, /*On fail goto*//*Label 661*/ 30787, // Rule ID 4089 // |
| 12867 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12868 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 12869 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 12870 | // (or:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (ORRv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) |
| 12871 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv16i8, |
| 12872 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12873 | // GIR_Coverage, 4089, |
| 12874 | GIR_Done, |
| 12875 | // Label 661: @30787 |
| 12876 | GIM_Reject, |
| 12877 | // Label 640: @30788 |
| 12878 | GIM_Reject, |
| 12879 | // Label 531: @30789 |
| 12880 | GIM_Try, /*On fail goto*//*Label 662*/ 32731, |
| 12881 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 12882 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 12883 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 12884 | GIM_Try, /*On fail goto*//*Label 663*/ 30907, // Rule ID 7679 // |
| 12885 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12886 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12887 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 12888 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 12889 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 12890 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 12891 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 12892 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 12893 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 12894 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 12895 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12896 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 12897 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 12898 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 12899 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 12900 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 12901 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8, |
| 12902 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 12903 | // MIs[4] Rd |
| 12904 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 12905 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12906 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12907 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 12908 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 12909 | // (or:{ *:[v8i8] } (and:{ *:[v8i8] } (xor:{ *:[v8i8] } immAllOnesV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rd), V64:{ *:[v8i8] }:$Rm), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rd)) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 12910 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 12911 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12912 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rd |
| 12913 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 12914 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 12915 | GIR_EraseFromParent, /*InsnID*/0, |
| 12916 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12917 | // GIR_Coverage, 7679, |
| 12918 | GIR_Done, |
| 12919 | // Label 663: @30907 |
| 12920 | GIM_Try, /*On fail goto*//*Label 664*/ 31011, // Rule ID 7678 // |
| 12921 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12922 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12923 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 12924 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 12925 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 12926 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 12927 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 12928 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 12929 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 12930 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 12931 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12932 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 12933 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 12934 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 12935 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 12936 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 12937 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s8, |
| 12938 | // MIs[4] Rd |
| 12939 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 12940 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 12941 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12942 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12943 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 12944 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 12945 | // (or:{ *:[v8i8] } (and:{ *:[v8i8] } (xor:{ *:[v8i8] } immAllOnesV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rd), V64:{ *:[v8i8] }:$Rm), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn)) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 12946 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 12947 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12948 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rd |
| 12949 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Rn |
| 12950 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 12951 | GIR_EraseFromParent, /*InsnID*/0, |
| 12952 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12953 | // GIR_Coverage, 7678, |
| 12954 | GIR_Done, |
| 12955 | // Label 664: @31011 |
| 12956 | GIM_Try, /*On fail goto*//*Label 665*/ 31115, // Rule ID 7677 // |
| 12957 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12958 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12959 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 12960 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 12961 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 12962 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 12963 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 12964 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 12965 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 12966 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 12967 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 12968 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 12969 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 12970 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 12971 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 12972 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 12973 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8, |
| 12974 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 12975 | // MIs[4] Rd |
| 12976 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 12977 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12978 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12979 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 12980 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 12981 | // (or:{ *:[v8i8] } (and:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rm), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rd)) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 12982 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 12983 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12984 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd |
| 12985 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 12986 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 12987 | GIR_EraseFromParent, /*InsnID*/0, |
| 12988 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12989 | // GIR_Coverage, 7677, |
| 12990 | GIR_Done, |
| 12991 | // Label 665: @31115 |
| 12992 | GIM_Try, /*On fail goto*//*Label 666*/ 31219, // Rule ID 7676 // |
| 12993 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 12994 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12995 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 12996 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 12997 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 12998 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 12999 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 13000 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13001 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13002 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 13003 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 13004 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13005 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 13006 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 13007 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 13008 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 13009 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13010 | // MIs[4] Rd |
| 13011 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 13012 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 13013 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13014 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13015 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13016 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13017 | // (or:{ *:[v8i8] } (and:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rm), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn)) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 13018 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 13019 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 13020 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd |
| 13021 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Rn |
| 13022 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 13023 | GIR_EraseFromParent, /*InsnID*/0, |
| 13024 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13025 | // GIR_Coverage, 7676, |
| 13026 | GIR_Done, |
| 13027 | // Label 666: @31219 |
| 13028 | GIM_Try, /*On fail goto*//*Label 667*/ 31323, // Rule ID 7683 // |
| 13029 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13030 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13031 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13032 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13033 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13034 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 13035 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 13036 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 13037 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13038 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13039 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 13040 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13041 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 13042 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 13043 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 13044 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 13045 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13046 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 13047 | // MIs[4] Rd |
| 13048 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 13049 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13050 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13051 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13052 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13053 | // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, (xor:{ *:[v8i8] } immAllOnesV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rd)), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rd)) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 13054 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 13055 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 13056 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rd |
| 13057 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 13058 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 13059 | GIR_EraseFromParent, /*InsnID*/0, |
| 13060 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13061 | // GIR_Coverage, 7683, |
| 13062 | GIR_Done, |
| 13063 | // Label 667: @31323 |
| 13064 | GIM_Try, /*On fail goto*//*Label 668*/ 31427, // Rule ID 7682 // |
| 13065 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13066 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13067 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13068 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13069 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13070 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 13071 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 13072 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 13073 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13074 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13075 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 13076 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13077 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 13078 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 13079 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 13080 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 13081 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13082 | // MIs[4] Rd |
| 13083 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 13084 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 13085 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13086 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13087 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13088 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13089 | // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, (xor:{ *:[v8i8] } immAllOnesV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rd)), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn)) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 13090 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 13091 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 13092 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rd |
| 13093 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Rn |
| 13094 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 13095 | GIR_EraseFromParent, /*InsnID*/0, |
| 13096 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13097 | // GIR_Coverage, 7682, |
| 13098 | GIR_Done, |
| 13099 | // Label 668: @31427 |
| 13100 | GIM_Try, /*On fail goto*//*Label 669*/ 31531, // Rule ID 7681 // |
| 13101 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13102 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13103 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13104 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13105 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13106 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 13107 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 13108 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 13109 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13110 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13111 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 13112 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 13113 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13114 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 13115 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 13116 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 13117 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13118 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 13119 | // MIs[4] Rd |
| 13120 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 13121 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13122 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13123 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13124 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13125 | // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] })), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rd)) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 13126 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 13127 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 13128 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd |
| 13129 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 13130 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 13131 | GIR_EraseFromParent, /*InsnID*/0, |
| 13132 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13133 | // GIR_Coverage, 7681, |
| 13134 | GIR_Done, |
| 13135 | // Label 669: @31531 |
| 13136 | GIM_Try, /*On fail goto*//*Label 670*/ 31635, // Rule ID 7680 // |
| 13137 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13138 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13139 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13140 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13141 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13142 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 13143 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 13144 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 13145 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13146 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13147 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 13148 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 13149 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13150 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 13151 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 13152 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 13153 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13154 | // MIs[4] Rd |
| 13155 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 13156 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 13157 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13158 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13159 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13160 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13161 | // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] })), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn)) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 13162 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 13163 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 13164 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd |
| 13165 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Rn |
| 13166 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 13167 | GIR_EraseFromParent, /*InsnID*/0, |
| 13168 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13169 | // GIR_Coverage, 7680, |
| 13170 | GIR_Done, |
| 13171 | // Label 670: @31635 |
| 13172 | GIM_Try, /*On fail goto*//*Label 671*/ 31739, // Rule ID 7669 // |
| 13173 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13174 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13175 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13176 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13177 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13178 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 13179 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 13180 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 13181 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 13182 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13183 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13184 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 13185 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 13186 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13187 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 13188 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13189 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 13190 | // MIs[3] Rd |
| 13191 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 13192 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 13193 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13194 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13195 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13196 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13197 | // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn), (and:{ *:[v8i8] } (xor:{ *:[v8i8] } immAllOnesV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rd), V64:{ *:[v8i8] }:$Rm)) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 13198 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 13199 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 13200 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rd |
| 13201 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 13202 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm |
| 13203 | GIR_EraseFromParent, /*InsnID*/0, |
| 13204 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13205 | // GIR_Coverage, 7669, |
| 13206 | GIR_Done, |
| 13207 | // Label 671: @31739 |
| 13208 | GIM_Try, /*On fail goto*//*Label 672*/ 31843, // Rule ID 7673 // |
| 13209 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13210 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13211 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13212 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13213 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13214 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 13215 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 13216 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 13217 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 13218 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13219 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13220 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 13221 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 13222 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13223 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 13224 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13225 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 13226 | // MIs[3] Rd |
| 13227 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 13228 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 13229 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13230 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13231 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13232 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13233 | // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rd), (and:{ *:[v8i8] } (xor:{ *:[v8i8] } immAllOnesV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rd), V64:{ *:[v8i8] }:$Rm)) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 13234 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 13235 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 13236 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rd |
| 13237 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 13238 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm |
| 13239 | GIR_EraseFromParent, /*InsnID*/0, |
| 13240 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13241 | // GIR_Coverage, 7673, |
| 13242 | GIR_Done, |
| 13243 | // Label 672: @31843 |
| 13244 | GIM_Try, /*On fail goto*//*Label 673*/ 31947, // Rule ID 1323 // |
| 13245 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13246 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13247 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13248 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13249 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13250 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 13251 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 13252 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 13253 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 13254 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13255 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13256 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 13257 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 13258 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13259 | // MIs[3] Rd |
| 13260 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 13261 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 13262 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13263 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 13264 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 13265 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13266 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13267 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13268 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13269 | // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn), (and:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rm)) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 13270 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 13271 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 13272 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rd |
| 13273 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 13274 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm |
| 13275 | GIR_EraseFromParent, /*InsnID*/0, |
| 13276 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13277 | // GIR_Coverage, 1323, |
| 13278 | GIR_Done, |
| 13279 | // Label 673: @31947 |
| 13280 | GIM_Try, /*On fail goto*//*Label 674*/ 32051, // Rule ID 7672 // |
| 13281 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13282 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13283 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13284 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13285 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13286 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 13287 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 13288 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 13289 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 13290 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13291 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13292 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 13293 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 13294 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13295 | // MIs[3] Rd |
| 13296 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 13297 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 13298 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13299 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 13300 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 13301 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13302 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13303 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13304 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13305 | // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rd), (and:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rm)) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 13306 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 13307 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 13308 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rd |
| 13309 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 13310 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm |
| 13311 | GIR_EraseFromParent, /*InsnID*/0, |
| 13312 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13313 | // GIR_Coverage, 7672, |
| 13314 | GIR_Done, |
| 13315 | // Label 674: @32051 |
| 13316 | GIM_Try, /*On fail goto*//*Label 675*/ 32155, // Rule ID 7671 // |
| 13317 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13318 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13319 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13320 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13321 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13322 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 13323 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 13324 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 13325 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 13326 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13327 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13328 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 13329 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 13330 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 13331 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13332 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 13333 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13334 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 13335 | // MIs[3] Rd |
| 13336 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 13337 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13338 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13339 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13340 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13341 | // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, (xor:{ *:[v8i8] } immAllOnesV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rd))) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 13342 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 13343 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 13344 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rd |
| 13345 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 13346 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 13347 | GIR_EraseFromParent, /*InsnID*/0, |
| 13348 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13349 | // GIR_Coverage, 7671, |
| 13350 | GIR_Done, |
| 13351 | // Label 675: @32155 |
| 13352 | GIM_Try, /*On fail goto*//*Label 676*/ 32259, // Rule ID 7675 // |
| 13353 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13354 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13355 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13356 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13357 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13358 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 13359 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 13360 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 13361 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 13362 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13363 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13364 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 13365 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 13366 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 13367 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13368 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 13369 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13370 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 13371 | // MIs[3] Rd |
| 13372 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 13373 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13374 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13375 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13376 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13377 | // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rd), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, (xor:{ *:[v8i8] } immAllOnesV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rd))) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 13378 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 13379 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 13380 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rd |
| 13381 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 13382 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 13383 | GIR_EraseFromParent, /*InsnID*/0, |
| 13384 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13385 | // GIR_Coverage, 7675, |
| 13386 | GIR_Done, |
| 13387 | // Label 676: @32259 |
| 13388 | GIM_Try, /*On fail goto*//*Label 677*/ 32363, // Rule ID 7670 // |
| 13389 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13390 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13391 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13392 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13393 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13394 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 13395 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 13396 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 13397 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 13398 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13399 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13400 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 13401 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 13402 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 13403 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13404 | // MIs[3] Rd |
| 13405 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 13406 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 13407 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13408 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 13409 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13410 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13411 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13412 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13413 | // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] }))) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 13414 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 13415 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 13416 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rd |
| 13417 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 13418 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 13419 | GIR_EraseFromParent, /*InsnID*/0, |
| 13420 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13421 | // GIR_Coverage, 7670, |
| 13422 | GIR_Done, |
| 13423 | // Label 677: @32363 |
| 13424 | GIM_Try, /*On fail goto*//*Label 678*/ 32467, // Rule ID 7674 // |
| 13425 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13426 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13427 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13428 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13429 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13430 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 13431 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 13432 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 13433 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 13434 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13435 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13436 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 13437 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 13438 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 13439 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13440 | // MIs[3] Rd |
| 13441 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 13442 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 13443 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13444 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 13445 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13446 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13447 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13448 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13449 | // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rd), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] }))) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 13450 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv8i8, |
| 13451 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 13452 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rd |
| 13453 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 13454 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 13455 | GIR_EraseFromParent, /*InsnID*/0, |
| 13456 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13457 | // GIR_Coverage, 7674, |
| 13458 | GIR_Done, |
| 13459 | // Label 678: @32467 |
| 13460 | GIM_Try, /*On fail goto*//*Label 679*/ 32528, // Rule ID 7665 // |
| 13461 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13462 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13463 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 13464 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13465 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13466 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 13467 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13468 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 13469 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 13470 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 13471 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13472 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13473 | // (or:{ *:[v8i8] } (xor:{ *:[v8i8] } immAllOnesV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rn) => (ORNv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 13474 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv8i8, |
| 13475 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 13476 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 13477 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 13478 | GIR_EraseFromParent, /*InsnID*/0, |
| 13479 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13480 | // GIR_Coverage, 7665, |
| 13481 | GIR_Done, |
| 13482 | // Label 679: @32528 |
| 13483 | GIM_Try, /*On fail goto*//*Label 680*/ 32589, // Rule ID 7664 // |
| 13484 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13485 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13486 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 13487 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13488 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13489 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 13490 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 13491 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13492 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 13493 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 13494 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13495 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13496 | // (or:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rn) => (ORNv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 13497 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv8i8, |
| 13498 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 13499 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 13500 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 13501 | GIR_EraseFromParent, /*InsnID*/0, |
| 13502 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13503 | // GIR_Coverage, 7664, |
| 13504 | GIR_Done, |
| 13505 | // Label 680: @32589 |
| 13506 | GIM_Try, /*On fail goto*//*Label 681*/ 32650, // Rule ID 7663 // |
| 13507 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13508 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 13509 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13510 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 13511 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13512 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13513 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 13514 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13515 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 13516 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 13517 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13518 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13519 | // (or:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (xor:{ *:[v8i8] } immAllOnesV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rm)) => (ORNv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 13520 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv8i8, |
| 13521 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 13522 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 13523 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 13524 | GIR_EraseFromParent, /*InsnID*/0, |
| 13525 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13526 | // GIR_Coverage, 7663, |
| 13527 | GIR_Done, |
| 13528 | // Label 681: @32650 |
| 13529 | GIM_Try, /*On fail goto*//*Label 682*/ 32711, // Rule ID 1319 // |
| 13530 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13531 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 13532 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13533 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 13534 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 13535 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 13536 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 13537 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 13538 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13539 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 13540 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13541 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13542 | // (or:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, immAllOnesV:{ *:[v8i8] })) => (ORNv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 13543 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv8i8, |
| 13544 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 13545 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 13546 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 13547 | GIR_EraseFromParent, /*InsnID*/0, |
| 13548 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13549 | // GIR_Coverage, 1319, |
| 13550 | GIR_Done, |
| 13551 | // Label 682: @32711 |
| 13552 | GIM_Try, /*On fail goto*//*Label 683*/ 32730, // Rule ID 1321 // |
| 13553 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13554 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 13555 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 13556 | // (or:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (ORRv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 13557 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv8i8, |
| 13558 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13559 | // GIR_Coverage, 1321, |
| 13560 | GIR_Done, |
| 13561 | // Label 683: @32730 |
| 13562 | GIM_Reject, |
| 13563 | // Label 662: @32731 |
| 13564 | GIM_Reject, |
| 13565 | // Label 532: @32732 |
| 13566 | GIM_Try, /*On fail goto*//*Label 684*/ 34674, |
| 13567 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13568 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13569 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 13570 | GIM_Try, /*On fail goto*//*Label 685*/ 32850, // Rule ID 7870 // |
| 13571 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13572 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13573 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13574 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13575 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13576 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 13577 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 13578 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13579 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13580 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 13581 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13582 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 13583 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 13584 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 13585 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 13586 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 13587 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13588 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 13589 | // MIs[4] LHS |
| 13590 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 13591 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13592 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13593 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13594 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13595 | // (or:{ *:[v8i16] } (and:{ *:[v8i16] } (xor:{ *:[v8i16] } immAllOnesV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$LHS), V128:{ *:[v8i16] }:$RHS), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$LHS)) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS) |
| 13596 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 13597 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 13598 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // LHS |
| 13599 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS |
| 13600 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 13601 | GIR_EraseFromParent, /*InsnID*/0, |
| 13602 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13603 | // GIR_Coverage, 7870, |
| 13604 | GIR_Done, |
| 13605 | // Label 685: @32850 |
| 13606 | GIM_Try, /*On fail goto*//*Label 686*/ 32954, // Rule ID 7869 // |
| 13607 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13608 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13609 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13610 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13611 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13612 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 13613 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 13614 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13615 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13616 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 13617 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13618 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 13619 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 13620 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 13621 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 13622 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 13623 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13624 | // MIs[4] LHS |
| 13625 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 13626 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 13627 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13628 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13629 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13630 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13631 | // (or:{ *:[v8i16] } (and:{ *:[v8i16] } (xor:{ *:[v8i16] } immAllOnesV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$LHS), V128:{ *:[v8i16] }:$RHS), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS)) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS) |
| 13632 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 13633 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 13634 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // LHS |
| 13635 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS |
| 13636 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 13637 | GIR_EraseFromParent, /*InsnID*/0, |
| 13638 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13639 | // GIR_Coverage, 7869, |
| 13640 | GIR_Done, |
| 13641 | // Label 686: @32954 |
| 13642 | GIM_Try, /*On fail goto*//*Label 687*/ 33058, // Rule ID 7868 // |
| 13643 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13644 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13645 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13646 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13647 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13648 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 13649 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 13650 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13651 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13652 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 13653 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 13654 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13655 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 13656 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 13657 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 13658 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 13659 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13660 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 13661 | // MIs[4] LHS |
| 13662 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 13663 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13664 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13665 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13666 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13667 | // (or:{ *:[v8i16] } (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$RHS), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$LHS)) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS) |
| 13668 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 13669 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 13670 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS |
| 13671 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS |
| 13672 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 13673 | GIR_EraseFromParent, /*InsnID*/0, |
| 13674 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13675 | // GIR_Coverage, 7868, |
| 13676 | GIR_Done, |
| 13677 | // Label 687: @33058 |
| 13678 | GIM_Try, /*On fail goto*//*Label 688*/ 33162, // Rule ID 7867 // |
| 13679 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13680 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13681 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13682 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13683 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13684 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 13685 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 13686 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13687 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13688 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 13689 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 13690 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13691 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 13692 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 13693 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 13694 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 13695 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13696 | // MIs[4] LHS |
| 13697 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 13698 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 13699 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13700 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13701 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13702 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13703 | // (or:{ *:[v8i16] } (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$RHS), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS)) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS) |
| 13704 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 13705 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 13706 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS |
| 13707 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS |
| 13708 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 13709 | GIR_EraseFromParent, /*InsnID*/0, |
| 13710 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13711 | // GIR_Coverage, 7867, |
| 13712 | GIR_Done, |
| 13713 | // Label 688: @33162 |
| 13714 | GIM_Try, /*On fail goto*//*Label 689*/ 33266, // Rule ID 7874 // |
| 13715 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13716 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13717 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13718 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13719 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13720 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 13721 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 13722 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 13723 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13724 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13725 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 13726 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13727 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 13728 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 13729 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 13730 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 13731 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13732 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 13733 | // MIs[4] LHS |
| 13734 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 13735 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13736 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13737 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13738 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13739 | // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, (xor:{ *:[v8i16] } immAllOnesV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$LHS)), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$LHS)) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS) |
| 13740 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 13741 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 13742 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // LHS |
| 13743 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS |
| 13744 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 13745 | GIR_EraseFromParent, /*InsnID*/0, |
| 13746 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13747 | // GIR_Coverage, 7874, |
| 13748 | GIR_Done, |
| 13749 | // Label 689: @33266 |
| 13750 | GIM_Try, /*On fail goto*//*Label 690*/ 33370, // Rule ID 7873 // |
| 13751 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13752 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13753 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13754 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13755 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13756 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 13757 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 13758 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 13759 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13760 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13761 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 13762 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13763 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 13764 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 13765 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 13766 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 13767 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13768 | // MIs[4] LHS |
| 13769 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 13770 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 13771 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13772 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13773 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13774 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13775 | // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, (xor:{ *:[v8i16] } immAllOnesV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$LHS)), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS)) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS) |
| 13776 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 13777 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 13778 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // LHS |
| 13779 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS |
| 13780 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 13781 | GIR_EraseFromParent, /*InsnID*/0, |
| 13782 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13783 | // GIR_Coverage, 7873, |
| 13784 | GIR_Done, |
| 13785 | // Label 690: @33370 |
| 13786 | GIM_Try, /*On fail goto*//*Label 691*/ 33474, // Rule ID 7872 // |
| 13787 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13788 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13789 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13790 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13791 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13792 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 13793 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 13794 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 13795 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13796 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13797 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 13798 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 13799 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13800 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 13801 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 13802 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 13803 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13804 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 13805 | // MIs[4] LHS |
| 13806 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 13807 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13808 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13809 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13810 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13811 | // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] })), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$LHS)) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS) |
| 13812 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 13813 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 13814 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS |
| 13815 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS |
| 13816 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 13817 | GIR_EraseFromParent, /*InsnID*/0, |
| 13818 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13819 | // GIR_Coverage, 7872, |
| 13820 | GIR_Done, |
| 13821 | // Label 691: @33474 |
| 13822 | GIM_Try, /*On fail goto*//*Label 692*/ 33578, // Rule ID 7871 // |
| 13823 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13824 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13825 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13826 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13827 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13828 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 13829 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 13830 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 13831 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13832 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13833 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 13834 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 13835 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13836 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 13837 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 13838 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 13839 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13840 | // MIs[4] LHS |
| 13841 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 13842 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 13843 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13844 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13845 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13846 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13847 | // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] })), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS)) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS) |
| 13848 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 13849 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 13850 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS |
| 13851 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS |
| 13852 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 13853 | GIR_EraseFromParent, /*InsnID*/0, |
| 13854 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13855 | // GIR_Coverage, 7871, |
| 13856 | GIR_Done, |
| 13857 | // Label 692: @33578 |
| 13858 | GIM_Try, /*On fail goto*//*Label 693*/ 33682, // Rule ID 7860 // |
| 13859 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13860 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13861 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13862 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13863 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13864 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 13865 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 13866 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 13867 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 13868 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13869 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13870 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 13871 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 13872 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13873 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 13874 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13875 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 13876 | // MIs[3] LHS |
| 13877 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 13878 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 13879 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13880 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13881 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13882 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13883 | // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS), (and:{ *:[v8i16] } (xor:{ *:[v8i16] } immAllOnesV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$LHS), V128:{ *:[v8i16] }:$RHS)) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS) |
| 13884 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 13885 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 13886 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS |
| 13887 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS |
| 13888 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS |
| 13889 | GIR_EraseFromParent, /*InsnID*/0, |
| 13890 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13891 | // GIR_Coverage, 7860, |
| 13892 | GIR_Done, |
| 13893 | // Label 693: @33682 |
| 13894 | GIM_Try, /*On fail goto*//*Label 694*/ 33786, // Rule ID 7864 // |
| 13895 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13896 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13897 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13898 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13899 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13900 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 13901 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 13902 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 13903 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 13904 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13905 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13906 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 13907 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 13908 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13909 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 13910 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13911 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 13912 | // MIs[3] LHS |
| 13913 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 13914 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 13915 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13916 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13917 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13918 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13919 | // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$LHS), (and:{ *:[v8i16] } (xor:{ *:[v8i16] } immAllOnesV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$LHS), V128:{ *:[v8i16] }:$RHS)) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS) |
| 13920 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 13921 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 13922 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS |
| 13923 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS |
| 13924 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS |
| 13925 | GIR_EraseFromParent, /*InsnID*/0, |
| 13926 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13927 | // GIR_Coverage, 7864, |
| 13928 | GIR_Done, |
| 13929 | // Label 694: @33786 |
| 13930 | GIM_Try, /*On fail goto*//*Label 695*/ 33890, // Rule ID 2674 // |
| 13931 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13932 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13933 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13934 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13935 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13936 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 13937 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 13938 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 13939 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 13940 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13941 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13942 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 13943 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 13944 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13945 | // MIs[3] LHS |
| 13946 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 13947 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 13948 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13949 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 13950 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 13951 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13952 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13953 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13954 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13955 | // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS), (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$RHS)) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS) |
| 13956 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 13957 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 13958 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS |
| 13959 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS |
| 13960 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS |
| 13961 | GIR_EraseFromParent, /*InsnID*/0, |
| 13962 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13963 | // GIR_Coverage, 2674, |
| 13964 | GIR_Done, |
| 13965 | // Label 695: @33890 |
| 13966 | GIM_Try, /*On fail goto*//*Label 696*/ 33994, // Rule ID 7863 // |
| 13967 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 13968 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13969 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13970 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13971 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13972 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 13973 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 13974 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 13975 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 13976 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13977 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13978 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 13979 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 13980 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13981 | // MIs[3] LHS |
| 13982 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 13983 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 13984 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 13985 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 13986 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 13987 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13988 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13989 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13990 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13991 | // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$LHS), (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$RHS)) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS) |
| 13992 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 13993 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 13994 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS |
| 13995 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS |
| 13996 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS |
| 13997 | GIR_EraseFromParent, /*InsnID*/0, |
| 13998 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13999 | // GIR_Coverage, 7863, |
| 14000 | GIR_Done, |
| 14001 | // Label 696: @33994 |
| 14002 | GIM_Try, /*On fail goto*//*Label 697*/ 34098, // Rule ID 7862 // |
| 14003 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14004 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14005 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14006 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14007 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14008 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14009 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14010 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 14011 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 14012 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14013 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14014 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14015 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 14016 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 14017 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14018 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 14019 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14020 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 14021 | // MIs[3] LHS |
| 14022 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 14023 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14024 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14025 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14026 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14027 | // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, (xor:{ *:[v8i16] } immAllOnesV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$LHS))) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS) |
| 14028 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 14029 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 14030 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS |
| 14031 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS |
| 14032 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS |
| 14033 | GIR_EraseFromParent, /*InsnID*/0, |
| 14034 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14035 | // GIR_Coverage, 7862, |
| 14036 | GIR_Done, |
| 14037 | // Label 697: @34098 |
| 14038 | GIM_Try, /*On fail goto*//*Label 698*/ 34202, // Rule ID 7866 // |
| 14039 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14040 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14041 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14042 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14043 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14044 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14045 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14046 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 14047 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 14048 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14049 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14050 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14051 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 14052 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 14053 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14054 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 14055 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14056 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 14057 | // MIs[3] LHS |
| 14058 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 14059 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14060 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14061 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14062 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14063 | // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$LHS), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, (xor:{ *:[v8i16] } immAllOnesV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$LHS))) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS) |
| 14064 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 14065 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 14066 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS |
| 14067 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS |
| 14068 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS |
| 14069 | GIR_EraseFromParent, /*InsnID*/0, |
| 14070 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14071 | // GIR_Coverage, 7866, |
| 14072 | GIR_Done, |
| 14073 | // Label 698: @34202 |
| 14074 | GIM_Try, /*On fail goto*//*Label 699*/ 34306, // Rule ID 7861 // |
| 14075 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14076 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14077 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14078 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14079 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14080 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14081 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14082 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 14083 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 14084 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14085 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14086 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14087 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 14088 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 14089 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14090 | // MIs[3] LHS |
| 14091 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 14092 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 14093 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14094 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 14095 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14096 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14097 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14098 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14099 | // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] }))) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS) |
| 14100 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 14101 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 14102 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS |
| 14103 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS |
| 14104 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS |
| 14105 | GIR_EraseFromParent, /*InsnID*/0, |
| 14106 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14107 | // GIR_Coverage, 7861, |
| 14108 | GIR_Done, |
| 14109 | // Label 699: @34306 |
| 14110 | GIM_Try, /*On fail goto*//*Label 700*/ 34410, // Rule ID 7865 // |
| 14111 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14112 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14113 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14114 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14115 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14116 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14117 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14118 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 14119 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 14120 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14121 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14122 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14123 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 14124 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 14125 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14126 | // MIs[3] LHS |
| 14127 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 14128 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 14129 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14130 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 14131 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14132 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14133 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14134 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14135 | // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$LHS), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] }))) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS) |
| 14136 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 14137 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 14138 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS |
| 14139 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS |
| 14140 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS |
| 14141 | GIR_EraseFromParent, /*InsnID*/0, |
| 14142 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14143 | // GIR_Coverage, 7865, |
| 14144 | GIR_Done, |
| 14145 | // Label 700: @34410 |
| 14146 | GIM_Try, /*On fail goto*//*Label 701*/ 34471, // Rule ID 7990 // |
| 14147 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14148 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14149 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 14150 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14151 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14152 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 14153 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14154 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 14155 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14156 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14157 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14158 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14159 | // (or:{ *:[v8i16] } (xor:{ *:[v8i16] } immAllOnesV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$RHS), V128:{ *:[v8i16] }:$LHS) => (ORNv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) |
| 14160 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv16i8, |
| 14161 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 14162 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS |
| 14163 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 14164 | GIR_EraseFromParent, /*InsnID*/0, |
| 14165 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14166 | // GIR_Coverage, 7990, |
| 14167 | GIR_Done, |
| 14168 | // Label 701: @34471 |
| 14169 | GIM_Try, /*On fail goto*//*Label 702*/ 34532, // Rule ID 7989 // |
| 14170 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14171 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14172 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 14173 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14174 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14175 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14176 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 14177 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14178 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 14179 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14180 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14181 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14182 | // (or:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$LHS) => (ORNv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) |
| 14183 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv16i8, |
| 14184 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 14185 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS |
| 14186 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 14187 | GIR_EraseFromParent, /*InsnID*/0, |
| 14188 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14189 | // GIR_Coverage, 7989, |
| 14190 | GIR_Done, |
| 14191 | // Label 702: @34532 |
| 14192 | GIM_Try, /*On fail goto*//*Label 703*/ 34593, // Rule ID 7988 // |
| 14193 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14194 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14195 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14196 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 14197 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14198 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14199 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 14200 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14201 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 14202 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14203 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14204 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14205 | // (or:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, (xor:{ *:[v8i16] } immAllOnesV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$RHS)) => (ORNv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) |
| 14206 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv16i8, |
| 14207 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 14208 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS |
| 14209 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS |
| 14210 | GIR_EraseFromParent, /*InsnID*/0, |
| 14211 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14212 | // GIR_Coverage, 7988, |
| 14213 | GIR_Done, |
| 14214 | // Label 703: @34593 |
| 14215 | GIM_Try, /*On fail goto*//*Label 704*/ 34654, // Rule ID 4082 // |
| 14216 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14217 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14218 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14219 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 14220 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14221 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14222 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14223 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 14224 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14225 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 14226 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14227 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14228 | // (or:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, immAllOnesV:{ *:[v8i16] })) => (ORNv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) |
| 14229 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv16i8, |
| 14230 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 14231 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // LHS |
| 14232 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS |
| 14233 | GIR_EraseFromParent, /*InsnID*/0, |
| 14234 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14235 | // GIR_Coverage, 4082, |
| 14236 | GIR_Done, |
| 14237 | // Label 704: @34654 |
| 14238 | GIM_Try, /*On fail goto*//*Label 705*/ 34673, // Rule ID 4088 // |
| 14239 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14240 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14241 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14242 | // (or:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (ORRv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) |
| 14243 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv16i8, |
| 14244 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14245 | // GIR_Coverage, 4088, |
| 14246 | GIR_Done, |
| 14247 | // Label 705: @34673 |
| 14248 | GIM_Reject, |
| 14249 | // Label 684: @34674 |
| 14250 | GIM_Reject, |
| 14251 | // Label 533: @34675 |
| 14252 | GIM_Try, /*On fail goto*//*Label 706*/ 36617, |
| 14253 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14254 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14255 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 14256 | GIM_Try, /*On fail goto*//*Label 707*/ 34793, // Rule ID 7694 // |
| 14257 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14258 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14259 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14260 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14261 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14262 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 14263 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 14264 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14265 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14266 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 14267 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14268 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 14269 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14270 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14271 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 14272 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 14273 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14274 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14275 | // MIs[4] Rd |
| 14276 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 14277 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14278 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14279 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14280 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14281 | // (or:{ *:[v16i8] } (and:{ *:[v16i8] } (xor:{ *:[v16i8] } immAllOnesV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rd), V128:{ *:[v16i8] }:$Rm), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rd)) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 14282 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 14283 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 14284 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rd |
| 14285 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 14286 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 14287 | GIR_EraseFromParent, /*InsnID*/0, |
| 14288 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14289 | // GIR_Coverage, 7694, |
| 14290 | GIR_Done, |
| 14291 | // Label 707: @34793 |
| 14292 | GIM_Try, /*On fail goto*//*Label 708*/ 34897, // Rule ID 7693 // |
| 14293 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14294 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14295 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14296 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14297 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14298 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 14299 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 14300 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14301 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14302 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 14303 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14304 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 14305 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14306 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14307 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 14308 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 14309 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14310 | // MIs[4] Rd |
| 14311 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 14312 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14313 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14314 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14315 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14316 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14317 | // (or:{ *:[v16i8] } (and:{ *:[v16i8] } (xor:{ *:[v16i8] } immAllOnesV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rd), V128:{ *:[v16i8] }:$Rm), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 14318 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 14319 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 14320 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rd |
| 14321 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Rn |
| 14322 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 14323 | GIR_EraseFromParent, /*InsnID*/0, |
| 14324 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14325 | // GIR_Coverage, 7693, |
| 14326 | GIR_Done, |
| 14327 | // Label 708: @34897 |
| 14328 | GIM_Try, /*On fail goto*//*Label 709*/ 35001, // Rule ID 7692 // |
| 14329 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14330 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14331 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14332 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14333 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14334 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 14335 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 14336 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14337 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14338 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14339 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 14340 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14341 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 14342 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14343 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 14344 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 14345 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14346 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14347 | // MIs[4] Rd |
| 14348 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 14349 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14350 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14351 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14352 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14353 | // (or:{ *:[v16i8] } (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rm), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rd)) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 14354 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 14355 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 14356 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd |
| 14357 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 14358 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 14359 | GIR_EraseFromParent, /*InsnID*/0, |
| 14360 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14361 | // GIR_Coverage, 7692, |
| 14362 | GIR_Done, |
| 14363 | // Label 709: @35001 |
| 14364 | GIM_Try, /*On fail goto*//*Label 710*/ 35105, // Rule ID 7691 // |
| 14365 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14366 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14367 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14368 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14369 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14370 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 14371 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 14372 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14373 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14374 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14375 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 14376 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14377 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 14378 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14379 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 14380 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 14381 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14382 | // MIs[4] Rd |
| 14383 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 14384 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14385 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14386 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14387 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14388 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14389 | // (or:{ *:[v16i8] } (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rm), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 14390 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 14391 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 14392 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd |
| 14393 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Rn |
| 14394 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 14395 | GIR_EraseFromParent, /*InsnID*/0, |
| 14396 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14397 | // GIR_Coverage, 7691, |
| 14398 | GIR_Done, |
| 14399 | // Label 710: @35105 |
| 14400 | GIM_Try, /*On fail goto*//*Label 711*/ 35209, // Rule ID 7698 // |
| 14401 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14402 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14403 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14404 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14405 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14406 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14407 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 14408 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 14409 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14410 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14411 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 14412 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14413 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 14414 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14415 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 14416 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 14417 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14418 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14419 | // MIs[4] Rd |
| 14420 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 14421 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14422 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14423 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14424 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14425 | // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, (xor:{ *:[v16i8] } immAllOnesV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rd)), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rd)) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 14426 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 14427 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 14428 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rd |
| 14429 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 14430 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 14431 | GIR_EraseFromParent, /*InsnID*/0, |
| 14432 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14433 | // GIR_Coverage, 7698, |
| 14434 | GIR_Done, |
| 14435 | // Label 711: @35209 |
| 14436 | GIM_Try, /*On fail goto*//*Label 712*/ 35313, // Rule ID 7697 // |
| 14437 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14438 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14439 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14440 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14441 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14442 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14443 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 14444 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 14445 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14446 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14447 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 14448 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14449 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 14450 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14451 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 14452 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 14453 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14454 | // MIs[4] Rd |
| 14455 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 14456 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14457 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14458 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14459 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14460 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14461 | // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, (xor:{ *:[v16i8] } immAllOnesV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rd)), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 14462 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 14463 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 14464 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rd |
| 14465 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Rn |
| 14466 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 14467 | GIR_EraseFromParent, /*InsnID*/0, |
| 14468 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14469 | // GIR_Coverage, 7697, |
| 14470 | GIR_Done, |
| 14471 | // Label 712: @35313 |
| 14472 | GIM_Try, /*On fail goto*//*Label 713*/ 35417, // Rule ID 7696 // |
| 14473 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14474 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14475 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14476 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14477 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14478 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14479 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 14480 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 14481 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14482 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14483 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14484 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 14485 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14486 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 14487 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 14488 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 14489 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14490 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14491 | // MIs[4] Rd |
| 14492 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 14493 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14494 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14495 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14496 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14497 | // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] })), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rd)) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 14498 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 14499 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 14500 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd |
| 14501 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 14502 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 14503 | GIR_EraseFromParent, /*InsnID*/0, |
| 14504 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14505 | // GIR_Coverage, 7696, |
| 14506 | GIR_Done, |
| 14507 | // Label 713: @35417 |
| 14508 | GIM_Try, /*On fail goto*//*Label 714*/ 35521, // Rule ID 7695 // |
| 14509 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14510 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14511 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14512 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14513 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14514 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14515 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 14516 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, |
| 14517 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14518 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14519 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14520 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 14521 | GIM_CheckOpcodeIsEither, /*MI*/3, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14522 | GIM_CheckIsBuildVectorAllOnes, /*MI*/3, |
| 14523 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 14524 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, |
| 14525 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14526 | // MIs[4] Rd |
| 14527 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 14528 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14529 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14530 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14531 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14532 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14533 | // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] })), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 14534 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 14535 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 14536 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd |
| 14537 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Rn |
| 14538 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 14539 | GIR_EraseFromParent, /*InsnID*/0, |
| 14540 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14541 | // GIR_Coverage, 7695, |
| 14542 | GIR_Done, |
| 14543 | // Label 714: @35521 |
| 14544 | GIM_Try, /*On fail goto*//*Label 715*/ 35625, // Rule ID 7684 // |
| 14545 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14546 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14547 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14548 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14549 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14550 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14551 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14552 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 14553 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 14554 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14555 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14556 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 14557 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 14558 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14559 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 14560 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14561 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 14562 | // MIs[3] Rd |
| 14563 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 14564 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14565 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14566 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14567 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14568 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14569 | // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn), (and:{ *:[v16i8] } (xor:{ *:[v16i8] } immAllOnesV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rd), V128:{ *:[v16i8] }:$Rm)) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 14570 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 14571 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 14572 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rd |
| 14573 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 14574 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm |
| 14575 | GIR_EraseFromParent, /*InsnID*/0, |
| 14576 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14577 | // GIR_Coverage, 7684, |
| 14578 | GIR_Done, |
| 14579 | // Label 715: @35625 |
| 14580 | GIM_Try, /*On fail goto*//*Label 716*/ 35729, // Rule ID 7688 // |
| 14581 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14582 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14583 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14584 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14585 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14586 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14587 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14588 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 14589 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 14590 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14591 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14592 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 14593 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 14594 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14595 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 14596 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14597 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 14598 | // MIs[3] Rd |
| 14599 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 14600 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14601 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14602 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14603 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14604 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14605 | // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rd), (and:{ *:[v16i8] } (xor:{ *:[v16i8] } immAllOnesV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rd), V128:{ *:[v16i8] }:$Rm)) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 14606 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 14607 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 14608 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rd |
| 14609 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 14610 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm |
| 14611 | GIR_EraseFromParent, /*InsnID*/0, |
| 14612 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14613 | // GIR_Coverage, 7688, |
| 14614 | GIR_Done, |
| 14615 | // Label 716: @35729 |
| 14616 | GIM_Try, /*On fail goto*//*Label 717*/ 35833, // Rule ID 1324 // |
| 14617 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14618 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14619 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14620 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14621 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14622 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14623 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14624 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 14625 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 14626 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14627 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14628 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 14629 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 14630 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14631 | // MIs[3] Rd |
| 14632 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 14633 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 14634 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14635 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 14636 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14637 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14638 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14639 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14640 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14641 | // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn), (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rm)) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 14642 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 14643 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 14644 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rd |
| 14645 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 14646 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm |
| 14647 | GIR_EraseFromParent, /*InsnID*/0, |
| 14648 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14649 | // GIR_Coverage, 1324, |
| 14650 | GIR_Done, |
| 14651 | // Label 717: @35833 |
| 14652 | GIM_Try, /*On fail goto*//*Label 718*/ 35937, // Rule ID 7687 // |
| 14653 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14654 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14655 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14656 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14657 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14658 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14659 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14660 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 14661 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 14662 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14663 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14664 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 14665 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 14666 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14667 | // MIs[3] Rd |
| 14668 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 14669 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 14670 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14671 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 14672 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14673 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14674 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14675 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14676 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14677 | // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rd), (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rm)) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 14678 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 14679 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 14680 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rd |
| 14681 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 14682 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm |
| 14683 | GIR_EraseFromParent, /*InsnID*/0, |
| 14684 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14685 | // GIR_Coverage, 7687, |
| 14686 | GIR_Done, |
| 14687 | // Label 718: @35937 |
| 14688 | GIM_Try, /*On fail goto*//*Label 719*/ 36041, // Rule ID 7686 // |
| 14689 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14690 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14691 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14692 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14693 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14694 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14695 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14696 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 14697 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 14698 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14699 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14700 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14701 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 14702 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 14703 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14704 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 14705 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14706 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 14707 | // MIs[3] Rd |
| 14708 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 14709 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14710 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14711 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14712 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14713 | // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, (xor:{ *:[v16i8] } immAllOnesV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rd))) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 14714 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 14715 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 14716 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rd |
| 14717 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 14718 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 14719 | GIR_EraseFromParent, /*InsnID*/0, |
| 14720 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14721 | // GIR_Coverage, 7686, |
| 14722 | GIR_Done, |
| 14723 | // Label 719: @36041 |
| 14724 | GIM_Try, /*On fail goto*//*Label 720*/ 36145, // Rule ID 7690 // |
| 14725 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14726 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14727 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14728 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14729 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14730 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14731 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14732 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 14733 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 14734 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14735 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14736 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14737 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 14738 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 14739 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14740 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 14741 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14742 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 14743 | // MIs[3] Rd |
| 14744 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 14745 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14746 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14747 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14748 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14749 | // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rd), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, (xor:{ *:[v16i8] } immAllOnesV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rd))) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 14750 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 14751 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 14752 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rd |
| 14753 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 14754 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 14755 | GIR_EraseFromParent, /*InsnID*/0, |
| 14756 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14757 | // GIR_Coverage, 7690, |
| 14758 | GIR_Done, |
| 14759 | // Label 720: @36145 |
| 14760 | GIM_Try, /*On fail goto*//*Label 721*/ 36249, // Rule ID 7685 // |
| 14761 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14762 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14763 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14764 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14765 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14766 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14767 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14768 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 14769 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 14770 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14771 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14772 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14773 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 14774 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 14775 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14776 | // MIs[3] Rd |
| 14777 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 14778 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 14779 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14780 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 14781 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14782 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14783 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14784 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14785 | // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] }))) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 14786 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 14787 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 14788 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rd |
| 14789 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 14790 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 14791 | GIR_EraseFromParent, /*InsnID*/0, |
| 14792 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14793 | // GIR_Coverage, 7685, |
| 14794 | GIR_Done, |
| 14795 | // Label 721: @36249 |
| 14796 | GIM_Try, /*On fail goto*//*Label 722*/ 36353, // Rule ID 7689 // |
| 14797 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14798 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14799 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14800 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14801 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14802 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14803 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14804 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 14805 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 14806 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14807 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14808 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14809 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 14810 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 14811 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14812 | // MIs[3] Rd |
| 14813 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 14814 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 14815 | GIM_CheckOpcodeIsEither, /*MI*/4, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14816 | GIM_CheckIsBuildVectorAllOnes, /*MI*/4, |
| 14817 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14818 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14819 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14820 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14821 | // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rd), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] }))) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 14822 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BSPv16i8, |
| 14823 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 14824 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rd |
| 14825 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 14826 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 14827 | GIR_EraseFromParent, /*InsnID*/0, |
| 14828 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14829 | // GIR_Coverage, 7689, |
| 14830 | GIR_Done, |
| 14831 | // Label 722: @36353 |
| 14832 | GIM_Try, /*On fail goto*//*Label 723*/ 36414, // Rule ID 7668 // |
| 14833 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14834 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14835 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 14836 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14837 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14838 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 14839 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14840 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 14841 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14842 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14843 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14844 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14845 | // (or:{ *:[v16i8] } (xor:{ *:[v16i8] } immAllOnesV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rn) => (ORNv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 14846 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv16i8, |
| 14847 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 14848 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 14849 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 14850 | GIR_EraseFromParent, /*InsnID*/0, |
| 14851 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14852 | // GIR_Coverage, 7668, |
| 14853 | GIR_Done, |
| 14854 | // Label 723: @36414 |
| 14855 | GIM_Try, /*On fail goto*//*Label 724*/ 36475, // Rule ID 7667 // |
| 14856 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14857 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14858 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 14859 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14860 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14861 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14862 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 14863 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14864 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 14865 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14866 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14867 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14868 | // (or:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rn) => (ORNv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 14869 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv16i8, |
| 14870 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 14871 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 14872 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 14873 | GIR_EraseFromParent, /*InsnID*/0, |
| 14874 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14875 | // GIR_Coverage, 7667, |
| 14876 | GIR_Done, |
| 14877 | // Label 724: @36475 |
| 14878 | GIM_Try, /*On fail goto*//*Label 725*/ 36536, // Rule ID 7666 // |
| 14879 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14880 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14881 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14882 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 14883 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14884 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14885 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 14886 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14887 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 14888 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14889 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14890 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14891 | // (or:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (xor:{ *:[v16i8] } immAllOnesV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rm)) => (ORNv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 14892 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv16i8, |
| 14893 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 14894 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 14895 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 14896 | GIR_EraseFromParent, /*InsnID*/0, |
| 14897 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14898 | // GIR_Coverage, 7666, |
| 14899 | GIR_Done, |
| 14900 | // Label 725: @36536 |
| 14901 | GIM_Try, /*On fail goto*//*Label 726*/ 36597, // Rule ID 1320 // |
| 14902 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14903 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14904 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14905 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 14906 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14907 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14908 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14909 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 14910 | GIM_CheckOpcodeIsEither, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 14911 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 14912 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14913 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14914 | // (or:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, immAllOnesV:{ *:[v16i8] })) => (ORNv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 14915 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNv16i8, |
| 14916 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 14917 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 14918 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 14919 | GIR_EraseFromParent, /*InsnID*/0, |
| 14920 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14921 | // GIR_Coverage, 1320, |
| 14922 | GIR_Done, |
| 14923 | // Label 726: @36597 |
| 14924 | GIM_Try, /*On fail goto*//*Label 727*/ 36616, // Rule ID 1322 // |
| 14925 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 14926 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 14927 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 14928 | // (or:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (ORRv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 14929 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ORRv16i8, |
| 14930 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14931 | // GIR_Coverage, 1322, |
| 14932 | GIR_Done, |
| 14933 | // Label 727: @36616 |
| 14934 | GIM_Reject, |
| 14935 | // Label 706: @36617 |
| 14936 | GIM_Reject, |
| 14937 | // Label 534: @36618 |
| 14938 | GIM_Reject, |
| 14939 | // Label 7: @36619 |
| 14940 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 737*/ 39307, |
| 14941 | /*GILLT_s32*//*Label 728*/ 36635, |
| 14942 | /*GILLT_s64*//*Label 729*/ 37307, 0, |
| 14943 | /*GILLT_v2s32*//*Label 730*/ 38078, |
| 14944 | /*GILLT_v2s64*//*Label 731*/ 38181, |
| 14945 | /*GILLT_v4s16*//*Label 732*/ 38284, |
| 14946 | /*GILLT_v4s32*//*Label 733*/ 38387, |
| 14947 | /*GILLT_v8s8*//*Label 734*/ 38490, |
| 14948 | /*GILLT_v8s16*//*Label 735*/ 38597, |
| 14949 | /*GILLT_v16s8*//*Label 736*/ 39200, |
| 14950 | // Label 728: @36635 |
| 14951 | GIM_Try, /*On fail goto*//*Label 738*/ 37306, |
| 14952 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 14953 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 14954 | GIM_Try, /*On fail goto*//*Label 739*/ 36700, // Rule ID 7565 // |
| 14955 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 14956 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14957 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 14958 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 14959 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 14960 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 14961 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 14962 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14963 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, |
| 14964 | // (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, -1:{ *:[i32] })) => (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) |
| 14965 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrs, |
| 14966 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 14967 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 14968 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 14969 | GIR_EraseFromParent, /*InsnID*/0, |
| 14970 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14971 | // GIR_Coverage, 7565, |
| 14972 | GIR_Done, |
| 14973 | // Label 739: @36700 |
| 14974 | GIM_Try, /*On fail goto*//*Label 740*/ 36755, // Rule ID 7564 // |
| 14975 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 14976 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14977 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 14978 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 14979 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 14980 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 14981 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 14982 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14983 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, |
| 14984 | // (xor:{ *:[i32] } (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn) => (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) |
| 14985 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrs, |
| 14986 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 14987 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 14988 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 14989 | GIR_EraseFromParent, /*InsnID*/0, |
| 14990 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14991 | // GIR_Coverage, 7564, |
| 14992 | GIR_Done, |
| 14993 | // Label 740: @36755 |
| 14994 | GIM_Try, /*On fail goto*//*Label 741*/ 36810, // Rule ID 7562 // |
| 14995 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 14996 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14997 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 14998 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 14999 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 15000 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 15001 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
| 15002 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15003 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, |
| 15004 | // (xor:{ *:[i32] } (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm, GPR32:{ *:[i32] }:$Rn), -1:{ *:[i32] }) => (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) |
| 15005 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrs, |
| 15006 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15007 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 15008 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 15009 | GIR_EraseFromParent, /*InsnID*/0, |
| 15010 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15011 | // GIR_Coverage, 7562, |
| 15012 | GIR_Done, |
| 15013 | // Label 741: @36810 |
| 15014 | GIM_Try, /*On fail goto*//*Label 742*/ 36865, // Rule ID 157 // |
| 15015 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 15016 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15017 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 15018 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 15019 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 15020 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 15021 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
| 15022 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15023 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg32, |
| 15024 | // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm), -1:{ *:[i32] }) => (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) |
| 15025 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrs, |
| 15026 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15027 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 15028 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 15029 | GIR_EraseFromParent, /*InsnID*/0, |
| 15030 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15031 | // GIR_Coverage, 157, |
| 15032 | GIR_Done, |
| 15033 | // Label 742: @36865 |
| 15034 | GIM_Try, /*On fail goto*//*Label 743*/ 36920, // Rule ID 7563 // |
| 15035 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 15036 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15037 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 15038 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 15039 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 15040 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 15041 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 15042 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15043 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg32, |
| 15044 | // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, -1:{ *:[i32] }), logical_shifted_reg32:{ *:[i32] }:$Rm) => (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) |
| 15045 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrs, |
| 15046 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15047 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 15048 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 15049 | GIR_EraseFromParent, /*InsnID*/0, |
| 15050 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15051 | // GIR_Coverage, 7563, |
| 15052 | GIR_Done, |
| 15053 | // Label 743: @36920 |
| 15054 | GIM_Try, /*On fail goto*//*Label 744*/ 36975, // Rule ID 7566 // |
| 15055 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 15056 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 15057 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15058 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 15059 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 15060 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 15061 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 15062 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15063 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, |
| 15064 | // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) |
| 15065 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrs, |
| 15066 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15067 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 15068 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 15069 | GIR_EraseFromParent, /*InsnID*/0, |
| 15070 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15071 | // GIR_Coverage, 7566, |
| 15072 | GIR_Done, |
| 15073 | // Label 744: @36975 |
| 15074 | GIM_Try, /*On fail goto*//*Label 745*/ 37017, // Rule ID 135 // |
| 15075 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID, |
| 15076 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 15077 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15078 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 15079 | GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_logical_imm32, |
| 15080 | // MIs[1] Operand 1 |
| 15081 | // No operand predicates |
| 15082 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15083 | // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_logical_imm32>><<X:logical_imm32_XFORM>>:$imm) => (EORWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (logical_imm32_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm)) |
| 15084 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EORWri, |
| 15085 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15086 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 15087 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GICR_renderLogicalImm32, // imm |
| 15088 | GIR_EraseFromParent, /*InsnID*/0, |
| 15089 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15090 | // GIR_Coverage, 135, |
| 15091 | GIR_Done, |
| 15092 | // Label 745: @37017 |
| 15093 | GIM_Try, /*On fail goto*//*Label 746*/ 37051, // Rule ID 7572 // |
| 15094 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 15095 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 15096 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg32, |
| 15097 | // (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm, GPR32:{ *:[i32] }:$Rn) => (EORWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) |
| 15098 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EORWrs, |
| 15099 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15100 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 15101 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 15102 | GIR_EraseFromParent, /*InsnID*/0, |
| 15103 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15104 | // GIR_Coverage, 7572, |
| 15105 | GIR_Done, |
| 15106 | // Label 746: @37051 |
| 15107 | GIM_Try, /*On fail goto*//*Label 747*/ 37085, // Rule ID 161 // |
| 15108 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 15109 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 15110 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg32, |
| 15111 | // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) => (EORWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm) |
| 15112 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EORWrs, |
| 15113 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15114 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 15115 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 15116 | GIR_EraseFromParent, /*InsnID*/0, |
| 15117 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15118 | // GIR_Coverage, 161, |
| 15119 | GIR_Done, |
| 15120 | // Label 747: @37085 |
| 15121 | GIM_Try, /*On fail goto*//*Label 748*/ 37140, // Rule ID 7558 // |
| 15122 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 15123 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15124 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 15125 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 15126 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 15127 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 15128 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 15129 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 15130 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15131 | // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rm) => (EONWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 15132 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrr, |
| 15133 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15134 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 15135 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 15136 | GIR_EraseFromParent, /*InsnID*/0, |
| 15137 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15138 | // GIR_Coverage, 7558, |
| 15139 | GIR_Done, |
| 15140 | // Label 748: @37140 |
| 15141 | GIM_Try, /*On fail goto*//*Label 749*/ 37195, // Rule ID 155 // |
| 15142 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 15143 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15144 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 15145 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 15146 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 15147 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 15148 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 15149 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
| 15150 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15151 | // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm), -1:{ *:[i32] }) => (EONWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 15152 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrr, |
| 15153 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15154 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 15155 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 15156 | GIR_EraseFromParent, /*InsnID*/0, |
| 15157 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15158 | // GIR_Coverage, 155, |
| 15159 | GIR_Done, |
| 15160 | // Label 749: @37195 |
| 15161 | GIM_Try, /*On fail goto*//*Label 750*/ 37250, // Rule ID 7559 // |
| 15162 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 15163 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 15164 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15165 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 15166 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 15167 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 15168 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 15169 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 15170 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15171 | // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, -1:{ *:[i32] })) => (EONWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 15172 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONWrr, |
| 15173 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15174 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 15175 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm |
| 15176 | GIR_EraseFromParent, /*InsnID*/0, |
| 15177 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15178 | // GIR_Coverage, 7559, |
| 15179 | GIR_Done, |
| 15180 | // Label 750: @37250 |
| 15181 | GIM_Try, /*On fail goto*//*Label 751*/ 37284, // Rule ID 3532 // |
| 15182 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 15183 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 15184 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
| 15185 | // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Wm, -1:{ *:[i32] }) => (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Wm) |
| 15186 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrr, |
| 15187 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15188 | GIR_AddRegister, /*InsnID*/0, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 15189 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Wm |
| 15190 | GIR_EraseFromParent, /*InsnID*/0, |
| 15191 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15192 | // GIR_Coverage, 3532, |
| 15193 | GIR_Done, |
| 15194 | // Label 751: @37284 |
| 15195 | GIM_Try, /*On fail goto*//*Label 752*/ 37305, // Rule ID 159 // |
| 15196 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 15197 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 15198 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 15199 | // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (EORWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 15200 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORWrr, |
| 15201 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15202 | // GIR_Coverage, 159, |
| 15203 | GIR_Done, |
| 15204 | // Label 752: @37305 |
| 15205 | GIM_Reject, |
| 15206 | // Label 738: @37306 |
| 15207 | GIM_Reject, |
| 15208 | // Label 729: @37307 |
| 15209 | GIM_Try, /*On fail goto*//*Label 753*/ 38077, |
| 15210 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 15211 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 15212 | GIM_Try, /*On fail goto*//*Label 754*/ 37372, // Rule ID 7570 // |
| 15213 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 15214 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15215 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 15216 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 15217 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 15218 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 15219 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 15220 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15221 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, |
| 15222 | // (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, -1:{ *:[i64] })) => (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) |
| 15223 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrs, |
| 15224 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15225 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 15226 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 15227 | GIR_EraseFromParent, /*InsnID*/0, |
| 15228 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15229 | // GIR_Coverage, 7570, |
| 15230 | GIR_Done, |
| 15231 | // Label 754: @37372 |
| 15232 | GIM_Try, /*On fail goto*//*Label 755*/ 37427, // Rule ID 7569 // |
| 15233 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 15234 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15235 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 15236 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 15237 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 15238 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 15239 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 15240 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15241 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, |
| 15242 | // (xor:{ *:[i64] } (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn) => (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) |
| 15243 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrs, |
| 15244 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15245 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 15246 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 15247 | GIR_EraseFromParent, /*InsnID*/0, |
| 15248 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15249 | // GIR_Coverage, 7569, |
| 15250 | GIR_Done, |
| 15251 | // Label 755: @37427 |
| 15252 | GIM_Try, /*On fail goto*//*Label 756*/ 37482, // Rule ID 7567 // |
| 15253 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 15254 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15255 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 15256 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 15257 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 15258 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 15259 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
| 15260 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15261 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, |
| 15262 | // (xor:{ *:[i64] } (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm, GPR64:{ *:[i64] }:$Rn), -1:{ *:[i64] }) => (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) |
| 15263 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrs, |
| 15264 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15265 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 15266 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 15267 | GIR_EraseFromParent, /*InsnID*/0, |
| 15268 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15269 | // GIR_Coverage, 7567, |
| 15270 | GIR_Done, |
| 15271 | // Label 756: @37482 |
| 15272 | GIM_Try, /*On fail goto*//*Label 757*/ 37537, // Rule ID 158 // |
| 15273 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 15274 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15275 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 15276 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 15277 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 15278 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 15279 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
| 15280 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15281 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg64, |
| 15282 | // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm), -1:{ *:[i64] }) => (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) |
| 15283 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrs, |
| 15284 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15285 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 15286 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 15287 | GIR_EraseFromParent, /*InsnID*/0, |
| 15288 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15289 | // GIR_Coverage, 158, |
| 15290 | GIR_Done, |
| 15291 | // Label 757: @37537 |
| 15292 | GIM_Try, /*On fail goto*//*Label 758*/ 37592, // Rule ID 7568 // |
| 15293 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 15294 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15295 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 15296 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 15297 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 15298 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 15299 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 15300 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15301 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg64, |
| 15302 | // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, -1:{ *:[i64] }), logical_shifted_reg64:{ *:[i64] }:$Rm) => (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) |
| 15303 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrs, |
| 15304 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15305 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 15306 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 15307 | GIR_EraseFromParent, /*InsnID*/0, |
| 15308 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15309 | // GIR_Coverage, 7568, |
| 15310 | GIR_Done, |
| 15311 | // Label 758: @37592 |
| 15312 | GIM_Try, /*On fail goto*//*Label 759*/ 37647, // Rule ID 7571 // |
| 15313 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 15314 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 15315 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15316 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 15317 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 15318 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 15319 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 15320 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15321 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, |
| 15322 | // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm, -1:{ *:[i64] })) => (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) |
| 15323 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrs, |
| 15324 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15325 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 15326 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 15327 | GIR_EraseFromParent, /*InsnID*/0, |
| 15328 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15329 | // GIR_Coverage, 7571, |
| 15330 | GIR_Done, |
| 15331 | // Label 759: @37647 |
| 15332 | GIM_Try, /*On fail goto*//*Label 760*/ 37689, // Rule ID 136 // |
| 15333 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, |
| 15334 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 15335 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15336 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 15337 | GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_logical_imm64, |
| 15338 | // MIs[1] Operand 1 |
| 15339 | // No operand predicates |
| 15340 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15341 | // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_logical_imm64>><<X:logical_imm64_XFORM>>:$imm) => (EORXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (logical_imm64_XFORM:{ *:[i64] } (imm:{ *:[i64] }):$imm)) |
| 15342 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EORXri, |
| 15343 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15344 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 15345 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GICR_renderLogicalImm64, // imm |
| 15346 | GIR_EraseFromParent, /*InsnID*/0, |
| 15347 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15348 | // GIR_Coverage, 136, |
| 15349 | GIR_Done, |
| 15350 | // Label 760: @37689 |
| 15351 | GIM_Try, /*On fail goto*//*Label 761*/ 37723, // Rule ID 7573 // |
| 15352 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 15353 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 15354 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_logical_shifted_reg64, |
| 15355 | // (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm, GPR64:{ *:[i64] }:$Rn) => (EORXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) |
| 15356 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EORXrs, |
| 15357 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15358 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 15359 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 15360 | GIR_EraseFromParent, /*InsnID*/0, |
| 15361 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15362 | // GIR_Coverage, 7573, |
| 15363 | GIR_Done, |
| 15364 | // Label 761: @37723 |
| 15365 | GIM_Try, /*On fail goto*//*Label 762*/ 37757, // Rule ID 162 // |
| 15366 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 15367 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 15368 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_logical_shifted_reg64, |
| 15369 | // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) => (EORXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm) |
| 15370 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EORXrs, |
| 15371 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15372 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 15373 | GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, // Rm |
| 15374 | GIR_EraseFromParent, /*InsnID*/0, |
| 15375 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15376 | // GIR_Coverage, 162, |
| 15377 | GIR_Done, |
| 15378 | // Label 762: @37757 |
| 15379 | GIM_Try, /*On fail goto*//*Label 763*/ 37812, // Rule ID 7560 // |
| 15380 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 15381 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15382 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 15383 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 15384 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 15385 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 15386 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 15387 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 15388 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15389 | // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rm) => (EONXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) |
| 15390 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrr, |
| 15391 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15392 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 15393 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 15394 | GIR_EraseFromParent, /*InsnID*/0, |
| 15395 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15396 | // GIR_Coverage, 7560, |
| 15397 | GIR_Done, |
| 15398 | // Label 763: @37812 |
| 15399 | GIM_Try, /*On fail goto*//*Label 764*/ 37867, // Rule ID 156 // |
| 15400 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 15401 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15402 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 15403 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 15404 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 15405 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 15406 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 15407 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
| 15408 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15409 | // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm), -1:{ *:[i64] }) => (EONXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) |
| 15410 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrr, |
| 15411 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15412 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 15413 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 15414 | GIR_EraseFromParent, /*InsnID*/0, |
| 15415 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15416 | // GIR_Coverage, 156, |
| 15417 | GIR_Done, |
| 15418 | // Label 764: @37867 |
| 15419 | GIM_Try, /*On fail goto*//*Label 765*/ 37922, // Rule ID 7561 // |
| 15420 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 15421 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 15422 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15423 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 15424 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 15425 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 15426 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 15427 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 15428 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15429 | // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, -1:{ *:[i64] })) => (EONXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) |
| 15430 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EONXrr, |
| 15431 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15432 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 15433 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm |
| 15434 | GIR_EraseFromParent, /*InsnID*/0, |
| 15435 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15436 | // GIR_Coverage, 7561, |
| 15437 | GIR_Done, |
| 15438 | // Label 765: @37922 |
| 15439 | GIM_Try, /*On fail goto*//*Label 766*/ 37956, // Rule ID 3533 // |
| 15440 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 15441 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 15442 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
| 15443 | // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Xm, -1:{ *:[i64] }) => (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Xm) |
| 15444 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNXrr, |
| 15445 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15446 | GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0, |
| 15447 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Xm |
| 15448 | GIR_EraseFromParent, /*InsnID*/0, |
| 15449 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15450 | // GIR_Coverage, 3533, |
| 15451 | GIR_Done, |
| 15452 | // Label 766: @37956 |
| 15453 | GIM_Try, /*On fail goto*//*Label 767*/ 37994, // Rule ID 7959 // |
| 15454 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 15455 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15456 | GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 15457 | GIM_CheckIsBuildVectorAllOnes, /*MI*/1, |
| 15458 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 15459 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15460 | // (xor:{ *:[v1i64] } immAllOnesV:{ *:[v1i64] }, V64:{ *:[v1i64] }:$Rn) => (NOTv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn) |
| 15461 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NOTv8i8, |
| 15462 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15463 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 15464 | GIR_EraseFromParent, /*InsnID*/0, |
| 15465 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15466 | // GIR_Coverage, 7959, |
| 15467 | GIR_Done, |
| 15468 | // Label 767: @37994 |
| 15469 | GIM_Try, /*On fail goto*//*Label 768*/ 38032, // Rule ID 4002 // |
| 15470 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 15471 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 15472 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15473 | GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 15474 | GIM_CheckIsBuildVectorAllOnes, /*MI*/1, |
| 15475 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15476 | // (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, immAllOnesV:{ *:[v1i64] }) => (NOTv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn) |
| 15477 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NOTv8i8, |
| 15478 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15479 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 15480 | GIR_EraseFromParent, /*InsnID*/0, |
| 15481 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15482 | // GIR_Coverage, 4002, |
| 15483 | GIR_Done, |
| 15484 | // Label 768: @38032 |
| 15485 | GIM_Try, /*On fail goto*//*Label 769*/ 38053, // Rule ID 160 // |
| 15486 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 15487 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 15488 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 15489 | // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (EORXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) |
| 15490 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORXrr, |
| 15491 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15492 | // GIR_Coverage, 160, |
| 15493 | GIR_Done, |
| 15494 | // Label 769: @38053 |
| 15495 | GIM_Try, /*On fail goto*//*Label 770*/ 38076, // Rule ID 4075 // |
| 15496 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 15497 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 15498 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 15499 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 15500 | // (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) => (EORv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) |
| 15501 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv8i8, |
| 15502 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15503 | // GIR_Coverage, 4075, |
| 15504 | GIR_Done, |
| 15505 | // Label 770: @38076 |
| 15506 | GIM_Reject, |
| 15507 | // Label 753: @38077 |
| 15508 | GIM_Reject, |
| 15509 | // Label 730: @38078 |
| 15510 | GIM_Try, /*On fail goto*//*Label 771*/ 38180, |
| 15511 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 15512 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15513 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 15514 | GIM_Try, /*On fail goto*//*Label 772*/ 38126, // Rule ID 7957 // |
| 15515 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15516 | GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 15517 | GIM_CheckIsBuildVectorAllOnes, /*MI*/1, |
| 15518 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 15519 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15520 | // (xor:{ *:[v2i32] } immAllOnesV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$Rn) => (NOTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) |
| 15521 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NOTv8i8, |
| 15522 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15523 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 15524 | GIR_EraseFromParent, /*InsnID*/0, |
| 15525 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15526 | // GIR_Coverage, 7957, |
| 15527 | GIR_Done, |
| 15528 | // Label 772: @38126 |
| 15529 | GIM_Try, /*On fail goto*//*Label 773*/ 38160, // Rule ID 4000 // |
| 15530 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 15531 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15532 | GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 15533 | GIM_CheckIsBuildVectorAllOnes, /*MI*/1, |
| 15534 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15535 | // (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllOnesV:{ *:[v2i32] }) => (NOTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) |
| 15536 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NOTv8i8, |
| 15537 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15538 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 15539 | GIR_EraseFromParent, /*InsnID*/0, |
| 15540 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15541 | // GIR_Coverage, 4000, |
| 15542 | GIR_Done, |
| 15543 | // Label 773: @38160 |
| 15544 | GIM_Try, /*On fail goto*//*Label 774*/ 38179, // Rule ID 4074 // |
| 15545 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 15546 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 15547 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 15548 | // (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (EORv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) |
| 15549 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv8i8, |
| 15550 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15551 | // GIR_Coverage, 4074, |
| 15552 | GIR_Done, |
| 15553 | // Label 774: @38179 |
| 15554 | GIM_Reject, |
| 15555 | // Label 771: @38180 |
| 15556 | GIM_Reject, |
| 15557 | // Label 731: @38181 |
| 15558 | GIM_Try, /*On fail goto*//*Label 775*/ 38283, |
| 15559 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 15560 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 15561 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 15562 | GIM_Try, /*On fail goto*//*Label 776*/ 38229, // Rule ID 7960 // |
| 15563 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15564 | GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 15565 | GIM_CheckIsBuildVectorAllOnes, /*MI*/1, |
| 15566 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 15567 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15568 | // (xor:{ *:[v2i64] } immAllOnesV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$Rn) => (NOTv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn) |
| 15569 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NOTv16i8, |
| 15570 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15571 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 15572 | GIR_EraseFromParent, /*InsnID*/0, |
| 15573 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15574 | // GIR_Coverage, 7960, |
| 15575 | GIR_Done, |
| 15576 | // Label 776: @38229 |
| 15577 | GIM_Try, /*On fail goto*//*Label 777*/ 38263, // Rule ID 4003 // |
| 15578 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 15579 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15580 | GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 15581 | GIM_CheckIsBuildVectorAllOnes, /*MI*/1, |
| 15582 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15583 | // (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllOnesV:{ *:[v2i64] }) => (NOTv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn) |
| 15584 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NOTv16i8, |
| 15585 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15586 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 15587 | GIR_EraseFromParent, /*InsnID*/0, |
| 15588 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15589 | // GIR_Coverage, 4003, |
| 15590 | GIR_Done, |
| 15591 | // Label 777: @38263 |
| 15592 | GIM_Try, /*On fail goto*//*Label 778*/ 38282, // Rule ID 4078 // |
| 15593 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 15594 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 15595 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 15596 | // (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (EORv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) |
| 15597 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv16i8, |
| 15598 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15599 | // GIR_Coverage, 4078, |
| 15600 | GIR_Done, |
| 15601 | // Label 778: @38282 |
| 15602 | GIM_Reject, |
| 15603 | // Label 775: @38283 |
| 15604 | GIM_Reject, |
| 15605 | // Label 732: @38284 |
| 15606 | GIM_Try, /*On fail goto*//*Label 779*/ 38386, |
| 15607 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 15608 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15609 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 15610 | GIM_Try, /*On fail goto*//*Label 780*/ 38332, // Rule ID 7955 // |
| 15611 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15612 | GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 15613 | GIM_CheckIsBuildVectorAllOnes, /*MI*/1, |
| 15614 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 15615 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15616 | // (xor:{ *:[v4i16] } immAllOnesV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$Rn) => (NOTv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) |
| 15617 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NOTv8i8, |
| 15618 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15619 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 15620 | GIR_EraseFromParent, /*InsnID*/0, |
| 15621 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15622 | // GIR_Coverage, 7955, |
| 15623 | GIR_Done, |
| 15624 | // Label 780: @38332 |
| 15625 | GIM_Try, /*On fail goto*//*Label 781*/ 38366, // Rule ID 3998 // |
| 15626 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 15627 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15628 | GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 15629 | GIM_CheckIsBuildVectorAllOnes, /*MI*/1, |
| 15630 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15631 | // (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllOnesV:{ *:[v4i16] }) => (NOTv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) |
| 15632 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NOTv8i8, |
| 15633 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15634 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 15635 | GIR_EraseFromParent, /*InsnID*/0, |
| 15636 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15637 | // GIR_Coverage, 3998, |
| 15638 | GIR_Done, |
| 15639 | // Label 781: @38366 |
| 15640 | GIM_Try, /*On fail goto*//*Label 782*/ 38385, // Rule ID 4073 // |
| 15641 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 15642 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 15643 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 15644 | // (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (EORv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) |
| 15645 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv8i8, |
| 15646 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15647 | // GIR_Coverage, 4073, |
| 15648 | GIR_Done, |
| 15649 | // Label 782: @38385 |
| 15650 | GIM_Reject, |
| 15651 | // Label 779: @38386 |
| 15652 | GIM_Reject, |
| 15653 | // Label 733: @38387 |
| 15654 | GIM_Try, /*On fail goto*//*Label 783*/ 38489, |
| 15655 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 15656 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15657 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 15658 | GIM_Try, /*On fail goto*//*Label 784*/ 38435, // Rule ID 7958 // |
| 15659 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15660 | GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 15661 | GIM_CheckIsBuildVectorAllOnes, /*MI*/1, |
| 15662 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 15663 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15664 | // (xor:{ *:[v4i32] } immAllOnesV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$Rn) => (NOTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) |
| 15665 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NOTv16i8, |
| 15666 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15667 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 15668 | GIR_EraseFromParent, /*InsnID*/0, |
| 15669 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15670 | // GIR_Coverage, 7958, |
| 15671 | GIR_Done, |
| 15672 | // Label 784: @38435 |
| 15673 | GIM_Try, /*On fail goto*//*Label 785*/ 38469, // Rule ID 4001 // |
| 15674 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 15675 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15676 | GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 15677 | GIM_CheckIsBuildVectorAllOnes, /*MI*/1, |
| 15678 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15679 | // (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllOnesV:{ *:[v4i32] }) => (NOTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) |
| 15680 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NOTv16i8, |
| 15681 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15682 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 15683 | GIR_EraseFromParent, /*InsnID*/0, |
| 15684 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15685 | // GIR_Coverage, 4001, |
| 15686 | GIR_Done, |
| 15687 | // Label 785: @38469 |
| 15688 | GIM_Try, /*On fail goto*//*Label 786*/ 38488, // Rule ID 4077 // |
| 15689 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 15690 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 15691 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 15692 | // (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (EORv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) |
| 15693 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv16i8, |
| 15694 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15695 | // GIR_Coverage, 4077, |
| 15696 | GIR_Done, |
| 15697 | // Label 786: @38488 |
| 15698 | GIM_Reject, |
| 15699 | // Label 783: @38489 |
| 15700 | GIM_Reject, |
| 15701 | // Label 734: @38490 |
| 15702 | GIM_Try, /*On fail goto*//*Label 787*/ 38596, |
| 15703 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 15704 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 15705 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 15706 | GIM_Try, /*On fail goto*//*Label 788*/ 38540, // Rule ID 7607 // |
| 15707 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 15708 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15709 | GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 15710 | GIM_CheckIsBuildVectorAllOnes, /*MI*/1, |
| 15711 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 15712 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15713 | // (xor:{ *:[v8i8] } immAllOnesV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rn) => (NOTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) |
| 15714 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NOTv8i8, |
| 15715 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15716 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 15717 | GIR_EraseFromParent, /*InsnID*/0, |
| 15718 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15719 | // GIR_Coverage, 7607, |
| 15720 | GIR_Done, |
| 15721 | // Label 788: @38540 |
| 15722 | GIM_Try, /*On fail goto*//*Label 789*/ 38576, // Rule ID 796 // |
| 15723 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 15724 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 15725 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15726 | GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 15727 | GIM_CheckIsBuildVectorAllOnes, /*MI*/1, |
| 15728 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15729 | // (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllOnesV:{ *:[v8i8] }) => (NOTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) |
| 15730 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NOTv8i8, |
| 15731 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15732 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 15733 | GIR_EraseFromParent, /*InsnID*/0, |
| 15734 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15735 | // GIR_Coverage, 796, |
| 15736 | GIR_Done, |
| 15737 | // Label 789: @38576 |
| 15738 | GIM_Try, /*On fail goto*//*Label 790*/ 38595, // Rule ID 1317 // |
| 15739 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 15740 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 15741 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 15742 | // (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (EORv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 15743 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv8i8, |
| 15744 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15745 | // GIR_Coverage, 1317, |
| 15746 | GIR_Done, |
| 15747 | // Label 790: @38595 |
| 15748 | GIM_Reject, |
| 15749 | // Label 787: @38596 |
| 15750 | GIM_Reject, |
| 15751 | // Label 735: @38597 |
| 15752 | GIM_Try, /*On fail goto*//*Label 791*/ 39199, |
| 15753 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 15754 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15755 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 15756 | GIM_Try, /*On fail goto*//*Label 792*/ 38736, // Rule ID 7950 // |
| 15757 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15758 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, |
| 15759 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 15760 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15761 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 15762 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SUB, |
| 15763 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 15764 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15765 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 15766 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT, |
| 15767 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s8, |
| 15768 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 15769 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 15770 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_ZEXT, |
| 15771 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8, |
| 15772 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 15773 | GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5] |
| 15774 | GIM_CheckOpcode, /*MI*/5, AArch64::G_VASHR, |
| 15775 | GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v8s16, |
| 15776 | // MIs[5] Operand 2 |
| 15777 | GIM_CheckLiteralInt, /*MI*/5, /*Op*/2, 15, |
| 15778 | GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6] |
| 15779 | GIM_CheckOpcode, /*MI*/6, AArch64::G_VASHR, |
| 15780 | // MIs[6] src |
| 15781 | GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/5, /*OtherOpIdx*/1, |
| 15782 | // MIs[6] Operand 2 |
| 15783 | GIM_CheckLiteralInt, /*MI*/6, /*Op*/2, 15, |
| 15784 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15785 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 15786 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 15787 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 15788 | GIM_CheckIsSafeToFold, /*InsnID*/5, |
| 15789 | GIM_CheckIsSafeToFold, /*InsnID*/6, |
| 15790 | // (xor:{ *:[v8i16] } (add:{ *:[v8i16] } (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$opA), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$opB)), (AArch64vashr:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, 15:{ *:[i32] })), (AArch64vashr:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, 15:{ *:[i32] })) => (UABDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$opA, V64:{ *:[v8i8] }:$opB) |
| 15791 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv8i8_v8i16, |
| 15792 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15793 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // opA |
| 15794 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // opB |
| 15795 | GIR_EraseFromParent, /*InsnID*/0, |
| 15796 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15797 | // GIR_Coverage, 7950, |
| 15798 | GIR_Done, |
| 15799 | // Label 792: @38736 |
| 15800 | GIM_Try, /*On fail goto*//*Label 793*/ 38861, // Rule ID 7951 // |
| 15801 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15802 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, |
| 15803 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 15804 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15805 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 15806 | GIM_CheckOpcode, /*MI*/2, AArch64::G_VASHR, |
| 15807 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 15808 | // MIs[2] Operand 2 |
| 15809 | GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, 15, |
| 15810 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 15811 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SUB, |
| 15812 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16, |
| 15813 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15814 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 15815 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_ZEXT, |
| 15816 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8, |
| 15817 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 15818 | GIM_RecordInsn, /*DefineMI*/5, /*MI*/3, /*OpIdx*/2, // MIs[5] |
| 15819 | GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_ZEXT, |
| 15820 | GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v8s8, |
| 15821 | GIM_CheckRegBankForClass, /*MI*/5, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 15822 | GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6] |
| 15823 | GIM_CheckOpcode, /*MI*/6, AArch64::G_VASHR, |
| 15824 | // MIs[6] src |
| 15825 | GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 15826 | // MIs[6] Operand 2 |
| 15827 | GIM_CheckLiteralInt, /*MI*/6, /*Op*/2, 15, |
| 15828 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15829 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 15830 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 15831 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 15832 | GIM_CheckIsSafeToFold, /*InsnID*/5, |
| 15833 | GIM_CheckIsSafeToFold, /*InsnID*/6, |
| 15834 | // (xor:{ *:[v8i16] } (add:{ *:[v8i16] } (AArch64vashr:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, 15:{ *:[i32] }), (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$opA), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$opB))), (AArch64vashr:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, 15:{ *:[i32] })) => (UABDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$opA, V64:{ *:[v8i8] }:$opB) |
| 15835 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv8i8_v8i16, |
| 15836 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15837 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // opA |
| 15838 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // opB |
| 15839 | GIR_EraseFromParent, /*InsnID*/0, |
| 15840 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15841 | // GIR_Coverage, 7951, |
| 15842 | GIR_Done, |
| 15843 | // Label 793: @38861 |
| 15844 | GIM_Try, /*On fail goto*//*Label 794*/ 38986, // Rule ID 3965 // |
| 15845 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15846 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, |
| 15847 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 15848 | // MIs[1] Operand 2 |
| 15849 | GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, 15, |
| 15850 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 15851 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, |
| 15852 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 15853 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15854 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 15855 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SUB, |
| 15856 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16, |
| 15857 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15858 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 15859 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_ZEXT, |
| 15860 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8, |
| 15861 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 15862 | GIM_RecordInsn, /*DefineMI*/5, /*MI*/3, /*OpIdx*/2, // MIs[5] |
| 15863 | GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_ZEXT, |
| 15864 | GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v8s8, |
| 15865 | GIM_CheckRegBankForClass, /*MI*/5, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 15866 | GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/2, // MIs[6] |
| 15867 | GIM_CheckOpcode, /*MI*/6, AArch64::G_VASHR, |
| 15868 | // MIs[6] src |
| 15869 | GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 15870 | // MIs[6] Operand 2 |
| 15871 | GIM_CheckLiteralInt, /*MI*/6, /*Op*/2, 15, |
| 15872 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15873 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 15874 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 15875 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 15876 | GIM_CheckIsSafeToFold, /*InsnID*/5, |
| 15877 | GIM_CheckIsSafeToFold, /*InsnID*/6, |
| 15878 | // (xor:{ *:[v8i16] } (AArch64vashr:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, 15:{ *:[i32] }), (add:{ *:[v8i16] } (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$opA), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$opB)), (AArch64vashr:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, 15:{ *:[i32] }))) => (UABDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$opA, V64:{ *:[v8i8] }:$opB) |
| 15879 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv8i8_v8i16, |
| 15880 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15881 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // opA |
| 15882 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // opB |
| 15883 | GIR_EraseFromParent, /*InsnID*/0, |
| 15884 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15885 | // GIR_Coverage, 3965, |
| 15886 | GIR_Done, |
| 15887 | // Label 794: @38986 |
| 15888 | GIM_Try, /*On fail goto*//*Label 795*/ 39111, // Rule ID 7949 // |
| 15889 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15890 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, |
| 15891 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 15892 | // MIs[1] Operand 2 |
| 15893 | GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, 15, |
| 15894 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 15895 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, |
| 15896 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 15897 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15898 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 15899 | GIM_CheckOpcode, /*MI*/3, AArch64::G_VASHR, |
| 15900 | // MIs[3] src |
| 15901 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 15902 | // MIs[3] Operand 2 |
| 15903 | GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, 15, |
| 15904 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 15905 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_SUB, |
| 15906 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16, |
| 15907 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15908 | GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5] |
| 15909 | GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_ZEXT, |
| 15910 | GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_v8s8, |
| 15911 | GIM_CheckRegBankForClass, /*MI*/5, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 15912 | GIM_RecordInsn, /*DefineMI*/6, /*MI*/4, /*OpIdx*/2, // MIs[6] |
| 15913 | GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_ZEXT, |
| 15914 | GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_v8s8, |
| 15915 | GIM_CheckRegBankForClass, /*MI*/6, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 15916 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15917 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 15918 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 15919 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 15920 | GIM_CheckIsSafeToFold, /*InsnID*/5, |
| 15921 | GIM_CheckIsSafeToFold, /*InsnID*/6, |
| 15922 | // (xor:{ *:[v8i16] } (AArch64vashr:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, 15:{ *:[i32] }), (add:{ *:[v8i16] } (AArch64vashr:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, 15:{ *:[i32] }), (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$opA), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$opB)))) => (UABDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$opA, V64:{ *:[v8i8] }:$opB) |
| 15923 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv8i8_v8i16, |
| 15924 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15925 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // opA |
| 15926 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // opB |
| 15927 | GIR_EraseFromParent, /*InsnID*/0, |
| 15928 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15929 | // GIR_Coverage, 7949, |
| 15930 | GIR_Done, |
| 15931 | // Label 795: @39111 |
| 15932 | GIM_Try, /*On fail goto*//*Label 796*/ 39145, // Rule ID 7956 // |
| 15933 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15934 | GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 15935 | GIM_CheckIsBuildVectorAllOnes, /*MI*/1, |
| 15936 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 15937 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15938 | // (xor:{ *:[v8i16] } immAllOnesV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$Rn) => (NOTv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) |
| 15939 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NOTv16i8, |
| 15940 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15941 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 15942 | GIR_EraseFromParent, /*InsnID*/0, |
| 15943 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15944 | // GIR_Coverage, 7956, |
| 15945 | GIR_Done, |
| 15946 | // Label 796: @39145 |
| 15947 | GIM_Try, /*On fail goto*//*Label 797*/ 39179, // Rule ID 3999 // |
| 15948 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 15949 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15950 | GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 15951 | GIM_CheckIsBuildVectorAllOnes, /*MI*/1, |
| 15952 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15953 | // (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllOnesV:{ *:[v8i16] }) => (NOTv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) |
| 15954 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NOTv16i8, |
| 15955 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15956 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 15957 | GIR_EraseFromParent, /*InsnID*/0, |
| 15958 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15959 | // GIR_Coverage, 3999, |
| 15960 | GIR_Done, |
| 15961 | // Label 797: @39179 |
| 15962 | GIM_Try, /*On fail goto*//*Label 798*/ 39198, // Rule ID 4076 // |
| 15963 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 15964 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 15965 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 15966 | // (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (EORv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) |
| 15967 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv16i8, |
| 15968 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15969 | // GIR_Coverage, 4076, |
| 15970 | GIR_Done, |
| 15971 | // Label 798: @39198 |
| 15972 | GIM_Reject, |
| 15973 | // Label 791: @39199 |
| 15974 | GIM_Reject, |
| 15975 | // Label 736: @39200 |
| 15976 | GIM_Try, /*On fail goto*//*Label 799*/ 39306, |
| 15977 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 15978 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 15979 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 15980 | GIM_Try, /*On fail goto*//*Label 800*/ 39250, // Rule ID 7608 // |
| 15981 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 15982 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15983 | GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 15984 | GIM_CheckIsBuildVectorAllOnes, /*MI*/1, |
| 15985 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 15986 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15987 | // (xor:{ *:[v16i8] } immAllOnesV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rn) => (NOTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) |
| 15988 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NOTv16i8, |
| 15989 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 15990 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 15991 | GIR_EraseFromParent, /*InsnID*/0, |
| 15992 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15993 | // GIR_Coverage, 7608, |
| 15994 | GIR_Done, |
| 15995 | // Label 800: @39250 |
| 15996 | GIM_Try, /*On fail goto*//*Label 801*/ 39286, // Rule ID 797 // |
| 15997 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 15998 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 15999 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16000 | GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, |
| 16001 | GIM_CheckIsBuildVectorAllOnes, /*MI*/1, |
| 16002 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 16003 | // (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllOnesV:{ *:[v16i8] }) => (NOTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) |
| 16004 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::NOTv16i8, |
| 16005 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 16006 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 16007 | GIR_EraseFromParent, /*InsnID*/0, |
| 16008 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16009 | // GIR_Coverage, 797, |
| 16010 | GIR_Done, |
| 16011 | // Label 801: @39286 |
| 16012 | GIM_Try, /*On fail goto*//*Label 802*/ 39305, // Rule ID 1318 // |
| 16013 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 16014 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 16015 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 16016 | // (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (EORv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 16017 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::EORv16i8, |
| 16018 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16019 | // GIR_Coverage, 1318, |
| 16020 | GIR_Done, |
| 16021 | // Label 802: @39305 |
| 16022 | GIM_Reject, |
| 16023 | // Label 799: @39306 |
| 16024 | GIM_Reject, |
| 16025 | // Label 737: @39307 |
| 16026 | GIM_Reject, |
| 16027 | // Label 8: @39308 |
| 16028 | GIM_Try, /*On fail goto*//*Label 803*/ 47025, |
| 16029 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 16030 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 11, /*)*//*default:*//*Label 808*/ 47024, |
| 16031 | /*GILLT_v2s64*//*Label 804*/ 39325, 0, |
| 16032 | /*GILLT_v4s32*//*Label 805*/ 39701, 0, |
| 16033 | /*GILLT_v8s16*//*Label 806*/ 42267, |
| 16034 | /*GILLT_v16s8*//*Label 807*/ 44813, |
| 16035 | // Label 804: @39325 |
| 16036 | GIM_Try, /*On fail goto*//*Label 809*/ 39700, |
| 16037 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 16038 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 16039 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 16040 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 16041 | GIM_Try, /*On fail goto*//*Label 810*/ 39399, // Rule ID 4469 // |
| 16042 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16043 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_IMPLICIT_DEF, |
| 16044 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 16045 | // (concat_vectors:{ *:[v2i64] } V64:{ *:[v1i64] }:$Rn, (undef:{ *:[v1i64] })) => (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }) |
| 16046 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64, |
| 16047 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16048 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16049 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16050 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16051 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16052 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16053 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 16054 | GIR_AddImm, /*InsnID*/0, /*Imm*/2, |
| 16055 | GIR_EraseFromParent, /*InsnID*/0, |
| 16056 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 16057 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, |
| 16058 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::FPR64RegClassID, |
| 16059 | // GIR_Coverage, 4469, |
| 16060 | GIR_Done, |
| 16061 | // Label 810: @39399 |
| 16062 | GIM_Try, /*On fail goto*//*Label 811*/ 39455, // Rule ID 4470 // |
| 16063 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16064 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_IMPLICIT_DEF, |
| 16065 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 16066 | // (concat_vectors:{ *:[v2f64] } V64:{ *:[v1f64] }:$Rn, (undef:{ *:[v1f64] })) => (INSERT_SUBREG:{ *:[v2f64] } (IMPLICIT_DEF:{ *:[v2f64] }), V64:{ *:[v1f64] }:$Rn, dsub:{ *:[i32] }) |
| 16067 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64, |
| 16068 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16069 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16070 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16071 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16072 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16073 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16074 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 16075 | GIR_AddImm, /*InsnID*/0, /*Imm*/2, |
| 16076 | GIR_EraseFromParent, /*InsnID*/0, |
| 16077 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 16078 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, |
| 16079 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::FPR64RegClassID, |
| 16080 | // GIR_Coverage, 4470, |
| 16081 | GIR_Done, |
| 16082 | // Label 811: @39455 |
| 16083 | GIM_Try, /*On fail goto*//*Label 812*/ 39577, // Rule ID 4461 // |
| 16084 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 16085 | // (concat_vectors:{ *:[v2i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v1i64] }:$Rn) => (INSvi64lane:{ *:[v2i64] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1i64] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 16086 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 16087 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 16088 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128, |
| 16089 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, |
| 16090 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16091 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 16092 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 16093 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16094 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 16095 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, |
| 16096 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 16097 | GIR_AddImm, /*InsnID*/3, /*Imm*/2, |
| 16098 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR128RegClassID, |
| 16099 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, |
| 16100 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR64RegClassID, |
| 16101 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16102 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16103 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16104 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16105 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16106 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 16107 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 16108 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 16109 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 16110 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 16111 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 16112 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, |
| 16113 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16114 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16115 | GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 16116 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, |
| 16117 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 16118 | GIR_EraseFromParent, /*InsnID*/0, |
| 16119 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16120 | // GIR_Coverage, 4461, |
| 16121 | GIR_Done, |
| 16122 | // Label 812: @39577 |
| 16123 | GIM_Try, /*On fail goto*//*Label 813*/ 39699, // Rule ID 4462 // |
| 16124 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 16125 | // (concat_vectors:{ *:[v2f64] } V64:{ *:[v1f64] }:$Rd, V64:{ *:[v1f64] }:$Rn) => (INSvi64lane:{ *:[v2f64] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1f64] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1f64] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 16126 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 16127 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 16128 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128, |
| 16129 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, |
| 16130 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16131 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 16132 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 16133 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16134 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 16135 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, |
| 16136 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 16137 | GIR_AddImm, /*InsnID*/3, /*Imm*/2, |
| 16138 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR128RegClassID, |
| 16139 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, |
| 16140 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR64RegClassID, |
| 16141 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16142 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16143 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16144 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16145 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16146 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 16147 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 16148 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 16149 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 16150 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 16151 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 16152 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, |
| 16153 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16154 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16155 | GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 16156 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, |
| 16157 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 16158 | GIR_EraseFromParent, /*InsnID*/0, |
| 16159 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16160 | // GIR_Coverage, 4462, |
| 16161 | GIR_Done, |
| 16162 | // Label 813: @39699 |
| 16163 | GIM_Reject, |
| 16164 | // Label 809: @39700 |
| 16165 | GIM_Reject, |
| 16166 | // Label 805: @39701 |
| 16167 | GIM_Try, /*On fail goto*//*Label 814*/ 42266, |
| 16168 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 16169 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 16170 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 16171 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 16172 | GIM_Try, /*On fail goto*//*Label 815*/ 39828, // Rule ID 4261 // |
| 16173 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16174 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, |
| 16175 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 16176 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 16177 | GIM_CheckOpcode, /*MI*/2, AArch64::G_VLSHR, |
| 16178 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 16179 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 16180 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ADD, |
| 16181 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64, |
| 16182 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64, |
| 16183 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 16184 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 16185 | // MIs[2] Operand 2 |
| 16186 | GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, 32, |
| 16187 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 16188 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 16189 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 16190 | // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm), 32:{ *:[i32] }))) => (ADDHNv2i64_v4i32:{ *:[v4i32] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 16191 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 16192 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 16193 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16194 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 16195 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 16196 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 16197 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 16198 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 16199 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv2i64_v4i32, |
| 16200 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16201 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16202 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 16203 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm |
| 16204 | GIR_EraseFromParent, /*InsnID*/0, |
| 16205 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16206 | // GIR_Coverage, 4261, |
| 16207 | GIR_Done, |
| 16208 | // Label 815: @39828 |
| 16209 | GIM_Try, /*On fail goto*//*Label 816*/ 39937, // Rule ID 4267 // |
| 16210 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16211 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, |
| 16212 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 16213 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 16214 | GIM_CheckOpcode, /*MI*/2, AArch64::G_VLSHR, |
| 16215 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 16216 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 16217 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SUB, |
| 16218 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64, |
| 16219 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64, |
| 16220 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 16221 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 16222 | // MIs[2] Operand 2 |
| 16223 | GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, 32, |
| 16224 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 16225 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 16226 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 16227 | // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm), 32:{ *:[i32] }))) => (SUBHNv2i64_v4i32:{ *:[v4i32] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 16228 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 16229 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 16230 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16231 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 16232 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 16233 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 16234 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 16235 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 16236 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv2i64_v4i32, |
| 16237 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16238 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16239 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 16240 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm |
| 16241 | GIR_EraseFromParent, /*InsnID*/0, |
| 16242 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16243 | // GIR_Coverage, 4267, |
| 16244 | GIR_Done, |
| 16245 | // Label 816: @39937 |
| 16246 | GIM_Try, /*On fail goto*//*Label 817*/ 40049, // Rule ID 2739 // |
| 16247 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 16248 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16249 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 16250 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 16251 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_rshrn, |
| 16252 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 16253 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 16254 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 16255 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 16256 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 16257 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, |
| 16258 | // MIs[2] Operand 1 |
| 16259 | // No operand predicates |
| 16260 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 16261 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 16262 | // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 424:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)) => (RSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) |
| 16263 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 16264 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 16265 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16266 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16267 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16268 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16269 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16270 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 16271 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 16272 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 16273 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 16274 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 16275 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 16276 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv4i32_shift, |
| 16277 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16278 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16279 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16280 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 16281 | GIR_EraseFromParent, /*InsnID*/0, |
| 16282 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16283 | // GIR_Coverage, 2739, |
| 16284 | GIR_Done, |
| 16285 | // Label 817: @40049 |
| 16286 | GIM_Try, /*On fail goto*//*Label 818*/ 40161, // Rule ID 4743 // |
| 16287 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 16288 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16289 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 16290 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 16291 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn, |
| 16292 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 16293 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 16294 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 16295 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 16296 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 16297 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, |
| 16298 | // MIs[2] Operand 1 |
| 16299 | // No operand predicates |
| 16300 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 16301 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 16302 | // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 457:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)) => (SQRSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) |
| 16303 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 16304 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 16305 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16306 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16307 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16308 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16309 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16310 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 16311 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 16312 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 16313 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 16314 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 16315 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 16316 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv4i32_shift, |
| 16317 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16318 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16319 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16320 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 16321 | GIR_EraseFromParent, /*InsnID*/0, |
| 16322 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16323 | // GIR_Coverage, 4743, |
| 16324 | GIR_Done, |
| 16325 | // Label 818: @40161 |
| 16326 | GIM_Try, /*On fail goto*//*Label 819*/ 40273, // Rule ID 4746 // |
| 16327 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 16328 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16329 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 16330 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 16331 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun, |
| 16332 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 16333 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 16334 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 16335 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 16336 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 16337 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, |
| 16338 | // MIs[2] Operand 1 |
| 16339 | // No operand predicates |
| 16340 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 16341 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 16342 | // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 458:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)) => (SQRSHRUNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) |
| 16343 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 16344 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 16345 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16346 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16347 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16348 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16349 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16350 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 16351 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 16352 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 16353 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 16354 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 16355 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 16356 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv4i32_shift, |
| 16357 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16358 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16359 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16360 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 16361 | GIR_EraseFromParent, /*InsnID*/0, |
| 16362 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16363 | // GIR_Coverage, 4746, |
| 16364 | GIR_Done, |
| 16365 | // Label 819: @40273 |
| 16366 | GIM_Try, /*On fail goto*//*Label 820*/ 40385, // Rule ID 4749 // |
| 16367 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 16368 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16369 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 16370 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 16371 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqshrn, |
| 16372 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 16373 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 16374 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 16375 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 16376 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 16377 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, |
| 16378 | // MIs[2] Operand 1 |
| 16379 | // No operand predicates |
| 16380 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 16381 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 16382 | // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 461:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)) => (SQSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) |
| 16383 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 16384 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 16385 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16386 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16387 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16388 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16389 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16390 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 16391 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 16392 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 16393 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 16394 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 16395 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 16396 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv4i32_shift, |
| 16397 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16398 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16399 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16400 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 16401 | GIR_EraseFromParent, /*InsnID*/0, |
| 16402 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16403 | // GIR_Coverage, 4749, |
| 16404 | GIR_Done, |
| 16405 | // Label 820: @40385 |
| 16406 | GIM_Try, /*On fail goto*//*Label 821*/ 40497, // Rule ID 4752 // |
| 16407 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 16408 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16409 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 16410 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 16411 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqshrun, |
| 16412 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 16413 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 16414 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 16415 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 16416 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 16417 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, |
| 16418 | // MIs[2] Operand 1 |
| 16419 | // No operand predicates |
| 16420 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 16421 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 16422 | // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 462:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)) => (SQSHRUNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) |
| 16423 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 16424 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 16425 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16426 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16427 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16428 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16429 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16430 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 16431 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 16432 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 16433 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 16434 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 16435 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 16436 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv4i32_shift, |
| 16437 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16438 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16439 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16440 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 16441 | GIR_EraseFromParent, /*InsnID*/0, |
| 16442 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16443 | // GIR_Coverage, 4752, |
| 16444 | GIR_Done, |
| 16445 | // Label 821: @40497 |
| 16446 | GIM_Try, /*On fail goto*//*Label 822*/ 40609, // Rule ID 4756 // |
| 16447 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 16448 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16449 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 16450 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 16451 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn, |
| 16452 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 16453 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 16454 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 16455 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 16456 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 16457 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, |
| 16458 | // MIs[2] Operand 1 |
| 16459 | // No operand predicates |
| 16460 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 16461 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 16462 | // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 506:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)) => (UQRSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) |
| 16463 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 16464 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 16465 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16466 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16467 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16468 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16469 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16470 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 16471 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 16472 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 16473 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 16474 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 16475 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 16476 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv4i32_shift, |
| 16477 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16478 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16479 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16480 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 16481 | GIR_EraseFromParent, /*InsnID*/0, |
| 16482 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16483 | // GIR_Coverage, 4756, |
| 16484 | GIR_Done, |
| 16485 | // Label 822: @40609 |
| 16486 | GIM_Try, /*On fail goto*//*Label 823*/ 40721, // Rule ID 4759 // |
| 16487 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 16488 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16489 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 16490 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 16491 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqshrn, |
| 16492 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 16493 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 16494 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 16495 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 16496 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 16497 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, |
| 16498 | // MIs[2] Operand 1 |
| 16499 | // No operand predicates |
| 16500 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 16501 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 16502 | // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 508:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)) => (UQSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) |
| 16503 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 16504 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 16505 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16506 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16507 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16508 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16509 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16510 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 16511 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 16512 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 16513 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 16514 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 16515 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 16516 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv4i32_shift, |
| 16517 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16518 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16519 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16520 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 16521 | GIR_EraseFromParent, /*InsnID*/0, |
| 16522 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16523 | // GIR_Coverage, 4759, |
| 16524 | GIR_Done, |
| 16525 | // Label 823: @40721 |
| 16526 | GIM_Try, /*On fail goto*//*Label 824*/ 40835, // Rule ID 4739 // |
| 16527 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 16528 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16529 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, |
| 16530 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 16531 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 16532 | GIM_CheckOpcode, /*MI*/2, AArch64::G_VASHR, |
| 16533 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 16534 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 16535 | // MIs[2] imm |
| 16536 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 16537 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 16538 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, |
| 16539 | // MIs[3] Operand 1 |
| 16540 | // No operand predicates |
| 16541 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 16542 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 16543 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 16544 | // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm))) => (SHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) |
| 16545 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 16546 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 16547 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16548 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16549 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16550 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16551 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16552 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 16553 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 16554 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 16555 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 16556 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 16557 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 16558 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHRNv4i32_shift, |
| 16559 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16560 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16561 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 16562 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // imm |
| 16563 | GIR_EraseFromParent, /*InsnID*/0, |
| 16564 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16565 | // GIR_Coverage, 4739, |
| 16566 | GIR_Done, |
| 16567 | // Label 824: @40835 |
| 16568 | GIM_Try, /*On fail goto*//*Label 825*/ 40947, // Rule ID 4765 // |
| 16569 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16570 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, |
| 16571 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 16572 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 16573 | GIM_CheckOpcode, /*MI*/2, AArch64::G_VLSHR, |
| 16574 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 16575 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 16576 | // MIs[2] imm |
| 16577 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 16578 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 16579 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, |
| 16580 | // MIs[3] Operand 1 |
| 16581 | // No operand predicates |
| 16582 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 16583 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 16584 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 16585 | // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm))) => (SHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) |
| 16586 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 16587 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 16588 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16589 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16590 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16591 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16592 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16593 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 16594 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 16595 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 16596 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 16597 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 16598 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 16599 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHRNv4i32_shift, |
| 16600 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16601 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16602 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 16603 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // imm |
| 16604 | GIR_EraseFromParent, /*InsnID*/0, |
| 16605 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16606 | // GIR_Coverage, 4765, |
| 16607 | GIR_Done, |
| 16608 | // Label 825: @40947 |
| 16609 | GIM_Try, /*On fail goto*//*Label 826*/ 41052, // Rule ID 2696 // |
| 16610 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 16611 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16612 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 16613 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 16614 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_addhn, |
| 16615 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 16616 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64, |
| 16617 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 16618 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 16619 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 16620 | // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 358:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)) => (ADDHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 16621 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 16622 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 16623 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16624 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16625 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16626 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16627 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16628 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 16629 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 16630 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 16631 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 16632 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 16633 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 16634 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv2i64_v4i32, |
| 16635 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16636 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16637 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16638 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 16639 | GIR_EraseFromParent, /*InsnID*/0, |
| 16640 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16641 | // GIR_Coverage, 2696, |
| 16642 | GIR_Done, |
| 16643 | // Label 826: @41052 |
| 16644 | GIM_Try, /*On fail goto*//*Label 827*/ 41157, // Rule ID 4211 // |
| 16645 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 16646 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16647 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 16648 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 16649 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_subhn, |
| 16650 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 16651 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64, |
| 16652 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 16653 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 16654 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 16655 | // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 479:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)) => (SUBHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 16656 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 16657 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 16658 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16659 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16660 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16661 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16662 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16663 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 16664 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 16665 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 16666 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 16667 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 16668 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 16669 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv2i64_v4i32, |
| 16670 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16671 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16672 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16673 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 16674 | GIR_EraseFromParent, /*InsnID*/0, |
| 16675 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16676 | // GIR_Coverage, 4211, |
| 16677 | GIR_Done, |
| 16678 | // Label 827: @41157 |
| 16679 | GIM_Try, /*On fail goto*//*Label 828*/ 41262, // Rule ID 4214 // |
| 16680 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 16681 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16682 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 16683 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 16684 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_raddhn, |
| 16685 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 16686 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64, |
| 16687 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 16688 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 16689 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 16690 | // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 422:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)) => (RADDHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 16691 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 16692 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 16693 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16694 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16695 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16696 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16697 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16698 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 16699 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 16700 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 16701 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 16702 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 16703 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 16704 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv2i64_v4i32, |
| 16705 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16706 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16707 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16708 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 16709 | GIR_EraseFromParent, /*InsnID*/0, |
| 16710 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16711 | // GIR_Coverage, 4214, |
| 16712 | GIR_Done, |
| 16713 | // Label 828: @41262 |
| 16714 | GIM_Try, /*On fail goto*//*Label 829*/ 41367, // Rule ID 4217 // |
| 16715 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 16716 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16717 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 16718 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 16719 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_rsubhn, |
| 16720 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 16721 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64, |
| 16722 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 16723 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 16724 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 16725 | // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 425:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)) => (RSUBHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 16726 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 16727 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 16728 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16729 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16730 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16731 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16732 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16733 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 16734 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 16735 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 16736 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 16737 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 16738 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 16739 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv2i64_v4i32, |
| 16740 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16741 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16742 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16743 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 16744 | GIR_EraseFromParent, /*InsnID*/0, |
| 16745 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16746 | // GIR_Coverage, 4217, |
| 16747 | GIR_Done, |
| 16748 | // Label 829: @41367 |
| 16749 | GIM_Try, /*On fail goto*//*Label 830*/ 41460, // Rule ID 2692 // |
| 16750 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 16751 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16752 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 16753 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 16754 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqxtn, |
| 16755 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 16756 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 16757 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 16758 | // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 464:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn)) => (SQXTNv4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn) |
| 16759 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 16760 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 16761 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16762 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16763 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16764 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16765 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16766 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 16767 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 16768 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 16769 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 16770 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 16771 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 16772 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv4i32, |
| 16773 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16774 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16775 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16776 | GIR_EraseFromParent, /*InsnID*/0, |
| 16777 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16778 | // GIR_Coverage, 2692, |
| 16779 | GIR_Done, |
| 16780 | // Label 830: @41460 |
| 16781 | GIM_Try, /*On fail goto*//*Label 831*/ 41553, // Rule ID 2693 // |
| 16782 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 16783 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16784 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 16785 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 16786 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_fcvtxn, |
| 16787 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 16788 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 16789 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 16790 | // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rd, (intrinsic_wo_chain:{ *:[v2f32] } 381:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)) => (FCVTXNv4f32:{ *:[v4f32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2f32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rn) |
| 16791 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 16792 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 16793 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16794 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16795 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16796 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16797 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16798 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 16799 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 16800 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 16801 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 16802 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 16803 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 16804 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTXNv4f32, |
| 16805 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16806 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16807 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16808 | GIR_EraseFromParent, /*InsnID*/0, |
| 16809 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16810 | // GIR_Coverage, 2693, |
| 16811 | GIR_Done, |
| 16812 | // Label 831: @41553 |
| 16813 | GIM_Try, /*On fail goto*//*Label 832*/ 41646, // Rule ID 4006 // |
| 16814 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 16815 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16816 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 16817 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 16818 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqxtun, |
| 16819 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 16820 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 16821 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 16822 | // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 465:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn)) => (SQXTUNv4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn) |
| 16823 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 16824 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 16825 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16826 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16827 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16828 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16829 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16830 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 16831 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 16832 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 16833 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 16834 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 16835 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 16836 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv4i32, |
| 16837 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16838 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16839 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16840 | GIR_EraseFromParent, /*InsnID*/0, |
| 16841 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16842 | // GIR_Coverage, 4006, |
| 16843 | GIR_Done, |
| 16844 | // Label 832: @41646 |
| 16845 | GIM_Try, /*On fail goto*//*Label 833*/ 41739, // Rule ID 4009 // |
| 16846 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 16847 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16848 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 16849 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 16850 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqxtn, |
| 16851 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 16852 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 16853 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 16854 | // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 510:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn)) => (UQXTNv4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn) |
| 16855 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 16856 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 16857 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16858 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16859 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16860 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16861 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16862 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 16863 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 16864 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 16865 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 16866 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 16867 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 16868 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv4i32, |
| 16869 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16870 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16871 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16872 | GIR_EraseFromParent, /*InsnID*/0, |
| 16873 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16874 | // GIR_Coverage, 4009, |
| 16875 | GIR_Done, |
| 16876 | // Label 833: @41739 |
| 16877 | GIM_Try, /*On fail goto*//*Label 834*/ 41823, // Rule ID 3980 // |
| 16878 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16879 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FPTRUNC, |
| 16880 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 16881 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 16882 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 16883 | // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rd, (fpround:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn)) => (FCVTNv4i32:{ *:[v4f32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2f32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rn) |
| 16884 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 16885 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 16886 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16887 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16888 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16889 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16890 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16891 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 16892 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 16893 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 16894 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 16895 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 16896 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 16897 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNv4i32, |
| 16898 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16899 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16900 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 16901 | GIR_EraseFromParent, /*InsnID*/0, |
| 16902 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16903 | // GIR_Coverage, 3980, |
| 16904 | GIR_Done, |
| 16905 | // Label 834: @41823 |
| 16906 | GIM_Try, /*On fail goto*//*Label 835*/ 41909, // Rule ID 4012 // |
| 16907 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 16908 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16909 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, |
| 16910 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 16911 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 16912 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 16913 | // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn)) => (XTNv4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn) |
| 16914 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 16915 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 16916 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16917 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16918 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16919 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16920 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16921 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 16922 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 16923 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 16924 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 16925 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 16926 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 16927 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::XTNv4i32, |
| 16928 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16929 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16930 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 16931 | GIR_EraseFromParent, /*InsnID*/0, |
| 16932 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16933 | // GIR_Coverage, 4012, |
| 16934 | GIR_Done, |
| 16935 | // Label 835: @41909 |
| 16936 | GIM_Try, /*On fail goto*//*Label 836*/ 41965, // Rule ID 4471 // |
| 16937 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16938 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_IMPLICIT_DEF, |
| 16939 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 16940 | // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rn, (undef:{ *:[v2i32] })) => (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }) |
| 16941 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16942 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16943 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16944 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16945 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16946 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16947 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16948 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 16949 | GIR_AddImm, /*InsnID*/0, /*Imm*/2, |
| 16950 | GIR_EraseFromParent, /*InsnID*/0, |
| 16951 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 16952 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, |
| 16953 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::FPR64RegClassID, |
| 16954 | // GIR_Coverage, 4471, |
| 16955 | GIR_Done, |
| 16956 | // Label 836: @41965 |
| 16957 | GIM_Try, /*On fail goto*//*Label 837*/ 42021, // Rule ID 4472 // |
| 16958 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16959 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_IMPLICIT_DEF, |
| 16960 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 16961 | // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rn, (undef:{ *:[v2f32] })) => (INSERT_SUBREG:{ *:[v4f32] } (IMPLICIT_DEF:{ *:[v4f32] }), V64:{ *:[v2f32] }:$Rn, dsub:{ *:[i32] }) |
| 16962 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16963 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16964 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16965 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16966 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16967 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 16968 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16969 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 16970 | GIR_AddImm, /*InsnID*/0, /*Imm*/2, |
| 16971 | GIR_EraseFromParent, /*InsnID*/0, |
| 16972 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 16973 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, |
| 16974 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::FPR64RegClassID, |
| 16975 | // GIR_Coverage, 4472, |
| 16976 | GIR_Done, |
| 16977 | // Label 837: @42021 |
| 16978 | GIM_Try, /*On fail goto*//*Label 838*/ 42143, // Rule ID 4463 // |
| 16979 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 16980 | // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn) => (INSvi64lane:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 16981 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 16982 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 16983 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128, |
| 16984 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, |
| 16985 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16986 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 16987 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 16988 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 16989 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 16990 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, |
| 16991 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 16992 | GIR_AddImm, /*InsnID*/3, /*Imm*/2, |
| 16993 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR128RegClassID, |
| 16994 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, |
| 16995 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR64RegClassID, |
| 16996 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 16997 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16998 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16999 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17000 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17001 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 17002 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 17003 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 17004 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 17005 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 17006 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 17007 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, |
| 17008 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17009 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17010 | GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 17011 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, |
| 17012 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 17013 | GIR_EraseFromParent, /*InsnID*/0, |
| 17014 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17015 | // GIR_Coverage, 4463, |
| 17016 | GIR_Done, |
| 17017 | // Label 838: @42143 |
| 17018 | GIM_Try, /*On fail goto*//*Label 839*/ 42265, // Rule ID 4464 // |
| 17019 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 17020 | // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn) => (INSvi64lane:{ *:[v4f32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2f32] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2f32] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 17021 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 17022 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 17023 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128, |
| 17024 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, |
| 17025 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17026 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 17027 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 17028 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17029 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 17030 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, |
| 17031 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 17032 | GIR_AddImm, /*InsnID*/3, /*Imm*/2, |
| 17033 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR128RegClassID, |
| 17034 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, |
| 17035 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR64RegClassID, |
| 17036 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17037 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 17038 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17039 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17040 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17041 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 17042 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 17043 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 17044 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 17045 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 17046 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 17047 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, |
| 17048 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17049 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17050 | GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 17051 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, |
| 17052 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 17053 | GIR_EraseFromParent, /*InsnID*/0, |
| 17054 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17055 | // GIR_Coverage, 4464, |
| 17056 | GIR_Done, |
| 17057 | // Label 839: @42265 |
| 17058 | GIM_Reject, |
| 17059 | // Label 814: @42266 |
| 17060 | GIM_Reject, |
| 17061 | // Label 806: @42267 |
| 17062 | GIM_Try, /*On fail goto*//*Label 840*/ 44812, |
| 17063 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 17064 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 17065 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 17066 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 17067 | GIM_Try, /*On fail goto*//*Label 841*/ 42394, // Rule ID 4260 // |
| 17068 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17069 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, |
| 17070 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 17071 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 17072 | GIM_CheckOpcode, /*MI*/2, AArch64::G_VLSHR, |
| 17073 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 17074 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 17075 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ADD, |
| 17076 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32, |
| 17077 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17078 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 17079 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 17080 | // MIs[2] Operand 2 |
| 17081 | GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, 16, |
| 17082 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17083 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 17084 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 17085 | // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), 16:{ *:[i32] }))) => (ADDHNv4i32_v8i16:{ *:[v8i16] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 17086 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 17087 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 17088 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17089 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 17090 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 17091 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 17092 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 17093 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 17094 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv4i32_v8i16, |
| 17095 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17096 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17097 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 17098 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm |
| 17099 | GIR_EraseFromParent, /*InsnID*/0, |
| 17100 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17101 | // GIR_Coverage, 4260, |
| 17102 | GIR_Done, |
| 17103 | // Label 841: @42394 |
| 17104 | GIM_Try, /*On fail goto*//*Label 842*/ 42503, // Rule ID 4266 // |
| 17105 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17106 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, |
| 17107 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 17108 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 17109 | GIM_CheckOpcode, /*MI*/2, AArch64::G_VLSHR, |
| 17110 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 17111 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 17112 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SUB, |
| 17113 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32, |
| 17114 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17115 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 17116 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 17117 | // MIs[2] Operand 2 |
| 17118 | GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, 16, |
| 17119 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17120 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 17121 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 17122 | // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), 16:{ *:[i32] }))) => (SUBHNv4i32_v8i16:{ *:[v8i16] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 17123 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 17124 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 17125 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17126 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 17127 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 17128 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 17129 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 17130 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 17131 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv4i32_v8i16, |
| 17132 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17133 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17134 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 17135 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm |
| 17136 | GIR_EraseFromParent, /*InsnID*/0, |
| 17137 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17138 | // GIR_Coverage, 4266, |
| 17139 | GIR_Done, |
| 17140 | // Label 842: @42503 |
| 17141 | GIM_Try, /*On fail goto*//*Label 843*/ 42615, // Rule ID 2738 // |
| 17142 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 17143 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17144 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 17145 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 17146 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_rshrn, |
| 17147 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17148 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 17149 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 17150 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 17151 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 17152 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, |
| 17153 | // MIs[2] Operand 1 |
| 17154 | // No operand predicates |
| 17155 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17156 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 17157 | // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 424:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)) => (RSHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) |
| 17158 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 17159 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 17160 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17161 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 17162 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17163 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17164 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17165 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 17166 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 17167 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 17168 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 17169 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 17170 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 17171 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv8i16_shift, |
| 17172 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17173 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17174 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 17175 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 17176 | GIR_EraseFromParent, /*InsnID*/0, |
| 17177 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17178 | // GIR_Coverage, 2738, |
| 17179 | GIR_Done, |
| 17180 | // Label 843: @42615 |
| 17181 | GIM_Try, /*On fail goto*//*Label 844*/ 42727, // Rule ID 4742 // |
| 17182 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 17183 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17184 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 17185 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 17186 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn, |
| 17187 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17188 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 17189 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 17190 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 17191 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 17192 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, |
| 17193 | // MIs[2] Operand 1 |
| 17194 | // No operand predicates |
| 17195 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17196 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 17197 | // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 457:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)) => (SQRSHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) |
| 17198 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 17199 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 17200 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17201 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 17202 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17203 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17204 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17205 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 17206 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 17207 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 17208 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 17209 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 17210 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 17211 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv8i16_shift, |
| 17212 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17213 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17214 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 17215 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 17216 | GIR_EraseFromParent, /*InsnID*/0, |
| 17217 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17218 | // GIR_Coverage, 4742, |
| 17219 | GIR_Done, |
| 17220 | // Label 844: @42727 |
| 17221 | GIM_Try, /*On fail goto*//*Label 845*/ 42839, // Rule ID 4745 // |
| 17222 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 17223 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17224 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 17225 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 17226 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun, |
| 17227 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17228 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 17229 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 17230 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 17231 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 17232 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, |
| 17233 | // MIs[2] Operand 1 |
| 17234 | // No operand predicates |
| 17235 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17236 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 17237 | // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 458:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)) => (SQRSHRUNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) |
| 17238 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 17239 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 17240 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17241 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 17242 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17243 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17244 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17245 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 17246 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 17247 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 17248 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 17249 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 17250 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 17251 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv8i16_shift, |
| 17252 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17253 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17254 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 17255 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 17256 | GIR_EraseFromParent, /*InsnID*/0, |
| 17257 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17258 | // GIR_Coverage, 4745, |
| 17259 | GIR_Done, |
| 17260 | // Label 845: @42839 |
| 17261 | GIM_Try, /*On fail goto*//*Label 846*/ 42951, // Rule ID 4748 // |
| 17262 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 17263 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17264 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 17265 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 17266 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqshrn, |
| 17267 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17268 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 17269 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 17270 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 17271 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 17272 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, |
| 17273 | // MIs[2] Operand 1 |
| 17274 | // No operand predicates |
| 17275 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17276 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 17277 | // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 461:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)) => (SQSHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) |
| 17278 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 17279 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 17280 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17281 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 17282 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17283 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17284 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17285 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 17286 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 17287 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 17288 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 17289 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 17290 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 17291 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv8i16_shift, |
| 17292 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17293 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17294 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 17295 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 17296 | GIR_EraseFromParent, /*InsnID*/0, |
| 17297 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17298 | // GIR_Coverage, 4748, |
| 17299 | GIR_Done, |
| 17300 | // Label 846: @42951 |
| 17301 | GIM_Try, /*On fail goto*//*Label 847*/ 43063, // Rule ID 4751 // |
| 17302 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 17303 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17304 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 17305 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 17306 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqshrun, |
| 17307 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17308 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 17309 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 17310 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 17311 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 17312 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, |
| 17313 | // MIs[2] Operand 1 |
| 17314 | // No operand predicates |
| 17315 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17316 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 17317 | // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 462:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)) => (SQSHRUNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) |
| 17318 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 17319 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 17320 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17321 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 17322 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17323 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17324 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17325 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 17326 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 17327 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 17328 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 17329 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 17330 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 17331 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv8i16_shift, |
| 17332 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17333 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17334 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 17335 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 17336 | GIR_EraseFromParent, /*InsnID*/0, |
| 17337 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17338 | // GIR_Coverage, 4751, |
| 17339 | GIR_Done, |
| 17340 | // Label 847: @43063 |
| 17341 | GIM_Try, /*On fail goto*//*Label 848*/ 43175, // Rule ID 4755 // |
| 17342 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 17343 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17344 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 17345 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 17346 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn, |
| 17347 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17348 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 17349 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 17350 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 17351 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 17352 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, |
| 17353 | // MIs[2] Operand 1 |
| 17354 | // No operand predicates |
| 17355 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17356 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 17357 | // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 506:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)) => (UQRSHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) |
| 17358 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 17359 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 17360 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17361 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 17362 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17363 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17364 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17365 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 17366 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 17367 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 17368 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 17369 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 17370 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 17371 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv8i16_shift, |
| 17372 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17373 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17374 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 17375 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 17376 | GIR_EraseFromParent, /*InsnID*/0, |
| 17377 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17378 | // GIR_Coverage, 4755, |
| 17379 | GIR_Done, |
| 17380 | // Label 848: @43175 |
| 17381 | GIM_Try, /*On fail goto*//*Label 849*/ 43287, // Rule ID 4758 // |
| 17382 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 17383 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17384 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 17385 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 17386 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqshrn, |
| 17387 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17388 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 17389 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 17390 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 17391 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 17392 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, |
| 17393 | // MIs[2] Operand 1 |
| 17394 | // No operand predicates |
| 17395 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17396 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 17397 | // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 508:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)) => (UQSHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) |
| 17398 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 17399 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 17400 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17401 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 17402 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17403 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17404 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17405 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 17406 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 17407 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 17408 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 17409 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 17410 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 17411 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv8i16_shift, |
| 17412 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17413 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17414 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 17415 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 17416 | GIR_EraseFromParent, /*InsnID*/0, |
| 17417 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17418 | // GIR_Coverage, 4758, |
| 17419 | GIR_Done, |
| 17420 | // Label 849: @43287 |
| 17421 | GIM_Try, /*On fail goto*//*Label 850*/ 43401, // Rule ID 4738 // |
| 17422 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 17423 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17424 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, |
| 17425 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 17426 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 17427 | GIM_CheckOpcode, /*MI*/2, AArch64::G_VASHR, |
| 17428 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 17429 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 17430 | // MIs[2] imm |
| 17431 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 17432 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 17433 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, |
| 17434 | // MIs[3] Operand 1 |
| 17435 | // No operand predicates |
| 17436 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17437 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 17438 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 17439 | // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm))) => (SHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) |
| 17440 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 17441 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 17442 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17443 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 17444 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17445 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17446 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17447 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 17448 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 17449 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 17450 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 17451 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 17452 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 17453 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHRNv8i16_shift, |
| 17454 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17455 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17456 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 17457 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // imm |
| 17458 | GIR_EraseFromParent, /*InsnID*/0, |
| 17459 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17460 | // GIR_Coverage, 4738, |
| 17461 | GIR_Done, |
| 17462 | // Label 850: @43401 |
| 17463 | GIM_Try, /*On fail goto*//*Label 851*/ 43513, // Rule ID 4764 // |
| 17464 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17465 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, |
| 17466 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 17467 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 17468 | GIM_CheckOpcode, /*MI*/2, AArch64::G_VLSHR, |
| 17469 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 17470 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 17471 | // MIs[2] imm |
| 17472 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 17473 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 17474 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, |
| 17475 | // MIs[3] Operand 1 |
| 17476 | // No operand predicates |
| 17477 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17478 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 17479 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 17480 | // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm))) => (SHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) |
| 17481 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 17482 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 17483 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17484 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 17485 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17486 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17487 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17488 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 17489 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 17490 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 17491 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 17492 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 17493 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 17494 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHRNv8i16_shift, |
| 17495 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17496 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17497 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 17498 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // imm |
| 17499 | GIR_EraseFromParent, /*InsnID*/0, |
| 17500 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17501 | // GIR_Coverage, 4764, |
| 17502 | GIR_Done, |
| 17503 | // Label 851: @43513 |
| 17504 | GIM_Try, /*On fail goto*//*Label 852*/ 43618, // Rule ID 2695 // |
| 17505 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 17506 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17507 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 17508 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 17509 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_addhn, |
| 17510 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17511 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, |
| 17512 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 17513 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 17514 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17515 | // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 358:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (ADDHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 17516 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 17517 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 17518 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17519 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 17520 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17521 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17522 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17523 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 17524 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 17525 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 17526 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 17527 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 17528 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 17529 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv4i32_v8i16, |
| 17530 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17531 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17532 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 17533 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 17534 | GIR_EraseFromParent, /*InsnID*/0, |
| 17535 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17536 | // GIR_Coverage, 2695, |
| 17537 | GIR_Done, |
| 17538 | // Label 852: @43618 |
| 17539 | GIM_Try, /*On fail goto*//*Label 853*/ 43723, // Rule ID 4210 // |
| 17540 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 17541 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17542 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 17543 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 17544 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_subhn, |
| 17545 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17546 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, |
| 17547 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 17548 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 17549 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17550 | // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 479:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (SUBHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 17551 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 17552 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 17553 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17554 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 17555 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17556 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17557 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17558 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 17559 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 17560 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 17561 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 17562 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 17563 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 17564 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv4i32_v8i16, |
| 17565 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17566 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17567 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 17568 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 17569 | GIR_EraseFromParent, /*InsnID*/0, |
| 17570 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17571 | // GIR_Coverage, 4210, |
| 17572 | GIR_Done, |
| 17573 | // Label 853: @43723 |
| 17574 | GIM_Try, /*On fail goto*//*Label 854*/ 43828, // Rule ID 4213 // |
| 17575 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 17576 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17577 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 17578 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 17579 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_raddhn, |
| 17580 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17581 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, |
| 17582 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 17583 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 17584 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17585 | // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 422:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (RADDHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 17586 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 17587 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 17588 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17589 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 17590 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17591 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17592 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17593 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 17594 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 17595 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 17596 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 17597 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 17598 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 17599 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv4i32_v8i16, |
| 17600 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17601 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17602 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 17603 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 17604 | GIR_EraseFromParent, /*InsnID*/0, |
| 17605 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17606 | // GIR_Coverage, 4213, |
| 17607 | GIR_Done, |
| 17608 | // Label 854: @43828 |
| 17609 | GIM_Try, /*On fail goto*//*Label 855*/ 43933, // Rule ID 4216 // |
| 17610 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 17611 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17612 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 17613 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 17614 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_rsubhn, |
| 17615 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17616 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, |
| 17617 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 17618 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 17619 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17620 | // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 425:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (RSUBHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 17621 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 17622 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 17623 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17624 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 17625 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17626 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17627 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17628 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 17629 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 17630 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 17631 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 17632 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 17633 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 17634 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv4i32_v8i16, |
| 17635 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17636 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17637 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 17638 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 17639 | GIR_EraseFromParent, /*InsnID*/0, |
| 17640 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17641 | // GIR_Coverage, 4216, |
| 17642 | GIR_Done, |
| 17643 | // Label 855: @43933 |
| 17644 | GIM_Try, /*On fail goto*//*Label 856*/ 44026, // Rule ID 2691 // |
| 17645 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 17646 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17647 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 17648 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 17649 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqxtn, |
| 17650 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17651 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 17652 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17653 | // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 464:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)) => (SQXTNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn) |
| 17654 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 17655 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 17656 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17657 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 17658 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17659 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17660 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17661 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 17662 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 17663 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 17664 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 17665 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 17666 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 17667 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv8i16, |
| 17668 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17669 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17670 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 17671 | GIR_EraseFromParent, /*InsnID*/0, |
| 17672 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17673 | // GIR_Coverage, 2691, |
| 17674 | GIR_Done, |
| 17675 | // Label 856: @44026 |
| 17676 | GIM_Try, /*On fail goto*//*Label 857*/ 44117, // Rule ID 3977 // |
| 17677 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17678 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 17679 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 17680 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2hf, |
| 17681 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17682 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 17683 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17684 | // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 529:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)) => (FCVTNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rn) |
| 17685 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 17686 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 17687 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17688 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 17689 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17690 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17691 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17692 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 17693 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 17694 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 17695 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 17696 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 17697 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 17698 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNv8i16, |
| 17699 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17700 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17701 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 17702 | GIR_EraseFromParent, /*InsnID*/0, |
| 17703 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17704 | // GIR_Coverage, 3977, |
| 17705 | GIR_Done, |
| 17706 | // Label 857: @44117 |
| 17707 | GIM_Try, /*On fail goto*//*Label 858*/ 44210, // Rule ID 4005 // |
| 17708 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 17709 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17710 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 17711 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 17712 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqxtun, |
| 17713 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17714 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 17715 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17716 | // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 465:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)) => (SQXTUNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn) |
| 17717 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 17718 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 17719 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17720 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 17721 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17722 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17723 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17724 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 17725 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 17726 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 17727 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 17728 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 17729 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 17730 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv8i16, |
| 17731 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17732 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17733 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 17734 | GIR_EraseFromParent, /*InsnID*/0, |
| 17735 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17736 | // GIR_Coverage, 4005, |
| 17737 | GIR_Done, |
| 17738 | // Label 858: @44210 |
| 17739 | GIM_Try, /*On fail goto*//*Label 859*/ 44303, // Rule ID 4008 // |
| 17740 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 17741 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17742 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 17743 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 17744 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqxtn, |
| 17745 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17746 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 17747 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17748 | // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 510:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)) => (UQXTNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn) |
| 17749 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 17750 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 17751 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17752 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 17753 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17754 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17755 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17756 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 17757 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 17758 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 17759 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 17760 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 17761 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 17762 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv8i16, |
| 17763 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17764 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17765 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 17766 | GIR_EraseFromParent, /*InsnID*/0, |
| 17767 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17768 | // GIR_Coverage, 4008, |
| 17769 | GIR_Done, |
| 17770 | // Label 859: @44303 |
| 17771 | GIM_Try, /*On fail goto*//*Label 860*/ 44389, // Rule ID 4011 // |
| 17772 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 17773 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17774 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, |
| 17775 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 17776 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 17777 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17778 | // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn)) => (XTNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn) |
| 17779 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 17780 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 17781 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17782 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 17783 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17784 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17785 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17786 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 17787 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 17788 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 17789 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 17790 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 17791 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 17792 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::XTNv8i16, |
| 17793 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17794 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17795 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 17796 | GIR_EraseFromParent, /*InsnID*/0, |
| 17797 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17798 | // GIR_Coverage, 4011, |
| 17799 | GIR_Done, |
| 17800 | // Label 860: @44389 |
| 17801 | GIM_Try, /*On fail goto*//*Label 861*/ 44445, // Rule ID 4473 // |
| 17802 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17803 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_IMPLICIT_DEF, |
| 17804 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17805 | // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rn, (undef:{ *:[v4i16] })) => (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }) |
| 17806 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 17807 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17808 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17809 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17810 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17811 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17812 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17813 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 17814 | GIR_AddImm, /*InsnID*/0, /*Imm*/2, |
| 17815 | GIR_EraseFromParent, /*InsnID*/0, |
| 17816 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 17817 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, |
| 17818 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::FPR64RegClassID, |
| 17819 | // GIR_Coverage, 4473, |
| 17820 | GIR_Done, |
| 17821 | // Label 861: @44445 |
| 17822 | GIM_Try, /*On fail goto*//*Label 862*/ 44567, // Rule ID 4465 // |
| 17823 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 17824 | // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn) => (INSvi64lane:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 17825 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 17826 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 17827 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128, |
| 17828 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, |
| 17829 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17830 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 17831 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 17832 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17833 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 17834 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, |
| 17835 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 17836 | GIR_AddImm, /*InsnID*/3, /*Imm*/2, |
| 17837 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR128RegClassID, |
| 17838 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, |
| 17839 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR64RegClassID, |
| 17840 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17841 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 17842 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17843 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17844 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17845 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 17846 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 17847 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 17848 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 17849 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 17850 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 17851 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, |
| 17852 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17853 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17854 | GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 17855 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, |
| 17856 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 17857 | GIR_EraseFromParent, /*InsnID*/0, |
| 17858 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17859 | // GIR_Coverage, 4465, |
| 17860 | GIR_Done, |
| 17861 | // Label 862: @44567 |
| 17862 | GIM_Try, /*On fail goto*//*Label 863*/ 44689, // Rule ID 4466 // |
| 17863 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 17864 | // (concat_vectors:{ *:[v8f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn) => (INSvi64lane:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4f16] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4f16] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 17865 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 17866 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 17867 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128, |
| 17868 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, |
| 17869 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17870 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 17871 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 17872 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17873 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 17874 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, |
| 17875 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 17876 | GIR_AddImm, /*InsnID*/3, /*Imm*/2, |
| 17877 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR128RegClassID, |
| 17878 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, |
| 17879 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR64RegClassID, |
| 17880 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17881 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 17882 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17883 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17884 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17885 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 17886 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 17887 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 17888 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 17889 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 17890 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 17891 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, |
| 17892 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17893 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17894 | GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 17895 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, |
| 17896 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 17897 | GIR_EraseFromParent, /*InsnID*/0, |
| 17898 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17899 | // GIR_Coverage, 4466, |
| 17900 | GIR_Done, |
| 17901 | // Label 863: @44689 |
| 17902 | GIM_Try, /*On fail goto*//*Label 864*/ 44811, // Rule ID 4467 // |
| 17903 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 17904 | // (concat_vectors:{ *:[v8bf16] } V64:{ *:[v4bf16] }:$Rd, V64:{ *:[v4bf16] }:$Rn) => (INSvi64lane:{ *:[v8bf16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4bf16] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4bf16] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 17905 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 17906 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 17907 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128, |
| 17908 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, |
| 17909 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17910 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 17911 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 17912 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17913 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 17914 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, |
| 17915 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 17916 | GIR_AddImm, /*InsnID*/3, /*Imm*/2, |
| 17917 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR128RegClassID, |
| 17918 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, |
| 17919 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR64RegClassID, |
| 17920 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 17921 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 17922 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17923 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 17924 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17925 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 17926 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 17927 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 17928 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 17929 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 17930 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 17931 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, |
| 17932 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17933 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17934 | GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 17935 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, |
| 17936 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 17937 | GIR_EraseFromParent, /*InsnID*/0, |
| 17938 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17939 | // GIR_Coverage, 4467, |
| 17940 | GIR_Done, |
| 17941 | // Label 864: @44811 |
| 17942 | GIM_Reject, |
| 17943 | // Label 840: @44812 |
| 17944 | GIM_Reject, |
| 17945 | // Label 807: @44813 |
| 17946 | GIM_Try, /*On fail goto*//*Label 865*/ 47023, |
| 17947 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 17948 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 17949 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 17950 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 17951 | GIM_Try, /*On fail goto*//*Label 866*/ 44940, // Rule ID 4259 // |
| 17952 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17953 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, |
| 17954 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 17955 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 17956 | GIM_CheckOpcode, /*MI*/2, AArch64::G_VLSHR, |
| 17957 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 17958 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 17959 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ADD, |
| 17960 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16, |
| 17961 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17962 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 17963 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 17964 | // MIs[2] Operand 2 |
| 17965 | GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, 8, |
| 17966 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17967 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 17968 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 17969 | // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), 8:{ *:[i32] }))) => (ADDHNv8i16_v16i8:{ *:[v16i8] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 17970 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 17971 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 17972 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17973 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 17974 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 17975 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 17976 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 17977 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 17978 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv8i16_v16i8, |
| 17979 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 17980 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17981 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 17982 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm |
| 17983 | GIR_EraseFromParent, /*InsnID*/0, |
| 17984 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17985 | // GIR_Coverage, 4259, |
| 17986 | GIR_Done, |
| 17987 | // Label 866: @44940 |
| 17988 | GIM_Try, /*On fail goto*//*Label 867*/ 45049, // Rule ID 4265 // |
| 17989 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 17990 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, |
| 17991 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 17992 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 17993 | GIM_CheckOpcode, /*MI*/2, AArch64::G_VLSHR, |
| 17994 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 17995 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 17996 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SUB, |
| 17997 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16, |
| 17998 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17999 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 18000 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 18001 | // MIs[2] Operand 2 |
| 18002 | GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, 8, |
| 18003 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18004 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 18005 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 18006 | // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), 8:{ *:[i32] }))) => (SUBHNv8i16_v16i8:{ *:[v16i8] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 18007 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 18008 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 18009 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18010 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 18011 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 18012 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 18013 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 18014 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 18015 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv8i16_v16i8, |
| 18016 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 18017 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18018 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 18019 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm |
| 18020 | GIR_EraseFromParent, /*InsnID*/0, |
| 18021 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18022 | // GIR_Coverage, 4265, |
| 18023 | GIR_Done, |
| 18024 | // Label 867: @45049 |
| 18025 | GIM_Try, /*On fail goto*//*Label 868*/ 45161, // Rule ID 2737 // |
| 18026 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 18027 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18028 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 18029 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 18030 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_rshrn, |
| 18031 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18032 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 18033 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 18034 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 18035 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 18036 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, |
| 18037 | // MIs[2] Operand 1 |
| 18038 | // No operand predicates |
| 18039 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18040 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 18041 | // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 424:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)) => (RSHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) |
| 18042 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 18043 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 18044 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 18045 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 18046 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18047 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 18048 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18049 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 18050 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 18051 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 18052 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 18053 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 18054 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 18055 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv16i8_shift, |
| 18056 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 18057 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18058 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 18059 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 18060 | GIR_EraseFromParent, /*InsnID*/0, |
| 18061 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18062 | // GIR_Coverage, 2737, |
| 18063 | GIR_Done, |
| 18064 | // Label 868: @45161 |
| 18065 | GIM_Try, /*On fail goto*//*Label 869*/ 45273, // Rule ID 4741 // |
| 18066 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 18067 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18068 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 18069 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 18070 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn, |
| 18071 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18072 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 18073 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 18074 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 18075 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 18076 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, |
| 18077 | // MIs[2] Operand 1 |
| 18078 | // No operand predicates |
| 18079 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18080 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 18081 | // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 457:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)) => (SQRSHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) |
| 18082 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 18083 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 18084 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 18085 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 18086 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18087 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 18088 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18089 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 18090 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 18091 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 18092 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 18093 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 18094 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 18095 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv16i8_shift, |
| 18096 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 18097 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18098 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 18099 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 18100 | GIR_EraseFromParent, /*InsnID*/0, |
| 18101 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18102 | // GIR_Coverage, 4741, |
| 18103 | GIR_Done, |
| 18104 | // Label 869: @45273 |
| 18105 | GIM_Try, /*On fail goto*//*Label 870*/ 45385, // Rule ID 4744 // |
| 18106 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 18107 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18108 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 18109 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 18110 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun, |
| 18111 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18112 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 18113 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 18114 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 18115 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 18116 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, |
| 18117 | // MIs[2] Operand 1 |
| 18118 | // No operand predicates |
| 18119 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18120 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 18121 | // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 458:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)) => (SQRSHRUNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) |
| 18122 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 18123 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 18124 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 18125 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 18126 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18127 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 18128 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18129 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 18130 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 18131 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 18132 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 18133 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 18134 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 18135 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv16i8_shift, |
| 18136 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 18137 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18138 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 18139 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 18140 | GIR_EraseFromParent, /*InsnID*/0, |
| 18141 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18142 | // GIR_Coverage, 4744, |
| 18143 | GIR_Done, |
| 18144 | // Label 870: @45385 |
| 18145 | GIM_Try, /*On fail goto*//*Label 871*/ 45497, // Rule ID 4747 // |
| 18146 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 18147 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18148 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 18149 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 18150 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqshrn, |
| 18151 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18152 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 18153 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 18154 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 18155 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 18156 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, |
| 18157 | // MIs[2] Operand 1 |
| 18158 | // No operand predicates |
| 18159 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18160 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 18161 | // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 461:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)) => (SQSHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) |
| 18162 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 18163 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 18164 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 18165 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 18166 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18167 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 18168 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18169 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 18170 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 18171 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 18172 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 18173 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 18174 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 18175 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv16i8_shift, |
| 18176 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 18177 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18178 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 18179 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 18180 | GIR_EraseFromParent, /*InsnID*/0, |
| 18181 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18182 | // GIR_Coverage, 4747, |
| 18183 | GIR_Done, |
| 18184 | // Label 871: @45497 |
| 18185 | GIM_Try, /*On fail goto*//*Label 872*/ 45609, // Rule ID 4750 // |
| 18186 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 18187 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18188 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 18189 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 18190 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqshrun, |
| 18191 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18192 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 18193 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 18194 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 18195 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 18196 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, |
| 18197 | // MIs[2] Operand 1 |
| 18198 | // No operand predicates |
| 18199 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18200 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 18201 | // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 462:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)) => (SQSHRUNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) |
| 18202 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 18203 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 18204 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 18205 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 18206 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18207 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 18208 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18209 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 18210 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 18211 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 18212 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 18213 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 18214 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 18215 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv16i8_shift, |
| 18216 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 18217 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18218 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 18219 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 18220 | GIR_EraseFromParent, /*InsnID*/0, |
| 18221 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18222 | // GIR_Coverage, 4750, |
| 18223 | GIR_Done, |
| 18224 | // Label 872: @45609 |
| 18225 | GIM_Try, /*On fail goto*//*Label 873*/ 45721, // Rule ID 4754 // |
| 18226 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 18227 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18228 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 18229 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 18230 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn, |
| 18231 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18232 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 18233 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 18234 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 18235 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 18236 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, |
| 18237 | // MIs[2] Operand 1 |
| 18238 | // No operand predicates |
| 18239 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18240 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 18241 | // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 506:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)) => (UQRSHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) |
| 18242 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 18243 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 18244 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 18245 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 18246 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18247 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 18248 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18249 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 18250 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 18251 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 18252 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 18253 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 18254 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 18255 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv16i8_shift, |
| 18256 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 18257 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18258 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 18259 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 18260 | GIR_EraseFromParent, /*InsnID*/0, |
| 18261 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18262 | // GIR_Coverage, 4754, |
| 18263 | GIR_Done, |
| 18264 | // Label 873: @45721 |
| 18265 | GIM_Try, /*On fail goto*//*Label 874*/ 45833, // Rule ID 4757 // |
| 18266 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 18267 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18268 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 18269 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 18270 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqshrn, |
| 18271 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18272 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 18273 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 18274 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 18275 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 18276 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, |
| 18277 | // MIs[2] Operand 1 |
| 18278 | // No operand predicates |
| 18279 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18280 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 18281 | // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 508:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)) => (UQSHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) |
| 18282 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 18283 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 18284 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 18285 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 18286 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18287 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 18288 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18289 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 18290 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 18291 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 18292 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 18293 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 18294 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 18295 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv16i8_shift, |
| 18296 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 18297 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18298 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 18299 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 18300 | GIR_EraseFromParent, /*InsnID*/0, |
| 18301 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18302 | // GIR_Coverage, 4757, |
| 18303 | GIR_Done, |
| 18304 | // Label 874: @45833 |
| 18305 | GIM_Try, /*On fail goto*//*Label 875*/ 45947, // Rule ID 4737 // |
| 18306 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 18307 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18308 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, |
| 18309 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 18310 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 18311 | GIM_CheckOpcode, /*MI*/2, AArch64::G_VASHR, |
| 18312 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 18313 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 18314 | // MIs[2] imm |
| 18315 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 18316 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 18317 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, |
| 18318 | // MIs[3] Operand 1 |
| 18319 | // No operand predicates |
| 18320 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18321 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 18322 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 18323 | // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm))) => (SHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) |
| 18324 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 18325 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 18326 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 18327 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 18328 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18329 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 18330 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18331 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 18332 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 18333 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 18334 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 18335 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 18336 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 18337 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHRNv16i8_shift, |
| 18338 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 18339 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18340 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 18341 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // imm |
| 18342 | GIR_EraseFromParent, /*InsnID*/0, |
| 18343 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18344 | // GIR_Coverage, 4737, |
| 18345 | GIR_Done, |
| 18346 | // Label 875: @45947 |
| 18347 | GIM_Try, /*On fail goto*//*Label 876*/ 46059, // Rule ID 4763 // |
| 18348 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18349 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, |
| 18350 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 18351 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 18352 | GIM_CheckOpcode, /*MI*/2, AArch64::G_VLSHR, |
| 18353 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 18354 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 18355 | // MIs[2] imm |
| 18356 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 18357 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 18358 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, |
| 18359 | // MIs[3] Operand 1 |
| 18360 | // No operand predicates |
| 18361 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18362 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 18363 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 18364 | // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm))) => (SHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) |
| 18365 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 18366 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 18367 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 18368 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 18369 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18370 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 18371 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18372 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 18373 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 18374 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 18375 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 18376 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 18377 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 18378 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHRNv16i8_shift, |
| 18379 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 18380 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18381 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 18382 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // imm |
| 18383 | GIR_EraseFromParent, /*InsnID*/0, |
| 18384 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18385 | // GIR_Coverage, 4763, |
| 18386 | GIR_Done, |
| 18387 | // Label 876: @46059 |
| 18388 | GIM_Try, /*On fail goto*//*Label 877*/ 46164, // Rule ID 2694 // |
| 18389 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 18390 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18391 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 18392 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 18393 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_addhn, |
| 18394 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18395 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, |
| 18396 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 18397 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 18398 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18399 | // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 358:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (ADDHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 18400 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 18401 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 18402 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 18403 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 18404 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18405 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 18406 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18407 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 18408 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 18409 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 18410 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 18411 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 18412 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 18413 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv8i16_v16i8, |
| 18414 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 18415 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18416 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 18417 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 18418 | GIR_EraseFromParent, /*InsnID*/0, |
| 18419 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18420 | // GIR_Coverage, 2694, |
| 18421 | GIR_Done, |
| 18422 | // Label 877: @46164 |
| 18423 | GIM_Try, /*On fail goto*//*Label 878*/ 46269, // Rule ID 4209 // |
| 18424 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 18425 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18426 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 18427 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 18428 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_subhn, |
| 18429 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18430 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, |
| 18431 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 18432 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 18433 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18434 | // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 479:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (SUBHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 18435 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 18436 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 18437 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 18438 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 18439 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18440 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 18441 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18442 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 18443 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 18444 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 18445 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 18446 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 18447 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 18448 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv8i16_v16i8, |
| 18449 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 18450 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18451 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 18452 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 18453 | GIR_EraseFromParent, /*InsnID*/0, |
| 18454 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18455 | // GIR_Coverage, 4209, |
| 18456 | GIR_Done, |
| 18457 | // Label 878: @46269 |
| 18458 | GIM_Try, /*On fail goto*//*Label 879*/ 46374, // Rule ID 4212 // |
| 18459 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 18460 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18461 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 18462 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 18463 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_raddhn, |
| 18464 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18465 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, |
| 18466 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 18467 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 18468 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18469 | // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 422:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (RADDHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 18470 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 18471 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 18472 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 18473 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 18474 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18475 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 18476 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18477 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 18478 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 18479 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 18480 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 18481 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 18482 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 18483 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv8i16_v16i8, |
| 18484 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 18485 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18486 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 18487 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 18488 | GIR_EraseFromParent, /*InsnID*/0, |
| 18489 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18490 | // GIR_Coverage, 4212, |
| 18491 | GIR_Done, |
| 18492 | // Label 879: @46374 |
| 18493 | GIM_Try, /*On fail goto*//*Label 880*/ 46479, // Rule ID 4215 // |
| 18494 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 18495 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18496 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 18497 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 18498 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_rsubhn, |
| 18499 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18500 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, |
| 18501 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 18502 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 18503 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18504 | // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 425:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (RSUBHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 18505 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 18506 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 18507 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 18508 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 18509 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18510 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 18511 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18512 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 18513 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 18514 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 18515 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 18516 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 18517 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 18518 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv8i16_v16i8, |
| 18519 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 18520 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18521 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 18522 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 18523 | GIR_EraseFromParent, /*InsnID*/0, |
| 18524 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18525 | // GIR_Coverage, 4215, |
| 18526 | GIR_Done, |
| 18527 | // Label 880: @46479 |
| 18528 | GIM_Try, /*On fail goto*//*Label 881*/ 46572, // Rule ID 2690 // |
| 18529 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 18530 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18531 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 18532 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 18533 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqxtn, |
| 18534 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18535 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 18536 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18537 | // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 464:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (SQXTNv16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn) |
| 18538 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 18539 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 18540 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 18541 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 18542 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18543 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 18544 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18545 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 18546 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 18547 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 18548 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 18549 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 18550 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 18551 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv16i8, |
| 18552 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 18553 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18554 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 18555 | GIR_EraseFromParent, /*InsnID*/0, |
| 18556 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18557 | // GIR_Coverage, 2690, |
| 18558 | GIR_Done, |
| 18559 | // Label 881: @46572 |
| 18560 | GIM_Try, /*On fail goto*//*Label 882*/ 46665, // Rule ID 4004 // |
| 18561 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 18562 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18563 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 18564 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 18565 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqxtun, |
| 18566 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18567 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 18568 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18569 | // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 465:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (SQXTUNv16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn) |
| 18570 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 18571 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 18572 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 18573 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 18574 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18575 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 18576 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18577 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 18578 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 18579 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 18580 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 18581 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 18582 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 18583 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv16i8, |
| 18584 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 18585 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18586 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 18587 | GIR_EraseFromParent, /*InsnID*/0, |
| 18588 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18589 | // GIR_Coverage, 4004, |
| 18590 | GIR_Done, |
| 18591 | // Label 882: @46665 |
| 18592 | GIM_Try, /*On fail goto*//*Label 883*/ 46758, // Rule ID 4007 // |
| 18593 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 18594 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18595 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 18596 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 18597 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uqxtn, |
| 18598 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 18599 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 18600 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18601 | // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 510:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (UQXTNv16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn) |
| 18602 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 18603 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 18604 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 18605 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 18606 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18607 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 18608 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18609 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 18610 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 18611 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 18612 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 18613 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 18614 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 18615 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv16i8, |
| 18616 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 18617 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18618 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 18619 | GIR_EraseFromParent, /*InsnID*/0, |
| 18620 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18621 | // GIR_Coverage, 4007, |
| 18622 | GIR_Done, |
| 18623 | // Label 883: @46758 |
| 18624 | GIM_Try, /*On fail goto*//*Label 884*/ 46844, // Rule ID 4010 // |
| 18625 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 18626 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18627 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, |
| 18628 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 18629 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 18630 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18631 | // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn)) => (XTNv16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn) |
| 18632 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 18633 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 18634 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 18635 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 18636 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18637 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 18638 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18639 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 18640 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 18641 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 18642 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 18643 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 18644 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 18645 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::XTNv16i8, |
| 18646 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 18647 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18648 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 18649 | GIR_EraseFromParent, /*InsnID*/0, |
| 18650 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18651 | // GIR_Coverage, 4010, |
| 18652 | GIR_Done, |
| 18653 | // Label 884: @46844 |
| 18654 | GIM_Try, /*On fail goto*//*Label 885*/ 46900, // Rule ID 4474 // |
| 18655 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 18656 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_IMPLICIT_DEF, |
| 18657 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18658 | // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rn, (undef:{ *:[v8i8] })) => (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }) |
| 18659 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 18660 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 18661 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18662 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18663 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 18664 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 18665 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18666 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 18667 | GIR_AddImm, /*InsnID*/0, /*Imm*/2, |
| 18668 | GIR_EraseFromParent, /*InsnID*/0, |
| 18669 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 18670 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, |
| 18671 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::FPR64RegClassID, |
| 18672 | // GIR_Coverage, 4474, |
| 18673 | GIR_Done, |
| 18674 | // Label 885: @46900 |
| 18675 | GIM_Try, /*On fail goto*//*Label 886*/ 47022, // Rule ID 4468 // |
| 18676 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 18677 | // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn) => (INSvi64lane:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 18678 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 18679 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 18680 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128, |
| 18681 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, |
| 18682 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 18683 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 18684 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 18685 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 18686 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 18687 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, |
| 18688 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 18689 | GIR_AddImm, /*InsnID*/3, /*Imm*/2, |
| 18690 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR128RegClassID, |
| 18691 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, |
| 18692 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR64RegClassID, |
| 18693 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 18694 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 18695 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18696 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 18697 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18698 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 18699 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd |
| 18700 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 18701 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 18702 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 18703 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 18704 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, |
| 18705 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 18706 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18707 | GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 18708 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, |
| 18709 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 18710 | GIR_EraseFromParent, /*InsnID*/0, |
| 18711 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18712 | // GIR_Coverage, 4468, |
| 18713 | GIR_Done, |
| 18714 | // Label 886: @47022 |
| 18715 | GIM_Reject, |
| 18716 | // Label 865: @47023 |
| 18717 | GIM_Reject, |
| 18718 | // Label 808: @47024 |
| 18719 | GIM_Reject, |
| 18720 | // Label 803: @47025 |
| 18721 | GIM_Reject, |
| 18722 | // Label 9: @47026 |
| 18723 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 897*/ 56256, |
| 18724 | /*GILLT_s32*//*Label 887*/ 47042, |
| 18725 | /*GILLT_s64*//*Label 888*/ 47088, |
| 18726 | /*GILLT_s128*//*Label 889*/ 48908, |
| 18727 | /*GILLT_v2s32*//*Label 890*/ 49685, |
| 18728 | /*GILLT_v2s64*//*Label 891*/ 50694, |
| 18729 | /*GILLT_v4s16*//*Label 892*/ 51589, |
| 18730 | /*GILLT_v4s32*//*Label 893*/ 52963, |
| 18731 | /*GILLT_v8s8*//*Label 894*/ 53922, |
| 18732 | /*GILLT_v8s16*//*Label 895*/ 54452, |
| 18733 | /*GILLT_v16s8*//*Label 896*/ 55751, |
| 18734 | // Label 887: @47042 |
| 18735 | GIM_Try, /*On fail goto*//*Label 898*/ 47087, |
| 18736 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18737 | GIM_Try, /*On fail goto*//*Label 899*/ 47067, // Rule ID 5038 // |
| 18738 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 18739 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 18740 | // (bitconvert:{ *:[f32] } GPR32:{ *:[i32] }:$Xn) => (COPY_TO_REGCLASS:{ *:[f32] } GPR32:{ *:[i32] }:$Xn, FPR32:{ *:[i32] }) |
| 18741 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 18742 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, |
| 18743 | // GIR_Coverage, 5038, |
| 18744 | GIR_Done, |
| 18745 | // Label 899: @47067 |
| 18746 | GIM_Try, /*On fail goto*//*Label 900*/ 47086, // Rule ID 5039 // |
| 18747 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 18748 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 18749 | // (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$Xn) => (COPY_TO_REGCLASS:{ *:[i32] } FPR32:{ *:[f32] }:$Xn, GPR32:{ *:[i32] }) |
| 18750 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 18751 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR32RegClassID, |
| 18752 | // GIR_Coverage, 5039, |
| 18753 | GIR_Done, |
| 18754 | // Label 900: @47086 |
| 18755 | GIM_Reject, |
| 18756 | // Label 898: @47087 |
| 18757 | GIM_Reject, |
| 18758 | // Label 888: @47088 |
| 18759 | GIM_Try, /*On fail goto*//*Label 901*/ 47113, // Rule ID 5013 // |
| 18760 | GIM_CheckFeatures, GIFBS_IsLE, |
| 18761 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 18762 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 18763 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 18764 | // (bitconvert:{ *:[i64] } V64:{ *:[v8i8] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v8i8] }:$Vn, GPR64:{ *:[i32] }) |
| 18765 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 18766 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64RegClassID, |
| 18767 | // GIR_Coverage, 5013, |
| 18768 | GIR_Done, |
| 18769 | // Label 901: @47113 |
| 18770 | GIM_Try, /*On fail goto*//*Label 902*/ 47138, // Rule ID 5014 // |
| 18771 | GIM_CheckFeatures, GIFBS_IsLE, |
| 18772 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 18773 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 18774 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 18775 | // (bitconvert:{ *:[i64] } V64:{ *:[v4i16] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4i16] }:$Vn, GPR64:{ *:[i32] }) |
| 18776 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 18777 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64RegClassID, |
| 18778 | // GIR_Coverage, 5014, |
| 18779 | GIR_Done, |
| 18780 | // Label 902: @47138 |
| 18781 | GIM_Try, /*On fail goto*//*Label 903*/ 47163, // Rule ID 5015 // |
| 18782 | GIM_CheckFeatures, GIFBS_IsLE, |
| 18783 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 18784 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 18785 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 18786 | // (bitconvert:{ *:[i64] } V64:{ *:[v2i32] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2i32] }:$Vn, GPR64:{ *:[i32] }) |
| 18787 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 18788 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64RegClassID, |
| 18789 | // GIR_Coverage, 5015, |
| 18790 | GIR_Done, |
| 18791 | // Label 903: @47163 |
| 18792 | GIM_Try, /*On fail goto*//*Label 904*/ 47188, // Rule ID 5016 // |
| 18793 | GIM_CheckFeatures, GIFBS_IsLE, |
| 18794 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 18795 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 18796 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 18797 | // (bitconvert:{ *:[i64] } V64:{ *:[v4f16] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4f16] }:$Vn, GPR64:{ *:[i32] }) |
| 18798 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 18799 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64RegClassID, |
| 18800 | // GIR_Coverage, 5016, |
| 18801 | GIR_Done, |
| 18802 | // Label 904: @47188 |
| 18803 | GIM_Try, /*On fail goto*//*Label 905*/ 47213, // Rule ID 5017 // |
| 18804 | GIM_CheckFeatures, GIFBS_IsLE, |
| 18805 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 18806 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 18807 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 18808 | // (bitconvert:{ *:[i64] } V64:{ *:[v4bf16] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4bf16] }:$Vn, GPR64:{ *:[i32] }) |
| 18809 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 18810 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64RegClassID, |
| 18811 | // GIR_Coverage, 5017, |
| 18812 | GIR_Done, |
| 18813 | // Label 905: @47213 |
| 18814 | GIM_Try, /*On fail goto*//*Label 906*/ 47238, // Rule ID 5018 // |
| 18815 | GIM_CheckFeatures, GIFBS_IsLE, |
| 18816 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 18817 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 18818 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 18819 | // (bitconvert:{ *:[i64] } V64:{ *:[v2f32] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2f32] }:$Vn, GPR64:{ *:[i32] }) |
| 18820 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 18821 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64RegClassID, |
| 18822 | // GIR_Coverage, 5018, |
| 18823 | GIR_Done, |
| 18824 | // Label 906: @47238 |
| 18825 | GIM_Try, /*On fail goto*//*Label 907*/ 47263, // Rule ID 5019 // |
| 18826 | GIM_CheckFeatures, GIFBS_IsLE, |
| 18827 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 18828 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 18829 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 18830 | // (bitconvert:{ *:[i64] } V64:{ *:[v1f64] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v1f64] }:$Vn, GPR64:{ *:[i32] }) |
| 18831 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 18832 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64RegClassID, |
| 18833 | // GIR_Coverage, 5019, |
| 18834 | GIR_Done, |
| 18835 | // Label 907: @47263 |
| 18836 | GIM_Try, /*On fail goto*//*Label 908*/ 47311, // Rule ID 5026 // |
| 18837 | GIM_CheckFeatures, GIFBS_IsBE, |
| 18838 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 18839 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 18840 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 18841 | // (bitconvert:{ *:[i64] } V64:{ *:[v8i8] }:$Vn) => (REV64v8i8:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v8i8] }:$Vn, GPR64:{ *:[i32] })) |
| 18842 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 18843 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 18844 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18845 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn |
| 18846 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18847 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v8i8, |
| 18848 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 18849 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18850 | GIR_EraseFromParent, /*InsnID*/0, |
| 18851 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18852 | // GIR_Coverage, 5026, |
| 18853 | GIR_Done, |
| 18854 | // Label 908: @47311 |
| 18855 | GIM_Try, /*On fail goto*//*Label 909*/ 47359, // Rule ID 5027 // |
| 18856 | GIM_CheckFeatures, GIFBS_IsBE, |
| 18857 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 18858 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 18859 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 18860 | // (bitconvert:{ *:[i64] } V64:{ *:[v4i16] }:$Vn) => (REV64v4i16:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4i16] }:$Vn, GPR64:{ *:[i32] })) |
| 18861 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 18862 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 18863 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18864 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn |
| 18865 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18866 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 18867 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 18868 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18869 | GIR_EraseFromParent, /*InsnID*/0, |
| 18870 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18871 | // GIR_Coverage, 5027, |
| 18872 | GIR_Done, |
| 18873 | // Label 909: @47359 |
| 18874 | GIM_Try, /*On fail goto*//*Label 910*/ 47407, // Rule ID 5028 // |
| 18875 | GIM_CheckFeatures, GIFBS_IsBE, |
| 18876 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 18877 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 18878 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 18879 | // (bitconvert:{ *:[i64] } V64:{ *:[v2i32] }:$Vn) => (REV64v2i32:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2i32] }:$Vn, GPR64:{ *:[i32] })) |
| 18880 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 18881 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 18882 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18883 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn |
| 18884 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18885 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v2i32, |
| 18886 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 18887 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18888 | GIR_EraseFromParent, /*InsnID*/0, |
| 18889 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18890 | // GIR_Coverage, 5028, |
| 18891 | GIR_Done, |
| 18892 | // Label 910: @47407 |
| 18893 | GIM_Try, /*On fail goto*//*Label 911*/ 47455, // Rule ID 5029 // |
| 18894 | GIM_CheckFeatures, GIFBS_IsBE, |
| 18895 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 18896 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 18897 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 18898 | // (bitconvert:{ *:[i64] } V64:{ *:[v4f16] }:$Vn) => (REV64v4i16:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4f16] }:$Vn, GPR64:{ *:[i32] })) |
| 18899 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 18900 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 18901 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18902 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn |
| 18903 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18904 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 18905 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 18906 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18907 | GIR_EraseFromParent, /*InsnID*/0, |
| 18908 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18909 | // GIR_Coverage, 5029, |
| 18910 | GIR_Done, |
| 18911 | // Label 911: @47455 |
| 18912 | GIM_Try, /*On fail goto*//*Label 912*/ 47503, // Rule ID 5030 // |
| 18913 | GIM_CheckFeatures, GIFBS_IsBE, |
| 18914 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 18915 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 18916 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 18917 | // (bitconvert:{ *:[i64] } V64:{ *:[v4bf16] }:$Vn) => (REV64v4i16:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4bf16] }:$Vn, GPR64:{ *:[i32] })) |
| 18918 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 18919 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 18920 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18921 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn |
| 18922 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18923 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 18924 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 18925 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18926 | GIR_EraseFromParent, /*InsnID*/0, |
| 18927 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18928 | // GIR_Coverage, 5030, |
| 18929 | GIR_Done, |
| 18930 | // Label 912: @47503 |
| 18931 | GIM_Try, /*On fail goto*//*Label 913*/ 47551, // Rule ID 5031 // |
| 18932 | GIM_CheckFeatures, GIFBS_IsBE, |
| 18933 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 18934 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 18935 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 18936 | // (bitconvert:{ *:[i64] } V64:{ *:[v2f32] }:$Vn) => (REV64v2i32:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2f32] }:$Vn, GPR64:{ *:[i32] })) |
| 18937 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 18938 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 18939 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18940 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn |
| 18941 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18942 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v2i32, |
| 18943 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 18944 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18945 | GIR_EraseFromParent, /*InsnID*/0, |
| 18946 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18947 | // GIR_Coverage, 5031, |
| 18948 | GIR_Done, |
| 18949 | // Label 913: @47551 |
| 18950 | GIM_Try, /*On fail goto*//*Label 914*/ 47574, // Rule ID 5032 // |
| 18951 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 18952 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 18953 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 18954 | // (bitconvert:{ *:[v1i64] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v1i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) |
| 18955 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 18956 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 18957 | // GIR_Coverage, 5032, |
| 18958 | GIR_Done, |
| 18959 | // Label 914: @47574 |
| 18960 | GIM_Try, /*On fail goto*//*Label 915*/ 47597, // Rule ID 5033 // |
| 18961 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 18962 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 18963 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 18964 | // (bitconvert:{ *:[v1f64] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v1f64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) |
| 18965 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 18966 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 18967 | // GIR_Coverage, 5033, |
| 18968 | GIR_Done, |
| 18969 | // Label 915: @47597 |
| 18970 | GIM_Try, /*On fail goto*//*Label 916*/ 47620, // Rule ID 5034 // |
| 18971 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 18972 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 18973 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 18974 | // (bitconvert:{ *:[i64] } V64:{ *:[v1i64] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v1i64] }:$Vn, GPR64:{ *:[i32] }) |
| 18975 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 18976 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64RegClassID, |
| 18977 | // GIR_Coverage, 5034, |
| 18978 | GIR_Done, |
| 18979 | // Label 916: @47620 |
| 18980 | GIM_Try, /*On fail goto*//*Label 917*/ 47643, // Rule ID 5040 // |
| 18981 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 18982 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 18983 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 18984 | // (bitconvert:{ *:[f64] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[f64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) |
| 18985 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 18986 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 18987 | // GIR_Coverage, 5040, |
| 18988 | GIR_Done, |
| 18989 | // Label 917: @47643 |
| 18990 | GIM_Try, /*On fail goto*//*Label 918*/ 47666, // Rule ID 5041 // |
| 18991 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 18992 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 18993 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 18994 | // (bitconvert:{ *:[i64] } FPR64:{ *:[f64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[i64] } FPR64:{ *:[f64] }:$Xn, GPR64:{ *:[i32] }) |
| 18995 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 18996 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64RegClassID, |
| 18997 | // GIR_Coverage, 5041, |
| 18998 | GIR_Done, |
| 18999 | // Label 918: @47666 |
| 19000 | GIM_Try, /*On fail goto*//*Label 919*/ 47689, // Rule ID 5042 // |
| 19001 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 19002 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 19003 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19004 | // (bitconvert:{ *:[i64] } V64:{ *:[v1f64] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v1f64] }:$Vn, GPR64:{ *:[i32] }) |
| 19005 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19006 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64RegClassID, |
| 19007 | // GIR_Coverage, 5042, |
| 19008 | GIR_Done, |
| 19009 | // Label 919: @47689 |
| 19010 | GIM_Try, /*On fail goto*//*Label 920*/ 47723, // Rule ID 5043 // |
| 19011 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19012 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 19013 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19014 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19015 | // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v1i64] }:$src |
| 19016 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19017 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19018 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19019 | GIR_EraseFromParent, /*InsnID*/0, |
| 19020 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19021 | // GIR_Coverage, 5043, |
| 19022 | GIR_Done, |
| 19023 | // Label 920: @47723 |
| 19024 | GIM_Try, /*On fail goto*//*Label 921*/ 47757, // Rule ID 5044 // |
| 19025 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19026 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 19027 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19028 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19029 | // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v1i64] }:$src |
| 19030 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19031 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19032 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19033 | GIR_EraseFromParent, /*InsnID*/0, |
| 19034 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19035 | // GIR_Coverage, 5044, |
| 19036 | GIR_Done, |
| 19037 | // Label 921: @47757 |
| 19038 | GIM_Try, /*On fail goto*//*Label 922*/ 47791, // Rule ID 5045 // |
| 19039 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19040 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 19041 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19042 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19043 | // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v1i64] }:$src |
| 19044 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19045 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19046 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19047 | GIR_EraseFromParent, /*InsnID*/0, |
| 19048 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19049 | // GIR_Coverage, 5045, |
| 19050 | GIR_Done, |
| 19051 | // Label 922: @47791 |
| 19052 | GIM_Try, /*On fail goto*//*Label 923*/ 47825, // Rule ID 5046 // |
| 19053 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19054 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 19055 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19056 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19057 | // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v1i64] }:$src |
| 19058 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19059 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19060 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19061 | GIR_EraseFromParent, /*InsnID*/0, |
| 19062 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19063 | // GIR_Coverage, 5046, |
| 19064 | GIR_Done, |
| 19065 | // Label 923: @47825 |
| 19066 | GIM_Try, /*On fail goto*//*Label 924*/ 47859, // Rule ID 5047 // |
| 19067 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19068 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 19069 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19070 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19071 | // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4bf16] }:$src) => FPR64:{ *:[v1i64] }:$src |
| 19072 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19073 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19074 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19075 | GIR_EraseFromParent, /*InsnID*/0, |
| 19076 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19077 | // GIR_Coverage, 5047, |
| 19078 | GIR_Done, |
| 19079 | // Label 924: @47859 |
| 19080 | GIM_Try, /*On fail goto*//*Label 925*/ 47893, // Rule ID 5048 // |
| 19081 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19082 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 19083 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19084 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19085 | // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v1i64] }:$src |
| 19086 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19087 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19088 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19089 | GIR_EraseFromParent, /*InsnID*/0, |
| 19090 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19091 | // GIR_Coverage, 5048, |
| 19092 | GIR_Done, |
| 19093 | // Label 925: @47893 |
| 19094 | GIM_Try, /*On fail goto*//*Label 926*/ 47916, // Rule ID 5049 // |
| 19095 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19096 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 19097 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19098 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19099 | // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2i32] }:$src) => (REV64v2i32:{ *:[v1i64] } FPR64:{ *:[v2i32] }:$src) |
| 19100 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, |
| 19101 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19102 | // GIR_Coverage, 5049, |
| 19103 | GIR_Done, |
| 19104 | // Label 926: @47916 |
| 19105 | GIM_Try, /*On fail goto*//*Label 927*/ 47939, // Rule ID 5050 // |
| 19106 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19107 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 19108 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19109 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19110 | // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4i16] }:$src) => (REV64v4i16:{ *:[v1i64] } FPR64:{ *:[v4i16] }:$src) |
| 19111 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 19112 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19113 | // GIR_Coverage, 5050, |
| 19114 | GIR_Done, |
| 19115 | // Label 927: @47939 |
| 19116 | GIM_Try, /*On fail goto*//*Label 928*/ 47962, // Rule ID 5051 // |
| 19117 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19118 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 19119 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19120 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19121 | // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v8i8] }:$src) => (REV64v8i8:{ *:[v1i64] } FPR64:{ *:[v8i8] }:$src) |
| 19122 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i8, |
| 19123 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19124 | // GIR_Coverage, 5051, |
| 19125 | GIR_Done, |
| 19126 | // Label 928: @47962 |
| 19127 | GIM_Try, /*On fail goto*//*Label 929*/ 47985, // Rule ID 5052 // |
| 19128 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19129 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 19130 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19131 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19132 | // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4f16] }:$src) => (REV64v4i16:{ *:[v1i64] } FPR64:{ *:[v4f16] }:$src) |
| 19133 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 19134 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19135 | // GIR_Coverage, 5052, |
| 19136 | GIR_Done, |
| 19137 | // Label 929: @47985 |
| 19138 | GIM_Try, /*On fail goto*//*Label 930*/ 48008, // Rule ID 5053 // |
| 19139 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19140 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 19141 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19142 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19143 | // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4bf16] }:$src) => (REV64v4i16:{ *:[v1i64] } FPR64:{ *:[v4bf16] }:$src) |
| 19144 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 19145 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19146 | // GIR_Coverage, 5053, |
| 19147 | GIR_Done, |
| 19148 | // Label 930: @48008 |
| 19149 | GIM_Try, /*On fail goto*//*Label 931*/ 48031, // Rule ID 5054 // |
| 19150 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19151 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 19152 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19153 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19154 | // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2f32] }:$src) => (REV64v2i32:{ *:[v1i64] } FPR64:{ *:[v2f32] }:$src) |
| 19155 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, |
| 19156 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19157 | // GIR_Coverage, 5054, |
| 19158 | GIR_Done, |
| 19159 | // Label 931: @48031 |
| 19160 | GIM_Try, /*On fail goto*//*Label 932*/ 48063, // Rule ID 5055 // |
| 19161 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 19162 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19163 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19164 | // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v1i64] }:$src |
| 19165 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19166 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19167 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19168 | GIR_EraseFromParent, /*InsnID*/0, |
| 19169 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19170 | // GIR_Coverage, 5055, |
| 19171 | GIR_Done, |
| 19172 | // Label 932: @48063 |
| 19173 | GIM_Try, /*On fail goto*//*Label 933*/ 48095, // Rule ID 5056 // |
| 19174 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 19175 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19176 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19177 | // (bitconvert:{ *:[v1i64] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v1i64] }:$src |
| 19178 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19179 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19180 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19181 | GIR_EraseFromParent, /*InsnID*/0, |
| 19182 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19183 | // GIR_Coverage, 5056, |
| 19184 | GIR_Done, |
| 19185 | // Label 933: @48095 |
| 19186 | GIM_Try, /*On fail goto*//*Label 934*/ 48129, // Rule ID 5128 // |
| 19187 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19188 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 19189 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19190 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19191 | // (bitconvert:{ *:[f64] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[f64] }:$src |
| 19192 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19193 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19194 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19195 | GIR_EraseFromParent, /*InsnID*/0, |
| 19196 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19197 | // GIR_Coverage, 5128, |
| 19198 | GIR_Done, |
| 19199 | // Label 934: @48129 |
| 19200 | GIM_Try, /*On fail goto*//*Label 935*/ 48163, // Rule ID 5129 // |
| 19201 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19202 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 19203 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19204 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19205 | // (bitconvert:{ *:[f64] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[f64] }:$src |
| 19206 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19207 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19208 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19209 | GIR_EraseFromParent, /*InsnID*/0, |
| 19210 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19211 | // GIR_Coverage, 5129, |
| 19212 | GIR_Done, |
| 19213 | // Label 935: @48163 |
| 19214 | GIM_Try, /*On fail goto*//*Label 936*/ 48197, // Rule ID 5130 // |
| 19215 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19216 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 19217 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19218 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19219 | // (bitconvert:{ *:[f64] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[f64] }:$src |
| 19220 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19221 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19222 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19223 | GIR_EraseFromParent, /*InsnID*/0, |
| 19224 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19225 | // GIR_Coverage, 5130, |
| 19226 | GIR_Done, |
| 19227 | // Label 936: @48197 |
| 19228 | GIM_Try, /*On fail goto*//*Label 937*/ 48231, // Rule ID 5131 // |
| 19229 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19230 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 19231 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19232 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19233 | // (bitconvert:{ *:[f64] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[f64] }:$src |
| 19234 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19235 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19236 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19237 | GIR_EraseFromParent, /*InsnID*/0, |
| 19238 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19239 | // GIR_Coverage, 5131, |
| 19240 | GIR_Done, |
| 19241 | // Label 937: @48231 |
| 19242 | GIM_Try, /*On fail goto*//*Label 938*/ 48265, // Rule ID 5132 // |
| 19243 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19244 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 19245 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19246 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19247 | // (bitconvert:{ *:[f64] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[f64] }:$src |
| 19248 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19249 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19250 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19251 | GIR_EraseFromParent, /*InsnID*/0, |
| 19252 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19253 | // GIR_Coverage, 5132, |
| 19254 | GIR_Done, |
| 19255 | // Label 938: @48265 |
| 19256 | GIM_Try, /*On fail goto*//*Label 939*/ 48299, // Rule ID 5133 // |
| 19257 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19258 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 19259 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19260 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19261 | // (bitconvert:{ *:[f64] } FPR64:{ *:[v4bf16] }:$src) => FPR64:{ *:[f64] }:$src |
| 19262 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19263 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19264 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19265 | GIR_EraseFromParent, /*InsnID*/0, |
| 19266 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19267 | // GIR_Coverage, 5133, |
| 19268 | GIR_Done, |
| 19269 | // Label 939: @48299 |
| 19270 | GIM_Try, /*On fail goto*//*Label 940*/ 48322, // Rule ID 5134 // |
| 19271 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19272 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 19273 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19274 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19275 | // (bitconvert:{ *:[f64] } FPR64:{ *:[v2i32] }:$src) => (REV64v2i32:{ *:[f64] } FPR64:{ *:[v2i32] }:$src) |
| 19276 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, |
| 19277 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19278 | // GIR_Coverage, 5134, |
| 19279 | GIR_Done, |
| 19280 | // Label 940: @48322 |
| 19281 | GIM_Try, /*On fail goto*//*Label 941*/ 48345, // Rule ID 5135 // |
| 19282 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19283 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 19284 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19285 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19286 | // (bitconvert:{ *:[f64] } FPR64:{ *:[v4i16] }:$src) => (REV64v4i16:{ *:[f64] } FPR64:{ *:[v4i16] }:$src) |
| 19287 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 19288 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19289 | // GIR_Coverage, 5135, |
| 19290 | GIR_Done, |
| 19291 | // Label 941: @48345 |
| 19292 | GIM_Try, /*On fail goto*//*Label 942*/ 48368, // Rule ID 5136 // |
| 19293 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19294 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 19295 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19296 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19297 | // (bitconvert:{ *:[f64] } FPR64:{ *:[v2f32] }:$src) => (REV64v2i32:{ *:[f64] } FPR64:{ *:[v2f32] }:$src) |
| 19298 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, |
| 19299 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19300 | // GIR_Coverage, 5136, |
| 19301 | GIR_Done, |
| 19302 | // Label 942: @48368 |
| 19303 | GIM_Try, /*On fail goto*//*Label 943*/ 48391, // Rule ID 5137 // |
| 19304 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19305 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 19306 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19307 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19308 | // (bitconvert:{ *:[f64] } FPR64:{ *:[v8i8] }:$src) => (REV64v8i8:{ *:[f64] } FPR64:{ *:[v8i8] }:$src) |
| 19309 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i8, |
| 19310 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19311 | // GIR_Coverage, 5137, |
| 19312 | GIR_Done, |
| 19313 | // Label 943: @48391 |
| 19314 | GIM_Try, /*On fail goto*//*Label 944*/ 48414, // Rule ID 5138 // |
| 19315 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19316 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 19317 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19318 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19319 | // (bitconvert:{ *:[f64] } FPR64:{ *:[v4f16] }:$src) => (REV64v4i16:{ *:[f64] } FPR64:{ *:[v4f16] }:$src) |
| 19320 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 19321 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19322 | // GIR_Coverage, 5138, |
| 19323 | GIR_Done, |
| 19324 | // Label 944: @48414 |
| 19325 | GIM_Try, /*On fail goto*//*Label 945*/ 48437, // Rule ID 5139 // |
| 19326 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19327 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 19328 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19329 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19330 | // (bitconvert:{ *:[f64] } FPR64:{ *:[v4bf16] }:$src) => (REV64v4i16:{ *:[f64] } FPR64:{ *:[v4bf16] }:$src) |
| 19331 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 19332 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19333 | // GIR_Coverage, 5139, |
| 19334 | GIR_Done, |
| 19335 | // Label 945: @48437 |
| 19336 | GIM_Try, /*On fail goto*//*Label 946*/ 48469, // Rule ID 5140 // |
| 19337 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 19338 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19339 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19340 | // (bitconvert:{ *:[f64] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[f64] }:$src |
| 19341 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19342 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19343 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19344 | GIR_EraseFromParent, /*InsnID*/0, |
| 19345 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19346 | // GIR_Coverage, 5140, |
| 19347 | GIR_Done, |
| 19348 | // Label 946: @48469 |
| 19349 | GIM_Try, /*On fail goto*//*Label 947*/ 48501, // Rule ID 5141 // |
| 19350 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 19351 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19352 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19353 | // (bitconvert:{ *:[f64] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[f64] }:$src |
| 19354 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19355 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19356 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19357 | GIR_EraseFromParent, /*InsnID*/0, |
| 19358 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19359 | // GIR_Coverage, 5141, |
| 19360 | GIR_Done, |
| 19361 | // Label 947: @48501 |
| 19362 | GIM_Try, /*On fail goto*//*Label 948*/ 48535, // Rule ID 5142 // |
| 19363 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19364 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 19365 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19366 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19367 | // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v1f64] }:$src |
| 19368 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19369 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19370 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19371 | GIR_EraseFromParent, /*InsnID*/0, |
| 19372 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19373 | // GIR_Coverage, 5142, |
| 19374 | GIR_Done, |
| 19375 | // Label 948: @48535 |
| 19376 | GIM_Try, /*On fail goto*//*Label 949*/ 48569, // Rule ID 5143 // |
| 19377 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19378 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 19379 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19380 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19381 | // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v1f64] }:$src |
| 19382 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19383 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19384 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19385 | GIR_EraseFromParent, /*InsnID*/0, |
| 19386 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19387 | // GIR_Coverage, 5143, |
| 19388 | GIR_Done, |
| 19389 | // Label 949: @48569 |
| 19390 | GIM_Try, /*On fail goto*//*Label 950*/ 48603, // Rule ID 5144 // |
| 19391 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19392 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 19393 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19394 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19395 | // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v1f64] }:$src |
| 19396 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19397 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19398 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19399 | GIR_EraseFromParent, /*InsnID*/0, |
| 19400 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19401 | // GIR_Coverage, 5144, |
| 19402 | GIR_Done, |
| 19403 | // Label 950: @48603 |
| 19404 | GIM_Try, /*On fail goto*//*Label 951*/ 48637, // Rule ID 5145 // |
| 19405 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19406 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 19407 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19408 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19409 | // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v1f64] }:$src |
| 19410 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19411 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19412 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19413 | GIR_EraseFromParent, /*InsnID*/0, |
| 19414 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19415 | // GIR_Coverage, 5145, |
| 19416 | GIR_Done, |
| 19417 | // Label 951: @48637 |
| 19418 | GIM_Try, /*On fail goto*//*Label 952*/ 48671, // Rule ID 5146 // |
| 19419 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19420 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 19421 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19422 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19423 | // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v1f64] }:$src |
| 19424 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19425 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19426 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19427 | GIR_EraseFromParent, /*InsnID*/0, |
| 19428 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19429 | // GIR_Coverage, 5146, |
| 19430 | GIR_Done, |
| 19431 | // Label 952: @48671 |
| 19432 | GIM_Try, /*On fail goto*//*Label 953*/ 48705, // Rule ID 5147 // |
| 19433 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19434 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 19435 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19436 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19437 | // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4bf16] }:$src) => FPR64:{ *:[v1f64] }:$src |
| 19438 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19439 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19440 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19441 | GIR_EraseFromParent, /*InsnID*/0, |
| 19442 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19443 | // GIR_Coverage, 5147, |
| 19444 | GIR_Done, |
| 19445 | // Label 953: @48705 |
| 19446 | GIM_Try, /*On fail goto*//*Label 954*/ 48728, // Rule ID 5148 // |
| 19447 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19448 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 19449 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19450 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19451 | // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2i32] }:$src) => (REV64v2i32:{ *:[v1f64] } FPR64:{ *:[v2i32] }:$src) |
| 19452 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, |
| 19453 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19454 | // GIR_Coverage, 5148, |
| 19455 | GIR_Done, |
| 19456 | // Label 954: @48728 |
| 19457 | GIM_Try, /*On fail goto*//*Label 955*/ 48751, // Rule ID 5149 // |
| 19458 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19459 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 19460 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19461 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19462 | // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4i16] }:$src) => (REV64v4i16:{ *:[v1f64] } FPR64:{ *:[v4i16] }:$src) |
| 19463 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 19464 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19465 | // GIR_Coverage, 5149, |
| 19466 | GIR_Done, |
| 19467 | // Label 955: @48751 |
| 19468 | GIM_Try, /*On fail goto*//*Label 956*/ 48774, // Rule ID 5150 // |
| 19469 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19470 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 19471 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19472 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19473 | // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v8i8] }:$src) => (REV64v8i8:{ *:[v1f64] } FPR64:{ *:[v8i8] }:$src) |
| 19474 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i8, |
| 19475 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19476 | // GIR_Coverage, 5150, |
| 19477 | GIR_Done, |
| 19478 | // Label 956: @48774 |
| 19479 | GIM_Try, /*On fail goto*//*Label 957*/ 48797, // Rule ID 5151 // |
| 19480 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19481 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 19482 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19483 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19484 | // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2f32] }:$src) => (REV64v2i32:{ *:[v1f64] } FPR64:{ *:[v2f32] }:$src) |
| 19485 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, |
| 19486 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19487 | // GIR_Coverage, 5151, |
| 19488 | GIR_Done, |
| 19489 | // Label 957: @48797 |
| 19490 | GIM_Try, /*On fail goto*//*Label 958*/ 48820, // Rule ID 5152 // |
| 19491 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19492 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 19493 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19494 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19495 | // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4f16] }:$src) => (REV64v4i16:{ *:[v1f64] } FPR64:{ *:[v4f16] }:$src) |
| 19496 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 19497 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19498 | // GIR_Coverage, 5152, |
| 19499 | GIR_Done, |
| 19500 | // Label 958: @48820 |
| 19501 | GIM_Try, /*On fail goto*//*Label 959*/ 48843, // Rule ID 5153 // |
| 19502 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19503 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 19504 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19505 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19506 | // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4bf16] }:$src) => (REV64v4i16:{ *:[v1f64] } FPR64:{ *:[v4bf16] }:$src) |
| 19507 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 19508 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19509 | // GIR_Coverage, 5153, |
| 19510 | GIR_Done, |
| 19511 | // Label 959: @48843 |
| 19512 | GIM_Try, /*On fail goto*//*Label 960*/ 48875, // Rule ID 5154 // |
| 19513 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 19514 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19515 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19516 | // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v1f64] }:$src |
| 19517 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19518 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19519 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19520 | GIR_EraseFromParent, /*InsnID*/0, |
| 19521 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19522 | // GIR_Coverage, 5154, |
| 19523 | GIR_Done, |
| 19524 | // Label 960: @48875 |
| 19525 | GIM_Try, /*On fail goto*//*Label 961*/ 48907, // Rule ID 5155 // |
| 19526 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 19527 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19528 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19529 | // (bitconvert:{ *:[v1f64] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v1f64] }:$src |
| 19530 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19531 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19532 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19533 | GIR_EraseFromParent, /*InsnID*/0, |
| 19534 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19535 | // GIR_Coverage, 5155, |
| 19536 | GIR_Done, |
| 19537 | // Label 961: @48907 |
| 19538 | GIM_Reject, |
| 19539 | // Label 889: @48908 |
| 19540 | GIM_Try, /*On fail goto*//*Label 962*/ 48942, // Rule ID 5171 // |
| 19541 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19542 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 19543 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 19544 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 19545 | // (bitconvert:{ *:[f128] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[f128] }:$src |
| 19546 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19547 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19548 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19549 | GIR_EraseFromParent, /*InsnID*/0, |
| 19550 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 19551 | // GIR_Coverage, 5171, |
| 19552 | GIR_Done, |
| 19553 | // Label 962: @48942 |
| 19554 | GIM_Try, /*On fail goto*//*Label 963*/ 48976, // Rule ID 5172 // |
| 19555 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19556 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 19557 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 19558 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 19559 | // (bitconvert:{ *:[f128] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[f128] }:$src |
| 19560 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19561 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19562 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19563 | GIR_EraseFromParent, /*InsnID*/0, |
| 19564 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 19565 | // GIR_Coverage, 5172, |
| 19566 | GIR_Done, |
| 19567 | // Label 963: @48976 |
| 19568 | GIM_Try, /*On fail goto*//*Label 964*/ 49010, // Rule ID 5173 // |
| 19569 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19570 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 19571 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 19572 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 19573 | // (bitconvert:{ *:[f128] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[f128] }:$src |
| 19574 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19575 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19576 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19577 | GIR_EraseFromParent, /*InsnID*/0, |
| 19578 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 19579 | // GIR_Coverage, 5173, |
| 19580 | GIR_Done, |
| 19581 | // Label 964: @49010 |
| 19582 | GIM_Try, /*On fail goto*//*Label 965*/ 49044, // Rule ID 5174 // |
| 19583 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19584 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 19585 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 19586 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 19587 | // (bitconvert:{ *:[f128] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[f128] }:$src |
| 19588 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19589 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19590 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19591 | GIR_EraseFromParent, /*InsnID*/0, |
| 19592 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 19593 | // GIR_Coverage, 5174, |
| 19594 | GIR_Done, |
| 19595 | // Label 965: @49044 |
| 19596 | GIM_Try, /*On fail goto*//*Label 966*/ 49078, // Rule ID 5175 // |
| 19597 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19598 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 19599 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 19600 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 19601 | // (bitconvert:{ *:[f128] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[f128] }:$src |
| 19602 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19603 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19604 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19605 | GIR_EraseFromParent, /*InsnID*/0, |
| 19606 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 19607 | // GIR_Coverage, 5175, |
| 19608 | GIR_Done, |
| 19609 | // Label 966: @49078 |
| 19610 | GIM_Try, /*On fail goto*//*Label 967*/ 49112, // Rule ID 5176 // |
| 19611 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19612 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 19613 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 19614 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 19615 | // (bitconvert:{ *:[f128] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[f128] }:$src |
| 19616 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19617 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19618 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19619 | GIR_EraseFromParent, /*InsnID*/0, |
| 19620 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 19621 | // GIR_Coverage, 5176, |
| 19622 | GIR_Done, |
| 19623 | // Label 967: @49112 |
| 19624 | GIM_Try, /*On fail goto*//*Label 968*/ 49146, // Rule ID 5177 // |
| 19625 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19626 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 19627 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 19628 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 19629 | // (bitconvert:{ *:[f128] } FPR128:{ *:[v8bf16] }:$src) => FPR128:{ *:[f128] }:$src |
| 19630 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19631 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19632 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19633 | GIR_EraseFromParent, /*InsnID*/0, |
| 19634 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 19635 | // GIR_Coverage, 5177, |
| 19636 | GIR_Done, |
| 19637 | // Label 968: @49146 |
| 19638 | GIM_Try, /*On fail goto*//*Label 969*/ 49180, // Rule ID 5178 // |
| 19639 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19640 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 19641 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 19642 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 19643 | // (bitconvert:{ *:[f128] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[f128] }:$src |
| 19644 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19645 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19646 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19647 | GIR_EraseFromParent, /*InsnID*/0, |
| 19648 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 19649 | // GIR_Coverage, 5178, |
| 19650 | GIR_Done, |
| 19651 | // Label 969: @49180 |
| 19652 | GIM_Try, /*On fail goto*//*Label 970*/ 49219, // Rule ID 5179 // |
| 19653 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19654 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 19655 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 19656 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 19657 | // (bitconvert:{ *:[f128] } FPR128:{ *:[v2i64] }:$src) => (EXTv16i8:{ *:[f128] } FPR128:{ *:[v2i64] }:$src, FPR128:{ *:[v2i64] }:$src, 8:{ *:[i32] }) |
| 19658 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, |
| 19659 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 19660 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19661 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19662 | GIR_AddImm, /*InsnID*/0, /*Imm*/8, |
| 19663 | GIR_EraseFromParent, /*InsnID*/0, |
| 19664 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19665 | // GIR_Coverage, 5179, |
| 19666 | GIR_Done, |
| 19667 | // Label 970: @49219 |
| 19668 | GIM_Try, /*On fail goto*//*Label 971*/ 49290, // Rule ID 5180 // |
| 19669 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19670 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 19671 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 19672 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 19673 | // (bitconvert:{ *:[f128] } FPR128:{ *:[v4i32] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4i32] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4i32] }:$src), 8:{ *:[i32] }) |
| 19674 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 19675 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 19676 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v4i32, |
| 19677 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 19678 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19679 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 19680 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v4i32, |
| 19681 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 19682 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19683 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19684 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, |
| 19685 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 19686 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 19687 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 19688 | GIR_AddImm, /*InsnID*/0, /*Imm*/8, |
| 19689 | GIR_EraseFromParent, /*InsnID*/0, |
| 19690 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19691 | // GIR_Coverage, 5180, |
| 19692 | GIR_Done, |
| 19693 | // Label 971: @49290 |
| 19694 | GIM_Try, /*On fail goto*//*Label 972*/ 49361, // Rule ID 5181 // |
| 19695 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19696 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 19697 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 19698 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 19699 | // (bitconvert:{ *:[f128] } FPR128:{ *:[v8i16] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8i16] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8i16] }:$src), 8:{ *:[i32] }) |
| 19700 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 19701 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 19702 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v8i16, |
| 19703 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 19704 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19705 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 19706 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v8i16, |
| 19707 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 19708 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19709 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19710 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, |
| 19711 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 19712 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 19713 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 19714 | GIR_AddImm, /*InsnID*/0, /*Imm*/8, |
| 19715 | GIR_EraseFromParent, /*InsnID*/0, |
| 19716 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19717 | // GIR_Coverage, 5181, |
| 19718 | GIR_Done, |
| 19719 | // Label 972: @49361 |
| 19720 | GIM_Try, /*On fail goto*//*Label 973*/ 49432, // Rule ID 5182 // |
| 19721 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19722 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 19723 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 19724 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 19725 | // (bitconvert:{ *:[f128] } FPR128:{ *:[v8f16] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8f16] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8f16] }:$src), 8:{ *:[i32] }) |
| 19726 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 19727 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 19728 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v8i16, |
| 19729 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 19730 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19731 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 19732 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v8i16, |
| 19733 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 19734 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19735 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19736 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, |
| 19737 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 19738 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 19739 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 19740 | GIR_AddImm, /*InsnID*/0, /*Imm*/8, |
| 19741 | GIR_EraseFromParent, /*InsnID*/0, |
| 19742 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19743 | // GIR_Coverage, 5182, |
| 19744 | GIR_Done, |
| 19745 | // Label 973: @49432 |
| 19746 | GIM_Try, /*On fail goto*//*Label 974*/ 49503, // Rule ID 5183 // |
| 19747 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19748 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 19749 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 19750 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 19751 | // (bitconvert:{ *:[f128] } FPR128:{ *:[v8bf16] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8bf16] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8bf16] }:$src), 8:{ *:[i32] }) |
| 19752 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 19753 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 19754 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v8i16, |
| 19755 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 19756 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19757 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 19758 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v8i16, |
| 19759 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 19760 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19761 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19762 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, |
| 19763 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 19764 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 19765 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 19766 | GIR_AddImm, /*InsnID*/0, /*Imm*/8, |
| 19767 | GIR_EraseFromParent, /*InsnID*/0, |
| 19768 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19769 | // GIR_Coverage, 5183, |
| 19770 | GIR_Done, |
| 19771 | // Label 974: @49503 |
| 19772 | GIM_Try, /*On fail goto*//*Label 975*/ 49542, // Rule ID 5184 // |
| 19773 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19774 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 19775 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 19776 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 19777 | // (bitconvert:{ *:[f128] } FPR128:{ *:[v2f64] }:$src) => (EXTv16i8:{ *:[f128] } FPR128:{ *:[v2f64] }:$src, FPR128:{ *:[v2f64] }:$src, 8:{ *:[i32] }) |
| 19778 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, |
| 19779 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 19780 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19781 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19782 | GIR_AddImm, /*InsnID*/0, /*Imm*/8, |
| 19783 | GIR_EraseFromParent, /*InsnID*/0, |
| 19784 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19785 | // GIR_Coverage, 5184, |
| 19786 | GIR_Done, |
| 19787 | // Label 975: @49542 |
| 19788 | GIM_Try, /*On fail goto*//*Label 976*/ 49613, // Rule ID 5185 // |
| 19789 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19790 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 19791 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 19792 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 19793 | // (bitconvert:{ *:[f128] } FPR128:{ *:[v4f32] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4f32] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4f32] }:$src), 8:{ *:[i32] }) |
| 19794 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 19795 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 19796 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v4i32, |
| 19797 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 19798 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19799 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 19800 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v4i32, |
| 19801 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 19802 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19803 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19804 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, |
| 19805 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 19806 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 19807 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 19808 | GIR_AddImm, /*InsnID*/0, /*Imm*/8, |
| 19809 | GIR_EraseFromParent, /*InsnID*/0, |
| 19810 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19811 | // GIR_Coverage, 5185, |
| 19812 | GIR_Done, |
| 19813 | // Label 976: @49613 |
| 19814 | GIM_Try, /*On fail goto*//*Label 977*/ 49684, // Rule ID 5186 // |
| 19815 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19816 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 19817 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 19818 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 19819 | // (bitconvert:{ *:[f128] } FPR128:{ *:[v16i8] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v16i8:{ *:[f128] } FPR128:{ *:[v16i8] }:$src), (REV64v16i8:{ *:[f128] } FPR128:{ *:[v16i8] }:$src), 8:{ *:[i32] }) |
| 19820 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 19821 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 19822 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v16i8, |
| 19823 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 19824 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19825 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 19826 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v16i8, |
| 19827 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 19828 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19829 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19830 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, |
| 19831 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 19832 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 19833 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 19834 | GIR_AddImm, /*InsnID*/0, /*Imm*/8, |
| 19835 | GIR_EraseFromParent, /*InsnID*/0, |
| 19836 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19837 | // GIR_Coverage, 5186, |
| 19838 | GIR_Done, |
| 19839 | // Label 977: @49684 |
| 19840 | GIM_Reject, |
| 19841 | // Label 890: @49685 |
| 19842 | GIM_Try, /*On fail goto*//*Label 978*/ 49710, // Rule ID 5009 // |
| 19843 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19844 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 19845 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19846 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 19847 | // (bitconvert:{ *:[v2i32] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v2i32] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) |
| 19848 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19849 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19850 | // GIR_Coverage, 5009, |
| 19851 | GIR_Done, |
| 19852 | // Label 978: @49710 |
| 19853 | GIM_Try, /*On fail goto*//*Label 979*/ 49735, // Rule ID 5012 // |
| 19854 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19855 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 19856 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19857 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 19858 | // (bitconvert:{ *:[v2f32] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v2f32] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) |
| 19859 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19860 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19861 | // GIR_Coverage, 5012, |
| 19862 | GIR_Done, |
| 19863 | // Label 979: @49735 |
| 19864 | GIM_Try, /*On fail goto*//*Label 980*/ 49783, // Rule ID 5022 // |
| 19865 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19866 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 19867 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19868 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 19869 | // (bitconvert:{ *:[v2i32] } GPR64:{ *:[i64] }:$Xn) => (REV64v2i32:{ *:[v2i32] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })) |
| 19870 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 19871 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 19872 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 19873 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn |
| 19874 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19875 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v2i32, |
| 19876 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 19877 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 19878 | GIR_EraseFromParent, /*InsnID*/0, |
| 19879 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19880 | // GIR_Coverage, 5022, |
| 19881 | GIR_Done, |
| 19882 | // Label 980: @49783 |
| 19883 | GIM_Try, /*On fail goto*//*Label 981*/ 49831, // Rule ID 5025 // |
| 19884 | GIM_CheckFeatures, GIFBS_IsBE, |
| 19885 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 19886 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19887 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 19888 | // (bitconvert:{ *:[v2f32] } GPR64:{ *:[i64] }:$Xn) => (REV64v2i32:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })) |
| 19889 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 19890 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 19891 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 19892 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn |
| 19893 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19894 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v2i32, |
| 19895 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 19896 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 19897 | GIR_EraseFromParent, /*InsnID*/0, |
| 19898 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19899 | // GIR_Coverage, 5025, |
| 19900 | GIR_Done, |
| 19901 | // Label 981: @49831 |
| 19902 | GIM_Try, /*On fail goto*//*Label 982*/ 49865, // Rule ID 5057 // |
| 19903 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19904 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 19905 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19906 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19907 | // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v2i32] }:$src |
| 19908 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19909 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19910 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19911 | GIR_EraseFromParent, /*InsnID*/0, |
| 19912 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19913 | // GIR_Coverage, 5057, |
| 19914 | GIR_Done, |
| 19915 | // Label 982: @49865 |
| 19916 | GIM_Try, /*On fail goto*//*Label 983*/ 49899, // Rule ID 5058 // |
| 19917 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19918 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 19919 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19920 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19921 | // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v2i32] }:$src |
| 19922 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19923 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19924 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19925 | GIR_EraseFromParent, /*InsnID*/0, |
| 19926 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19927 | // GIR_Coverage, 5058, |
| 19928 | GIR_Done, |
| 19929 | // Label 983: @49899 |
| 19930 | GIM_Try, /*On fail goto*//*Label 984*/ 49933, // Rule ID 5059 // |
| 19931 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19932 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 19933 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19934 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19935 | // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v2i32] }:$src |
| 19936 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19937 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19938 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19939 | GIR_EraseFromParent, /*InsnID*/0, |
| 19940 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19941 | // GIR_Coverage, 5059, |
| 19942 | GIR_Done, |
| 19943 | // Label 984: @49933 |
| 19944 | GIM_Try, /*On fail goto*//*Label 985*/ 49967, // Rule ID 5060 // |
| 19945 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19946 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 19947 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19948 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19949 | // (bitconvert:{ *:[v2i32] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v2i32] }:$src |
| 19950 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19951 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19952 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19953 | GIR_EraseFromParent, /*InsnID*/0, |
| 19954 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19955 | // GIR_Coverage, 5060, |
| 19956 | GIR_Done, |
| 19957 | // Label 985: @49967 |
| 19958 | GIM_Try, /*On fail goto*//*Label 986*/ 50001, // Rule ID 5061 // |
| 19959 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19960 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 19961 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19962 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19963 | // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v2i32] }:$src |
| 19964 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19965 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19966 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19967 | GIR_EraseFromParent, /*InsnID*/0, |
| 19968 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19969 | // GIR_Coverage, 5061, |
| 19970 | GIR_Done, |
| 19971 | // Label 986: @50001 |
| 19972 | GIM_Try, /*On fail goto*//*Label 987*/ 50035, // Rule ID 5062 // |
| 19973 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19974 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 19975 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19976 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19977 | // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v2i32] }:$src |
| 19978 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19979 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19980 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19981 | GIR_EraseFromParent, /*InsnID*/0, |
| 19982 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19983 | // GIR_Coverage, 5062, |
| 19984 | GIR_Done, |
| 19985 | // Label 987: @50035 |
| 19986 | GIM_Try, /*On fail goto*//*Label 988*/ 50069, // Rule ID 5063 // |
| 19987 | GIM_CheckFeatures, GIFBS_IsLE, |
| 19988 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 19989 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 19990 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 19991 | // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4bf16] }:$src) => FPR64:{ *:[v2i32] }:$src |
| 19992 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 19993 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 19994 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 19995 | GIR_EraseFromParent, /*InsnID*/0, |
| 19996 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 19997 | // GIR_Coverage, 5063, |
| 19998 | GIR_Done, |
| 19999 | // Label 988: @50069 |
| 20000 | GIM_Try, /*On fail goto*//*Label 989*/ 50092, // Rule ID 5064 // |
| 20001 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20002 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 20003 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20004 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20005 | // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1i64] }:$src) => (REV64v2i32:{ *:[v2i32] } FPR64:{ *:[v1i64] }:$src) |
| 20006 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, |
| 20007 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20008 | // GIR_Coverage, 5064, |
| 20009 | GIR_Done, |
| 20010 | // Label 989: @50092 |
| 20011 | GIM_Try, /*On fail goto*//*Label 990*/ 50115, // Rule ID 5065 // |
| 20012 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20013 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 20014 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20015 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20016 | // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4i16] }:$src) => (REV32v4i16:{ *:[v2i32] } FPR64:{ *:[v4i16] }:$src) |
| 20017 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, |
| 20018 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20019 | // GIR_Coverage, 5065, |
| 20020 | GIR_Done, |
| 20021 | // Label 990: @50115 |
| 20022 | GIM_Try, /*On fail goto*//*Label 991*/ 50138, // Rule ID 5066 // |
| 20023 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20024 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 20025 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20026 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20027 | // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v8i8] }:$src) => (REV32v8i8:{ *:[v2i32] } FPR64:{ *:[v8i8] }:$src) |
| 20028 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i8, |
| 20029 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20030 | // GIR_Coverage, 5066, |
| 20031 | GIR_Done, |
| 20032 | // Label 991: @50138 |
| 20033 | GIM_Try, /*On fail goto*//*Label 992*/ 50161, // Rule ID 5067 // |
| 20034 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20035 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 20036 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20037 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20038 | // (bitconvert:{ *:[v2i32] } FPR64:{ *:[f64] }:$src) => (REV64v2i32:{ *:[v2i32] } FPR64:{ *:[f64] }:$src) |
| 20039 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, |
| 20040 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20041 | // GIR_Coverage, 5067, |
| 20042 | GIR_Done, |
| 20043 | // Label 992: @50161 |
| 20044 | GIM_Try, /*On fail goto*//*Label 993*/ 50184, // Rule ID 5068 // |
| 20045 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20046 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 20047 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20048 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20049 | // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1f64] }:$src) => (REV64v2i32:{ *:[v2i32] } FPR64:{ *:[v1f64] }:$src) |
| 20050 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, |
| 20051 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20052 | // GIR_Coverage, 5068, |
| 20053 | GIR_Done, |
| 20054 | // Label 993: @50184 |
| 20055 | GIM_Try, /*On fail goto*//*Label 994*/ 50207, // Rule ID 5069 // |
| 20056 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20057 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 20058 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20059 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20060 | // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4f16] }:$src) => (REV32v4i16:{ *:[v2i32] } FPR64:{ *:[v4f16] }:$src) |
| 20061 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, |
| 20062 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20063 | // GIR_Coverage, 5069, |
| 20064 | GIR_Done, |
| 20065 | // Label 994: @50207 |
| 20066 | GIM_Try, /*On fail goto*//*Label 995*/ 50230, // Rule ID 5070 // |
| 20067 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20068 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 20069 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20070 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20071 | // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4bf16] }:$src) => (REV32v4i16:{ *:[v2i32] } FPR64:{ *:[v4bf16] }:$src) |
| 20072 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, |
| 20073 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20074 | // GIR_Coverage, 5070, |
| 20075 | GIR_Done, |
| 20076 | // Label 995: @50230 |
| 20077 | GIM_Try, /*On fail goto*//*Label 996*/ 50262, // Rule ID 5071 // |
| 20078 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 20079 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20080 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20081 | // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v2i32] }:$src |
| 20082 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20083 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20084 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20085 | GIR_EraseFromParent, /*InsnID*/0, |
| 20086 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 20087 | // GIR_Coverage, 5071, |
| 20088 | GIR_Done, |
| 20089 | // Label 996: @50262 |
| 20090 | GIM_Try, /*On fail goto*//*Label 997*/ 50296, // Rule ID 5156 // |
| 20091 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20092 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 20093 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20094 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20095 | // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v2f32] }:$src |
| 20096 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20097 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20098 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20099 | GIR_EraseFromParent, /*InsnID*/0, |
| 20100 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 20101 | // GIR_Coverage, 5156, |
| 20102 | GIR_Done, |
| 20103 | // Label 997: @50296 |
| 20104 | GIM_Try, /*On fail goto*//*Label 998*/ 50330, // Rule ID 5157 // |
| 20105 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20106 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 20107 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20108 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20109 | // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v2f32] }:$src |
| 20110 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20111 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20112 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20113 | GIR_EraseFromParent, /*InsnID*/0, |
| 20114 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 20115 | // GIR_Coverage, 5157, |
| 20116 | GIR_Done, |
| 20117 | // Label 998: @50330 |
| 20118 | GIM_Try, /*On fail goto*//*Label 999*/ 50364, // Rule ID 5158 // |
| 20119 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20120 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 20121 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20122 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20123 | // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v2f32] }:$src |
| 20124 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20125 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20126 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20127 | GIR_EraseFromParent, /*InsnID*/0, |
| 20128 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 20129 | // GIR_Coverage, 5158, |
| 20130 | GIR_Done, |
| 20131 | // Label 999: @50364 |
| 20132 | GIM_Try, /*On fail goto*//*Label 1000*/ 50398, // Rule ID 5159 // |
| 20133 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20134 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 20135 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20136 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20137 | // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v2f32] }:$src |
| 20138 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20139 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20140 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20141 | GIR_EraseFromParent, /*InsnID*/0, |
| 20142 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 20143 | // GIR_Coverage, 5159, |
| 20144 | GIR_Done, |
| 20145 | // Label 1000: @50398 |
| 20146 | GIM_Try, /*On fail goto*//*Label 1001*/ 50432, // Rule ID 5160 // |
| 20147 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20148 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 20149 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20150 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20151 | // (bitconvert:{ *:[v2f32] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v2f32] }:$src |
| 20152 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20153 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20154 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20155 | GIR_EraseFromParent, /*InsnID*/0, |
| 20156 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 20157 | // GIR_Coverage, 5160, |
| 20158 | GIR_Done, |
| 20159 | // Label 1001: @50432 |
| 20160 | GIM_Try, /*On fail goto*//*Label 1002*/ 50466, // Rule ID 5161 // |
| 20161 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20162 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 20163 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20164 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20165 | // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v2f32] }:$src |
| 20166 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20167 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20168 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20169 | GIR_EraseFromParent, /*InsnID*/0, |
| 20170 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 20171 | // GIR_Coverage, 5161, |
| 20172 | GIR_Done, |
| 20173 | // Label 1002: @50466 |
| 20174 | GIM_Try, /*On fail goto*//*Label 1003*/ 50500, // Rule ID 5162 // |
| 20175 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20176 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 20177 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20178 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20179 | // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4bf16] }:$src) => FPR64:{ *:[v2f32] }:$src |
| 20180 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20181 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20182 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20183 | GIR_EraseFromParent, /*InsnID*/0, |
| 20184 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 20185 | // GIR_Coverage, 5162, |
| 20186 | GIR_Done, |
| 20187 | // Label 1003: @50500 |
| 20188 | GIM_Try, /*On fail goto*//*Label 1004*/ 50523, // Rule ID 5163 // |
| 20189 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20190 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 20191 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20192 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20193 | // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1i64] }:$src) => (REV64v2i32:{ *:[v2f32] } FPR64:{ *:[v1i64] }:$src) |
| 20194 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, |
| 20195 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20196 | // GIR_Coverage, 5163, |
| 20197 | GIR_Done, |
| 20198 | // Label 1004: @50523 |
| 20199 | GIM_Try, /*On fail goto*//*Label 1005*/ 50546, // Rule ID 5164 // |
| 20200 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20201 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 20202 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20203 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20204 | // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4i16] }:$src) => (REV32v4i16:{ *:[v2f32] } FPR64:{ *:[v4i16] }:$src) |
| 20205 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, |
| 20206 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20207 | // GIR_Coverage, 5164, |
| 20208 | GIR_Done, |
| 20209 | // Label 1005: @50546 |
| 20210 | GIM_Try, /*On fail goto*//*Label 1006*/ 50569, // Rule ID 5165 // |
| 20211 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20212 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 20213 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20214 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20215 | // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v8i8] }:$src) => (REV32v8i8:{ *:[v2f32] } FPR64:{ *:[v8i8] }:$src) |
| 20216 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i8, |
| 20217 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20218 | // GIR_Coverage, 5165, |
| 20219 | GIR_Done, |
| 20220 | // Label 1006: @50569 |
| 20221 | GIM_Try, /*On fail goto*//*Label 1007*/ 50592, // Rule ID 5166 // |
| 20222 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20223 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 20224 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20225 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20226 | // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1f64] }:$src) => (REV64v2i32:{ *:[v2f32] } FPR64:{ *:[v1f64] }:$src) |
| 20227 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, |
| 20228 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20229 | // GIR_Coverage, 5166, |
| 20230 | GIR_Done, |
| 20231 | // Label 1007: @50592 |
| 20232 | GIM_Try, /*On fail goto*//*Label 1008*/ 50615, // Rule ID 5167 // |
| 20233 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20234 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 20235 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20236 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20237 | // (bitconvert:{ *:[v2f32] } FPR64:{ *:[f64] }:$src) => (REV64v2i32:{ *:[v2f32] } FPR64:{ *:[f64] }:$src) |
| 20238 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, |
| 20239 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20240 | // GIR_Coverage, 5167, |
| 20241 | GIR_Done, |
| 20242 | // Label 1008: @50615 |
| 20243 | GIM_Try, /*On fail goto*//*Label 1009*/ 50638, // Rule ID 5168 // |
| 20244 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20245 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 20246 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20247 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20248 | // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4f16] }:$src) => (REV32v4i16:{ *:[v2f32] } FPR64:{ *:[v4f16] }:$src) |
| 20249 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, |
| 20250 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20251 | // GIR_Coverage, 5168, |
| 20252 | GIR_Done, |
| 20253 | // Label 1009: @50638 |
| 20254 | GIM_Try, /*On fail goto*//*Label 1010*/ 50661, // Rule ID 5169 // |
| 20255 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20256 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 20257 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20258 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20259 | // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4bf16] }:$src) => (REV32v4i16:{ *:[v2f32] } FPR64:{ *:[v4bf16] }:$src) |
| 20260 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, |
| 20261 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20262 | // GIR_Coverage, 5169, |
| 20263 | GIR_Done, |
| 20264 | // Label 1010: @50661 |
| 20265 | GIM_Try, /*On fail goto*//*Label 1011*/ 50693, // Rule ID 5170 // |
| 20266 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 20267 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20268 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20269 | // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v2f32] }:$src |
| 20270 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20271 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20272 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20273 | GIR_EraseFromParent, /*InsnID*/0, |
| 20274 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 20275 | // GIR_Coverage, 5170, |
| 20276 | GIR_Done, |
| 20277 | // Label 1011: @50693 |
| 20278 | GIM_Reject, |
| 20279 | // Label 891: @50694 |
| 20280 | GIM_Try, /*On fail goto*//*Label 1012*/ 50728, // Rule ID 5187 // |
| 20281 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20282 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, |
| 20283 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20284 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20285 | // (bitconvert:{ *:[v2f64] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v2f64] }:$src |
| 20286 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20287 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20288 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20289 | GIR_EraseFromParent, /*InsnID*/0, |
| 20290 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 20291 | // GIR_Coverage, 5187, |
| 20292 | GIR_Done, |
| 20293 | // Label 1012: @50728 |
| 20294 | GIM_Try, /*On fail goto*//*Label 1013*/ 50762, // Rule ID 5188 // |
| 20295 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20296 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 20297 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20298 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20299 | // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v2f64] }:$src |
| 20300 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20301 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20302 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20303 | GIR_EraseFromParent, /*InsnID*/0, |
| 20304 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 20305 | // GIR_Coverage, 5188, |
| 20306 | GIR_Done, |
| 20307 | // Label 1013: @50762 |
| 20308 | GIM_Try, /*On fail goto*//*Label 1014*/ 50796, // Rule ID 5189 // |
| 20309 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20310 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 20311 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20312 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20313 | // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v2f64] }:$src |
| 20314 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20315 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20316 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20317 | GIR_EraseFromParent, /*InsnID*/0, |
| 20318 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 20319 | // GIR_Coverage, 5189, |
| 20320 | GIR_Done, |
| 20321 | // Label 1014: @50796 |
| 20322 | GIM_Try, /*On fail goto*//*Label 1015*/ 50830, // Rule ID 5190 // |
| 20323 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20324 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 20325 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20326 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20327 | // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v2f64] }:$src |
| 20328 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20329 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20330 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20331 | GIR_EraseFromParent, /*InsnID*/0, |
| 20332 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 20333 | // GIR_Coverage, 5190, |
| 20334 | GIR_Done, |
| 20335 | // Label 1015: @50830 |
| 20336 | GIM_Try, /*On fail goto*//*Label 1016*/ 50864, // Rule ID 5191 // |
| 20337 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20338 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 20339 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20340 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20341 | // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8bf16] }:$src) => FPR128:{ *:[v2f64] }:$src |
| 20342 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20343 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20344 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20345 | GIR_EraseFromParent, /*InsnID*/0, |
| 20346 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 20347 | // GIR_Coverage, 5191, |
| 20348 | GIR_Done, |
| 20349 | // Label 1016: @50864 |
| 20350 | GIM_Try, /*On fail goto*//*Label 1017*/ 50898, // Rule ID 5192 // |
| 20351 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20352 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 20353 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20354 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20355 | // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v2f64] }:$src |
| 20356 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20357 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20358 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20359 | GIR_EraseFromParent, /*InsnID*/0, |
| 20360 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 20361 | // GIR_Coverage, 5192, |
| 20362 | GIR_Done, |
| 20363 | // Label 1017: @50898 |
| 20364 | GIM_Try, /*On fail goto*//*Label 1018*/ 50932, // Rule ID 5193 // |
| 20365 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20366 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 20367 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20368 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20369 | // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v2f64] }:$src |
| 20370 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20371 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20372 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20373 | GIR_EraseFromParent, /*InsnID*/0, |
| 20374 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 20375 | // GIR_Coverage, 5193, |
| 20376 | GIR_Done, |
| 20377 | // Label 1018: @50932 |
| 20378 | GIM_Try, /*On fail goto*//*Label 1019*/ 50971, // Rule ID 5194 // |
| 20379 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20380 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, |
| 20381 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20382 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20383 | // (bitconvert:{ *:[v2f64] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v2f64] } FPR128:{ *:[f128] }:$src, FPR128:{ *:[f128] }:$src, 8:{ *:[i32] }) |
| 20384 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, |
| 20385 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 20386 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20387 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20388 | GIR_AddImm, /*InsnID*/0, /*Imm*/8, |
| 20389 | GIR_EraseFromParent, /*InsnID*/0, |
| 20390 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20391 | // GIR_Coverage, 5194, |
| 20392 | GIR_Done, |
| 20393 | // Label 1019: @50971 |
| 20394 | GIM_Try, /*On fail goto*//*Label 1020*/ 50994, // Rule ID 5195 // |
| 20395 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20396 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 20397 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20398 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20399 | // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4i32] }:$src) => (REV64v4i32:{ *:[v2f64] } FPR128:{ *:[v4i32] }:$src) |
| 20400 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, |
| 20401 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20402 | // GIR_Coverage, 5195, |
| 20403 | GIR_Done, |
| 20404 | // Label 1020: @50994 |
| 20405 | GIM_Try, /*On fail goto*//*Label 1021*/ 51017, // Rule ID 5196 // |
| 20406 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20407 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 20408 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20409 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20410 | // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8i16] }:$src) => (REV64v8i16:{ *:[v2f64] } FPR128:{ *:[v8i16] }:$src) |
| 20411 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, |
| 20412 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20413 | // GIR_Coverage, 5196, |
| 20414 | GIR_Done, |
| 20415 | // Label 1021: @51017 |
| 20416 | GIM_Try, /*On fail goto*//*Label 1022*/ 51040, // Rule ID 5197 // |
| 20417 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20418 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 20419 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20420 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20421 | // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8f16] }:$src) => (REV64v8i16:{ *:[v2f64] } FPR128:{ *:[v8f16] }:$src) |
| 20422 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, |
| 20423 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20424 | // GIR_Coverage, 5197, |
| 20425 | GIR_Done, |
| 20426 | // Label 1022: @51040 |
| 20427 | GIM_Try, /*On fail goto*//*Label 1023*/ 51063, // Rule ID 5198 // |
| 20428 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20429 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 20430 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20431 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20432 | // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8bf16] }:$src) => (REV64v8i16:{ *:[v2f64] } FPR128:{ *:[v8bf16] }:$src) |
| 20433 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, |
| 20434 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20435 | // GIR_Coverage, 5198, |
| 20436 | GIR_Done, |
| 20437 | // Label 1023: @51063 |
| 20438 | GIM_Try, /*On fail goto*//*Label 1024*/ 51086, // Rule ID 5199 // |
| 20439 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20440 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 20441 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20442 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20443 | // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v16i8] }:$src) => (REV64v16i8:{ *:[v2f64] } FPR128:{ *:[v16i8] }:$src) |
| 20444 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v16i8, |
| 20445 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20446 | // GIR_Coverage, 5199, |
| 20447 | GIR_Done, |
| 20448 | // Label 1024: @51086 |
| 20449 | GIM_Try, /*On fail goto*//*Label 1025*/ 51109, // Rule ID 5200 // |
| 20450 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20451 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 20452 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20453 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20454 | // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4f32] }:$src) => (REV64v4i32:{ *:[v2f64] } FPR128:{ *:[v4f32] }:$src) |
| 20455 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, |
| 20456 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20457 | // GIR_Coverage, 5200, |
| 20458 | GIR_Done, |
| 20459 | // Label 1025: @51109 |
| 20460 | GIM_Try, /*On fail goto*//*Label 1026*/ 51141, // Rule ID 5201 // |
| 20461 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 20462 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20463 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20464 | // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v2f64] }:$src |
| 20465 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20466 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20467 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20468 | GIR_EraseFromParent, /*InsnID*/0, |
| 20469 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 20470 | // GIR_Coverage, 5201, |
| 20471 | GIR_Done, |
| 20472 | // Label 1026: @51141 |
| 20473 | GIM_Try, /*On fail goto*//*Label 1027*/ 51175, // Rule ID 5217 // |
| 20474 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20475 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, |
| 20476 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20477 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20478 | // (bitconvert:{ *:[v2i64] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v2i64] }:$src |
| 20479 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20480 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20481 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20482 | GIR_EraseFromParent, /*InsnID*/0, |
| 20483 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 20484 | // GIR_Coverage, 5217, |
| 20485 | GIR_Done, |
| 20486 | // Label 1027: @51175 |
| 20487 | GIM_Try, /*On fail goto*//*Label 1028*/ 51209, // Rule ID 5218 // |
| 20488 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20489 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 20490 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20491 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20492 | // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v2i64] }:$src |
| 20493 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20494 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20495 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20496 | GIR_EraseFromParent, /*InsnID*/0, |
| 20497 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 20498 | // GIR_Coverage, 5218, |
| 20499 | GIR_Done, |
| 20500 | // Label 1028: @51209 |
| 20501 | GIM_Try, /*On fail goto*//*Label 1029*/ 51243, // Rule ID 5219 // |
| 20502 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20503 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 20504 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20505 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20506 | // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v2i64] }:$src |
| 20507 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20508 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20509 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20510 | GIR_EraseFromParent, /*InsnID*/0, |
| 20511 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 20512 | // GIR_Coverage, 5219, |
| 20513 | GIR_Done, |
| 20514 | // Label 1029: @51243 |
| 20515 | GIM_Try, /*On fail goto*//*Label 1030*/ 51277, // Rule ID 5220 // |
| 20516 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20517 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 20518 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20519 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20520 | // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v2i64] }:$src |
| 20521 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20522 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20523 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20524 | GIR_EraseFromParent, /*InsnID*/0, |
| 20525 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 20526 | // GIR_Coverage, 5220, |
| 20527 | GIR_Done, |
| 20528 | // Label 1030: @51277 |
| 20529 | GIM_Try, /*On fail goto*//*Label 1031*/ 51311, // Rule ID 5221 // |
| 20530 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20531 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 20532 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20533 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20534 | // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v2i64] }:$src |
| 20535 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20536 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20537 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20538 | GIR_EraseFromParent, /*InsnID*/0, |
| 20539 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 20540 | // GIR_Coverage, 5221, |
| 20541 | GIR_Done, |
| 20542 | // Label 1031: @51311 |
| 20543 | GIM_Try, /*On fail goto*//*Label 1032*/ 51345, // Rule ID 5222 // |
| 20544 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20545 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 20546 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20547 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20548 | // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v2i64] }:$src |
| 20549 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20550 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20551 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20552 | GIR_EraseFromParent, /*InsnID*/0, |
| 20553 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 20554 | // GIR_Coverage, 5222, |
| 20555 | GIR_Done, |
| 20556 | // Label 1032: @51345 |
| 20557 | GIM_Try, /*On fail goto*//*Label 1033*/ 51379, // Rule ID 5223 // |
| 20558 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20559 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 20560 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20561 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20562 | // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8bf16] }:$src) => FPR128:{ *:[v2i64] }:$src |
| 20563 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20564 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20565 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20566 | GIR_EraseFromParent, /*InsnID*/0, |
| 20567 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 20568 | // GIR_Coverage, 5223, |
| 20569 | GIR_Done, |
| 20570 | // Label 1033: @51379 |
| 20571 | GIM_Try, /*On fail goto*//*Label 1034*/ 51418, // Rule ID 5224 // |
| 20572 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20573 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, |
| 20574 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20575 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20576 | // (bitconvert:{ *:[v2i64] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v2i64] } FPR128:{ *:[f128] }:$src, FPR128:{ *:[f128] }:$src, 8:{ *:[i32] }) |
| 20577 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, |
| 20578 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 20579 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20580 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20581 | GIR_AddImm, /*InsnID*/0, /*Imm*/8, |
| 20582 | GIR_EraseFromParent, /*InsnID*/0, |
| 20583 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20584 | // GIR_Coverage, 5224, |
| 20585 | GIR_Done, |
| 20586 | // Label 1034: @51418 |
| 20587 | GIM_Try, /*On fail goto*//*Label 1035*/ 51441, // Rule ID 5225 // |
| 20588 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20589 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 20590 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20591 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20592 | // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4i32] }:$src) => (REV64v4i32:{ *:[v2i64] } FPR128:{ *:[v4i32] }:$src) |
| 20593 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, |
| 20594 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20595 | // GIR_Coverage, 5225, |
| 20596 | GIR_Done, |
| 20597 | // Label 1035: @51441 |
| 20598 | GIM_Try, /*On fail goto*//*Label 1036*/ 51464, // Rule ID 5226 // |
| 20599 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20600 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 20601 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20602 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20603 | // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8i16] }:$src) => (REV64v8i16:{ *:[v2i64] } FPR128:{ *:[v8i16] }:$src) |
| 20604 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, |
| 20605 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20606 | // GIR_Coverage, 5226, |
| 20607 | GIR_Done, |
| 20608 | // Label 1036: @51464 |
| 20609 | GIM_Try, /*On fail goto*//*Label 1037*/ 51487, // Rule ID 5227 // |
| 20610 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20611 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 20612 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20613 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20614 | // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v16i8] }:$src) => (REV64v16i8:{ *:[v2i64] } FPR128:{ *:[v16i8] }:$src) |
| 20615 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v16i8, |
| 20616 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20617 | // GIR_Coverage, 5227, |
| 20618 | GIR_Done, |
| 20619 | // Label 1037: @51487 |
| 20620 | GIM_Try, /*On fail goto*//*Label 1038*/ 51510, // Rule ID 5228 // |
| 20621 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20622 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 20623 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20624 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20625 | // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4f32] }:$src) => (REV64v4i32:{ *:[v2i64] } FPR128:{ *:[v4f32] }:$src) |
| 20626 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, |
| 20627 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20628 | // GIR_Coverage, 5228, |
| 20629 | GIR_Done, |
| 20630 | // Label 1038: @51510 |
| 20631 | GIM_Try, /*On fail goto*//*Label 1039*/ 51533, // Rule ID 5229 // |
| 20632 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20633 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 20634 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20635 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20636 | // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8f16] }:$src) => (REV64v8i16:{ *:[v2i64] } FPR128:{ *:[v8f16] }:$src) |
| 20637 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, |
| 20638 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20639 | // GIR_Coverage, 5229, |
| 20640 | GIR_Done, |
| 20641 | // Label 1039: @51533 |
| 20642 | GIM_Try, /*On fail goto*//*Label 1040*/ 51556, // Rule ID 5230 // |
| 20643 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20644 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 20645 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20646 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20647 | // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8bf16] }:$src) => (REV64v8i16:{ *:[v2i64] } FPR128:{ *:[v8bf16] }:$src) |
| 20648 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, |
| 20649 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20650 | // GIR_Coverage, 5230, |
| 20651 | GIR_Done, |
| 20652 | // Label 1040: @51556 |
| 20653 | GIM_Try, /*On fail goto*//*Label 1041*/ 51588, // Rule ID 5231 // |
| 20654 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 20655 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 20656 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 20657 | // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v2i64] }:$src |
| 20658 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20659 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20660 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20661 | GIR_EraseFromParent, /*InsnID*/0, |
| 20662 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 20663 | // GIR_Coverage, 5231, |
| 20664 | GIR_Done, |
| 20665 | // Label 1041: @51588 |
| 20666 | GIM_Reject, |
| 20667 | // Label 892: @51589 |
| 20668 | GIM_Try, /*On fail goto*//*Label 1042*/ 51614, // Rule ID 5008 // |
| 20669 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20670 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 20671 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20672 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 20673 | // (bitconvert:{ *:[v4i16] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v4i16] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) |
| 20674 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20675 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 20676 | // GIR_Coverage, 5008, |
| 20677 | GIR_Done, |
| 20678 | // Label 1042: @51614 |
| 20679 | GIM_Try, /*On fail goto*//*Label 1043*/ 51639, // Rule ID 5010 // |
| 20680 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20681 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 20682 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20683 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 20684 | // (bitconvert:{ *:[v4f16] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v4f16] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) |
| 20685 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20686 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 20687 | // GIR_Coverage, 5010, |
| 20688 | GIR_Done, |
| 20689 | // Label 1043: @51639 |
| 20690 | GIM_Try, /*On fail goto*//*Label 1044*/ 51664, // Rule ID 5011 // |
| 20691 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20692 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 20693 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20694 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 20695 | // (bitconvert:{ *:[v4bf16] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v4bf16] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) |
| 20696 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20697 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 20698 | // GIR_Coverage, 5011, |
| 20699 | GIR_Done, |
| 20700 | // Label 1044: @51664 |
| 20701 | GIM_Try, /*On fail goto*//*Label 1045*/ 51712, // Rule ID 5021 // |
| 20702 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20703 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 20704 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20705 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 20706 | // (bitconvert:{ *:[v4i16] } GPR64:{ *:[i64] }:$Xn) => (REV64v4i16:{ *:[v4i16] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })) |
| 20707 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 20708 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 20709 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20710 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn |
| 20711 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20712 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 20713 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 20714 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20715 | GIR_EraseFromParent, /*InsnID*/0, |
| 20716 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20717 | // GIR_Coverage, 5021, |
| 20718 | GIR_Done, |
| 20719 | // Label 1045: @51712 |
| 20720 | GIM_Try, /*On fail goto*//*Label 1046*/ 51760, // Rule ID 5023 // |
| 20721 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20722 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 20723 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20724 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 20725 | // (bitconvert:{ *:[v4f16] } GPR64:{ *:[i64] }:$Xn) => (REV64v4i16:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })) |
| 20726 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 20727 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 20728 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20729 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn |
| 20730 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20731 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 20732 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 20733 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20734 | GIR_EraseFromParent, /*InsnID*/0, |
| 20735 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20736 | // GIR_Coverage, 5023, |
| 20737 | GIR_Done, |
| 20738 | // Label 1046: @51760 |
| 20739 | GIM_Try, /*On fail goto*//*Label 1047*/ 51808, // Rule ID 5024 // |
| 20740 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20741 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 20742 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20743 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 20744 | // (bitconvert:{ *:[v4bf16] } GPR64:{ *:[i64] }:$Xn) => (REV64v4i16:{ *:[v4bf16] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })) |
| 20745 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 20746 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 20747 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20748 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn |
| 20749 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20750 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 20751 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 20752 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20753 | GIR_EraseFromParent, /*InsnID*/0, |
| 20754 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20755 | // GIR_Coverage, 5024, |
| 20756 | GIR_Done, |
| 20757 | // Label 1047: @51808 |
| 20758 | GIM_Try, /*On fail goto*//*Label 1048*/ 51842, // Rule ID 5072 // |
| 20759 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20760 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 20761 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20762 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20763 | // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v4i16] }:$src |
| 20764 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20765 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20766 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20767 | GIR_EraseFromParent, /*InsnID*/0, |
| 20768 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 20769 | // GIR_Coverage, 5072, |
| 20770 | GIR_Done, |
| 20771 | // Label 1048: @51842 |
| 20772 | GIM_Try, /*On fail goto*//*Label 1049*/ 51876, // Rule ID 5073 // |
| 20773 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20774 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 20775 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20776 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20777 | // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v4i16] }:$src |
| 20778 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20779 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20780 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20781 | GIR_EraseFromParent, /*InsnID*/0, |
| 20782 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 20783 | // GIR_Coverage, 5073, |
| 20784 | GIR_Done, |
| 20785 | // Label 1049: @51876 |
| 20786 | GIM_Try, /*On fail goto*//*Label 1050*/ 51910, // Rule ID 5074 // |
| 20787 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20788 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 20789 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20790 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20791 | // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v4i16] }:$src |
| 20792 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20793 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20794 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20795 | GIR_EraseFromParent, /*InsnID*/0, |
| 20796 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 20797 | // GIR_Coverage, 5074, |
| 20798 | GIR_Done, |
| 20799 | // Label 1050: @51910 |
| 20800 | GIM_Try, /*On fail goto*//*Label 1051*/ 51944, // Rule ID 5075 // |
| 20801 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20802 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 20803 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20804 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20805 | // (bitconvert:{ *:[v4i16] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v4i16] }:$src |
| 20806 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20807 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20808 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20809 | GIR_EraseFromParent, /*InsnID*/0, |
| 20810 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 20811 | // GIR_Coverage, 5075, |
| 20812 | GIR_Done, |
| 20813 | // Label 1051: @51944 |
| 20814 | GIM_Try, /*On fail goto*//*Label 1052*/ 51978, // Rule ID 5076 // |
| 20815 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20816 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 20817 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20818 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20819 | // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v4i16] }:$src |
| 20820 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20821 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20822 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20823 | GIR_EraseFromParent, /*InsnID*/0, |
| 20824 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 20825 | // GIR_Coverage, 5076, |
| 20826 | GIR_Done, |
| 20827 | // Label 1052: @51978 |
| 20828 | GIM_Try, /*On fail goto*//*Label 1053*/ 52012, // Rule ID 5077 // |
| 20829 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20830 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 20831 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20832 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20833 | // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v4i16] }:$src |
| 20834 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20835 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20836 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20837 | GIR_EraseFromParent, /*InsnID*/0, |
| 20838 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 20839 | // GIR_Coverage, 5077, |
| 20840 | GIR_Done, |
| 20841 | // Label 1053: @52012 |
| 20842 | GIM_Try, /*On fail goto*//*Label 1054*/ 52035, // Rule ID 5078 // |
| 20843 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20844 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 20845 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20846 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20847 | // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1i64] }:$src) => (REV64v4i16:{ *:[v4i16] } FPR64:{ *:[v1i64] }:$src) |
| 20848 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 20849 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20850 | // GIR_Coverage, 5078, |
| 20851 | GIR_Done, |
| 20852 | // Label 1054: @52035 |
| 20853 | GIM_Try, /*On fail goto*//*Label 1055*/ 52058, // Rule ID 5079 // |
| 20854 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20855 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 20856 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20857 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20858 | // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2i32] }:$src) => (REV32v4i16:{ *:[v4i16] } FPR64:{ *:[v2i32] }:$src) |
| 20859 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, |
| 20860 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20861 | // GIR_Coverage, 5079, |
| 20862 | GIR_Done, |
| 20863 | // Label 1055: @52058 |
| 20864 | GIM_Try, /*On fail goto*//*Label 1056*/ 52081, // Rule ID 5080 // |
| 20865 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20866 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 20867 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20868 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20869 | // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v8i8] }:$src) => (REV16v8i8:{ *:[v4i16] } FPR64:{ *:[v8i8] }:$src) |
| 20870 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v8i8, |
| 20871 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20872 | // GIR_Coverage, 5080, |
| 20873 | GIR_Done, |
| 20874 | // Label 1056: @52081 |
| 20875 | GIM_Try, /*On fail goto*//*Label 1057*/ 52104, // Rule ID 5081 // |
| 20876 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20877 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 20878 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20879 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20880 | // (bitconvert:{ *:[v4i16] } FPR64:{ *:[f64] }:$src) => (REV64v4i16:{ *:[v4i16] } FPR64:{ *:[f64] }:$src) |
| 20881 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 20882 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20883 | // GIR_Coverage, 5081, |
| 20884 | GIR_Done, |
| 20885 | // Label 1057: @52104 |
| 20886 | GIM_Try, /*On fail goto*//*Label 1058*/ 52127, // Rule ID 5082 // |
| 20887 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20888 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 20889 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20890 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20891 | // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2f32] }:$src) => (REV32v4i16:{ *:[v4i16] } FPR64:{ *:[v2f32] }:$src) |
| 20892 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, |
| 20893 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20894 | // GIR_Coverage, 5082, |
| 20895 | GIR_Done, |
| 20896 | // Label 1058: @52127 |
| 20897 | GIM_Try, /*On fail goto*//*Label 1059*/ 52150, // Rule ID 5083 // |
| 20898 | GIM_CheckFeatures, GIFBS_IsBE, |
| 20899 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 20900 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20901 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20902 | // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1f64] }:$src) => (REV64v4i16:{ *:[v4i16] } FPR64:{ *:[v1f64] }:$src) |
| 20903 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 20904 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20905 | // GIR_Coverage, 5083, |
| 20906 | GIR_Done, |
| 20907 | // Label 1059: @52150 |
| 20908 | GIM_Try, /*On fail goto*//*Label 1060*/ 52182, // Rule ID 5084 // |
| 20909 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 20910 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20911 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20912 | // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v4i16] }:$src |
| 20913 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20914 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20915 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20916 | GIR_EraseFromParent, /*InsnID*/0, |
| 20917 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 20918 | // GIR_Coverage, 5084, |
| 20919 | GIR_Done, |
| 20920 | // Label 1060: @52182 |
| 20921 | GIM_Try, /*On fail goto*//*Label 1061*/ 52214, // Rule ID 5085 // |
| 20922 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 20923 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20924 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20925 | // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v4bf16] }:$src) => FPR64:{ *:[v4i16] }:$src |
| 20926 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20927 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20928 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20929 | GIR_EraseFromParent, /*InsnID*/0, |
| 20930 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 20931 | // GIR_Coverage, 5085, |
| 20932 | GIR_Done, |
| 20933 | // Label 1061: @52214 |
| 20934 | GIM_Try, /*On fail goto*//*Label 1062*/ 52248, // Rule ID 5086 // |
| 20935 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20936 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 20937 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20938 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20939 | // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v4f16] }:$src |
| 20940 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20941 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20942 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20943 | GIR_EraseFromParent, /*InsnID*/0, |
| 20944 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 20945 | // GIR_Coverage, 5086, |
| 20946 | GIR_Done, |
| 20947 | // Label 1062: @52248 |
| 20948 | GIM_Try, /*On fail goto*//*Label 1063*/ 52282, // Rule ID 5087 // |
| 20949 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20950 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 20951 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20952 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20953 | // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v4f16] }:$src |
| 20954 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20955 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20956 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20957 | GIR_EraseFromParent, /*InsnID*/0, |
| 20958 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 20959 | // GIR_Coverage, 5087, |
| 20960 | GIR_Done, |
| 20961 | // Label 1063: @52282 |
| 20962 | GIM_Try, /*On fail goto*//*Label 1064*/ 52316, // Rule ID 5088 // |
| 20963 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20964 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 20965 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20966 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20967 | // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v4f16] }:$src |
| 20968 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20969 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20970 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20971 | GIR_EraseFromParent, /*InsnID*/0, |
| 20972 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 20973 | // GIR_Coverage, 5088, |
| 20974 | GIR_Done, |
| 20975 | // Label 1064: @52316 |
| 20976 | GIM_Try, /*On fail goto*//*Label 1065*/ 52350, // Rule ID 5089 // |
| 20977 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20978 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 20979 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20980 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20981 | // (bitconvert:{ *:[v4f16] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v4f16] }:$src |
| 20982 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20983 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20984 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20985 | GIR_EraseFromParent, /*InsnID*/0, |
| 20986 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 20987 | // GIR_Coverage, 5089, |
| 20988 | GIR_Done, |
| 20989 | // Label 1065: @52350 |
| 20990 | GIM_Try, /*On fail goto*//*Label 1066*/ 52384, // Rule ID 5090 // |
| 20991 | GIM_CheckFeatures, GIFBS_IsLE, |
| 20992 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 20993 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 20994 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 20995 | // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v4f16] }:$src |
| 20996 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 20997 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 20998 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 20999 | GIR_EraseFromParent, /*InsnID*/0, |
| 21000 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 21001 | // GIR_Coverage, 5090, |
| 21002 | GIR_Done, |
| 21003 | // Label 1066: @52384 |
| 21004 | GIM_Try, /*On fail goto*//*Label 1067*/ 52418, // Rule ID 5091 // |
| 21005 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21006 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 21007 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21008 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21009 | // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v4f16] }:$src |
| 21010 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21011 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21012 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21013 | GIR_EraseFromParent, /*InsnID*/0, |
| 21014 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 21015 | // GIR_Coverage, 5091, |
| 21016 | GIR_Done, |
| 21017 | // Label 1067: @52418 |
| 21018 | GIM_Try, /*On fail goto*//*Label 1068*/ 52452, // Rule ID 5092 // |
| 21019 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21020 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 21021 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21022 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21023 | // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v4bf16] }:$src |
| 21024 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21025 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21026 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21027 | GIR_EraseFromParent, /*InsnID*/0, |
| 21028 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 21029 | // GIR_Coverage, 5092, |
| 21030 | GIR_Done, |
| 21031 | // Label 1068: @52452 |
| 21032 | GIM_Try, /*On fail goto*//*Label 1069*/ 52486, // Rule ID 5093 // |
| 21033 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21034 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 21035 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21036 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21037 | // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v4bf16] }:$src |
| 21038 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21039 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21040 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21041 | GIR_EraseFromParent, /*InsnID*/0, |
| 21042 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 21043 | // GIR_Coverage, 5093, |
| 21044 | GIR_Done, |
| 21045 | // Label 1069: @52486 |
| 21046 | GIM_Try, /*On fail goto*//*Label 1070*/ 52520, // Rule ID 5094 // |
| 21047 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21048 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 21049 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21050 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21051 | // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v4bf16] }:$src |
| 21052 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21053 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21054 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21055 | GIR_EraseFromParent, /*InsnID*/0, |
| 21056 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 21057 | // GIR_Coverage, 5094, |
| 21058 | GIR_Done, |
| 21059 | // Label 1070: @52520 |
| 21060 | GIM_Try, /*On fail goto*//*Label 1071*/ 52554, // Rule ID 5095 // |
| 21061 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21062 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 21063 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21064 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21065 | // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v4bf16] }:$src |
| 21066 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21067 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21068 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21069 | GIR_EraseFromParent, /*InsnID*/0, |
| 21070 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 21071 | // GIR_Coverage, 5095, |
| 21072 | GIR_Done, |
| 21073 | // Label 1071: @52554 |
| 21074 | GIM_Try, /*On fail goto*//*Label 1072*/ 52588, // Rule ID 5096 // |
| 21075 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21076 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 21077 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21078 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21079 | // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v4bf16] }:$src |
| 21080 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21081 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21082 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21083 | GIR_EraseFromParent, /*InsnID*/0, |
| 21084 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 21085 | // GIR_Coverage, 5096, |
| 21086 | GIR_Done, |
| 21087 | // Label 1072: @52588 |
| 21088 | GIM_Try, /*On fail goto*//*Label 1073*/ 52622, // Rule ID 5097 // |
| 21089 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21090 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 21091 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21092 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21093 | // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v4bf16] }:$src |
| 21094 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21095 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21096 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21097 | GIR_EraseFromParent, /*InsnID*/0, |
| 21098 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 21099 | // GIR_Coverage, 5097, |
| 21100 | GIR_Done, |
| 21101 | // Label 1073: @52622 |
| 21102 | GIM_Try, /*On fail goto*//*Label 1074*/ 52645, // Rule ID 5098 // |
| 21103 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21104 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 21105 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21106 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21107 | // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1i64] }:$src) => (REV64v4i16:{ *:[v4f16] } FPR64:{ *:[v1i64] }:$src) |
| 21108 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 21109 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21110 | // GIR_Coverage, 5098, |
| 21111 | GIR_Done, |
| 21112 | // Label 1074: @52645 |
| 21113 | GIM_Try, /*On fail goto*//*Label 1075*/ 52668, // Rule ID 5099 // |
| 21114 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21115 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 21116 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21117 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21118 | // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2i32] }:$src) => (REV32v4i16:{ *:[v4f16] } FPR64:{ *:[v2i32] }:$src) |
| 21119 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, |
| 21120 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21121 | // GIR_Coverage, 5099, |
| 21122 | GIR_Done, |
| 21123 | // Label 1075: @52668 |
| 21124 | GIM_Try, /*On fail goto*//*Label 1076*/ 52691, // Rule ID 5100 // |
| 21125 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21126 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 21127 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21128 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21129 | // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v8i8] }:$src) => (REV16v8i8:{ *:[v4f16] } FPR64:{ *:[v8i8] }:$src) |
| 21130 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v8i8, |
| 21131 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21132 | // GIR_Coverage, 5100, |
| 21133 | GIR_Done, |
| 21134 | // Label 1076: @52691 |
| 21135 | GIM_Try, /*On fail goto*//*Label 1077*/ 52714, // Rule ID 5101 // |
| 21136 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21137 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 21138 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21139 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21140 | // (bitconvert:{ *:[v4f16] } FPR64:{ *:[f64] }:$src) => (REV64v4i16:{ *:[v4f16] } FPR64:{ *:[f64] }:$src) |
| 21141 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 21142 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21143 | // GIR_Coverage, 5101, |
| 21144 | GIR_Done, |
| 21145 | // Label 1077: @52714 |
| 21146 | GIM_Try, /*On fail goto*//*Label 1078*/ 52737, // Rule ID 5102 // |
| 21147 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21148 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 21149 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21150 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21151 | // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2f32] }:$src) => (REV32v4i16:{ *:[v4f16] } FPR64:{ *:[v2f32] }:$src) |
| 21152 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, |
| 21153 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21154 | // GIR_Coverage, 5102, |
| 21155 | GIR_Done, |
| 21156 | // Label 1078: @52737 |
| 21157 | GIM_Try, /*On fail goto*//*Label 1079*/ 52760, // Rule ID 5103 // |
| 21158 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21159 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 21160 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21161 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21162 | // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1f64] }:$src) => (REV64v4i16:{ *:[v4f16] } FPR64:{ *:[v1f64] }:$src) |
| 21163 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 21164 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21165 | // GIR_Coverage, 5103, |
| 21166 | GIR_Done, |
| 21167 | // Label 1079: @52760 |
| 21168 | GIM_Try, /*On fail goto*//*Label 1080*/ 52783, // Rule ID 5104 // |
| 21169 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21170 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 21171 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21172 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21173 | // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v1i64] }:$src) => (REV64v4i16:{ *:[v4bf16] } FPR64:{ *:[v1i64] }:$src) |
| 21174 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 21175 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21176 | // GIR_Coverage, 5104, |
| 21177 | GIR_Done, |
| 21178 | // Label 1080: @52783 |
| 21179 | GIM_Try, /*On fail goto*//*Label 1081*/ 52806, // Rule ID 5105 // |
| 21180 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21181 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 21182 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21183 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21184 | // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v2i32] }:$src) => (REV32v4i16:{ *:[v4bf16] } FPR64:{ *:[v2i32] }:$src) |
| 21185 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, |
| 21186 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21187 | // GIR_Coverage, 5105, |
| 21188 | GIR_Done, |
| 21189 | // Label 1081: @52806 |
| 21190 | GIM_Try, /*On fail goto*//*Label 1082*/ 52829, // Rule ID 5106 // |
| 21191 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21192 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 21193 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21194 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21195 | // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v8i8] }:$src) => (REV16v8i8:{ *:[v4bf16] } FPR64:{ *:[v8i8] }:$src) |
| 21196 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v8i8, |
| 21197 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21198 | // GIR_Coverage, 5106, |
| 21199 | GIR_Done, |
| 21200 | // Label 1082: @52829 |
| 21201 | GIM_Try, /*On fail goto*//*Label 1083*/ 52852, // Rule ID 5107 // |
| 21202 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21203 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 21204 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21205 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21206 | // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[f64] }:$src) => (REV64v4i16:{ *:[v4bf16] } FPR64:{ *:[f64] }:$src) |
| 21207 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 21208 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21209 | // GIR_Coverage, 5107, |
| 21210 | GIR_Done, |
| 21211 | // Label 1083: @52852 |
| 21212 | GIM_Try, /*On fail goto*//*Label 1084*/ 52875, // Rule ID 5108 // |
| 21213 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21214 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 21215 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21216 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21217 | // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v2f32] }:$src) => (REV32v4i16:{ *:[v4bf16] } FPR64:{ *:[v2f32] }:$src) |
| 21218 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, |
| 21219 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21220 | // GIR_Coverage, 5108, |
| 21221 | GIR_Done, |
| 21222 | // Label 1084: @52875 |
| 21223 | GIM_Try, /*On fail goto*//*Label 1085*/ 52898, // Rule ID 5109 // |
| 21224 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21225 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 21226 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21227 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21228 | // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v1f64] }:$src) => (REV64v4i16:{ *:[v4bf16] } FPR64:{ *:[v1f64] }:$src) |
| 21229 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 21230 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21231 | // GIR_Coverage, 5109, |
| 21232 | GIR_Done, |
| 21233 | // Label 1085: @52898 |
| 21234 | GIM_Try, /*On fail goto*//*Label 1086*/ 52930, // Rule ID 5110 // |
| 21235 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 21236 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21237 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21238 | // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v4f16] }:$src |
| 21239 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21240 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21241 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21242 | GIR_EraseFromParent, /*InsnID*/0, |
| 21243 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 21244 | // GIR_Coverage, 5110, |
| 21245 | GIR_Done, |
| 21246 | // Label 1086: @52930 |
| 21247 | GIM_Try, /*On fail goto*//*Label 1087*/ 52962, // Rule ID 5111 // |
| 21248 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 21249 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21250 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21251 | // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v4bf16] }:$src |
| 21252 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21253 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21254 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21255 | GIR_EraseFromParent, /*InsnID*/0, |
| 21256 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 21257 | // GIR_Coverage, 5111, |
| 21258 | GIR_Done, |
| 21259 | // Label 1087: @52962 |
| 21260 | GIM_Reject, |
| 21261 | // Label 893: @52963 |
| 21262 | GIM_Try, /*On fail goto*//*Label 1088*/ 52997, // Rule ID 5202 // |
| 21263 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21264 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, |
| 21265 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21266 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21267 | // (bitconvert:{ *:[v4f32] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v4f32] }:$src |
| 21268 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21269 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21270 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21271 | GIR_EraseFromParent, /*InsnID*/0, |
| 21272 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 21273 | // GIR_Coverage, 5202, |
| 21274 | GIR_Done, |
| 21275 | // Label 1088: @52997 |
| 21276 | GIM_Try, /*On fail goto*//*Label 1089*/ 53031, // Rule ID 5203 // |
| 21277 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21278 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 21279 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21280 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21281 | // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v4f32] }:$src |
| 21282 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21283 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21284 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21285 | GIR_EraseFromParent, /*InsnID*/0, |
| 21286 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 21287 | // GIR_Coverage, 5203, |
| 21288 | GIR_Done, |
| 21289 | // Label 1089: @53031 |
| 21290 | GIM_Try, /*On fail goto*//*Label 1090*/ 53065, // Rule ID 5204 // |
| 21291 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21292 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 21293 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21294 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21295 | // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v4f32] }:$src |
| 21296 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21297 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21298 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21299 | GIR_EraseFromParent, /*InsnID*/0, |
| 21300 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 21301 | // GIR_Coverage, 5204, |
| 21302 | GIR_Done, |
| 21303 | // Label 1090: @53065 |
| 21304 | GIM_Try, /*On fail goto*//*Label 1091*/ 53099, // Rule ID 5205 // |
| 21305 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21306 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 21307 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21308 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21309 | // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8bf16] }:$src) => FPR128:{ *:[v4f32] }:$src |
| 21310 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21311 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21312 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21313 | GIR_EraseFromParent, /*InsnID*/0, |
| 21314 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 21315 | // GIR_Coverage, 5205, |
| 21316 | GIR_Done, |
| 21317 | // Label 1091: @53099 |
| 21318 | GIM_Try, /*On fail goto*//*Label 1092*/ 53133, // Rule ID 5206 // |
| 21319 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21320 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 21321 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21322 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21323 | // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v4f32] }:$src |
| 21324 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21325 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21326 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21327 | GIR_EraseFromParent, /*InsnID*/0, |
| 21328 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 21329 | // GIR_Coverage, 5206, |
| 21330 | GIR_Done, |
| 21331 | // Label 1092: @53133 |
| 21332 | GIM_Try, /*On fail goto*//*Label 1093*/ 53167, // Rule ID 5207 // |
| 21333 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21334 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 21335 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21336 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21337 | // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v4f32] }:$src |
| 21338 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21339 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21340 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21341 | GIR_EraseFromParent, /*InsnID*/0, |
| 21342 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 21343 | // GIR_Coverage, 5207, |
| 21344 | GIR_Done, |
| 21345 | // Label 1093: @53167 |
| 21346 | GIM_Try, /*On fail goto*//*Label 1094*/ 53201, // Rule ID 5208 // |
| 21347 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21348 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 21349 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21350 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21351 | // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v4f32] }:$src |
| 21352 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21353 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21354 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21355 | GIR_EraseFromParent, /*InsnID*/0, |
| 21356 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 21357 | // GIR_Coverage, 5208, |
| 21358 | GIR_Done, |
| 21359 | // Label 1094: @53201 |
| 21360 | GIM_Try, /*On fail goto*//*Label 1095*/ 53272, // Rule ID 5209 // |
| 21361 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21362 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, |
| 21363 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21364 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21365 | // (bitconvert:{ *:[v4f32] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v4f32] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] }) |
| 21366 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 21367 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 21368 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v4i32, |
| 21369 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 21370 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21371 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 21372 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v4i32, |
| 21373 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 21374 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21375 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21376 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, |
| 21377 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 21378 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 21379 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 21380 | GIR_AddImm, /*InsnID*/0, /*Imm*/8, |
| 21381 | GIR_EraseFromParent, /*InsnID*/0, |
| 21382 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21383 | // GIR_Coverage, 5209, |
| 21384 | GIR_Done, |
| 21385 | // Label 1095: @53272 |
| 21386 | GIM_Try, /*On fail goto*//*Label 1096*/ 53295, // Rule ID 5210 // |
| 21387 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21388 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 21389 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21390 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21391 | // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8i16] }:$src) => (REV32v8i16:{ *:[v4f32] } FPR128:{ *:[v8i16] }:$src) |
| 21392 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, |
| 21393 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21394 | // GIR_Coverage, 5210, |
| 21395 | GIR_Done, |
| 21396 | // Label 1096: @53295 |
| 21397 | GIM_Try, /*On fail goto*//*Label 1097*/ 53318, // Rule ID 5211 // |
| 21398 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21399 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 21400 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21401 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21402 | // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8f16] }:$src) => (REV32v8i16:{ *:[v4f32] } FPR128:{ *:[v8f16] }:$src) |
| 21403 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, |
| 21404 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21405 | // GIR_Coverage, 5211, |
| 21406 | GIR_Done, |
| 21407 | // Label 1097: @53318 |
| 21408 | GIM_Try, /*On fail goto*//*Label 1098*/ 53341, // Rule ID 5212 // |
| 21409 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21410 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 21411 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21412 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21413 | // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8bf16] }:$src) => (REV32v8i16:{ *:[v4f32] } FPR128:{ *:[v8bf16] }:$src) |
| 21414 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, |
| 21415 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21416 | // GIR_Coverage, 5212, |
| 21417 | GIR_Done, |
| 21418 | // Label 1098: @53341 |
| 21419 | GIM_Try, /*On fail goto*//*Label 1099*/ 53364, // Rule ID 5213 // |
| 21420 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21421 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 21422 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21423 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21424 | // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v16i8] }:$src) => (REV32v16i8:{ *:[v4f32] } FPR128:{ *:[v16i8] }:$src) |
| 21425 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v16i8, |
| 21426 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21427 | // GIR_Coverage, 5213, |
| 21428 | GIR_Done, |
| 21429 | // Label 1099: @53364 |
| 21430 | GIM_Try, /*On fail goto*//*Label 1100*/ 53387, // Rule ID 5214 // |
| 21431 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21432 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 21433 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21434 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21435 | // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2i64] }:$src) => (REV64v4i32:{ *:[v4f32] } FPR128:{ *:[v2i64] }:$src) |
| 21436 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, |
| 21437 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21438 | // GIR_Coverage, 5214, |
| 21439 | GIR_Done, |
| 21440 | // Label 1100: @53387 |
| 21441 | GIM_Try, /*On fail goto*//*Label 1101*/ 53410, // Rule ID 5215 // |
| 21442 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21443 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 21444 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21445 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21446 | // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2f64] }:$src) => (REV64v4i32:{ *:[v4f32] } FPR128:{ *:[v2f64] }:$src) |
| 21447 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, |
| 21448 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21449 | // GIR_Coverage, 5215, |
| 21450 | GIR_Done, |
| 21451 | // Label 1101: @53410 |
| 21452 | GIM_Try, /*On fail goto*//*Label 1102*/ 53442, // Rule ID 5216 // |
| 21453 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 21454 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21455 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21456 | // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v4f32] }:$src |
| 21457 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21458 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21459 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21460 | GIR_EraseFromParent, /*InsnID*/0, |
| 21461 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 21462 | // GIR_Coverage, 5216, |
| 21463 | GIR_Done, |
| 21464 | // Label 1102: @53442 |
| 21465 | GIM_Try, /*On fail goto*//*Label 1103*/ 53476, // Rule ID 5232 // |
| 21466 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21467 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, |
| 21468 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21469 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21470 | // (bitconvert:{ *:[v4i32] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v4i32] }:$src |
| 21471 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21472 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21473 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21474 | GIR_EraseFromParent, /*InsnID*/0, |
| 21475 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 21476 | // GIR_Coverage, 5232, |
| 21477 | GIR_Done, |
| 21478 | // Label 1103: @53476 |
| 21479 | GIM_Try, /*On fail goto*//*Label 1104*/ 53510, // Rule ID 5233 // |
| 21480 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21481 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 21482 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21483 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21484 | // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v4i32] }:$src |
| 21485 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21486 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21487 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21488 | GIR_EraseFromParent, /*InsnID*/0, |
| 21489 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 21490 | // GIR_Coverage, 5233, |
| 21491 | GIR_Done, |
| 21492 | // Label 1104: @53510 |
| 21493 | GIM_Try, /*On fail goto*//*Label 1105*/ 53544, // Rule ID 5234 // |
| 21494 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21495 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 21496 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21497 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21498 | // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v4i32] }:$src |
| 21499 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21500 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21501 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21502 | GIR_EraseFromParent, /*InsnID*/0, |
| 21503 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 21504 | // GIR_Coverage, 5234, |
| 21505 | GIR_Done, |
| 21506 | // Label 1105: @53544 |
| 21507 | GIM_Try, /*On fail goto*//*Label 1106*/ 53578, // Rule ID 5235 // |
| 21508 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21509 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 21510 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21511 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21512 | // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v4i32] }:$src |
| 21513 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21514 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21515 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21516 | GIR_EraseFromParent, /*InsnID*/0, |
| 21517 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 21518 | // GIR_Coverage, 5235, |
| 21519 | GIR_Done, |
| 21520 | // Label 1106: @53578 |
| 21521 | GIM_Try, /*On fail goto*//*Label 1107*/ 53612, // Rule ID 5236 // |
| 21522 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21523 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 21524 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21525 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21526 | // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v4i32] }:$src |
| 21527 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21528 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21529 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21530 | GIR_EraseFromParent, /*InsnID*/0, |
| 21531 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 21532 | // GIR_Coverage, 5236, |
| 21533 | GIR_Done, |
| 21534 | // Label 1107: @53612 |
| 21535 | GIM_Try, /*On fail goto*//*Label 1108*/ 53646, // Rule ID 5237 // |
| 21536 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21537 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 21538 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21539 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21540 | // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v4i32] }:$src |
| 21541 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21542 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21543 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21544 | GIR_EraseFromParent, /*InsnID*/0, |
| 21545 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 21546 | // GIR_Coverage, 5237, |
| 21547 | GIR_Done, |
| 21548 | // Label 1108: @53646 |
| 21549 | GIM_Try, /*On fail goto*//*Label 1109*/ 53680, // Rule ID 5238 // |
| 21550 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21551 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 21552 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21553 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21554 | // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8bf16] }:$src) => FPR128:{ *:[v4i32] }:$src |
| 21555 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21556 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21557 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21558 | GIR_EraseFromParent, /*InsnID*/0, |
| 21559 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 21560 | // GIR_Coverage, 5238, |
| 21561 | GIR_Done, |
| 21562 | // Label 1109: @53680 |
| 21563 | GIM_Try, /*On fail goto*//*Label 1110*/ 53751, // Rule ID 5239 // |
| 21564 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21565 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, |
| 21566 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21567 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21568 | // (bitconvert:{ *:[v4i32] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v4i32] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] }) |
| 21569 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 21570 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 21571 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v4i32, |
| 21572 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 21573 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21574 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 21575 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v4i32, |
| 21576 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 21577 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21578 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21579 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, |
| 21580 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 21581 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 21582 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 21583 | GIR_AddImm, /*InsnID*/0, /*Imm*/8, |
| 21584 | GIR_EraseFromParent, /*InsnID*/0, |
| 21585 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21586 | // GIR_Coverage, 5239, |
| 21587 | GIR_Done, |
| 21588 | // Label 1110: @53751 |
| 21589 | GIM_Try, /*On fail goto*//*Label 1111*/ 53774, // Rule ID 5240 // |
| 21590 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21591 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 21592 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21593 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21594 | // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2i64] }:$src) => (REV64v4i32:{ *:[v4i32] } FPR128:{ *:[v2i64] }:$src) |
| 21595 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, |
| 21596 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21597 | // GIR_Coverage, 5240, |
| 21598 | GIR_Done, |
| 21599 | // Label 1111: @53774 |
| 21600 | GIM_Try, /*On fail goto*//*Label 1112*/ 53797, // Rule ID 5241 // |
| 21601 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21602 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 21603 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21604 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21605 | // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8i16] }:$src) => (REV32v8i16:{ *:[v4i32] } FPR128:{ *:[v8i16] }:$src) |
| 21606 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, |
| 21607 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21608 | // GIR_Coverage, 5241, |
| 21609 | GIR_Done, |
| 21610 | // Label 1112: @53797 |
| 21611 | GIM_Try, /*On fail goto*//*Label 1113*/ 53820, // Rule ID 5242 // |
| 21612 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21613 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 21614 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21615 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21616 | // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v16i8] }:$src) => (REV32v16i8:{ *:[v4i32] } FPR128:{ *:[v16i8] }:$src) |
| 21617 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v16i8, |
| 21618 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21619 | // GIR_Coverage, 5242, |
| 21620 | GIR_Done, |
| 21621 | // Label 1113: @53820 |
| 21622 | GIM_Try, /*On fail goto*//*Label 1114*/ 53843, // Rule ID 5243 // |
| 21623 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21624 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 21625 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21626 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21627 | // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2f64] }:$src) => (REV64v4i32:{ *:[v4i32] } FPR128:{ *:[v2f64] }:$src) |
| 21628 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, |
| 21629 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21630 | // GIR_Coverage, 5243, |
| 21631 | GIR_Done, |
| 21632 | // Label 1114: @53843 |
| 21633 | GIM_Try, /*On fail goto*//*Label 1115*/ 53866, // Rule ID 5244 // |
| 21634 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21635 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 21636 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21637 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21638 | // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8f16] }:$src) => (REV32v8i16:{ *:[v4i32] } FPR128:{ *:[v8f16] }:$src) |
| 21639 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, |
| 21640 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21641 | // GIR_Coverage, 5244, |
| 21642 | GIR_Done, |
| 21643 | // Label 1115: @53866 |
| 21644 | GIM_Try, /*On fail goto*//*Label 1116*/ 53889, // Rule ID 5245 // |
| 21645 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21646 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 21647 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21648 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21649 | // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8bf16] }:$src) => (REV32v8i16:{ *:[v4i32] } FPR128:{ *:[v8bf16] }:$src) |
| 21650 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, |
| 21651 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21652 | // GIR_Coverage, 5245, |
| 21653 | GIR_Done, |
| 21654 | // Label 1116: @53889 |
| 21655 | GIM_Try, /*On fail goto*//*Label 1117*/ 53921, // Rule ID 5246 // |
| 21656 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 21657 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21658 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21659 | // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v4i32] }:$src |
| 21660 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21661 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21662 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21663 | GIR_EraseFromParent, /*InsnID*/0, |
| 21664 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 21665 | // GIR_Coverage, 5246, |
| 21666 | GIR_Done, |
| 21667 | // Label 1117: @53921 |
| 21668 | GIM_Reject, |
| 21669 | // Label 894: @53922 |
| 21670 | GIM_Try, /*On fail goto*//*Label 1118*/ 53947, // Rule ID 5007 // |
| 21671 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21672 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 21673 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21674 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 21675 | // (bitconvert:{ *:[v8i8] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v8i8] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }) |
| 21676 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21677 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 21678 | // GIR_Coverage, 5007, |
| 21679 | GIR_Done, |
| 21680 | // Label 1118: @53947 |
| 21681 | GIM_Try, /*On fail goto*//*Label 1119*/ 53995, // Rule ID 5020 // |
| 21682 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21683 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 21684 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21685 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 21686 | // (bitconvert:{ *:[v8i8] } GPR64:{ *:[i64] }:$Xn) => (REV64v8i8:{ *:[v8i8] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })) |
| 21687 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 21688 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 21689 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 21690 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn |
| 21691 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21692 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::REV64v8i8, |
| 21693 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 21694 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 21695 | GIR_EraseFromParent, /*InsnID*/0, |
| 21696 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21697 | // GIR_Coverage, 5020, |
| 21698 | GIR_Done, |
| 21699 | // Label 1119: @53995 |
| 21700 | GIM_Try, /*On fail goto*//*Label 1120*/ 54029, // Rule ID 5112 // |
| 21701 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21702 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 21703 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21704 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21705 | // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v8i8] }:$src |
| 21706 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21707 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21708 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21709 | GIR_EraseFromParent, /*InsnID*/0, |
| 21710 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 21711 | // GIR_Coverage, 5112, |
| 21712 | GIR_Done, |
| 21713 | // Label 1120: @54029 |
| 21714 | GIM_Try, /*On fail goto*//*Label 1121*/ 54063, // Rule ID 5113 // |
| 21715 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21716 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 21717 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21718 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21719 | // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v8i8] }:$src |
| 21720 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21721 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21722 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21723 | GIR_EraseFromParent, /*InsnID*/0, |
| 21724 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 21725 | // GIR_Coverage, 5113, |
| 21726 | GIR_Done, |
| 21727 | // Label 1121: @54063 |
| 21728 | GIM_Try, /*On fail goto*//*Label 1122*/ 54097, // Rule ID 5114 // |
| 21729 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21730 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 21731 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21732 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21733 | // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v8i8] }:$src |
| 21734 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21735 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21736 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21737 | GIR_EraseFromParent, /*InsnID*/0, |
| 21738 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 21739 | // GIR_Coverage, 5114, |
| 21740 | GIR_Done, |
| 21741 | // Label 1122: @54097 |
| 21742 | GIM_Try, /*On fail goto*//*Label 1123*/ 54131, // Rule ID 5115 // |
| 21743 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21744 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 21745 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21746 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21747 | // (bitconvert:{ *:[v8i8] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v8i8] }:$src |
| 21748 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21749 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21750 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21751 | GIR_EraseFromParent, /*InsnID*/0, |
| 21752 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 21753 | // GIR_Coverage, 5115, |
| 21754 | GIR_Done, |
| 21755 | // Label 1123: @54131 |
| 21756 | GIM_Try, /*On fail goto*//*Label 1124*/ 54165, // Rule ID 5116 // |
| 21757 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21758 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 21759 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21760 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21761 | // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v8i8] }:$src |
| 21762 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21763 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21764 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21765 | GIR_EraseFromParent, /*InsnID*/0, |
| 21766 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 21767 | // GIR_Coverage, 5116, |
| 21768 | GIR_Done, |
| 21769 | // Label 1124: @54165 |
| 21770 | GIM_Try, /*On fail goto*//*Label 1125*/ 54199, // Rule ID 5117 // |
| 21771 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21772 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 21773 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21774 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21775 | // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v8i8] }:$src |
| 21776 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21777 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21778 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21779 | GIR_EraseFromParent, /*InsnID*/0, |
| 21780 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 21781 | // GIR_Coverage, 5117, |
| 21782 | GIR_Done, |
| 21783 | // Label 1125: @54199 |
| 21784 | GIM_Try, /*On fail goto*//*Label 1126*/ 54233, // Rule ID 5118 // |
| 21785 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21786 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 21787 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21788 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21789 | // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v8i8] }:$src |
| 21790 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21791 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21792 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21793 | GIR_EraseFromParent, /*InsnID*/0, |
| 21794 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 21795 | // GIR_Coverage, 5118, |
| 21796 | GIR_Done, |
| 21797 | // Label 1126: @54233 |
| 21798 | GIM_Try, /*On fail goto*//*Label 1127*/ 54267, // Rule ID 5119 // |
| 21799 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21800 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 21801 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21802 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21803 | // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4bf16] }:$src) => FPR64:{ *:[v8i8] }:$src |
| 21804 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21805 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21806 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21807 | GIR_EraseFromParent, /*InsnID*/0, |
| 21808 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 21809 | // GIR_Coverage, 5119, |
| 21810 | GIR_Done, |
| 21811 | // Label 1127: @54267 |
| 21812 | GIM_Try, /*On fail goto*//*Label 1128*/ 54290, // Rule ID 5120 // |
| 21813 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21814 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 21815 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21816 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21817 | // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1i64] }:$src) => (REV64v8i8:{ *:[v8i8] } FPR64:{ *:[v1i64] }:$src) |
| 21818 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i8, |
| 21819 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21820 | // GIR_Coverage, 5120, |
| 21821 | GIR_Done, |
| 21822 | // Label 1128: @54290 |
| 21823 | GIM_Try, /*On fail goto*//*Label 1129*/ 54313, // Rule ID 5121 // |
| 21824 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21825 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 21826 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21827 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21828 | // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2i32] }:$src) => (REV32v8i8:{ *:[v8i8] } FPR64:{ *:[v2i32] }:$src) |
| 21829 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i8, |
| 21830 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21831 | // GIR_Coverage, 5121, |
| 21832 | GIR_Done, |
| 21833 | // Label 1129: @54313 |
| 21834 | GIM_Try, /*On fail goto*//*Label 1130*/ 54336, // Rule ID 5122 // |
| 21835 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21836 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 21837 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21838 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21839 | // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4i16] }:$src) => (REV16v8i8:{ *:[v8i8] } FPR64:{ *:[v4i16] }:$src) |
| 21840 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v8i8, |
| 21841 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21842 | // GIR_Coverage, 5122, |
| 21843 | GIR_Done, |
| 21844 | // Label 1130: @54336 |
| 21845 | GIM_Try, /*On fail goto*//*Label 1131*/ 54359, // Rule ID 5123 // |
| 21846 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21847 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 21848 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21849 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21850 | // (bitconvert:{ *:[v8i8] } FPR64:{ *:[f64] }:$src) => (REV64v8i8:{ *:[v8i8] } FPR64:{ *:[f64] }:$src) |
| 21851 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i8, |
| 21852 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21853 | // GIR_Coverage, 5123, |
| 21854 | GIR_Done, |
| 21855 | // Label 1131: @54359 |
| 21856 | GIM_Try, /*On fail goto*//*Label 1132*/ 54382, // Rule ID 5124 // |
| 21857 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21858 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 21859 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21860 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21861 | // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2f32] }:$src) => (REV32v8i8:{ *:[v8i8] } FPR64:{ *:[v2f32] }:$src) |
| 21862 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i8, |
| 21863 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21864 | // GIR_Coverage, 5124, |
| 21865 | GIR_Done, |
| 21866 | // Label 1132: @54382 |
| 21867 | GIM_Try, /*On fail goto*//*Label 1133*/ 54405, // Rule ID 5125 // |
| 21868 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21869 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 21870 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21871 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21872 | // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1f64] }:$src) => (REV64v8i8:{ *:[v8i8] } FPR64:{ *:[v1f64] }:$src) |
| 21873 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i8, |
| 21874 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21875 | // GIR_Coverage, 5125, |
| 21876 | GIR_Done, |
| 21877 | // Label 1133: @54405 |
| 21878 | GIM_Try, /*On fail goto*//*Label 1134*/ 54428, // Rule ID 5126 // |
| 21879 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21880 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 21881 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21882 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21883 | // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4f16] }:$src) => (REV16v8i8:{ *:[v8i8] } FPR64:{ *:[v4f16] }:$src) |
| 21884 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v8i8, |
| 21885 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21886 | // GIR_Coverage, 5126, |
| 21887 | GIR_Done, |
| 21888 | // Label 1134: @54428 |
| 21889 | GIM_Try, /*On fail goto*//*Label 1135*/ 54451, // Rule ID 5127 // |
| 21890 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21891 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 21892 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 21893 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 21894 | // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4bf16] }:$src) => (REV16v8i8:{ *:[v8i8] } FPR64:{ *:[v4bf16] }:$src) |
| 21895 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v8i8, |
| 21896 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21897 | // GIR_Coverage, 5127, |
| 21898 | GIR_Done, |
| 21899 | // Label 1135: @54451 |
| 21900 | GIM_Reject, |
| 21901 | // Label 895: @54452 |
| 21902 | GIM_Try, /*On fail goto*//*Label 1136*/ 54486, // Rule ID 5247 // |
| 21903 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21904 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, |
| 21905 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21906 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21907 | // (bitconvert:{ *:[v8i16] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v8i16] }:$src |
| 21908 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21909 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21910 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21911 | GIR_EraseFromParent, /*InsnID*/0, |
| 21912 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 21913 | // GIR_Coverage, 5247, |
| 21914 | GIR_Done, |
| 21915 | // Label 1136: @54486 |
| 21916 | GIM_Try, /*On fail goto*//*Label 1137*/ 54520, // Rule ID 5248 // |
| 21917 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21918 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 21919 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21920 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21921 | // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v8i16] }:$src |
| 21922 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21923 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21924 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21925 | GIR_EraseFromParent, /*InsnID*/0, |
| 21926 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 21927 | // GIR_Coverage, 5248, |
| 21928 | GIR_Done, |
| 21929 | // Label 1137: @54520 |
| 21930 | GIM_Try, /*On fail goto*//*Label 1138*/ 54554, // Rule ID 5249 // |
| 21931 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21932 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 21933 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21934 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21935 | // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v8i16] }:$src |
| 21936 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21937 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21938 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21939 | GIR_EraseFromParent, /*InsnID*/0, |
| 21940 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 21941 | // GIR_Coverage, 5249, |
| 21942 | GIR_Done, |
| 21943 | // Label 1138: @54554 |
| 21944 | GIM_Try, /*On fail goto*//*Label 1139*/ 54588, // Rule ID 5250 // |
| 21945 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21946 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 21947 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21948 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21949 | // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v8i16] }:$src |
| 21950 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21951 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21952 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21953 | GIR_EraseFromParent, /*InsnID*/0, |
| 21954 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 21955 | // GIR_Coverage, 5250, |
| 21956 | GIR_Done, |
| 21957 | // Label 1139: @54588 |
| 21958 | GIM_Try, /*On fail goto*//*Label 1140*/ 54622, // Rule ID 5251 // |
| 21959 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21960 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 21961 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21962 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21963 | // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v8i16] }:$src |
| 21964 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21965 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21966 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21967 | GIR_EraseFromParent, /*InsnID*/0, |
| 21968 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 21969 | // GIR_Coverage, 5251, |
| 21970 | GIR_Done, |
| 21971 | // Label 1140: @54622 |
| 21972 | GIM_Try, /*On fail goto*//*Label 1141*/ 54656, // Rule ID 5252 // |
| 21973 | GIM_CheckFeatures, GIFBS_IsLE, |
| 21974 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 21975 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21976 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21977 | // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v8i16] }:$src |
| 21978 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 21979 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 21980 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21981 | GIR_EraseFromParent, /*InsnID*/0, |
| 21982 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 21983 | // GIR_Coverage, 5252, |
| 21984 | GIR_Done, |
| 21985 | // Label 1141: @54656 |
| 21986 | GIM_Try, /*On fail goto*//*Label 1142*/ 54727, // Rule ID 5253 // |
| 21987 | GIM_CheckFeatures, GIFBS_IsBE, |
| 21988 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, |
| 21989 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 21990 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 21991 | // (bitconvert:{ *:[v8i16] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v8i16] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] }) |
| 21992 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 21993 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 21994 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v8i16, |
| 21995 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 21996 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21997 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 21998 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v8i16, |
| 21999 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 22000 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22001 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22002 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, |
| 22003 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 22004 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 22005 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 22006 | GIR_AddImm, /*InsnID*/0, /*Imm*/8, |
| 22007 | GIR_EraseFromParent, /*InsnID*/0, |
| 22008 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22009 | // GIR_Coverage, 5253, |
| 22010 | GIR_Done, |
| 22011 | // Label 1142: @54727 |
| 22012 | GIM_Try, /*On fail goto*//*Label 1143*/ 54750, // Rule ID 5254 // |
| 22013 | GIM_CheckFeatures, GIFBS_IsBE, |
| 22014 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22015 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22016 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22017 | // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2i64] }:$src) => (REV64v8i16:{ *:[v8i16] } FPR128:{ *:[v2i64] }:$src) |
| 22018 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, |
| 22019 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22020 | // GIR_Coverage, 5254, |
| 22021 | GIR_Done, |
| 22022 | // Label 1143: @54750 |
| 22023 | GIM_Try, /*On fail goto*//*Label 1144*/ 54773, // Rule ID 5255 // |
| 22024 | GIM_CheckFeatures, GIFBS_IsBE, |
| 22025 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22026 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22027 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22028 | // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4i32] }:$src) => (REV32v8i16:{ *:[v8i16] } FPR128:{ *:[v4i32] }:$src) |
| 22029 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, |
| 22030 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22031 | // GIR_Coverage, 5255, |
| 22032 | GIR_Done, |
| 22033 | // Label 1144: @54773 |
| 22034 | GIM_Try, /*On fail goto*//*Label 1145*/ 54796, // Rule ID 5256 // |
| 22035 | GIM_CheckFeatures, GIFBS_IsBE, |
| 22036 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 22037 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22038 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22039 | // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v16i8] }:$src) => (REV16v16i8:{ *:[v8i16] } FPR128:{ *:[v16i8] }:$src) |
| 22040 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v16i8, |
| 22041 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22042 | // GIR_Coverage, 5256, |
| 22043 | GIR_Done, |
| 22044 | // Label 1145: @54796 |
| 22045 | GIM_Try, /*On fail goto*//*Label 1146*/ 54819, // Rule ID 5257 // |
| 22046 | GIM_CheckFeatures, GIFBS_IsBE, |
| 22047 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22048 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22049 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22050 | // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2f64] }:$src) => (REV64v8i16:{ *:[v8i16] } FPR128:{ *:[v2f64] }:$src) |
| 22051 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, |
| 22052 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22053 | // GIR_Coverage, 5257, |
| 22054 | GIR_Done, |
| 22055 | // Label 1146: @54819 |
| 22056 | GIM_Try, /*On fail goto*//*Label 1147*/ 54842, // Rule ID 5258 // |
| 22057 | GIM_CheckFeatures, GIFBS_IsBE, |
| 22058 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22059 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22060 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22061 | // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4f32] }:$src) => (REV32v8i16:{ *:[v8i16] } FPR128:{ *:[v4f32] }:$src) |
| 22062 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, |
| 22063 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22064 | // GIR_Coverage, 5258, |
| 22065 | GIR_Done, |
| 22066 | // Label 1147: @54842 |
| 22067 | GIM_Try, /*On fail goto*//*Label 1148*/ 54874, // Rule ID 5259 // |
| 22068 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 22069 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22070 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22071 | // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v8i16] }:$src |
| 22072 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 22073 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 22074 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22075 | GIR_EraseFromParent, /*InsnID*/0, |
| 22076 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 22077 | // GIR_Coverage, 5259, |
| 22078 | GIR_Done, |
| 22079 | // Label 1148: @54874 |
| 22080 | GIM_Try, /*On fail goto*//*Label 1149*/ 54906, // Rule ID 5260 // |
| 22081 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 22082 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22083 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22084 | // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v8bf16] }:$src) => FPR128:{ *:[v8i16] }:$src |
| 22085 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 22086 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 22087 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22088 | GIR_EraseFromParent, /*InsnID*/0, |
| 22089 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 22090 | // GIR_Coverage, 5260, |
| 22091 | GIR_Done, |
| 22092 | // Label 1149: @54906 |
| 22093 | GIM_Try, /*On fail goto*//*Label 1150*/ 54940, // Rule ID 5261 // |
| 22094 | GIM_CheckFeatures, GIFBS_IsLE, |
| 22095 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, |
| 22096 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22097 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22098 | // (bitconvert:{ *:[v8f16] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v8f16] }:$src |
| 22099 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 22100 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 22101 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22102 | GIR_EraseFromParent, /*InsnID*/0, |
| 22103 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 22104 | // GIR_Coverage, 5261, |
| 22105 | GIR_Done, |
| 22106 | // Label 1150: @54940 |
| 22107 | GIM_Try, /*On fail goto*//*Label 1151*/ 54974, // Rule ID 5262 // |
| 22108 | GIM_CheckFeatures, GIFBS_IsLE, |
| 22109 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22110 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22111 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22112 | // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v8f16] }:$src |
| 22113 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 22114 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 22115 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22116 | GIR_EraseFromParent, /*InsnID*/0, |
| 22117 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 22118 | // GIR_Coverage, 5262, |
| 22119 | GIR_Done, |
| 22120 | // Label 1151: @54974 |
| 22121 | GIM_Try, /*On fail goto*//*Label 1152*/ 55008, // Rule ID 5263 // |
| 22122 | GIM_CheckFeatures, GIFBS_IsLE, |
| 22123 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22124 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22125 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22126 | // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v8f16] }:$src |
| 22127 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 22128 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 22129 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22130 | GIR_EraseFromParent, /*InsnID*/0, |
| 22131 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 22132 | // GIR_Coverage, 5263, |
| 22133 | GIR_Done, |
| 22134 | // Label 1152: @55008 |
| 22135 | GIM_Try, /*On fail goto*//*Label 1153*/ 55042, // Rule ID 5264 // |
| 22136 | GIM_CheckFeatures, GIFBS_IsLE, |
| 22137 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 22138 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22139 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22140 | // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v8f16] }:$src |
| 22141 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 22142 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 22143 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22144 | GIR_EraseFromParent, /*InsnID*/0, |
| 22145 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 22146 | // GIR_Coverage, 5264, |
| 22147 | GIR_Done, |
| 22148 | // Label 1153: @55042 |
| 22149 | GIM_Try, /*On fail goto*//*Label 1154*/ 55076, // Rule ID 5265 // |
| 22150 | GIM_CheckFeatures, GIFBS_IsLE, |
| 22151 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22152 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22153 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22154 | // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v8f16] }:$src |
| 22155 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 22156 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 22157 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22158 | GIR_EraseFromParent, /*InsnID*/0, |
| 22159 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 22160 | // GIR_Coverage, 5265, |
| 22161 | GIR_Done, |
| 22162 | // Label 1154: @55076 |
| 22163 | GIM_Try, /*On fail goto*//*Label 1155*/ 55110, // Rule ID 5266 // |
| 22164 | GIM_CheckFeatures, GIFBS_IsLE, |
| 22165 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22166 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22167 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22168 | // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v8f16] }:$src |
| 22169 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 22170 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 22171 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22172 | GIR_EraseFromParent, /*InsnID*/0, |
| 22173 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 22174 | // GIR_Coverage, 5266, |
| 22175 | GIR_Done, |
| 22176 | // Label 1155: @55110 |
| 22177 | GIM_Try, /*On fail goto*//*Label 1156*/ 55144, // Rule ID 5267 // |
| 22178 | GIM_CheckFeatures, GIFBS_IsLE, |
| 22179 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, |
| 22180 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22181 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22182 | // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v8bf16] }:$src |
| 22183 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 22184 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 22185 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22186 | GIR_EraseFromParent, /*InsnID*/0, |
| 22187 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 22188 | // GIR_Coverage, 5267, |
| 22189 | GIR_Done, |
| 22190 | // Label 1156: @55144 |
| 22191 | GIM_Try, /*On fail goto*//*Label 1157*/ 55178, // Rule ID 5268 // |
| 22192 | GIM_CheckFeatures, GIFBS_IsLE, |
| 22193 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22194 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22195 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22196 | // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v8bf16] }:$src |
| 22197 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 22198 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 22199 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22200 | GIR_EraseFromParent, /*InsnID*/0, |
| 22201 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 22202 | // GIR_Coverage, 5268, |
| 22203 | GIR_Done, |
| 22204 | // Label 1157: @55178 |
| 22205 | GIM_Try, /*On fail goto*//*Label 1158*/ 55212, // Rule ID 5269 // |
| 22206 | GIM_CheckFeatures, GIFBS_IsLE, |
| 22207 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22208 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22209 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22210 | // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v8bf16] }:$src |
| 22211 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 22212 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 22213 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22214 | GIR_EraseFromParent, /*InsnID*/0, |
| 22215 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 22216 | // GIR_Coverage, 5269, |
| 22217 | GIR_Done, |
| 22218 | // Label 1158: @55212 |
| 22219 | GIM_Try, /*On fail goto*//*Label 1159*/ 55246, // Rule ID 5270 // |
| 22220 | GIM_CheckFeatures, GIFBS_IsLE, |
| 22221 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 22222 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22223 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22224 | // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v8bf16] }:$src |
| 22225 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 22226 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 22227 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22228 | GIR_EraseFromParent, /*InsnID*/0, |
| 22229 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 22230 | // GIR_Coverage, 5270, |
| 22231 | GIR_Done, |
| 22232 | // Label 1159: @55246 |
| 22233 | GIM_Try, /*On fail goto*//*Label 1160*/ 55280, // Rule ID 5271 // |
| 22234 | GIM_CheckFeatures, GIFBS_IsLE, |
| 22235 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22236 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22237 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22238 | // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v8bf16] }:$src |
| 22239 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 22240 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 22241 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22242 | GIR_EraseFromParent, /*InsnID*/0, |
| 22243 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 22244 | // GIR_Coverage, 5271, |
| 22245 | GIR_Done, |
| 22246 | // Label 1160: @55280 |
| 22247 | GIM_Try, /*On fail goto*//*Label 1161*/ 55314, // Rule ID 5272 // |
| 22248 | GIM_CheckFeatures, GIFBS_IsLE, |
| 22249 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22250 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22251 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22252 | // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v8bf16] }:$src |
| 22253 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 22254 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 22255 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22256 | GIR_EraseFromParent, /*InsnID*/0, |
| 22257 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 22258 | // GIR_Coverage, 5272, |
| 22259 | GIR_Done, |
| 22260 | // Label 1161: @55314 |
| 22261 | GIM_Try, /*On fail goto*//*Label 1162*/ 55385, // Rule ID 5273 // |
| 22262 | GIM_CheckFeatures, GIFBS_IsBE, |
| 22263 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, |
| 22264 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22265 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22266 | // (bitconvert:{ *:[v8f16] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v8f16] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] }) |
| 22267 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 22268 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 22269 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v8i16, |
| 22270 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 22271 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22272 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 22273 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v8i16, |
| 22274 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 22275 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22276 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22277 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, |
| 22278 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 22279 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 22280 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 22281 | GIR_AddImm, /*InsnID*/0, /*Imm*/8, |
| 22282 | GIR_EraseFromParent, /*InsnID*/0, |
| 22283 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22284 | // GIR_Coverage, 5273, |
| 22285 | GIR_Done, |
| 22286 | // Label 1162: @55385 |
| 22287 | GIM_Try, /*On fail goto*//*Label 1163*/ 55408, // Rule ID 5274 // |
| 22288 | GIM_CheckFeatures, GIFBS_IsBE, |
| 22289 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22290 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22291 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22292 | // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2i64] }:$src) => (REV64v8i16:{ *:[v8f16] } FPR128:{ *:[v2i64] }:$src) |
| 22293 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, |
| 22294 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22295 | // GIR_Coverage, 5274, |
| 22296 | GIR_Done, |
| 22297 | // Label 1163: @55408 |
| 22298 | GIM_Try, /*On fail goto*//*Label 1164*/ 55431, // Rule ID 5275 // |
| 22299 | GIM_CheckFeatures, GIFBS_IsBE, |
| 22300 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22301 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22302 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22303 | // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4i32] }:$src) => (REV32v8i16:{ *:[v8f16] } FPR128:{ *:[v4i32] }:$src) |
| 22304 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, |
| 22305 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22306 | // GIR_Coverage, 5275, |
| 22307 | GIR_Done, |
| 22308 | // Label 1164: @55431 |
| 22309 | GIM_Try, /*On fail goto*//*Label 1165*/ 55454, // Rule ID 5276 // |
| 22310 | GIM_CheckFeatures, GIFBS_IsBE, |
| 22311 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 22312 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22313 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22314 | // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v16i8] }:$src) => (REV16v16i8:{ *:[v8f16] } FPR128:{ *:[v16i8] }:$src) |
| 22315 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v16i8, |
| 22316 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22317 | // GIR_Coverage, 5276, |
| 22318 | GIR_Done, |
| 22319 | // Label 1165: @55454 |
| 22320 | GIM_Try, /*On fail goto*//*Label 1166*/ 55477, // Rule ID 5277 // |
| 22321 | GIM_CheckFeatures, GIFBS_IsBE, |
| 22322 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22323 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22324 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22325 | // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2f64] }:$src) => (REV64v8i16:{ *:[v8f16] } FPR128:{ *:[v2f64] }:$src) |
| 22326 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, |
| 22327 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22328 | // GIR_Coverage, 5277, |
| 22329 | GIR_Done, |
| 22330 | // Label 1166: @55477 |
| 22331 | GIM_Try, /*On fail goto*//*Label 1167*/ 55500, // Rule ID 5278 // |
| 22332 | GIM_CheckFeatures, GIFBS_IsBE, |
| 22333 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22334 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22335 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22336 | // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4f32] }:$src) => (REV32v8i16:{ *:[v8f16] } FPR128:{ *:[v4f32] }:$src) |
| 22337 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, |
| 22338 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22339 | // GIR_Coverage, 5278, |
| 22340 | GIR_Done, |
| 22341 | // Label 1167: @55500 |
| 22342 | GIM_Try, /*On fail goto*//*Label 1168*/ 55571, // Rule ID 5279 // |
| 22343 | GIM_CheckFeatures, GIFBS_IsBE, |
| 22344 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, |
| 22345 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22346 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22347 | // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v8bf16] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] }) |
| 22348 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 22349 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 22350 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v8i16, |
| 22351 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 22352 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22353 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 22354 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v8i16, |
| 22355 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 22356 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22357 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22358 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, |
| 22359 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 22360 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 22361 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 22362 | GIR_AddImm, /*InsnID*/0, /*Imm*/8, |
| 22363 | GIR_EraseFromParent, /*InsnID*/0, |
| 22364 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22365 | // GIR_Coverage, 5279, |
| 22366 | GIR_Done, |
| 22367 | // Label 1168: @55571 |
| 22368 | GIM_Try, /*On fail goto*//*Label 1169*/ 55594, // Rule ID 5280 // |
| 22369 | GIM_CheckFeatures, GIFBS_IsBE, |
| 22370 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22371 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22372 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22373 | // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v2i64] }:$src) => (REV64v8i16:{ *:[v8bf16] } FPR128:{ *:[v2i64] }:$src) |
| 22374 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, |
| 22375 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22376 | // GIR_Coverage, 5280, |
| 22377 | GIR_Done, |
| 22378 | // Label 1169: @55594 |
| 22379 | GIM_Try, /*On fail goto*//*Label 1170*/ 55617, // Rule ID 5281 // |
| 22380 | GIM_CheckFeatures, GIFBS_IsBE, |
| 22381 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22382 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22383 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22384 | // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v4i32] }:$src) => (REV32v8i16:{ *:[v8bf16] } FPR128:{ *:[v4i32] }:$src) |
| 22385 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, |
| 22386 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22387 | // GIR_Coverage, 5281, |
| 22388 | GIR_Done, |
| 22389 | // Label 1170: @55617 |
| 22390 | GIM_Try, /*On fail goto*//*Label 1171*/ 55640, // Rule ID 5282 // |
| 22391 | GIM_CheckFeatures, GIFBS_IsBE, |
| 22392 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 22393 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22394 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22395 | // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v16i8] }:$src) => (REV16v16i8:{ *:[v8bf16] } FPR128:{ *:[v16i8] }:$src) |
| 22396 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v16i8, |
| 22397 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22398 | // GIR_Coverage, 5282, |
| 22399 | GIR_Done, |
| 22400 | // Label 1171: @55640 |
| 22401 | GIM_Try, /*On fail goto*//*Label 1172*/ 55663, // Rule ID 5283 // |
| 22402 | GIM_CheckFeatures, GIFBS_IsBE, |
| 22403 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22404 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22405 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22406 | // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v2f64] }:$src) => (REV64v8i16:{ *:[v8bf16] } FPR128:{ *:[v2f64] }:$src) |
| 22407 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, |
| 22408 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22409 | // GIR_Coverage, 5283, |
| 22410 | GIR_Done, |
| 22411 | // Label 1172: @55663 |
| 22412 | GIM_Try, /*On fail goto*//*Label 1173*/ 55686, // Rule ID 5284 // |
| 22413 | GIM_CheckFeatures, GIFBS_IsBE, |
| 22414 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22415 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22416 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22417 | // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v4f32] }:$src) => (REV32v8i16:{ *:[v8bf16] } FPR128:{ *:[v4f32] }:$src) |
| 22418 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, |
| 22419 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22420 | // GIR_Coverage, 5284, |
| 22421 | GIR_Done, |
| 22422 | // Label 1173: @55686 |
| 22423 | GIM_Try, /*On fail goto*//*Label 1174*/ 55718, // Rule ID 5285 // |
| 22424 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 22425 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22426 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22427 | // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v8f16] }:$src |
| 22428 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 22429 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 22430 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22431 | GIR_EraseFromParent, /*InsnID*/0, |
| 22432 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 22433 | // GIR_Coverage, 5285, |
| 22434 | GIR_Done, |
| 22435 | // Label 1174: @55718 |
| 22436 | GIM_Try, /*On fail goto*//*Label 1175*/ 55750, // Rule ID 5286 // |
| 22437 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 22438 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22439 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22440 | // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v8bf16] }:$src |
| 22441 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 22442 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 22443 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22444 | GIR_EraseFromParent, /*InsnID*/0, |
| 22445 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 22446 | // GIR_Coverage, 5286, |
| 22447 | GIR_Done, |
| 22448 | // Label 1175: @55750 |
| 22449 | GIM_Reject, |
| 22450 | // Label 896: @55751 |
| 22451 | GIM_Try, /*On fail goto*//*Label 1176*/ 55785, // Rule ID 5287 // |
| 22452 | GIM_CheckFeatures, GIFBS_IsLE, |
| 22453 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, |
| 22454 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22455 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22456 | // (bitconvert:{ *:[v16i8] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v16i8] }:$src |
| 22457 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 22458 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 22459 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22460 | GIR_EraseFromParent, /*InsnID*/0, |
| 22461 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 22462 | // GIR_Coverage, 5287, |
| 22463 | GIR_Done, |
| 22464 | // Label 1176: @55785 |
| 22465 | GIM_Try, /*On fail goto*//*Label 1177*/ 55819, // Rule ID 5288 // |
| 22466 | GIM_CheckFeatures, GIFBS_IsLE, |
| 22467 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22468 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22469 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22470 | // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v16i8] }:$src |
| 22471 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 22472 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 22473 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22474 | GIR_EraseFromParent, /*InsnID*/0, |
| 22475 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 22476 | // GIR_Coverage, 5288, |
| 22477 | GIR_Done, |
| 22478 | // Label 1177: @55819 |
| 22479 | GIM_Try, /*On fail goto*//*Label 1178*/ 55853, // Rule ID 5289 // |
| 22480 | GIM_CheckFeatures, GIFBS_IsLE, |
| 22481 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22482 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22483 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22484 | // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v16i8] }:$src |
| 22485 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 22486 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 22487 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22488 | GIR_EraseFromParent, /*InsnID*/0, |
| 22489 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 22490 | // GIR_Coverage, 5289, |
| 22491 | GIR_Done, |
| 22492 | // Label 1178: @55853 |
| 22493 | GIM_Try, /*On fail goto*//*Label 1179*/ 55887, // Rule ID 5290 // |
| 22494 | GIM_CheckFeatures, GIFBS_IsLE, |
| 22495 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 22496 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22497 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22498 | // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v16i8] }:$src |
| 22499 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 22500 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 22501 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22502 | GIR_EraseFromParent, /*InsnID*/0, |
| 22503 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 22504 | // GIR_Coverage, 5290, |
| 22505 | GIR_Done, |
| 22506 | // Label 1179: @55887 |
| 22507 | GIM_Try, /*On fail goto*//*Label 1180*/ 55921, // Rule ID 5291 // |
| 22508 | GIM_CheckFeatures, GIFBS_IsLE, |
| 22509 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22510 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22511 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22512 | // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v16i8] }:$src |
| 22513 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 22514 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 22515 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22516 | GIR_EraseFromParent, /*InsnID*/0, |
| 22517 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 22518 | // GIR_Coverage, 5291, |
| 22519 | GIR_Done, |
| 22520 | // Label 1180: @55921 |
| 22521 | GIM_Try, /*On fail goto*//*Label 1181*/ 55955, // Rule ID 5292 // |
| 22522 | GIM_CheckFeatures, GIFBS_IsLE, |
| 22523 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22524 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22525 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22526 | // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v16i8] }:$src |
| 22527 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 22528 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 22529 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22530 | GIR_EraseFromParent, /*InsnID*/0, |
| 22531 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 22532 | // GIR_Coverage, 5292, |
| 22533 | GIR_Done, |
| 22534 | // Label 1181: @55955 |
| 22535 | GIM_Try, /*On fail goto*//*Label 1182*/ 55989, // Rule ID 5293 // |
| 22536 | GIM_CheckFeatures, GIFBS_IsLE, |
| 22537 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 22538 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22539 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22540 | // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v16i8] }:$src |
| 22541 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 22542 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 22543 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22544 | GIR_EraseFromParent, /*InsnID*/0, |
| 22545 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 22546 | // GIR_Coverage, 5293, |
| 22547 | GIR_Done, |
| 22548 | // Label 1182: @55989 |
| 22549 | GIM_Try, /*On fail goto*//*Label 1183*/ 56023, // Rule ID 5294 // |
| 22550 | GIM_CheckFeatures, GIFBS_IsLE, |
| 22551 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 22552 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22553 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22554 | // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8bf16] }:$src) => FPR128:{ *:[v16i8] }:$src |
| 22555 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 22556 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 22557 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22558 | GIR_EraseFromParent, /*InsnID*/0, |
| 22559 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR128RegClassID, |
| 22560 | // GIR_Coverage, 5294, |
| 22561 | GIR_Done, |
| 22562 | // Label 1183: @56023 |
| 22563 | GIM_Try, /*On fail goto*//*Label 1184*/ 56094, // Rule ID 5295 // |
| 22564 | GIM_CheckFeatures, GIFBS_IsBE, |
| 22565 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s128, |
| 22566 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22567 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22568 | // (bitconvert:{ *:[v16i8] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v16i8] } (REV64v16i8:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v16i8:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] }) |
| 22569 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 22570 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 22571 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::REV64v16i8, |
| 22572 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 22573 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22574 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 22575 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::REV64v16i8, |
| 22576 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 22577 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 22578 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22579 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, |
| 22580 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 22581 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 22582 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 22583 | GIR_AddImm, /*InsnID*/0, /*Imm*/8, |
| 22584 | GIR_EraseFromParent, /*InsnID*/0, |
| 22585 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22586 | // GIR_Coverage, 5295, |
| 22587 | GIR_Done, |
| 22588 | // Label 1184: @56094 |
| 22589 | GIM_Try, /*On fail goto*//*Label 1185*/ 56117, // Rule ID 5296 // |
| 22590 | GIM_CheckFeatures, GIFBS_IsBE, |
| 22591 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22592 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22593 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22594 | // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2i64] }:$src) => (REV64v16i8:{ *:[v16i8] } FPR128:{ *:[v2i64] }:$src) |
| 22595 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v16i8, |
| 22596 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22597 | // GIR_Coverage, 5296, |
| 22598 | GIR_Done, |
| 22599 | // Label 1185: @56117 |
| 22600 | GIM_Try, /*On fail goto*//*Label 1186*/ 56140, // Rule ID 5297 // |
| 22601 | GIM_CheckFeatures, GIFBS_IsBE, |
| 22602 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22603 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22604 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22605 | // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4i32] }:$src) => (REV32v16i8:{ *:[v16i8] } FPR128:{ *:[v4i32] }:$src) |
| 22606 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v16i8, |
| 22607 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22608 | // GIR_Coverage, 5297, |
| 22609 | GIR_Done, |
| 22610 | // Label 1186: @56140 |
| 22611 | GIM_Try, /*On fail goto*//*Label 1187*/ 56163, // Rule ID 5298 // |
| 22612 | GIM_CheckFeatures, GIFBS_IsBE, |
| 22613 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 22614 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22615 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22616 | // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8i16] }:$src) => (REV16v16i8:{ *:[v16i8] } FPR128:{ *:[v8i16] }:$src) |
| 22617 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v16i8, |
| 22618 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22619 | // GIR_Coverage, 5298, |
| 22620 | GIR_Done, |
| 22621 | // Label 1187: @56163 |
| 22622 | GIM_Try, /*On fail goto*//*Label 1188*/ 56186, // Rule ID 5299 // |
| 22623 | GIM_CheckFeatures, GIFBS_IsBE, |
| 22624 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22625 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22626 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22627 | // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2f64] }:$src) => (REV64v16i8:{ *:[v16i8] } FPR128:{ *:[v2f64] }:$src) |
| 22628 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v16i8, |
| 22629 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22630 | // GIR_Coverage, 5299, |
| 22631 | GIR_Done, |
| 22632 | // Label 1188: @56186 |
| 22633 | GIM_Try, /*On fail goto*//*Label 1189*/ 56209, // Rule ID 5300 // |
| 22634 | GIM_CheckFeatures, GIFBS_IsBE, |
| 22635 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22636 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22637 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22638 | // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4f32] }:$src) => (REV32v16i8:{ *:[v16i8] } FPR128:{ *:[v4f32] }:$src) |
| 22639 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v16i8, |
| 22640 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22641 | // GIR_Coverage, 5300, |
| 22642 | GIR_Done, |
| 22643 | // Label 1189: @56209 |
| 22644 | GIM_Try, /*On fail goto*//*Label 1190*/ 56232, // Rule ID 5301 // |
| 22645 | GIM_CheckFeatures, GIFBS_IsBE, |
| 22646 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 22647 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22648 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22649 | // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8f16] }:$src) => (REV16v16i8:{ *:[v16i8] } FPR128:{ *:[v8f16] }:$src) |
| 22650 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v16i8, |
| 22651 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22652 | // GIR_Coverage, 5301, |
| 22653 | GIR_Done, |
| 22654 | // Label 1190: @56232 |
| 22655 | GIM_Try, /*On fail goto*//*Label 1191*/ 56255, // Rule ID 5302 // |
| 22656 | GIM_CheckFeatures, GIFBS_IsBE, |
| 22657 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 22658 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22659 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22660 | // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8bf16] }:$src) => (REV16v16i8:{ *:[v16i8] } FPR128:{ *:[v8bf16] }:$src) |
| 22661 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v16i8, |
| 22662 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22663 | // GIR_Coverage, 5302, |
| 22664 | GIR_Done, |
| 22665 | // Label 1191: @56255 |
| 22666 | GIM_Reject, |
| 22667 | // Label 897: @56256 |
| 22668 | GIM_Reject, |
| 22669 | // Label 10: @56257 |
| 22670 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 1200*/ 56465, |
| 22671 | /*GILLT_s16*//*Label 1192*/ 56273, |
| 22672 | /*GILLT_s32*//*Label 1193*/ 56297, |
| 22673 | /*GILLT_s64*//*Label 1194*/ 56321, 0, |
| 22674 | /*GILLT_v2s32*//*Label 1195*/ 56345, |
| 22675 | /*GILLT_v2s64*//*Label 1196*/ 56369, |
| 22676 | /*GILLT_v4s16*//*Label 1197*/ 56393, |
| 22677 | /*GILLT_v4s32*//*Label 1198*/ 56417, 0, |
| 22678 | /*GILLT_v8s16*//*Label 1199*/ 56441, |
| 22679 | // Label 1192: @56273 |
| 22680 | GIM_Try, /*On fail goto*//*Label 1201*/ 56296, // Rule ID 510 // |
| 22681 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 22682 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 22683 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 22684 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 22685 | // (ftrunc:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FRINTZHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) |
| 22686 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTZHr, |
| 22687 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22688 | // GIR_Coverage, 510, |
| 22689 | GIR_Done, |
| 22690 | // Label 1201: @56296 |
| 22691 | GIM_Reject, |
| 22692 | // Label 1193: @56297 |
| 22693 | GIM_Try, /*On fail goto*//*Label 1202*/ 56320, // Rule ID 511 // |
| 22694 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 22695 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 22696 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 22697 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 22698 | // (ftrunc:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FRINTZSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) |
| 22699 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTZSr, |
| 22700 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22701 | // GIR_Coverage, 511, |
| 22702 | GIR_Done, |
| 22703 | // Label 1202: @56320 |
| 22704 | GIM_Reject, |
| 22705 | // Label 1194: @56321 |
| 22706 | GIM_Try, /*On fail goto*//*Label 1203*/ 56344, // Rule ID 512 // |
| 22707 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 22708 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 22709 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 22710 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 22711 | // (ftrunc:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FRINTZDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) |
| 22712 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTZDr, |
| 22713 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22714 | // GIR_Coverage, 512, |
| 22715 | GIR_Done, |
| 22716 | // Label 1203: @56344 |
| 22717 | GIM_Reject, |
| 22718 | // Label 1195: @56345 |
| 22719 | GIM_Try, /*On fail goto*//*Label 1204*/ 56368, // Rule ID 776 // |
| 22720 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 22721 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 22722 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 22723 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 22724 | // (ftrunc:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FRINTZv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) |
| 22725 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTZv2f32, |
| 22726 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22727 | // GIR_Coverage, 776, |
| 22728 | GIR_Done, |
| 22729 | // Label 1204: @56368 |
| 22730 | GIM_Reject, |
| 22731 | // Label 1196: @56369 |
| 22732 | GIM_Try, /*On fail goto*//*Label 1205*/ 56392, // Rule ID 778 // |
| 22733 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 22734 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22735 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22736 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22737 | // (ftrunc:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FRINTZv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) |
| 22738 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTZv2f64, |
| 22739 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22740 | // GIR_Coverage, 778, |
| 22741 | GIR_Done, |
| 22742 | // Label 1205: @56392 |
| 22743 | GIM_Reject, |
| 22744 | // Label 1197: @56393 |
| 22745 | GIM_Try, /*On fail goto*//*Label 1206*/ 56416, // Rule ID 774 // |
| 22746 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 22747 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 22748 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 22749 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 22750 | // (ftrunc:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FRINTZv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) |
| 22751 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTZv4f16, |
| 22752 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22753 | // GIR_Coverage, 774, |
| 22754 | GIR_Done, |
| 22755 | // Label 1206: @56416 |
| 22756 | GIM_Reject, |
| 22757 | // Label 1198: @56417 |
| 22758 | GIM_Try, /*On fail goto*//*Label 1207*/ 56440, // Rule ID 777 // |
| 22759 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 22760 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22761 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22762 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22763 | // (ftrunc:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FRINTZv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) |
| 22764 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTZv4f32, |
| 22765 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22766 | // GIR_Coverage, 777, |
| 22767 | GIR_Done, |
| 22768 | // Label 1207: @56440 |
| 22769 | GIM_Reject, |
| 22770 | // Label 1199: @56441 |
| 22771 | GIM_Try, /*On fail goto*//*Label 1208*/ 56464, // Rule ID 775 // |
| 22772 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 22773 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 22774 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22775 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22776 | // (ftrunc:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FRINTZv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) |
| 22777 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTZv8f16, |
| 22778 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22779 | // GIR_Coverage, 775, |
| 22780 | GIR_Done, |
| 22781 | // Label 1208: @56464 |
| 22782 | GIM_Reject, |
| 22783 | // Label 1200: @56465 |
| 22784 | GIM_Reject, |
| 22785 | // Label 11: @56466 |
| 22786 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 1217*/ 56674, |
| 22787 | /*GILLT_s16*//*Label 1209*/ 56482, |
| 22788 | /*GILLT_s32*//*Label 1210*/ 56506, |
| 22789 | /*GILLT_s64*//*Label 1211*/ 56530, 0, |
| 22790 | /*GILLT_v2s32*//*Label 1212*/ 56554, |
| 22791 | /*GILLT_v2s64*//*Label 1213*/ 56578, |
| 22792 | /*GILLT_v4s16*//*Label 1214*/ 56602, |
| 22793 | /*GILLT_v4s32*//*Label 1215*/ 56626, 0, |
| 22794 | /*GILLT_v8s16*//*Label 1216*/ 56650, |
| 22795 | // Label 1209: @56482 |
| 22796 | GIM_Try, /*On fail goto*//*Label 1218*/ 56505, // Rule ID 492 // |
| 22797 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 22798 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 22799 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 22800 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 22801 | // (fround:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FRINTAHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) |
| 22802 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTAHr, |
| 22803 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22804 | // GIR_Coverage, 492, |
| 22805 | GIR_Done, |
| 22806 | // Label 1218: @56505 |
| 22807 | GIM_Reject, |
| 22808 | // Label 1210: @56506 |
| 22809 | GIM_Try, /*On fail goto*//*Label 1219*/ 56529, // Rule ID 493 // |
| 22810 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 22811 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 22812 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 22813 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 22814 | // (fround:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FRINTASr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) |
| 22815 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTASr, |
| 22816 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22817 | // GIR_Coverage, 493, |
| 22818 | GIR_Done, |
| 22819 | // Label 1219: @56529 |
| 22820 | GIM_Reject, |
| 22821 | // Label 1211: @56530 |
| 22822 | GIM_Try, /*On fail goto*//*Label 1220*/ 56553, // Rule ID 494 // |
| 22823 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 22824 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 22825 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 22826 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 22827 | // (fround:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FRINTADr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) |
| 22828 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTADr, |
| 22829 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22830 | // GIR_Coverage, 494, |
| 22831 | GIR_Done, |
| 22832 | // Label 1220: @56553 |
| 22833 | GIM_Reject, |
| 22834 | // Label 1212: @56554 |
| 22835 | GIM_Try, /*On fail goto*//*Label 1221*/ 56577, // Rule ID 746 // |
| 22836 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 22837 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 22838 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 22839 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 22840 | // (fround:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FRINTAv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) |
| 22841 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTAv2f32, |
| 22842 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22843 | // GIR_Coverage, 746, |
| 22844 | GIR_Done, |
| 22845 | // Label 1221: @56577 |
| 22846 | GIM_Reject, |
| 22847 | // Label 1213: @56578 |
| 22848 | GIM_Try, /*On fail goto*//*Label 1222*/ 56601, // Rule ID 748 // |
| 22849 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 22850 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22851 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22852 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22853 | // (fround:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FRINTAv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) |
| 22854 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTAv2f64, |
| 22855 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22856 | // GIR_Coverage, 748, |
| 22857 | GIR_Done, |
| 22858 | // Label 1222: @56601 |
| 22859 | GIM_Reject, |
| 22860 | // Label 1214: @56602 |
| 22861 | GIM_Try, /*On fail goto*//*Label 1223*/ 56625, // Rule ID 744 // |
| 22862 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 22863 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 22864 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 22865 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 22866 | // (fround:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FRINTAv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) |
| 22867 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTAv4f16, |
| 22868 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22869 | // GIR_Coverage, 744, |
| 22870 | GIR_Done, |
| 22871 | // Label 1223: @56625 |
| 22872 | GIM_Reject, |
| 22873 | // Label 1215: @56626 |
| 22874 | GIM_Try, /*On fail goto*//*Label 1224*/ 56649, // Rule ID 747 // |
| 22875 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 22876 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22877 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22878 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22879 | // (fround:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FRINTAv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) |
| 22880 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTAv4f32, |
| 22881 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22882 | // GIR_Coverage, 747, |
| 22883 | GIR_Done, |
| 22884 | // Label 1224: @56649 |
| 22885 | GIM_Reject, |
| 22886 | // Label 1216: @56650 |
| 22887 | GIM_Try, /*On fail goto*//*Label 1225*/ 56673, // Rule ID 745 // |
| 22888 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 22889 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 22890 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 22891 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 22892 | // (fround:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FRINTAv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) |
| 22893 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTAv8f16, |
| 22894 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22895 | // GIR_Coverage, 745, |
| 22896 | GIR_Done, |
| 22897 | // Label 1225: @56673 |
| 22898 | GIM_Reject, |
| 22899 | // Label 1217: @56674 |
| 22900 | GIM_Reject, |
| 22901 | // Label 12: @56675 |
| 22902 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1228*/ 56941, |
| 22903 | /*GILLT_s32*//*Label 1226*/ 56683, |
| 22904 | /*GILLT_s64*//*Label 1227*/ 56812, |
| 22905 | // Label 1226: @56683 |
| 22906 | GIM_Try, /*On fail goto*//*Label 1229*/ 56727, // Rule ID 3945 // |
| 22907 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 22908 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 22909 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 22910 | // (lrint:{ *:[i32] } f16:{ *:[f16] }:$Rn) => (FCVTZSUWHr:{ *:[i32] } (FRINTXHr:{ *:[bf16] } f16:{ *:[f16] }:$Rn)) |
| 22911 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 22912 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::FRINTXHr, |
| 22913 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 22914 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 22915 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22916 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSUWHr, |
| 22917 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 22918 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 22919 | GIR_EraseFromParent, /*InsnID*/0, |
| 22920 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22921 | // GIR_Coverage, 3945, |
| 22922 | GIR_Done, |
| 22923 | // Label 1229: @56727 |
| 22924 | GIM_Try, /*On fail goto*//*Label 1230*/ 56769, // Rule ID 3948 // |
| 22925 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 22926 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 22927 | // (lrint:{ *:[i32] } f32:{ *:[f32] }:$Rn) => (FCVTZSUWSr:{ *:[i32] } (FRINTXSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)) |
| 22928 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 22929 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::FRINTXSr, |
| 22930 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 22931 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 22932 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22933 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSUWSr, |
| 22934 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 22935 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 22936 | GIR_EraseFromParent, /*InsnID*/0, |
| 22937 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22938 | // GIR_Coverage, 3948, |
| 22939 | GIR_Done, |
| 22940 | // Label 1230: @56769 |
| 22941 | GIM_Try, /*On fail goto*//*Label 1231*/ 56811, // Rule ID 3949 // |
| 22942 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 22943 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 22944 | // (lrint:{ *:[i32] } f64:{ *:[f64] }:$Rn) => (FCVTZSUWDr:{ *:[i32] } (FRINTXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)) |
| 22945 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 22946 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::FRINTXDr, |
| 22947 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 22948 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 22949 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22950 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSUWDr, |
| 22951 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 22952 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 22953 | GIR_EraseFromParent, /*InsnID*/0, |
| 22954 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22955 | // GIR_Coverage, 3949, |
| 22956 | GIR_Done, |
| 22957 | // Label 1231: @56811 |
| 22958 | GIM_Reject, |
| 22959 | // Label 1227: @56812 |
| 22960 | GIM_Try, /*On fail goto*//*Label 1232*/ 56856, // Rule ID 3946 // |
| 22961 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 22962 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 22963 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 22964 | // (lrint:{ *:[i64] } f16:{ *:[f16] }:$Rn) => (FCVTZSUXHr:{ *:[i64] } (FRINTXHr:{ *:[bf16] } f16:{ *:[f16] }:$Rn)) |
| 22965 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 22966 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::FRINTXHr, |
| 22967 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 22968 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 22969 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22970 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSUXHr, |
| 22971 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 22972 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 22973 | GIR_EraseFromParent, /*InsnID*/0, |
| 22974 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22975 | // GIR_Coverage, 3946, |
| 22976 | GIR_Done, |
| 22977 | // Label 1232: @56856 |
| 22978 | GIM_Try, /*On fail goto*//*Label 1233*/ 56898, // Rule ID 3950 // |
| 22979 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 22980 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 22981 | // (lrint:{ *:[i64] } f32:{ *:[f32] }:$Rn) => (FCVTZSUXSr:{ *:[i64] } (FRINTXSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)) |
| 22982 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 22983 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::FRINTXSr, |
| 22984 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 22985 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 22986 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22987 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSUXSr, |
| 22988 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 22989 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 22990 | GIR_EraseFromParent, /*InsnID*/0, |
| 22991 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22992 | // GIR_Coverage, 3950, |
| 22993 | GIR_Done, |
| 22994 | // Label 1233: @56898 |
| 22995 | GIM_Try, /*On fail goto*//*Label 1234*/ 56940, // Rule ID 3951 // |
| 22996 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 22997 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 22998 | // (lrint:{ *:[i64] } f64:{ *:[f64] }:$Rn) => (FCVTZSUXDr:{ *:[i64] } (FRINTXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)) |
| 22999 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 23000 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::FRINTXDr, |
| 23001 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 23002 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 23003 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23004 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSUXDr, |
| 23005 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 23006 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 23007 | GIR_EraseFromParent, /*InsnID*/0, |
| 23008 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23009 | // GIR_Coverage, 3951, |
| 23010 | GIR_Done, |
| 23011 | // Label 1234: @56940 |
| 23012 | GIM_Reject, |
| 23013 | // Label 1228: @56941 |
| 23014 | GIM_Reject, |
| 23015 | // Label 13: @56942 |
| 23016 | GIM_Try, /*On fail goto*//*Label 1235*/ 56969, // Rule ID 3450 // |
| 23017 | GIM_CheckFeatures, GIFBS_HasPerfMon, |
| 23018 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 23019 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 23020 | // (readcyclecounter:{ *:[i64] }) => (MRS:{ *:[i64] } 56552:{ *:[i32] }) |
| 23021 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MRS, |
| 23022 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23023 | GIR_AddImm, /*InsnID*/0, /*Imm*/56552, |
| 23024 | GIR_EraseFromParent, /*InsnID*/0, |
| 23025 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23026 | // GIR_Coverage, 3450, |
| 23027 | GIR_Done, |
| 23028 | // Label 1235: @56969 |
| 23029 | GIM_Reject, |
| 23030 | // Label 14: @56970 |
| 23031 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 11, /*)*//*default:*//*Label 1247*/ 63711, |
| 23032 | /*GILLT_s16*//*Label 1236*/ 56987, |
| 23033 | /*GILLT_s32*//*Label 1237*/ 57169, |
| 23034 | /*GILLT_s64*//*Label 1238*/ 58883, |
| 23035 | /*GILLT_s128*//*Label 1239*/ 61195, |
| 23036 | /*GILLT_v2s32*//*Label 1240*/ 61377, |
| 23037 | /*GILLT_v2s64*//*Label 1241*/ 61721, |
| 23038 | /*GILLT_v4s16*//*Label 1242*/ 62065, |
| 23039 | /*GILLT_v4s32*//*Label 1243*/ 62528, |
| 23040 | /*GILLT_v8s8*//*Label 1244*/ 62872, |
| 23041 | /*GILLT_v8s16*//*Label 1245*/ 63060, |
| 23042 | /*GILLT_v16s8*//*Label 1246*/ 63523, |
| 23043 | // Label 1236: @56987 |
| 23044 | GIM_Try, /*On fail goto*//*Label 1248*/ 57168, |
| 23045 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23046 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23047 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 23048 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23049 | GIM_Try, /*On fail goto*//*Label 1249*/ 57039, // Rule ID 223 // |
| 23050 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, |
| 23051 | // (ld:{ *:[f16] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRHroW:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend) |
| 23052 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHroW, |
| 23053 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23054 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23055 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23056 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23057 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23058 | GIR_EraseFromParent, /*InsnID*/0, |
| 23059 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23060 | // GIR_Coverage, 223, |
| 23061 | GIR_Done, |
| 23062 | // Label 1249: @57039 |
| 23063 | GIM_Try, /*On fail goto*//*Label 1250*/ 57074, // Rule ID 224 // |
| 23064 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, |
| 23065 | // (ld:{ *:[f16] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRHroX:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend) |
| 23066 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHroX, |
| 23067 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23068 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23069 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23070 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23071 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23072 | GIR_EraseFromParent, /*InsnID*/0, |
| 23073 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23074 | // GIR_Coverage, 224, |
| 23075 | GIR_Done, |
| 23076 | // Label 1250: @57074 |
| 23077 | GIM_Try, /*On fail goto*//*Label 1251*/ 57105, // Rule ID 246 // |
| 23078 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, |
| 23079 | // (ld:{ *:[f16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRHui:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) |
| 23080 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHui, |
| 23081 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23082 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23083 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 23084 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23085 | GIR_EraseFromParent, /*InsnID*/0, |
| 23086 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23087 | // GIR_Coverage, 246, |
| 23088 | GIR_Done, |
| 23089 | // Label 1251: @57105 |
| 23090 | GIM_Try, /*On fail goto*//*Label 1252*/ 57136, // Rule ID 267 // |
| 23091 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, |
| 23092 | // (ld:{ *:[f16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURHi:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) |
| 23093 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHi, |
| 23094 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23095 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23096 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 23097 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23098 | GIR_EraseFromParent, /*InsnID*/0, |
| 23099 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23100 | // GIR_Coverage, 267, |
| 23101 | GIR_Done, |
| 23102 | // Label 1252: @57136 |
| 23103 | GIM_Try, /*On fail goto*//*Label 1253*/ 57167, // Rule ID 3668 // |
| 23104 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, |
| 23105 | // (ld:{ *:[bf16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRHui:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) |
| 23106 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHui, |
| 23107 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23108 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23109 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 23110 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23111 | GIR_EraseFromParent, /*InsnID*/0, |
| 23112 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23113 | // GIR_Coverage, 3668, |
| 23114 | GIR_Done, |
| 23115 | // Label 1253: @57167 |
| 23116 | GIM_Reject, |
| 23117 | // Label 1248: @57168 |
| 23118 | GIM_Reject, |
| 23119 | // Label 1237: @57169 |
| 23120 | GIM_Try, /*On fail goto*//*Label 1254*/ 57219, // Rule ID 217 // |
| 23121 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23122 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23123 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23124 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23125 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, |
| 23126 | // (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend) |
| 23127 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWroW, |
| 23128 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23129 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23130 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23131 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23132 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23133 | GIR_EraseFromParent, /*InsnID*/0, |
| 23134 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23135 | // GIR_Coverage, 217, |
| 23136 | GIR_Done, |
| 23137 | // Label 1254: @57219 |
| 23138 | GIM_Try, /*On fail goto*//*Label 1255*/ 57269, // Rule ID 218 // |
| 23139 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23140 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23141 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23142 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23143 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, |
| 23144 | // (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend) |
| 23145 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWroX, |
| 23146 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23147 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23148 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23149 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23150 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23151 | GIR_EraseFromParent, /*InsnID*/0, |
| 23152 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23153 | // GIR_Coverage, 218, |
| 23154 | GIR_Done, |
| 23155 | // Label 1255: @57269 |
| 23156 | GIM_Try, /*On fail goto*//*Label 1256*/ 57319, // Rule ID 225 // |
| 23157 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23158 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23159 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 23160 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23161 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, |
| 23162 | // (ld:{ *:[f32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRSroW:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend) |
| 23163 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSroW, |
| 23164 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23165 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23166 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23167 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23168 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23169 | GIR_EraseFromParent, /*InsnID*/0, |
| 23170 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23171 | // GIR_Coverage, 225, |
| 23172 | GIR_Done, |
| 23173 | // Label 1256: @57319 |
| 23174 | GIM_Try, /*On fail goto*//*Label 1257*/ 57369, // Rule ID 226 // |
| 23175 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23176 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23177 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 23178 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23179 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, |
| 23180 | // (ld:{ *:[f32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRSroX:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend) |
| 23181 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSroX, |
| 23182 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23183 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23184 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23185 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23186 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23187 | GIR_EraseFromParent, /*InsnID*/0, |
| 23188 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23189 | // GIR_Coverage, 226, |
| 23190 | GIR_Done, |
| 23191 | // Label 1257: @57369 |
| 23192 | GIM_Try, /*On fail goto*//*Label 1258*/ 57423, // Rule ID 3660 // |
| 23193 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23194 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 23195 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23196 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23197 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23198 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, |
| 23199 | // (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend) |
| 23200 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroW, |
| 23201 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23202 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23203 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23204 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23205 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23206 | GIR_EraseFromParent, /*InsnID*/0, |
| 23207 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23208 | // GIR_Coverage, 3660, |
| 23209 | GIR_Done, |
| 23210 | // Label 1258: @57423 |
| 23211 | GIM_Try, /*On fail goto*//*Label 1259*/ 57477, // Rule ID 3661 // |
| 23212 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23213 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 23214 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23215 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23216 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23217 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, |
| 23218 | // (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend) |
| 23219 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroX, |
| 23220 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23221 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23222 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23223 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23224 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23225 | GIR_EraseFromParent, /*InsnID*/0, |
| 23226 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23227 | // GIR_Coverage, 3661, |
| 23228 | GIR_Done, |
| 23229 | // Label 1259: @57477 |
| 23230 | GIM_Try, /*On fail goto*//*Label 1260*/ 57531, // Rule ID 3662 // |
| 23231 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23232 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 23233 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23234 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23235 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23236 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, |
| 23237 | // (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend) |
| 23238 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHroW, |
| 23239 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23240 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23241 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23242 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23243 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23244 | GIR_EraseFromParent, /*InsnID*/0, |
| 23245 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23246 | // GIR_Coverage, 3662, |
| 23247 | GIR_Done, |
| 23248 | // Label 1260: @57531 |
| 23249 | GIM_Try, /*On fail goto*//*Label 1261*/ 57585, // Rule ID 3663 // |
| 23250 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23251 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 23252 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23253 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23254 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23255 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, |
| 23256 | // (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend) |
| 23257 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHroX, |
| 23258 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23259 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23260 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23261 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23262 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23263 | GIR_EraseFromParent, /*InsnID*/0, |
| 23264 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23265 | // GIR_Coverage, 3663, |
| 23266 | GIR_Done, |
| 23267 | // Label 1261: @57585 |
| 23268 | GIM_Try, /*On fail goto*//*Label 1262*/ 57639, // Rule ID 3664 // |
| 23269 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23270 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 23271 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23272 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23273 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23274 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, |
| 23275 | // (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> => (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend) |
| 23276 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWroW, |
| 23277 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23278 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23279 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23280 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23281 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23282 | GIR_EraseFromParent, /*InsnID*/0, |
| 23283 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23284 | // GIR_Coverage, 3664, |
| 23285 | GIR_Done, |
| 23286 | // Label 1262: @57639 |
| 23287 | GIM_Try, /*On fail goto*//*Label 1263*/ 57693, // Rule ID 3665 // |
| 23288 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23289 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 23290 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23291 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23292 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23293 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, |
| 23294 | // (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> => (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend) |
| 23295 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWroX, |
| 23296 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23297 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23298 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23299 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23300 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23301 | GIR_EraseFromParent, /*InsnID*/0, |
| 23302 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23303 | // GIR_Coverage, 3665, |
| 23304 | GIR_Done, |
| 23305 | // Label 1263: @57693 |
| 23306 | GIM_Try, /*On fail goto*//*Label 1264*/ 57739, // Rule ID 244 // |
| 23307 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23308 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23309 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23310 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23311 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, |
| 23312 | // (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) |
| 23313 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWui, |
| 23314 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23315 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23316 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 23317 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23318 | GIR_EraseFromParent, /*InsnID*/0, |
| 23319 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23320 | // GIR_Coverage, 244, |
| 23321 | GIR_Done, |
| 23322 | // Label 1264: @57739 |
| 23323 | GIM_Try, /*On fail goto*//*Label 1265*/ 57785, // Rule ID 247 // |
| 23324 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23325 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23326 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 23327 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23328 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, |
| 23329 | // (ld:{ *:[f32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRSui:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) |
| 23330 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSui, |
| 23331 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23332 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23333 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 23334 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23335 | GIR_EraseFromParent, /*InsnID*/0, |
| 23336 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23337 | // GIR_Coverage, 247, |
| 23338 | GIR_Done, |
| 23339 | // Label 1265: @57785 |
| 23340 | GIM_Try, /*On fail goto*//*Label 1266*/ 57838, // Rule ID 5369 // |
| 23341 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 23342 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 23343 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 23344 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23345 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23346 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, |
| 23347 | // (atomic_load:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_anonymous_7071>> => (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$offset) |
| 23348 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroW, |
| 23349 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23350 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23351 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23352 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // offset |
| 23353 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23354 | GIR_EraseFromParent, /*InsnID*/0, |
| 23355 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23356 | // GIR_Coverage, 5369, |
| 23357 | GIR_Done, |
| 23358 | // Label 1266: @57838 |
| 23359 | GIM_Try, /*On fail goto*//*Label 1267*/ 57891, // Rule ID 5370 // |
| 23360 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 23361 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 23362 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 23363 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23364 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23365 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, |
| 23366 | // (atomic_load:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_anonymous_7071>> => (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$offset) |
| 23367 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroX, |
| 23368 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23370 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23371 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // offset |
| 23372 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23373 | GIR_EraseFromParent, /*InsnID*/0, |
| 23374 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23375 | // GIR_Coverage, 5370, |
| 23376 | GIR_Done, |
| 23377 | // Label 1267: @57891 |
| 23378 | GIM_Try, /*On fail goto*//*Label 1268*/ 57944, // Rule ID 5374 // |
| 23379 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 23380 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 23381 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 23382 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23383 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23384 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, |
| 23385 | // (atomic_load:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_16>><<P:Predicate_anonymous_7078>> => (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend) |
| 23386 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHroW, |
| 23387 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23388 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23389 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23390 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23391 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23392 | GIR_EraseFromParent, /*InsnID*/0, |
| 23393 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23394 | // GIR_Coverage, 5374, |
| 23395 | GIR_Done, |
| 23396 | // Label 1268: @57944 |
| 23397 | GIM_Try, /*On fail goto*//*Label 1269*/ 57997, // Rule ID 5375 // |
| 23398 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 23399 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 23400 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 23401 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23402 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23403 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, |
| 23404 | // (atomic_load:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_16>><<P:Predicate_anonymous_7078>> => (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend) |
| 23405 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHroX, |
| 23406 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23407 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23408 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23409 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23410 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23411 | GIR_EraseFromParent, /*InsnID*/0, |
| 23412 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23413 | // GIR_Coverage, 5375, |
| 23414 | GIR_Done, |
| 23415 | // Label 1269: @57997 |
| 23416 | GIM_Try, /*On fail goto*//*Label 1270*/ 58050, // Rule ID 5379 // |
| 23417 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 23418 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 23419 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 23420 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23421 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23422 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, |
| 23423 | // (atomic_load:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_32>><<P:Predicate_anonymous_7085>> => (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend) |
| 23424 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWroW, |
| 23425 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23426 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23427 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23428 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23429 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23430 | GIR_EraseFromParent, /*InsnID*/0, |
| 23431 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23432 | // GIR_Coverage, 5379, |
| 23433 | GIR_Done, |
| 23434 | // Label 1270: @58050 |
| 23435 | GIM_Try, /*On fail goto*//*Label 1271*/ 58103, // Rule ID 5380 // |
| 23436 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 23437 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 23438 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 23439 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23440 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23441 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, |
| 23442 | // (atomic_load:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_32>><<P:Predicate_anonymous_7085>> => (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend) |
| 23443 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWroX, |
| 23444 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23445 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23446 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23447 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23448 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23449 | GIR_EraseFromParent, /*InsnID*/0, |
| 23450 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23451 | // GIR_Coverage, 5380, |
| 23452 | GIR_Done, |
| 23453 | // Label 1271: @58103 |
| 23454 | GIM_Try, /*On fail goto*//*Label 1272*/ 58149, // Rule ID 265 // |
| 23455 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23456 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23457 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23458 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23459 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, |
| 23460 | // (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) |
| 23461 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURWi, |
| 23462 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23463 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23464 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 23465 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23466 | GIR_EraseFromParent, /*InsnID*/0, |
| 23467 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23468 | // GIR_Coverage, 265, |
| 23469 | GIR_Done, |
| 23470 | // Label 1272: @58149 |
| 23471 | GIM_Try, /*On fail goto*//*Label 1273*/ 58195, // Rule ID 268 // |
| 23472 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23473 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23474 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 23475 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23476 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, |
| 23477 | // (ld:{ *:[f32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURSi:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) |
| 23478 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSi, |
| 23479 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23480 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23481 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 23482 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23483 | GIR_EraseFromParent, /*InsnID*/0, |
| 23484 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23485 | // GIR_Coverage, 268, |
| 23486 | GIR_Done, |
| 23487 | // Label 1273: @58195 |
| 23488 | GIM_Try, /*On fail goto*//*Label 1274*/ 58244, // Rule ID 5371 // |
| 23489 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 23490 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 23491 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 23492 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23493 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23494 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, |
| 23495 | // (atomic_load:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_anonymous_7071>> => (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) |
| 23496 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui, |
| 23497 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23498 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23499 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 23500 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23501 | GIR_EraseFromParent, /*InsnID*/0, |
| 23502 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23503 | // GIR_Coverage, 5371, |
| 23504 | GIR_Done, |
| 23505 | // Label 1274: @58244 |
| 23506 | GIM_Try, /*On fail goto*//*Label 1275*/ 58293, // Rule ID 5372 // |
| 23507 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 23508 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 23509 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 23510 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23511 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23512 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, |
| 23513 | // (atomic_load:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_anonymous_7071>> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 23514 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi, |
| 23515 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23516 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23517 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 23518 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23519 | GIR_EraseFromParent, /*InsnID*/0, |
| 23520 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23521 | // GIR_Coverage, 5372, |
| 23522 | GIR_Done, |
| 23523 | // Label 1275: @58293 |
| 23524 | GIM_Try, /*On fail goto*//*Label 1276*/ 58342, // Rule ID 5376 // |
| 23525 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 23526 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 23527 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 23528 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23529 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23530 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, |
| 23531 | // (atomic_load:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_anonymous_7078>> => (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) |
| 23532 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHui, |
| 23533 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23534 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23535 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 23536 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23537 | GIR_EraseFromParent, /*InsnID*/0, |
| 23538 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23539 | // GIR_Coverage, 5376, |
| 23540 | GIR_Done, |
| 23541 | // Label 1276: @58342 |
| 23542 | GIM_Try, /*On fail goto*//*Label 1277*/ 58391, // Rule ID 5377 // |
| 23543 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 23544 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 23545 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 23546 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23547 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23548 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, |
| 23549 | // (atomic_load:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_anonymous_7078>> => (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 23550 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHHi, |
| 23551 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23552 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23553 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 23554 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23555 | GIR_EraseFromParent, /*InsnID*/0, |
| 23556 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23557 | // GIR_Coverage, 5377, |
| 23558 | GIR_Done, |
| 23559 | // Label 1277: @58391 |
| 23560 | GIM_Try, /*On fail goto*//*Label 1278*/ 58440, // Rule ID 5381 // |
| 23561 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 23562 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 23563 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 23564 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23565 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23566 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, |
| 23567 | // (atomic_load:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_32>><<P:Predicate_anonymous_7085>> => (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) |
| 23568 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRWui, |
| 23569 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23570 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23571 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 23572 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23573 | GIR_EraseFromParent, /*InsnID*/0, |
| 23574 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23575 | // GIR_Coverage, 5381, |
| 23576 | GIR_Done, |
| 23577 | // Label 1278: @58440 |
| 23578 | GIM_Try, /*On fail goto*//*Label 1279*/ 58489, // Rule ID 5382 // |
| 23579 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 23580 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 23581 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 23582 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23583 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23584 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, |
| 23585 | // (atomic_load:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_32>><<P:Predicate_anonymous_7085>> => (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 23586 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURWi, |
| 23587 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23588 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23589 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 23590 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23591 | GIR_EraseFromParent, /*InsnID*/0, |
| 23592 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23593 | // GIR_Coverage, 5382, |
| 23594 | GIR_Done, |
| 23595 | // Label 1279: @58489 |
| 23596 | GIM_Try, /*On fail goto*//*Label 1280*/ 58539, // Rule ID 3698 // |
| 23597 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23598 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 23599 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23600 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23601 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23602 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, |
| 23603 | // (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) |
| 23604 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHui, |
| 23605 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23606 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23607 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 23608 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23609 | GIR_EraseFromParent, /*InsnID*/0, |
| 23610 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23611 | // GIR_Coverage, 3698, |
| 23612 | GIR_Done, |
| 23613 | // Label 1280: @58539 |
| 23614 | GIM_Try, /*On fail goto*//*Label 1281*/ 58589, // Rule ID 3699 // |
| 23615 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23616 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 23617 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23618 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23619 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23620 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, |
| 23621 | // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) |
| 23622 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui, |
| 23623 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23624 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23625 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 23626 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23627 | GIR_EraseFromParent, /*InsnID*/0, |
| 23628 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23629 | // GIR_Coverage, 3699, |
| 23630 | GIR_Done, |
| 23631 | // Label 1281: @58589 |
| 23632 | GIM_Try, /*On fail goto*//*Label 1282*/ 58639, // Rule ID 3700 // |
| 23633 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23634 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 23635 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23636 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23637 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23638 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, |
| 23639 | // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>> => (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) |
| 23640 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui, |
| 23641 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23642 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23643 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 23644 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23645 | GIR_EraseFromParent, /*InsnID*/0, |
| 23646 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23647 | // GIR_Coverage, 3700, |
| 23648 | GIR_Done, |
| 23649 | // Label 1282: @58639 |
| 23650 | GIM_Try, /*On fail goto*//*Label 1283*/ 58689, // Rule ID 3721 // |
| 23651 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23652 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 23653 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23654 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23655 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23656 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, |
| 23657 | // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 23658 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHHi, |
| 23659 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23660 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23661 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 23662 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23663 | GIR_EraseFromParent, /*InsnID*/0, |
| 23664 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23665 | // GIR_Coverage, 3721, |
| 23666 | GIR_Done, |
| 23667 | // Label 1283: @58689 |
| 23668 | GIM_Try, /*On fail goto*//*Label 1284*/ 58739, // Rule ID 3722 // |
| 23669 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23670 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 23671 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23672 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23673 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23674 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, |
| 23675 | // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 23676 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi, |
| 23677 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23678 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23679 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 23680 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23681 | GIR_EraseFromParent, /*InsnID*/0, |
| 23682 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23683 | // GIR_Coverage, 3722, |
| 23684 | GIR_Done, |
| 23685 | // Label 1284: @58739 |
| 23686 | GIM_Try, /*On fail goto*//*Label 1285*/ 58789, // Rule ID 3723 // |
| 23687 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23688 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 23689 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23690 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23691 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23692 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, |
| 23693 | // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 23694 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi, |
| 23695 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23696 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23697 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 23698 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23699 | GIR_EraseFromParent, /*InsnID*/0, |
| 23700 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23701 | // GIR_Coverage, 3723, |
| 23702 | GIR_Done, |
| 23703 | // Label 1285: @58789 |
| 23704 | GIM_Try, /*On fail goto*//*Label 1286*/ 58820, // Rule ID 5368 // |
| 23705 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 23706 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 23707 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 23708 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23709 | // MIs[0] ptr |
| 23710 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 23711 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 23712 | // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_8>><<P:Predicate_anonymous_7069>> => (LDARB:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr) |
| 23713 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LDARB, |
| 23714 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23715 | // GIR_Coverage, 5368, |
| 23716 | GIR_Done, |
| 23717 | // Label 1286: @58820 |
| 23718 | GIM_Try, /*On fail goto*//*Label 1287*/ 58851, // Rule ID 5373 // |
| 23719 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 23720 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 23721 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 23722 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23723 | // MIs[0] ptr |
| 23724 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 23725 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 23726 | // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_16>><<P:Predicate_anonymous_7076>> => (LDARH:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr) |
| 23727 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LDARH, |
| 23728 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23729 | // GIR_Coverage, 5373, |
| 23730 | GIR_Done, |
| 23731 | // Label 1287: @58851 |
| 23732 | GIM_Try, /*On fail goto*//*Label 1288*/ 58882, // Rule ID 5378 // |
| 23733 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 23734 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 23735 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 23736 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 23737 | // MIs[0] ptr |
| 23738 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 23739 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 23740 | // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_32>><<P:Predicate_anonymous_7083>> => (LDARW:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr) |
| 23741 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LDARW, |
| 23742 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23743 | // GIR_Coverage, 5378, |
| 23744 | GIR_Done, |
| 23745 | // Label 1288: @58882 |
| 23746 | GIM_Reject, |
| 23747 | // Label 1238: @58883 |
| 23748 | GIM_Try, /*On fail goto*//*Label 1289*/ 58933, // Rule ID 219 // |
| 23749 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23750 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23751 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 23752 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23753 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, |
| 23754 | // (ld:{ *:[i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRXroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) |
| 23755 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRXroW, |
| 23756 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23757 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23758 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23759 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23760 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23761 | GIR_EraseFromParent, /*InsnID*/0, |
| 23762 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23763 | // GIR_Coverage, 219, |
| 23764 | GIR_Done, |
| 23765 | // Label 1289: @58933 |
| 23766 | GIM_Try, /*On fail goto*//*Label 1290*/ 58983, // Rule ID 220 // |
| 23767 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23768 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23769 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 23770 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23771 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, |
| 23772 | // (ld:{ *:[i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRXroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) |
| 23773 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRXroX, |
| 23774 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23775 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23776 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23778 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23779 | GIR_EraseFromParent, /*InsnID*/0, |
| 23780 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23781 | // GIR_Coverage, 220, |
| 23782 | GIR_Done, |
| 23783 | // Label 1290: @58983 |
| 23784 | GIM_Try, /*On fail goto*//*Label 1291*/ 59033, // Rule ID 227 // |
| 23785 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23786 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23787 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 23788 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23789 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, |
| 23790 | // (ld:{ *:[f64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroW:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) |
| 23791 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, |
| 23792 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23793 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23794 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23795 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23796 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23797 | GIR_EraseFromParent, /*InsnID*/0, |
| 23798 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23799 | // GIR_Coverage, 227, |
| 23800 | GIR_Done, |
| 23801 | // Label 1291: @59033 |
| 23802 | GIM_Try, /*On fail goto*//*Label 1292*/ 59083, // Rule ID 228 // |
| 23803 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23804 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23805 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 23806 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23807 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, |
| 23808 | // (ld:{ *:[f64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroX:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) |
| 23809 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, |
| 23810 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23811 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23813 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23814 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23815 | GIR_EraseFromParent, /*InsnID*/0, |
| 23816 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23817 | // GIR_Coverage, 228, |
| 23818 | GIR_Done, |
| 23819 | // Label 1292: @59083 |
| 23820 | GIM_Try, /*On fail goto*//*Label 1293*/ 59133, // Rule ID 3624 // |
| 23821 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23822 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23823 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 23824 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23825 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, |
| 23826 | // (ld:{ *:[v1i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroW:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) |
| 23827 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, |
| 23828 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23829 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23830 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23831 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23832 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23833 | GIR_EraseFromParent, /*InsnID*/0, |
| 23834 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23835 | // GIR_Coverage, 3624, |
| 23836 | GIR_Done, |
| 23837 | // Label 1293: @59133 |
| 23838 | GIM_Try, /*On fail goto*//*Label 1294*/ 59183, // Rule ID 3625 // |
| 23839 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23840 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23841 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 23842 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23843 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, |
| 23844 | // (ld:{ *:[v1i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroX:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) |
| 23845 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, |
| 23846 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23847 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23848 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23850 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23851 | GIR_EraseFromParent, /*InsnID*/0, |
| 23852 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23853 | // GIR_Coverage, 3625, |
| 23854 | GIR_Done, |
| 23855 | // Label 1294: @59183 |
| 23856 | GIM_Try, /*On fail goto*//*Label 1295*/ 59233, // Rule ID 3626 // |
| 23857 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23858 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23859 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 23860 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23861 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, |
| 23862 | // (ld:{ *:[v1f64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroW:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) |
| 23863 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, |
| 23864 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23865 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23866 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23867 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23868 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23869 | GIR_EraseFromParent, /*InsnID*/0, |
| 23870 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23871 | // GIR_Coverage, 3626, |
| 23872 | GIR_Done, |
| 23873 | // Label 1295: @59233 |
| 23874 | GIM_Try, /*On fail goto*//*Label 1296*/ 59283, // Rule ID 3627 // |
| 23875 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23876 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23877 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 23878 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23879 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, |
| 23880 | // (ld:{ *:[v1f64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroX:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) |
| 23881 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, |
| 23882 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 23883 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23884 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23885 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23886 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23887 | GIR_EraseFromParent, /*InsnID*/0, |
| 23888 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23889 | // GIR_Coverage, 3627, |
| 23890 | GIR_Done, |
| 23891 | // Label 1296: @59283 |
| 23892 | GIM_Try, /*On fail goto*//*Label 1297*/ 59365, // Rule ID 3652 // |
| 23893 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23894 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 23895 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23896 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 23897 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23898 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, |
| 23899 | // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) |
| 23900 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 23901 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroW, |
| 23902 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 23903 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23904 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23905 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23906 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23907 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23908 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 23909 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 23910 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 23911 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 23912 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 23913 | GIR_EraseFromParent, /*InsnID*/0, |
| 23914 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 23915 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 23916 | // GIR_Coverage, 3652, |
| 23917 | GIR_Done, |
| 23918 | // Label 1297: @59365 |
| 23919 | GIM_Try, /*On fail goto*//*Label 1298*/ 59447, // Rule ID 3653 // |
| 23920 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23921 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 23922 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23923 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 23924 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23925 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, |
| 23926 | // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) |
| 23927 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 23928 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroX, |
| 23929 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 23930 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23931 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23932 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23933 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23934 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23935 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 23936 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 23937 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 23938 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 23939 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 23940 | GIR_EraseFromParent, /*InsnID*/0, |
| 23941 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 23942 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 23943 | // GIR_Coverage, 3653, |
| 23944 | GIR_Done, |
| 23945 | // Label 1298: @59447 |
| 23946 | GIM_Try, /*On fail goto*//*Label 1299*/ 59529, // Rule ID 3654 // |
| 23947 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23948 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 23949 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23950 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 23951 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23952 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, |
| 23953 | // (ld:{ *:[i64] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) |
| 23954 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 23955 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRHHroW, |
| 23956 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 23957 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23958 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23959 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23960 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23961 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23962 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 23963 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 23964 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 23965 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 23966 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 23967 | GIR_EraseFromParent, /*InsnID*/0, |
| 23968 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 23969 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 23970 | // GIR_Coverage, 3654, |
| 23971 | GIR_Done, |
| 23972 | // Label 1299: @59529 |
| 23973 | GIM_Try, /*On fail goto*//*Label 1300*/ 59611, // Rule ID 3655 // |
| 23974 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23975 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 23976 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 23977 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 23978 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23979 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, |
| 23980 | // (ld:{ *:[i64] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) |
| 23981 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 23982 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRHHroX, |
| 23983 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 23984 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 23985 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 23986 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend |
| 23987 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 23988 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23989 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 23990 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 23991 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 23992 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 23993 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 23994 | GIR_EraseFromParent, /*InsnID*/0, |
| 23995 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 23996 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 23997 | // GIR_Coverage, 3655, |
| 23998 | GIR_Done, |
| 23999 | // Label 1300: @59611 |
| 24000 | GIM_Try, /*On fail goto*//*Label 1301*/ 59693, // Rule ID 3656 // |
| 24001 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24002 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 24003 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 24004 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 24005 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24006 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, |
| 24007 | // (ld:{ *:[i64] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) |
| 24008 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24009 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRWroW, |
| 24010 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 24011 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24012 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 24013 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend |
| 24014 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24015 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24016 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 24017 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 24018 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 24019 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 24020 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 24021 | GIR_EraseFromParent, /*InsnID*/0, |
| 24022 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 24023 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 24024 | // GIR_Coverage, 3656, |
| 24025 | GIR_Done, |
| 24026 | // Label 1301: @59693 |
| 24027 | GIM_Try, /*On fail goto*//*Label 1302*/ 59775, // Rule ID 3657 // |
| 24028 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24029 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 24030 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 24031 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 24032 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24033 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, |
| 24034 | // (ld:{ *:[i64] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) |
| 24035 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24036 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRWroX, |
| 24037 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 24038 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24039 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 24040 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend |
| 24041 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24042 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24043 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 24044 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 24045 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 24046 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 24047 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 24048 | GIR_EraseFromParent, /*InsnID*/0, |
| 24049 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 24050 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 24051 | // GIR_Coverage, 3657, |
| 24052 | GIR_Done, |
| 24053 | // Label 1302: @59775 |
| 24054 | GIM_Try, /*On fail goto*//*Label 1303*/ 59857, // Rule ID 3658 // |
| 24055 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24056 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 24057 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 24058 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 24059 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24060 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, |
| 24061 | // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) |
| 24062 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24063 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroW, |
| 24064 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 24065 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24066 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 24067 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend |
| 24068 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24069 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24070 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 24071 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 24072 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 24073 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 24074 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 24075 | GIR_EraseFromParent, /*InsnID*/0, |
| 24076 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 24077 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 24078 | // GIR_Coverage, 3658, |
| 24079 | GIR_Done, |
| 24080 | // Label 1303: @59857 |
| 24081 | GIM_Try, /*On fail goto*//*Label 1304*/ 59939, // Rule ID 3659 // |
| 24082 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24083 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 24084 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 24085 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 24086 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24087 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, |
| 24088 | // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) |
| 24089 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24090 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroX, |
| 24091 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 24092 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24093 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 24094 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend |
| 24095 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24096 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24097 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 24098 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 24099 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 24100 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 24101 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 24102 | GIR_EraseFromParent, /*InsnID*/0, |
| 24103 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 24104 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 24105 | // GIR_Coverage, 3659, |
| 24106 | GIR_Done, |
| 24107 | // Label 1304: @59939 |
| 24108 | GIM_Try, /*On fail goto*//*Label 1305*/ 59985, // Rule ID 243 // |
| 24109 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24110 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 24111 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 24112 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24113 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, |
| 24114 | // (ld:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) |
| 24115 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRXui, |
| 24116 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24117 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24118 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24119 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24120 | GIR_EraseFromParent, /*InsnID*/0, |
| 24121 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24122 | // GIR_Coverage, 243, |
| 24123 | GIR_Done, |
| 24124 | // Label 1305: @59985 |
| 24125 | GIM_Try, /*On fail goto*//*Label 1306*/ 60031, // Rule ID 248 // |
| 24126 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24127 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 24128 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 24129 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24130 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, |
| 24131 | // (ld:{ *:[f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDui:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) |
| 24132 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, |
| 24133 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24134 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24135 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24136 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24137 | GIR_EraseFromParent, /*InsnID*/0, |
| 24138 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24139 | // GIR_Coverage, 248, |
| 24140 | GIR_Done, |
| 24141 | // Label 1306: @60031 |
| 24142 | GIM_Try, /*On fail goto*//*Label 1307*/ 60084, // Rule ID 5384 // |
| 24143 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, |
| 24144 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 24145 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 24146 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 24147 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24148 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, |
| 24149 | // (atomic_load:{ *:[i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_64>><<P:Predicate_anonymous_7092>> => (LDRXroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) |
| 24150 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRXroW, |
| 24151 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24152 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24153 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 24154 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 24155 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24156 | GIR_EraseFromParent, /*InsnID*/0, |
| 24157 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24158 | // GIR_Coverage, 5384, |
| 24159 | GIR_Done, |
| 24160 | // Label 1307: @60084 |
| 24161 | GIM_Try, /*On fail goto*//*Label 1308*/ 60137, // Rule ID 5385 // |
| 24162 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, |
| 24163 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 24164 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 24165 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 24166 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24167 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, |
| 24168 | // (atomic_load:{ *:[i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_64>><<P:Predicate_anonymous_7092>> => (LDRXroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) |
| 24169 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRXroX, |
| 24170 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24171 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24172 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 24173 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 24174 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24175 | GIR_EraseFromParent, /*InsnID*/0, |
| 24176 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24177 | // GIR_Coverage, 5385, |
| 24178 | GIR_Done, |
| 24179 | // Label 1308: @60137 |
| 24180 | GIM_Try, /*On fail goto*//*Label 1309*/ 60183, // Rule ID 264 // |
| 24181 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24182 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 24183 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 24184 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24185 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, |
| 24186 | // (ld:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) |
| 24187 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURXi, |
| 24188 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24189 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24190 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24191 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24192 | GIR_EraseFromParent, /*InsnID*/0, |
| 24193 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24194 | // GIR_Coverage, 264, |
| 24195 | GIR_Done, |
| 24196 | // Label 1309: @60183 |
| 24197 | GIM_Try, /*On fail goto*//*Label 1310*/ 60229, // Rule ID 269 // |
| 24198 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24199 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 24200 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 24201 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24202 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, |
| 24203 | // (ld:{ *:[f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURDi:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) |
| 24204 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, |
| 24205 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24206 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24207 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24208 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24209 | GIR_EraseFromParent, /*InsnID*/0, |
| 24210 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24211 | // GIR_Coverage, 269, |
| 24212 | GIR_Done, |
| 24213 | // Label 1310: @60229 |
| 24214 | GIM_Try, /*On fail goto*//*Label 1311*/ 60278, // Rule ID 5386 // |
| 24215 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, |
| 24216 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 24217 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 24218 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 24219 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24220 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, |
| 24221 | // (atomic_load:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_64>><<P:Predicate_anonymous_7092>> => (LDRXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) |
| 24222 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRXui, |
| 24223 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24224 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24225 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24226 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24227 | GIR_EraseFromParent, /*InsnID*/0, |
| 24228 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24229 | // GIR_Coverage, 5386, |
| 24230 | GIR_Done, |
| 24231 | // Label 1311: @60278 |
| 24232 | GIM_Try, /*On fail goto*//*Label 1312*/ 60327, // Rule ID 5387 // |
| 24233 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, |
| 24234 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 24235 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 24236 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 24237 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24238 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, |
| 24239 | // (atomic_load:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_64>><<P:Predicate_anonymous_7092>> => (LDURXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 24240 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURXi, |
| 24241 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24242 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24243 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24244 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24245 | GIR_EraseFromParent, /*InsnID*/0, |
| 24246 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24247 | // GIR_Coverage, 5387, |
| 24248 | GIR_Done, |
| 24249 | // Label 1312: @60327 |
| 24250 | GIM_Try, /*On fail goto*//*Label 1313*/ 60373, // Rule ID 3683 // |
| 24251 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24252 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 24253 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 24254 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24255 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, |
| 24256 | // (ld:{ *:[v1f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDui:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) |
| 24257 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, |
| 24258 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24259 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24260 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24261 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24262 | GIR_EraseFromParent, /*InsnID*/0, |
| 24263 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24264 | // GIR_Coverage, 3683, |
| 24265 | GIR_Done, |
| 24266 | // Label 1313: @60373 |
| 24267 | GIM_Try, /*On fail goto*//*Label 1314*/ 60419, // Rule ID 3684 // |
| 24268 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24269 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 24270 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 24271 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24272 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, |
| 24273 | // (ld:{ *:[v1i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDui:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) |
| 24274 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, |
| 24275 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24276 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24277 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24278 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24279 | GIR_EraseFromParent, /*InsnID*/0, |
| 24280 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24281 | // GIR_Coverage, 3684, |
| 24282 | GIR_Done, |
| 24283 | // Label 1314: @60419 |
| 24284 | GIM_Try, /*On fail goto*//*Label 1315*/ 60465, // Rule ID 3712 // |
| 24285 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24286 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 24287 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 24288 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24289 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, |
| 24290 | // (ld:{ *:[v1f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURDi:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 24291 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, |
| 24292 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24293 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24294 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24295 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24296 | GIR_EraseFromParent, /*InsnID*/0, |
| 24297 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24298 | // GIR_Coverage, 3712, |
| 24299 | GIR_Done, |
| 24300 | // Label 1315: @60465 |
| 24301 | GIM_Try, /*On fail goto*//*Label 1316*/ 60511, // Rule ID 3713 // |
| 24302 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24303 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 24304 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 24305 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24306 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, |
| 24307 | // (ld:{ *:[v1i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURDi:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 24308 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, |
| 24309 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24310 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24311 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24312 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24313 | GIR_EraseFromParent, /*InsnID*/0, |
| 24314 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24315 | // GIR_Coverage, 3713, |
| 24316 | GIR_Done, |
| 24317 | // Label 1316: @60511 |
| 24318 | GIM_Try, /*On fail goto*//*Label 1317*/ 60589, // Rule ID 3701 // |
| 24319 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24320 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 24321 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 24322 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 24323 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24324 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, |
| 24325 | // (ld:{ *:[i64] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), sub_32:{ *:[i32] }) |
| 24326 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24327 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRWui, |
| 24328 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 24329 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24330 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24331 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24332 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24333 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 24334 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 24335 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 24336 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 24337 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 24338 | GIR_EraseFromParent, /*InsnID*/0, |
| 24339 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 24340 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 24341 | // GIR_Coverage, 3701, |
| 24342 | GIR_Done, |
| 24343 | // Label 1317: @60589 |
| 24344 | GIM_Try, /*On fail goto*//*Label 1318*/ 60667, // Rule ID 3702 // |
| 24345 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24346 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 24347 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 24348 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 24349 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24350 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, |
| 24351 | // (ld:{ *:[i64] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), sub_32:{ *:[i32] }) |
| 24352 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24353 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRHHui, |
| 24354 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 24355 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24356 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24357 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24358 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24359 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 24360 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 24361 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 24362 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 24363 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 24364 | GIR_EraseFromParent, /*InsnID*/0, |
| 24365 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 24366 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 24367 | // GIR_Coverage, 3702, |
| 24368 | GIR_Done, |
| 24369 | // Label 1318: @60667 |
| 24370 | GIM_Try, /*On fail goto*//*Label 1319*/ 60745, // Rule ID 3703 // |
| 24371 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24372 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 24373 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 24374 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 24375 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24376 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, |
| 24377 | // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), sub_32:{ *:[i32] }) |
| 24378 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24379 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBui, |
| 24380 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 24381 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24382 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24383 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24384 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24385 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 24386 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 24387 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 24388 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 24389 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 24390 | GIR_EraseFromParent, /*InsnID*/0, |
| 24391 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 24392 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 24393 | // GIR_Coverage, 3703, |
| 24394 | GIR_Done, |
| 24395 | // Label 1319: @60745 |
| 24396 | GIM_Try, /*On fail goto*//*Label 1320*/ 60823, // Rule ID 3704 // |
| 24397 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24398 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 24399 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 24400 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 24401 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24402 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, |
| 24403 | // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), sub_32:{ *:[i32] }) |
| 24404 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24405 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBui, |
| 24406 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 24407 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24408 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24409 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24410 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24411 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 24412 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 24413 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 24414 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 24415 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 24416 | GIR_EraseFromParent, /*InsnID*/0, |
| 24417 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 24418 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 24419 | // GIR_Coverage, 3704, |
| 24420 | GIR_Done, |
| 24421 | // Label 1320: @60823 |
| 24422 | GIM_Try, /*On fail goto*//*Label 1321*/ 60901, // Rule ID 3724 // |
| 24423 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24424 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 24425 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 24426 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 24427 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24428 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, |
| 24429 | // (ld:{ *:[i64] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] }) |
| 24430 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24431 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURWi, |
| 24432 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 24433 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24434 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24435 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24436 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24437 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 24438 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 24439 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 24440 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 24441 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 24442 | GIR_EraseFromParent, /*InsnID*/0, |
| 24443 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 24444 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 24445 | // GIR_Coverage, 3724, |
| 24446 | GIR_Done, |
| 24447 | // Label 1321: @60901 |
| 24448 | GIM_Try, /*On fail goto*//*Label 1322*/ 60979, // Rule ID 3725 // |
| 24449 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24450 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 24451 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 24452 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 24453 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24454 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, |
| 24455 | // (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] }) |
| 24456 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24457 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURHHi, |
| 24458 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 24459 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24460 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24461 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24462 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24463 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 24464 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 24465 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 24466 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 24467 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 24468 | GIR_EraseFromParent, /*InsnID*/0, |
| 24469 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 24470 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 24471 | // GIR_Coverage, 3725, |
| 24472 | GIR_Done, |
| 24473 | // Label 1322: @60979 |
| 24474 | GIM_Try, /*On fail goto*//*Label 1323*/ 61057, // Rule ID 3726 // |
| 24475 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24476 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 24477 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 24478 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 24479 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24480 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, |
| 24481 | // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] }) |
| 24482 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24483 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURBBi, |
| 24484 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 24485 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24486 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24487 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24488 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24489 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 24490 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 24491 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 24492 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 24493 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 24494 | GIR_EraseFromParent, /*InsnID*/0, |
| 24495 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 24496 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 24497 | // GIR_Coverage, 3726, |
| 24498 | GIR_Done, |
| 24499 | // Label 1323: @61057 |
| 24500 | GIM_Try, /*On fail goto*//*Label 1324*/ 61135, // Rule ID 3727 // |
| 24501 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24502 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 24503 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 24504 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 24505 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24506 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, |
| 24507 | // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] }) |
| 24508 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24509 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURBBi, |
| 24510 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 24511 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24512 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24513 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24514 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24515 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 24516 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 24517 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 24518 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 24519 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 24520 | GIR_EraseFromParent, /*InsnID*/0, |
| 24521 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 24522 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 24523 | // GIR_Coverage, 3727, |
| 24524 | GIR_Done, |
| 24525 | // Label 1324: @61135 |
| 24526 | GIM_Try, /*On fail goto*//*Label 1325*/ 61166, // Rule ID 5383 // |
| 24527 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, |
| 24528 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 24529 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 24530 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 24531 | // MIs[0] ptr |
| 24532 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 24533 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 24534 | // (atomic_load:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_64>><<P:Predicate_anonymous_7090>> => (LDARX:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr) |
| 24535 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LDARX, |
| 24536 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24537 | // GIR_Coverage, 5383, |
| 24538 | GIR_Done, |
| 24539 | // Label 1325: @61166 |
| 24540 | GIM_Try, /*On fail goto*//*Label 1326*/ 61194, // Rule ID 4807 // |
| 24541 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24542 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 24543 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 24544 | // MIs[0] Rn |
| 24545 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 24546 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 24547 | // (ld:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1Onev1d:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn) |
| 24548 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev1d, |
| 24549 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24550 | // GIR_Coverage, 4807, |
| 24551 | GIR_Done, |
| 24552 | // Label 1326: @61194 |
| 24553 | GIM_Reject, |
| 24554 | // Label 1239: @61195 |
| 24555 | GIM_Try, /*On fail goto*//*Label 1327*/ 61376, |
| 24556 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24557 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 24558 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 24559 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24560 | GIM_Try, /*On fail goto*//*Label 1328*/ 61247, // Rule ID 229 // |
| 24561 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, |
| 24562 | // (ld:{ *:[f128] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroW:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) |
| 24563 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroW, |
| 24564 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24565 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24566 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 24567 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 24568 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24569 | GIR_EraseFromParent, /*InsnID*/0, |
| 24570 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24571 | // GIR_Coverage, 229, |
| 24572 | GIR_Done, |
| 24573 | // Label 1328: @61247 |
| 24574 | GIM_Try, /*On fail goto*//*Label 1329*/ 61282, // Rule ID 230 // |
| 24575 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, |
| 24576 | // (ld:{ *:[f128] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroX:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) |
| 24577 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX, |
| 24578 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24579 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24580 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 24581 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 24582 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24583 | GIR_EraseFromParent, /*InsnID*/0, |
| 24584 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24585 | // GIR_Coverage, 230, |
| 24586 | GIR_Done, |
| 24587 | // Label 1329: @61282 |
| 24588 | GIM_Try, /*On fail goto*//*Label 1330*/ 61313, // Rule ID 249 // |
| 24589 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, |
| 24590 | // (ld:{ *:[f128] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) |
| 24591 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, |
| 24592 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24593 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24594 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24595 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24596 | GIR_EraseFromParent, /*InsnID*/0, |
| 24597 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24598 | // GIR_Coverage, 249, |
| 24599 | GIR_Done, |
| 24600 | // Label 1330: @61313 |
| 24601 | GIM_Try, /*On fail goto*//*Label 1331*/ 61344, // Rule ID 270 // |
| 24602 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, |
| 24603 | // (ld:{ *:[f128] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURQi:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) |
| 24604 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, |
| 24605 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24606 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24607 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24608 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24609 | GIR_EraseFromParent, /*InsnID*/0, |
| 24610 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24611 | // GIR_Coverage, 270, |
| 24612 | GIR_Done, |
| 24613 | // Label 1331: @61344 |
| 24614 | GIM_Try, /*On fail goto*//*Label 1332*/ 61375, // Rule ID 3693 // |
| 24615 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, |
| 24616 | // (ld:{ *:[f128] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) |
| 24617 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, |
| 24618 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24619 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24621 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24622 | GIR_EraseFromParent, /*InsnID*/0, |
| 24623 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24624 | // GIR_Coverage, 3693, |
| 24625 | GIR_Done, |
| 24626 | // Label 1332: @61375 |
| 24627 | GIM_Reject, |
| 24628 | // Label 1327: @61376 |
| 24629 | GIM_Reject, |
| 24630 | // Label 1240: @61377 |
| 24631 | GIM_Try, /*On fail goto*//*Label 1333*/ 61720, |
| 24632 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24633 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 24634 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 24635 | GIM_Try, /*On fail goto*//*Label 1334*/ 61431, // Rule ID 3612 // |
| 24636 | GIM_CheckFeatures, GIFBS_IsLE, |
| 24637 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24638 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, |
| 24639 | // (ld:{ *:[v2i32] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroW:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) |
| 24640 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, |
| 24641 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24642 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24643 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 24644 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 24645 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24646 | GIR_EraseFromParent, /*InsnID*/0, |
| 24647 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24648 | // GIR_Coverage, 3612, |
| 24649 | GIR_Done, |
| 24650 | // Label 1334: @61431 |
| 24651 | GIM_Try, /*On fail goto*//*Label 1335*/ 61472, // Rule ID 3613 // |
| 24652 | GIM_CheckFeatures, GIFBS_IsLE, |
| 24653 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24654 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, |
| 24655 | // (ld:{ *:[v2i32] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroX:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) |
| 24656 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, |
| 24657 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24658 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24659 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 24660 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 24661 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24662 | GIR_EraseFromParent, /*InsnID*/0, |
| 24663 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24664 | // GIR_Coverage, 3613, |
| 24665 | GIR_Done, |
| 24666 | // Label 1335: @61472 |
| 24667 | GIM_Try, /*On fail goto*//*Label 1336*/ 61513, // Rule ID 3614 // |
| 24668 | GIM_CheckFeatures, GIFBS_IsLE, |
| 24669 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24670 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, |
| 24671 | // (ld:{ *:[v2f32] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroW:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) |
| 24672 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, |
| 24673 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24674 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24675 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 24676 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 24677 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24678 | GIR_EraseFromParent, /*InsnID*/0, |
| 24679 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24680 | // GIR_Coverage, 3614, |
| 24681 | GIR_Done, |
| 24682 | // Label 1336: @61513 |
| 24683 | GIM_Try, /*On fail goto*//*Label 1337*/ 61554, // Rule ID 3615 // |
| 24684 | GIM_CheckFeatures, GIFBS_IsLE, |
| 24685 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24686 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, |
| 24687 | // (ld:{ *:[v2f32] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroX:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) |
| 24688 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, |
| 24689 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24690 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24691 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 24692 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 24693 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24694 | GIR_EraseFromParent, /*InsnID*/0, |
| 24695 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24696 | // GIR_Coverage, 3615, |
| 24697 | GIR_Done, |
| 24698 | // Label 1337: @61554 |
| 24699 | GIM_Try, /*On fail goto*//*Label 1338*/ 61591, // Rule ID 3677 // |
| 24700 | GIM_CheckFeatures, GIFBS_IsLE, |
| 24701 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24702 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, |
| 24703 | // (ld:{ *:[v2f32] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDui:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) |
| 24704 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, |
| 24705 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24706 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24707 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24708 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24709 | GIR_EraseFromParent, /*InsnID*/0, |
| 24710 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24711 | // GIR_Coverage, 3677, |
| 24712 | GIR_Done, |
| 24713 | // Label 1338: @61591 |
| 24714 | GIM_Try, /*On fail goto*//*Label 1339*/ 61628, // Rule ID 3680 // |
| 24715 | GIM_CheckFeatures, GIFBS_IsLE, |
| 24716 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24717 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, |
| 24718 | // (ld:{ *:[v2i32] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDui:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) |
| 24719 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, |
| 24720 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24721 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24722 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24723 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24724 | GIR_EraseFromParent, /*InsnID*/0, |
| 24725 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24726 | // GIR_Coverage, 3680, |
| 24727 | GIR_Done, |
| 24728 | // Label 1339: @61628 |
| 24729 | GIM_Try, /*On fail goto*//*Label 1340*/ 61665, // Rule ID 3707 // |
| 24730 | GIM_CheckFeatures, GIFBS_IsLE, |
| 24731 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24732 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, |
| 24733 | // (ld:{ *:[v2f32] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURDi:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 24734 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, |
| 24735 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24736 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24737 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24738 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24739 | GIR_EraseFromParent, /*InsnID*/0, |
| 24740 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24741 | // GIR_Coverage, 3707, |
| 24742 | GIR_Done, |
| 24743 | // Label 1340: @61665 |
| 24744 | GIM_Try, /*On fail goto*//*Label 1341*/ 61702, // Rule ID 3708 // |
| 24745 | GIM_CheckFeatures, GIFBS_IsLE, |
| 24746 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24747 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, |
| 24748 | // (ld:{ *:[v2i32] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURDi:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 24749 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, |
| 24750 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24751 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24752 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24753 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24754 | GIR_EraseFromParent, /*InsnID*/0, |
| 24755 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24756 | // GIR_Coverage, 3708, |
| 24757 | GIR_Done, |
| 24758 | // Label 1341: @61702 |
| 24759 | GIM_Try, /*On fail goto*//*Label 1342*/ 61719, // Rule ID 4806 // |
| 24760 | // MIs[0] Rn |
| 24761 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 24762 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 24763 | // (ld:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1Onev2s:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn) |
| 24764 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev2s, |
| 24765 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24766 | // GIR_Coverage, 4806, |
| 24767 | GIR_Done, |
| 24768 | // Label 1342: @61719 |
| 24769 | GIM_Reject, |
| 24770 | // Label 1333: @61720 |
| 24771 | GIM_Reject, |
| 24772 | // Label 1241: @61721 |
| 24773 | GIM_Try, /*On fail goto*//*Label 1343*/ 62064, |
| 24774 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24775 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 24776 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 24777 | GIM_Try, /*On fail goto*//*Label 1344*/ 61775, // Rule ID 3628 // |
| 24778 | GIM_CheckFeatures, GIFBS_IsLE, |
| 24779 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24780 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, |
| 24781 | // (ld:{ *:[v2i64] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroW:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) |
| 24782 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroW, |
| 24783 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24784 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24785 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 24786 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 24787 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24788 | GIR_EraseFromParent, /*InsnID*/0, |
| 24789 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24790 | // GIR_Coverage, 3628, |
| 24791 | GIR_Done, |
| 24792 | // Label 1344: @61775 |
| 24793 | GIM_Try, /*On fail goto*//*Label 1345*/ 61816, // Rule ID 3629 // |
| 24794 | GIM_CheckFeatures, GIFBS_IsLE, |
| 24795 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24796 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, |
| 24797 | // (ld:{ *:[v2i64] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroX:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) |
| 24798 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX, |
| 24799 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24800 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24801 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 24802 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 24803 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24804 | GIR_EraseFromParent, /*InsnID*/0, |
| 24805 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24806 | // GIR_Coverage, 3629, |
| 24807 | GIR_Done, |
| 24808 | // Label 1345: @61816 |
| 24809 | GIM_Try, /*On fail goto*//*Label 1346*/ 61857, // Rule ID 3630 // |
| 24810 | GIM_CheckFeatures, GIFBS_IsLE, |
| 24811 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24812 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, |
| 24813 | // (ld:{ *:[v2f64] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroW:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) |
| 24814 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroW, |
| 24815 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24816 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24817 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 24818 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 24819 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24820 | GIR_EraseFromParent, /*InsnID*/0, |
| 24821 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24822 | // GIR_Coverage, 3630, |
| 24823 | GIR_Done, |
| 24824 | // Label 1346: @61857 |
| 24825 | GIM_Try, /*On fail goto*//*Label 1347*/ 61898, // Rule ID 3631 // |
| 24826 | GIM_CheckFeatures, GIFBS_IsLE, |
| 24827 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24828 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, |
| 24829 | // (ld:{ *:[v2f64] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroX:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) |
| 24830 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX, |
| 24831 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24833 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 24834 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 24835 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24836 | GIR_EraseFromParent, /*InsnID*/0, |
| 24837 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24838 | // GIR_Coverage, 3631, |
| 24839 | GIR_Done, |
| 24840 | // Label 1347: @61898 |
| 24841 | GIM_Try, /*On fail goto*//*Label 1348*/ 61935, // Rule ID 3686 // |
| 24842 | GIM_CheckFeatures, GIFBS_IsLE, |
| 24843 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24844 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, |
| 24845 | // (ld:{ *:[v2f64] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) |
| 24846 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, |
| 24847 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24848 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24850 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24851 | GIR_EraseFromParent, /*InsnID*/0, |
| 24852 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24853 | // GIR_Coverage, 3686, |
| 24854 | GIR_Done, |
| 24855 | // Label 1348: @61935 |
| 24856 | GIM_Try, /*On fail goto*//*Label 1349*/ 61972, // Rule ID 3690 // |
| 24857 | GIM_CheckFeatures, GIFBS_IsLE, |
| 24858 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24859 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, |
| 24860 | // (ld:{ *:[v2i64] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) |
| 24861 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, |
| 24862 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24863 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24864 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24865 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24866 | GIR_EraseFromParent, /*InsnID*/0, |
| 24867 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24868 | // GIR_Coverage, 3690, |
| 24869 | GIR_Done, |
| 24870 | // Label 1349: @61972 |
| 24871 | GIM_Try, /*On fail goto*//*Label 1350*/ 62009, // Rule ID 3714 // |
| 24872 | GIM_CheckFeatures, GIFBS_IsLE, |
| 24873 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24874 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, |
| 24875 | // (ld:{ *:[v2f64] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURQi:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 24876 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, |
| 24877 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24878 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24879 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24880 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24881 | GIR_EraseFromParent, /*InsnID*/0, |
| 24882 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24883 | // GIR_Coverage, 3714, |
| 24884 | GIR_Done, |
| 24885 | // Label 1350: @62009 |
| 24886 | GIM_Try, /*On fail goto*//*Label 1351*/ 62046, // Rule ID 3715 // |
| 24887 | GIM_CheckFeatures, GIFBS_IsLE, |
| 24888 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24889 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, |
| 24890 | // (ld:{ *:[v2i64] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURQi:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 24891 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, |
| 24892 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24893 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24894 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 24895 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24896 | GIR_EraseFromParent, /*InsnID*/0, |
| 24897 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24898 | // GIR_Coverage, 3715, |
| 24899 | GIR_Done, |
| 24900 | // Label 1351: @62046 |
| 24901 | GIM_Try, /*On fail goto*//*Label 1352*/ 62063, // Rule ID 4803 // |
| 24902 | // MIs[0] Rn |
| 24903 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 24904 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 24905 | // (ld:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1Onev2d:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn) |
| 24906 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev2d, |
| 24907 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24908 | // GIR_Coverage, 4803, |
| 24909 | GIR_Done, |
| 24910 | // Label 1352: @62063 |
| 24911 | GIM_Reject, |
| 24912 | // Label 1343: @62064 |
| 24913 | GIM_Reject, |
| 24914 | // Label 1242: @62065 |
| 24915 | GIM_Try, /*On fail goto*//*Label 1353*/ 62527, |
| 24916 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24917 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 24918 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 24919 | GIM_Try, /*On fail goto*//*Label 1354*/ 62119, // Rule ID 3618 // |
| 24920 | GIM_CheckFeatures, GIFBS_IsLE, |
| 24921 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24922 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, |
| 24923 | // (ld:{ *:[v4i16] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroW:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) |
| 24924 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, |
| 24925 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24926 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24927 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 24928 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 24929 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24930 | GIR_EraseFromParent, /*InsnID*/0, |
| 24931 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24932 | // GIR_Coverage, 3618, |
| 24933 | GIR_Done, |
| 24934 | // Label 1354: @62119 |
| 24935 | GIM_Try, /*On fail goto*//*Label 1355*/ 62160, // Rule ID 3619 // |
| 24936 | GIM_CheckFeatures, GIFBS_IsLE, |
| 24937 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24938 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, |
| 24939 | // (ld:{ *:[v4i16] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroX:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) |
| 24940 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, |
| 24941 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24942 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24943 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 24944 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 24945 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24946 | GIR_EraseFromParent, /*InsnID*/0, |
| 24947 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24948 | // GIR_Coverage, 3619, |
| 24949 | GIR_Done, |
| 24950 | // Label 1355: @62160 |
| 24951 | GIM_Try, /*On fail goto*//*Label 1356*/ 62201, // Rule ID 3620 // |
| 24952 | GIM_CheckFeatures, GIFBS_IsLE, |
| 24953 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24954 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, |
| 24955 | // (ld:{ *:[v4f16] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroW:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) |
| 24956 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, |
| 24957 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24959 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 24960 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 24961 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24962 | GIR_EraseFromParent, /*InsnID*/0, |
| 24963 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24964 | // GIR_Coverage, 3620, |
| 24965 | GIR_Done, |
| 24966 | // Label 1356: @62201 |
| 24967 | GIM_Try, /*On fail goto*//*Label 1357*/ 62242, // Rule ID 3621 // |
| 24968 | GIM_CheckFeatures, GIFBS_IsLE, |
| 24969 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24970 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, |
| 24971 | // (ld:{ *:[v4f16] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroX:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) |
| 24972 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, |
| 24973 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24974 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24975 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 24976 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 24977 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24978 | GIR_EraseFromParent, /*InsnID*/0, |
| 24979 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24980 | // GIR_Coverage, 3621, |
| 24981 | GIR_Done, |
| 24982 | // Label 1357: @62242 |
| 24983 | GIM_Try, /*On fail goto*//*Label 1358*/ 62283, // Rule ID 3622 // |
| 24984 | GIM_CheckFeatures, GIFBS_IsLE, |
| 24985 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24986 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, |
| 24987 | // (ld:{ *:[v4bf16] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroW:{ *:[v4bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) |
| 24988 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, |
| 24989 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 24990 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 24991 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 24992 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 24993 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 24994 | GIR_EraseFromParent, /*InsnID*/0, |
| 24995 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24996 | // GIR_Coverage, 3622, |
| 24997 | GIR_Done, |
| 24998 | // Label 1358: @62283 |
| 24999 | GIM_Try, /*On fail goto*//*Label 1359*/ 62324, // Rule ID 3623 // |
| 25000 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25001 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25002 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, |
| 25003 | // (ld:{ *:[v4bf16] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroX:{ *:[v4bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) |
| 25004 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, |
| 25005 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25006 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25007 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25008 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25009 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25010 | GIR_EraseFromParent, /*InsnID*/0, |
| 25011 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25012 | // GIR_Coverage, 3623, |
| 25013 | GIR_Done, |
| 25014 | // Label 1359: @62324 |
| 25015 | GIM_Try, /*On fail goto*//*Label 1360*/ 62361, // Rule ID 3679 // |
| 25016 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25017 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25018 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, |
| 25019 | // (ld:{ *:[v4i16] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDui:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) |
| 25020 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, |
| 25021 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25022 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25023 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25024 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25025 | GIR_EraseFromParent, /*InsnID*/0, |
| 25026 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25027 | // GIR_Coverage, 3679, |
| 25028 | GIR_Done, |
| 25029 | // Label 1360: @62361 |
| 25030 | GIM_Try, /*On fail goto*//*Label 1361*/ 62398, // Rule ID 3681 // |
| 25031 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25032 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25033 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, |
| 25034 | // (ld:{ *:[v4f16] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDui:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) |
| 25035 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, |
| 25036 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25037 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25038 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25039 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25040 | GIR_EraseFromParent, /*InsnID*/0, |
| 25041 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25042 | // GIR_Coverage, 3681, |
| 25043 | GIR_Done, |
| 25044 | // Label 1361: @62398 |
| 25045 | GIM_Try, /*On fail goto*//*Label 1362*/ 62435, // Rule ID 3682 // |
| 25046 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25047 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25048 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, |
| 25049 | // (ld:{ *:[v4bf16] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDui:{ *:[v4bf16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) |
| 25050 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, |
| 25051 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25052 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25053 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25054 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25055 | GIR_EraseFromParent, /*InsnID*/0, |
| 25056 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25057 | // GIR_Coverage, 3682, |
| 25058 | GIR_Done, |
| 25059 | // Label 1362: @62435 |
| 25060 | GIM_Try, /*On fail goto*//*Label 1363*/ 62472, // Rule ID 3709 // |
| 25061 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25062 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25063 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, |
| 25064 | // (ld:{ *:[v4i16] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURDi:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 25065 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, |
| 25066 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25067 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25068 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25069 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25070 | GIR_EraseFromParent, /*InsnID*/0, |
| 25071 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25072 | // GIR_Coverage, 3709, |
| 25073 | GIR_Done, |
| 25074 | // Label 1363: @62472 |
| 25075 | GIM_Try, /*On fail goto*//*Label 1364*/ 62509, // Rule ID 3711 // |
| 25076 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25077 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25078 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, |
| 25079 | // (ld:{ *:[v4f16] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURDi:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 25080 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, |
| 25081 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25082 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25083 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25084 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25085 | GIR_EraseFromParent, /*InsnID*/0, |
| 25086 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25087 | // GIR_Coverage, 3711, |
| 25088 | GIR_Done, |
| 25089 | // Label 1364: @62509 |
| 25090 | GIM_Try, /*On fail goto*//*Label 1365*/ 62526, // Rule ID 4805 // |
| 25091 | // MIs[0] Rn |
| 25092 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 25093 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 25094 | // (ld:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1Onev4h:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn) |
| 25095 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev4h, |
| 25096 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25097 | // GIR_Coverage, 4805, |
| 25098 | GIR_Done, |
| 25099 | // Label 1365: @62526 |
| 25100 | GIM_Reject, |
| 25101 | // Label 1353: @62527 |
| 25102 | GIM_Reject, |
| 25103 | // Label 1243: @62528 |
| 25104 | GIM_Try, /*On fail goto*//*Label 1366*/ 62871, |
| 25105 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25106 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 25107 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 25108 | GIM_Try, /*On fail goto*//*Label 1367*/ 62582, // Rule ID 3632 // |
| 25109 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25110 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25111 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, |
| 25112 | // (ld:{ *:[v4i32] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroW:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) |
| 25113 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroW, |
| 25114 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25116 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25117 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25118 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25119 | GIR_EraseFromParent, /*InsnID*/0, |
| 25120 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25121 | // GIR_Coverage, 3632, |
| 25122 | GIR_Done, |
| 25123 | // Label 1367: @62582 |
| 25124 | GIM_Try, /*On fail goto*//*Label 1368*/ 62623, // Rule ID 3633 // |
| 25125 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25126 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25127 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, |
| 25128 | // (ld:{ *:[v4i32] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroX:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) |
| 25129 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX, |
| 25130 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25131 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25132 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25133 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25134 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25135 | GIR_EraseFromParent, /*InsnID*/0, |
| 25136 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25137 | // GIR_Coverage, 3633, |
| 25138 | GIR_Done, |
| 25139 | // Label 1368: @62623 |
| 25140 | GIM_Try, /*On fail goto*//*Label 1369*/ 62664, // Rule ID 3634 // |
| 25141 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25142 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25143 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, |
| 25144 | // (ld:{ *:[v4f32] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroW:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) |
| 25145 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroW, |
| 25146 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25147 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25148 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25149 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25150 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25151 | GIR_EraseFromParent, /*InsnID*/0, |
| 25152 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25153 | // GIR_Coverage, 3634, |
| 25154 | GIR_Done, |
| 25155 | // Label 1369: @62664 |
| 25156 | GIM_Try, /*On fail goto*//*Label 1370*/ 62705, // Rule ID 3635 // |
| 25157 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25158 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25159 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, |
| 25160 | // (ld:{ *:[v4f32] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroX:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) |
| 25161 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX, |
| 25162 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25163 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25164 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25165 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25166 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25167 | GIR_EraseFromParent, /*InsnID*/0, |
| 25168 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25169 | // GIR_Coverage, 3635, |
| 25170 | GIR_Done, |
| 25171 | // Label 1370: @62705 |
| 25172 | GIM_Try, /*On fail goto*//*Label 1371*/ 62742, // Rule ID 3685 // |
| 25173 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25174 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25175 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, |
| 25176 | // (ld:{ *:[v4f32] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) |
| 25177 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, |
| 25178 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25179 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25180 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25181 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25182 | GIR_EraseFromParent, /*InsnID*/0, |
| 25183 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25184 | // GIR_Coverage, 3685, |
| 25185 | GIR_Done, |
| 25186 | // Label 1371: @62742 |
| 25187 | GIM_Try, /*On fail goto*//*Label 1372*/ 62779, // Rule ID 3689 // |
| 25188 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25189 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25190 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, |
| 25191 | // (ld:{ *:[v4i32] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) |
| 25192 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, |
| 25193 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25194 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25195 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25196 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25197 | GIR_EraseFromParent, /*InsnID*/0, |
| 25198 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25199 | // GIR_Coverage, 3689, |
| 25200 | GIR_Done, |
| 25201 | // Label 1372: @62779 |
| 25202 | GIM_Try, /*On fail goto*//*Label 1373*/ 62816, // Rule ID 3716 // |
| 25203 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25204 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25205 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, |
| 25206 | // (ld:{ *:[v4f32] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURQi:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 25207 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, |
| 25208 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25209 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25210 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25211 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25212 | GIR_EraseFromParent, /*InsnID*/0, |
| 25213 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25214 | // GIR_Coverage, 3716, |
| 25215 | GIR_Done, |
| 25216 | // Label 1373: @62816 |
| 25217 | GIM_Try, /*On fail goto*//*Label 1374*/ 62853, // Rule ID 3717 // |
| 25218 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25219 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25220 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, |
| 25221 | // (ld:{ *:[v4i32] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURQi:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 25222 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, |
| 25223 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25224 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25225 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25226 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25227 | GIR_EraseFromParent, /*InsnID*/0, |
| 25228 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25229 | // GIR_Coverage, 3717, |
| 25230 | GIR_Done, |
| 25231 | // Label 1374: @62853 |
| 25232 | GIM_Try, /*On fail goto*//*Label 1375*/ 62870, // Rule ID 4802 // |
| 25233 | // MIs[0] Rn |
| 25234 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 25235 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 25236 | // (ld:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1Onev4s:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn) |
| 25237 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev4s, |
| 25238 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25239 | // GIR_Coverage, 4802, |
| 25240 | GIR_Done, |
| 25241 | // Label 1375: @62870 |
| 25242 | GIM_Reject, |
| 25243 | // Label 1366: @62871 |
| 25244 | GIM_Reject, |
| 25245 | // Label 1244: @62872 |
| 25246 | GIM_Try, /*On fail goto*//*Label 1376*/ 63059, |
| 25247 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25248 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 25249 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 25250 | GIM_Try, /*On fail goto*//*Label 1377*/ 62926, // Rule ID 3616 // |
| 25251 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25252 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25253 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, |
| 25254 | // (ld:{ *:[v8i8] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroW:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) |
| 25255 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroW, |
| 25256 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25257 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25258 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25259 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25260 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25261 | GIR_EraseFromParent, /*InsnID*/0, |
| 25262 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25263 | // GIR_Coverage, 3616, |
| 25264 | GIR_Done, |
| 25265 | // Label 1377: @62926 |
| 25266 | GIM_Try, /*On fail goto*//*Label 1378*/ 62967, // Rule ID 3617 // |
| 25267 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25268 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25269 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, |
| 25270 | // (ld:{ *:[v8i8] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroX:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) |
| 25271 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDroX, |
| 25272 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25273 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25274 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25275 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25276 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25277 | GIR_EraseFromParent, /*InsnID*/0, |
| 25278 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25279 | // GIR_Coverage, 3617, |
| 25280 | GIR_Done, |
| 25281 | // Label 1378: @62967 |
| 25282 | GIM_Try, /*On fail goto*//*Label 1379*/ 63004, // Rule ID 3678 // |
| 25283 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25284 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25285 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, |
| 25286 | // (ld:{ *:[v8i8] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDui:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) |
| 25287 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRDui, |
| 25288 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25289 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25290 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25291 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25292 | GIR_EraseFromParent, /*InsnID*/0, |
| 25293 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25294 | // GIR_Coverage, 3678, |
| 25295 | GIR_Done, |
| 25296 | // Label 1379: @63004 |
| 25297 | GIM_Try, /*On fail goto*//*Label 1380*/ 63041, // Rule ID 3710 // |
| 25298 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25299 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25300 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, |
| 25301 | // (ld:{ *:[v8i8] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURDi:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 25302 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURDi, |
| 25303 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25304 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25306 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25307 | GIR_EraseFromParent, /*InsnID*/0, |
| 25308 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25309 | // GIR_Coverage, 3710, |
| 25310 | GIR_Done, |
| 25311 | // Label 1380: @63041 |
| 25312 | GIM_Try, /*On fail goto*//*Label 1381*/ 63058, // Rule ID 4804 // |
| 25313 | // MIs[0] Rn |
| 25314 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 25315 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 25316 | // (ld:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1Onev8b:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn) |
| 25317 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev8b, |
| 25318 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25319 | // GIR_Coverage, 4804, |
| 25320 | GIR_Done, |
| 25321 | // Label 1381: @63058 |
| 25322 | GIM_Reject, |
| 25323 | // Label 1376: @63059 |
| 25324 | GIM_Reject, |
| 25325 | // Label 1245: @63060 |
| 25326 | GIM_Try, /*On fail goto*//*Label 1382*/ 63522, |
| 25327 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25328 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 25329 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 25330 | GIM_Try, /*On fail goto*//*Label 1383*/ 63114, // Rule ID 3636 // |
| 25331 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25332 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25333 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, |
| 25334 | // (ld:{ *:[v8i16] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroW:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) |
| 25335 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroW, |
| 25336 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25337 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25338 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25339 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25340 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25341 | GIR_EraseFromParent, /*InsnID*/0, |
| 25342 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25343 | // GIR_Coverage, 3636, |
| 25344 | GIR_Done, |
| 25345 | // Label 1383: @63114 |
| 25346 | GIM_Try, /*On fail goto*//*Label 1384*/ 63155, // Rule ID 3637 // |
| 25347 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25348 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25349 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, |
| 25350 | // (ld:{ *:[v8i16] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroX:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) |
| 25351 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX, |
| 25352 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25353 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25354 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25355 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25356 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25357 | GIR_EraseFromParent, /*InsnID*/0, |
| 25358 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25359 | // GIR_Coverage, 3637, |
| 25360 | GIR_Done, |
| 25361 | // Label 1384: @63155 |
| 25362 | GIM_Try, /*On fail goto*//*Label 1385*/ 63196, // Rule ID 3638 // |
| 25363 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25364 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25365 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, |
| 25366 | // (ld:{ *:[v8f16] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroW:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) |
| 25367 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroW, |
| 25368 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25370 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25371 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25372 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25373 | GIR_EraseFromParent, /*InsnID*/0, |
| 25374 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25375 | // GIR_Coverage, 3638, |
| 25376 | GIR_Done, |
| 25377 | // Label 1385: @63196 |
| 25378 | GIM_Try, /*On fail goto*//*Label 1386*/ 63237, // Rule ID 3639 // |
| 25379 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25380 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25381 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, |
| 25382 | // (ld:{ *:[v8f16] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroX:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) |
| 25383 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX, |
| 25384 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25385 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25386 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25387 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25388 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25389 | GIR_EraseFromParent, /*InsnID*/0, |
| 25390 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25391 | // GIR_Coverage, 3639, |
| 25392 | GIR_Done, |
| 25393 | // Label 1386: @63237 |
| 25394 | GIM_Try, /*On fail goto*//*Label 1387*/ 63278, // Rule ID 3640 // |
| 25395 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25396 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25397 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, |
| 25398 | // (ld:{ *:[v8bf16] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroW:{ *:[v8bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) |
| 25399 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroW, |
| 25400 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25401 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25402 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25403 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25404 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25405 | GIR_EraseFromParent, /*InsnID*/0, |
| 25406 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25407 | // GIR_Coverage, 3640, |
| 25408 | GIR_Done, |
| 25409 | // Label 1387: @63278 |
| 25410 | GIM_Try, /*On fail goto*//*Label 1388*/ 63319, // Rule ID 3641 // |
| 25411 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25412 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25413 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, |
| 25414 | // (ld:{ *:[v8bf16] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroX:{ *:[v8bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) |
| 25415 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX, |
| 25416 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25417 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25418 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25419 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25420 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25421 | GIR_EraseFromParent, /*InsnID*/0, |
| 25422 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25423 | // GIR_Coverage, 3641, |
| 25424 | GIR_Done, |
| 25425 | // Label 1388: @63319 |
| 25426 | GIM_Try, /*On fail goto*//*Label 1389*/ 63356, // Rule ID 3688 // |
| 25427 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25428 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25429 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, |
| 25430 | // (ld:{ *:[v8i16] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) |
| 25431 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, |
| 25432 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25433 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25434 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25435 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25436 | GIR_EraseFromParent, /*InsnID*/0, |
| 25437 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25438 | // GIR_Coverage, 3688, |
| 25439 | GIR_Done, |
| 25440 | // Label 1389: @63356 |
| 25441 | GIM_Try, /*On fail goto*//*Label 1390*/ 63393, // Rule ID 3691 // |
| 25442 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25443 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25444 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, |
| 25445 | // (ld:{ *:[v8f16] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) |
| 25446 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, |
| 25447 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25448 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25449 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25450 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25451 | GIR_EraseFromParent, /*InsnID*/0, |
| 25452 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25453 | // GIR_Coverage, 3691, |
| 25454 | GIR_Done, |
| 25455 | // Label 1390: @63393 |
| 25456 | GIM_Try, /*On fail goto*//*Label 1391*/ 63430, // Rule ID 3692 // |
| 25457 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25458 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25459 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, |
| 25460 | // (ld:{ *:[v8bf16] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[v8bf16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) |
| 25461 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, |
| 25462 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25463 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25464 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25465 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25466 | GIR_EraseFromParent, /*InsnID*/0, |
| 25467 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25468 | // GIR_Coverage, 3692, |
| 25469 | GIR_Done, |
| 25470 | // Label 1391: @63430 |
| 25471 | GIM_Try, /*On fail goto*//*Label 1392*/ 63467, // Rule ID 3718 // |
| 25472 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25473 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25474 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, |
| 25475 | // (ld:{ *:[v8i16] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURQi:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 25476 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, |
| 25477 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25478 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25479 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25480 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25481 | GIR_EraseFromParent, /*InsnID*/0, |
| 25482 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25483 | // GIR_Coverage, 3718, |
| 25484 | GIR_Done, |
| 25485 | // Label 1392: @63467 |
| 25486 | GIM_Try, /*On fail goto*//*Label 1393*/ 63504, // Rule ID 3720 // |
| 25487 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25488 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25489 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, |
| 25490 | // (ld:{ *:[v8f16] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURQi:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 25491 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, |
| 25492 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25493 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25494 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25495 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25496 | GIR_EraseFromParent, /*InsnID*/0, |
| 25497 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25498 | // GIR_Coverage, 3720, |
| 25499 | GIR_Done, |
| 25500 | // Label 1393: @63504 |
| 25501 | GIM_Try, /*On fail goto*//*Label 1394*/ 63521, // Rule ID 4801 // |
| 25502 | // MIs[0] Rn |
| 25503 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 25504 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 25505 | // (ld:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1Onev8h:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn) |
| 25506 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev8h, |
| 25507 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25508 | // GIR_Coverage, 4801, |
| 25509 | GIR_Done, |
| 25510 | // Label 1394: @63521 |
| 25511 | GIM_Reject, |
| 25512 | // Label 1382: @63522 |
| 25513 | GIM_Reject, |
| 25514 | // Label 1246: @63523 |
| 25515 | GIM_Try, /*On fail goto*//*Label 1395*/ 63710, |
| 25516 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25517 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 25518 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 25519 | GIM_Try, /*On fail goto*//*Label 1396*/ 63577, // Rule ID 3642 // |
| 25520 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25521 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25522 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, |
| 25523 | // (ld:{ *:[v16i8] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroW:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) |
| 25524 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroW, |
| 25525 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25526 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25527 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25528 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25529 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25530 | GIR_EraseFromParent, /*InsnID*/0, |
| 25531 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25532 | // GIR_Coverage, 3642, |
| 25533 | GIR_Done, |
| 25534 | // Label 1396: @63577 |
| 25535 | GIM_Try, /*On fail goto*//*Label 1397*/ 63618, // Rule ID 3643 // |
| 25536 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25537 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25538 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, |
| 25539 | // (ld:{ *:[v16i8] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroX:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) |
| 25540 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQroX, |
| 25541 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25542 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25543 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25544 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25545 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25546 | GIR_EraseFromParent, /*InsnID*/0, |
| 25547 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25548 | // GIR_Coverage, 3643, |
| 25549 | GIR_Done, |
| 25550 | // Label 1397: @63618 |
| 25551 | GIM_Try, /*On fail goto*//*Label 1398*/ 63655, // Rule ID 3687 // |
| 25552 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25553 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25554 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, |
| 25555 | // (ld:{ *:[v16i8] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) |
| 25556 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRQui, |
| 25557 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25558 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25559 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25560 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25561 | GIR_EraseFromParent, /*InsnID*/0, |
| 25562 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25563 | // GIR_Coverage, 3687, |
| 25564 | GIR_Done, |
| 25565 | // Label 1398: @63655 |
| 25566 | GIM_Try, /*On fail goto*//*Label 1399*/ 63692, // Rule ID 3719 // |
| 25567 | GIM_CheckFeatures, GIFBS_IsLE, |
| 25568 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25569 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, |
| 25570 | // (ld:{ *:[v16i8] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURQi:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 25571 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURQi, |
| 25572 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25573 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25574 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25575 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25576 | GIR_EraseFromParent, /*InsnID*/0, |
| 25577 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25578 | // GIR_Coverage, 3719, |
| 25579 | GIR_Done, |
| 25580 | // Label 1399: @63692 |
| 25581 | GIM_Try, /*On fail goto*//*Label 1400*/ 63709, // Rule ID 4800 // |
| 25582 | // MIs[0] Rn |
| 25583 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 25584 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 25585 | // (ld:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1Onev16b:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn) |
| 25586 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LD1Onev16b, |
| 25587 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25588 | // GIR_Coverage, 4800, |
| 25589 | GIR_Done, |
| 25590 | // Label 1400: @63709 |
| 25591 | GIM_Reject, |
| 25592 | // Label 1395: @63710 |
| 25593 | GIM_Reject, |
| 25594 | // Label 1247: @63711 |
| 25595 | GIM_Reject, |
| 25596 | // Label 15: @63712 |
| 25597 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1403*/ 64682, |
| 25598 | /*GILLT_s32*//*Label 1401*/ 63720, |
| 25599 | /*GILLT_s64*//*Label 1402*/ 64105, |
| 25600 | // Label 1401: @63720 |
| 25601 | GIM_Try, /*On fail goto*//*Label 1404*/ 63770, // Rule ID 231 // |
| 25602 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 25603 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 25604 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 25605 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25606 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, |
| 25607 | // (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LDRSHWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend) |
| 25608 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHWroW, |
| 25609 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25610 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25611 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25612 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25613 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25614 | GIR_EraseFromParent, /*InsnID*/0, |
| 25615 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25616 | // GIR_Coverage, 231, |
| 25617 | GIR_Done, |
| 25618 | // Label 1404: @63770 |
| 25619 | GIM_Try, /*On fail goto*//*Label 1405*/ 63820, // Rule ID 232 // |
| 25620 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 25621 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 25622 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 25623 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25624 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, |
| 25625 | // (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LDRSHWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend) |
| 25626 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHWroX, |
| 25627 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25628 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25629 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25630 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25631 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25632 | GIR_EraseFromParent, /*InsnID*/0, |
| 25633 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25634 | // GIR_Coverage, 232, |
| 25635 | GIR_Done, |
| 25636 | // Label 1405: @63820 |
| 25637 | GIM_Try, /*On fail goto*//*Label 1406*/ 63870, // Rule ID 235 // |
| 25638 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 25639 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 25640 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 25641 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25642 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, |
| 25643 | // (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LDRSBWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend) |
| 25644 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBWroW, |
| 25645 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25646 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25647 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25648 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25649 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25650 | GIR_EraseFromParent, /*InsnID*/0, |
| 25651 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25652 | // GIR_Coverage, 235, |
| 25653 | GIR_Done, |
| 25654 | // Label 1406: @63870 |
| 25655 | GIM_Try, /*On fail goto*//*Label 1407*/ 63920, // Rule ID 236 // |
| 25656 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 25657 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 25658 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 25659 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25660 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, |
| 25661 | // (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LDRSBWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend) |
| 25662 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBWroX, |
| 25663 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25664 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25665 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25666 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25667 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25668 | GIR_EraseFromParent, /*InsnID*/0, |
| 25669 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25670 | // GIR_Coverage, 236, |
| 25671 | GIR_Done, |
| 25672 | // Label 1407: @63920 |
| 25673 | GIM_Try, /*On fail goto*//*Label 1408*/ 63966, // Rule ID 252 // |
| 25674 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 25675 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 25676 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 25677 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25678 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, |
| 25679 | // (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LDRSHWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) |
| 25680 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHWui, |
| 25681 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25682 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25683 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25684 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25685 | GIR_EraseFromParent, /*InsnID*/0, |
| 25686 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25687 | // GIR_Coverage, 252, |
| 25688 | GIR_Done, |
| 25689 | // Label 1408: @63966 |
| 25690 | GIM_Try, /*On fail goto*//*Label 1409*/ 64012, // Rule ID 254 // |
| 25691 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 25692 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 25693 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 25694 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25695 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, |
| 25696 | // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LDRSBWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) |
| 25697 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBWui, |
| 25698 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25699 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25700 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25701 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25702 | GIR_EraseFromParent, /*InsnID*/0, |
| 25703 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25704 | // GIR_Coverage, 254, |
| 25705 | GIR_Done, |
| 25706 | // Label 1409: @64012 |
| 25707 | GIM_Try, /*On fail goto*//*Label 1410*/ 64058, // Rule ID 273 // |
| 25708 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 25709 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 25710 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 25711 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25712 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, |
| 25713 | // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LDURSHWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) |
| 25714 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSHWi, |
| 25715 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25716 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25717 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25718 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25719 | GIR_EraseFromParent, /*InsnID*/0, |
| 25720 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25721 | // GIR_Coverage, 273, |
| 25722 | GIR_Done, |
| 25723 | // Label 1410: @64058 |
| 25724 | GIM_Try, /*On fail goto*//*Label 1411*/ 64104, // Rule ID 275 // |
| 25725 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 25726 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 25727 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 25728 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25729 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, |
| 25730 | // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LDURSBWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) |
| 25731 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSBWi, |
| 25732 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25733 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25734 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25735 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25736 | GIR_EraseFromParent, /*InsnID*/0, |
| 25737 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25738 | // GIR_Coverage, 275, |
| 25739 | GIR_Done, |
| 25740 | // Label 1411: @64104 |
| 25741 | GIM_Reject, |
| 25742 | // Label 1402: @64105 |
| 25743 | GIM_Try, /*On fail goto*//*Label 1412*/ 64155, // Rule ID 233 // |
| 25744 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 25745 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 25746 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 25747 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25748 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, |
| 25749 | // (ld:{ *:[i64] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LDRSHXroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend) |
| 25750 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHXroW, |
| 25751 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25752 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25753 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25755 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25756 | GIR_EraseFromParent, /*InsnID*/0, |
| 25757 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25758 | // GIR_Coverage, 233, |
| 25759 | GIR_Done, |
| 25760 | // Label 1412: @64155 |
| 25761 | GIM_Try, /*On fail goto*//*Label 1413*/ 64205, // Rule ID 234 // |
| 25762 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 25763 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 25764 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 25765 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25766 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, |
| 25767 | // (ld:{ *:[i64] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LDRSHXroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend) |
| 25768 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHXroX, |
| 25769 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25770 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25771 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25772 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25773 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25774 | GIR_EraseFromParent, /*InsnID*/0, |
| 25775 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25776 | // GIR_Coverage, 234, |
| 25777 | GIR_Done, |
| 25778 | // Label 1413: @64205 |
| 25779 | GIM_Try, /*On fail goto*//*Label 1414*/ 64255, // Rule ID 237 // |
| 25780 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 25781 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 25782 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 25783 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25784 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, |
| 25785 | // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LDRSBXroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend) |
| 25786 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBXroW, |
| 25787 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25788 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25789 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25790 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25791 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25792 | GIR_EraseFromParent, /*InsnID*/0, |
| 25793 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25794 | // GIR_Coverage, 237, |
| 25795 | GIR_Done, |
| 25796 | // Label 1414: @64255 |
| 25797 | GIM_Try, /*On fail goto*//*Label 1415*/ 64305, // Rule ID 238 // |
| 25798 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 25799 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 25800 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 25801 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25802 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, |
| 25803 | // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LDRSBXroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend) |
| 25804 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBXroX, |
| 25805 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25806 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25807 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25808 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25809 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25810 | GIR_EraseFromParent, /*InsnID*/0, |
| 25811 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25812 | // GIR_Coverage, 238, |
| 25813 | GIR_Done, |
| 25814 | // Label 1415: @64305 |
| 25815 | GIM_Try, /*On fail goto*//*Label 1416*/ 64355, // Rule ID 239 // |
| 25816 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 25817 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 25818 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 25819 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25820 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, |
| 25821 | // (ld:{ *:[i64] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> => (LDRSWroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend) |
| 25822 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSWroW, |
| 25823 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25824 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25825 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25826 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25827 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25828 | GIR_EraseFromParent, /*InsnID*/0, |
| 25829 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25830 | // GIR_Coverage, 239, |
| 25831 | GIR_Done, |
| 25832 | // Label 1416: @64355 |
| 25833 | GIM_Try, /*On fail goto*//*Label 1417*/ 64405, // Rule ID 240 // |
| 25834 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 25835 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 25836 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 25837 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25838 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, |
| 25839 | // (ld:{ *:[i64] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> => (LDRSWroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend) |
| 25840 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSWroX, |
| 25841 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25842 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25843 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25844 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25845 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25846 | GIR_EraseFromParent, /*InsnID*/0, |
| 25847 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25848 | // GIR_Coverage, 240, |
| 25849 | GIR_Done, |
| 25850 | // Label 1417: @64405 |
| 25851 | GIM_Try, /*On fail goto*//*Label 1418*/ 64451, // Rule ID 253 // |
| 25852 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 25853 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 25854 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 25855 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25856 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, |
| 25857 | // (ld:{ *:[i64] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LDRSHXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) |
| 25858 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSHXui, |
| 25859 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25860 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25861 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25862 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25863 | GIR_EraseFromParent, /*InsnID*/0, |
| 25864 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25865 | // GIR_Coverage, 253, |
| 25866 | GIR_Done, |
| 25867 | // Label 1418: @64451 |
| 25868 | GIM_Try, /*On fail goto*//*Label 1419*/ 64497, // Rule ID 255 // |
| 25869 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 25870 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 25871 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 25872 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25873 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, |
| 25874 | // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LDRSBXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) |
| 25875 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSBXui, |
| 25876 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25877 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25878 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25879 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25880 | GIR_EraseFromParent, /*InsnID*/0, |
| 25881 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25882 | // GIR_Coverage, 255, |
| 25883 | GIR_Done, |
| 25884 | // Label 1419: @64497 |
| 25885 | GIM_Try, /*On fail goto*//*Label 1420*/ 64543, // Rule ID 256 // |
| 25886 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 25887 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 25888 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 25889 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25890 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, |
| 25891 | // (ld:{ *:[i64] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> => (LDRSWui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) |
| 25892 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRSWui, |
| 25893 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25894 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25895 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25896 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25897 | GIR_EraseFromParent, /*InsnID*/0, |
| 25898 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25899 | // GIR_Coverage, 256, |
| 25900 | GIR_Done, |
| 25901 | // Label 1420: @64543 |
| 25902 | GIM_Try, /*On fail goto*//*Label 1421*/ 64589, // Rule ID 274 // |
| 25903 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 25904 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 25905 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 25906 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25907 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, |
| 25908 | // (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LDURSHXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) |
| 25909 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSHXi, |
| 25910 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25911 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25912 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25913 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25914 | GIR_EraseFromParent, /*InsnID*/0, |
| 25915 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25916 | // GIR_Coverage, 274, |
| 25917 | GIR_Done, |
| 25918 | // Label 1421: @64589 |
| 25919 | GIM_Try, /*On fail goto*//*Label 1422*/ 64635, // Rule ID 276 // |
| 25920 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 25921 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 25922 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 25923 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25924 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, |
| 25925 | // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LDURSBXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) |
| 25926 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSBXi, |
| 25927 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25928 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25929 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25930 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25931 | GIR_EraseFromParent, /*InsnID*/0, |
| 25932 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25933 | // GIR_Coverage, 276, |
| 25934 | GIR_Done, |
| 25935 | // Label 1422: @64635 |
| 25936 | GIM_Try, /*On fail goto*//*Label 1423*/ 64681, // Rule ID 277 // |
| 25937 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 25938 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 25939 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 25940 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25941 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, |
| 25942 | // (ld:{ *:[i64] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> => (LDURSWi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) |
| 25943 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURSWi, |
| 25944 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25945 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25946 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 25947 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25948 | GIR_EraseFromParent, /*InsnID*/0, |
| 25949 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25950 | // GIR_Coverage, 277, |
| 25951 | GIR_Done, |
| 25952 | // Label 1423: @64681 |
| 25953 | GIM_Reject, |
| 25954 | // Label 1403: @64682 |
| 25955 | GIM_Reject, |
| 25956 | // Label 16: @64683 |
| 25957 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1426*/ 66725, |
| 25958 | /*GILLT_s32*//*Label 1424*/ 64691, |
| 25959 | /*GILLT_s64*//*Label 1425*/ 65360, |
| 25960 | // Label 1424: @64691 |
| 25961 | GIM_Try, /*On fail goto*//*Label 1427*/ 64741, // Rule ID 213 // |
| 25962 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 25963 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 25964 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 25965 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25966 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, |
| 25967 | // (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend) |
| 25968 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroW, |
| 25969 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25970 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25971 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25972 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25973 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25974 | GIR_EraseFromParent, /*InsnID*/0, |
| 25975 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25976 | // GIR_Coverage, 213, |
| 25977 | GIR_Done, |
| 25978 | // Label 1427: @64741 |
| 25979 | GIM_Try, /*On fail goto*//*Label 1428*/ 64791, // Rule ID 214 // |
| 25980 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 25981 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 25982 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 25983 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25984 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, |
| 25985 | // (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend) |
| 25986 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroX, |
| 25987 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 25988 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 25989 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 25990 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 25991 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 25992 | GIR_EraseFromParent, /*InsnID*/0, |
| 25993 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 25994 | // GIR_Coverage, 214, |
| 25995 | GIR_Done, |
| 25996 | // Label 1428: @64791 |
| 25997 | GIM_Try, /*On fail goto*//*Label 1429*/ 64841, // Rule ID 215 // |
| 25998 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 25999 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26000 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 26001 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26002 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, |
| 26003 | // (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend) |
| 26004 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHroW, |
| 26005 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 26006 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26007 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 26008 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 26009 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26010 | GIR_EraseFromParent, /*InsnID*/0, |
| 26011 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 26012 | // GIR_Coverage, 215, |
| 26013 | GIR_Done, |
| 26014 | // Label 1429: @64841 |
| 26015 | GIM_Try, /*On fail goto*//*Label 1430*/ 64891, // Rule ID 216 // |
| 26016 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 26017 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26018 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 26019 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26020 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, |
| 26021 | // (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend) |
| 26022 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHroX, |
| 26023 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 26024 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26025 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 26026 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 26027 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26028 | GIR_EraseFromParent, /*InsnID*/0, |
| 26029 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 26030 | // GIR_Coverage, 216, |
| 26031 | GIR_Done, |
| 26032 | // Label 1430: @64891 |
| 26033 | GIM_Try, /*On fail goto*//*Label 1431*/ 64941, // Rule ID 3666 // |
| 26034 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 26035 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26036 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 26037 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26038 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, |
| 26039 | // (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>> => (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend) |
| 26040 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroW, |
| 26041 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 26042 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26043 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 26044 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 26045 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26046 | GIR_EraseFromParent, /*InsnID*/0, |
| 26047 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 26048 | // GIR_Coverage, 3666, |
| 26049 | GIR_Done, |
| 26050 | // Label 1431: @64941 |
| 26051 | GIM_Try, /*On fail goto*//*Label 1432*/ 64991, // Rule ID 3667 // |
| 26052 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 26053 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26054 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 26055 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26056 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, |
| 26057 | // (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>> => (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend) |
| 26058 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBroX, |
| 26059 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 26060 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26061 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 26062 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 26063 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26064 | GIR_EraseFromParent, /*InsnID*/0, |
| 26065 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 26066 | // GIR_Coverage, 3667, |
| 26067 | GIR_Done, |
| 26068 | // Label 1432: @64991 |
| 26069 | GIM_Try, /*On fail goto*//*Label 1433*/ 65037, // Rule ID 250 // |
| 26070 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 26071 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26072 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 26073 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26074 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, |
| 26075 | // (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) |
| 26076 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRHHui, |
| 26077 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 26078 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26079 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 26080 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26081 | GIR_EraseFromParent, /*InsnID*/0, |
| 26082 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 26083 | // GIR_Coverage, 250, |
| 26084 | GIR_Done, |
| 26085 | // Label 1433: @65037 |
| 26086 | GIM_Try, /*On fail goto*//*Label 1434*/ 65083, // Rule ID 251 // |
| 26087 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 26088 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26089 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 26090 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26091 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, |
| 26092 | // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) |
| 26093 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui, |
| 26094 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 26095 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26096 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 26097 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26098 | GIR_EraseFromParent, /*InsnID*/0, |
| 26099 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 26100 | // GIR_Coverage, 251, |
| 26101 | GIR_Done, |
| 26102 | // Label 1434: @65083 |
| 26103 | GIM_Try, /*On fail goto*//*Label 1435*/ 65129, // Rule ID 271 // |
| 26104 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 26105 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26106 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 26107 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26108 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, |
| 26109 | // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) |
| 26110 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHHi, |
| 26111 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 26112 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26113 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 26114 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26115 | GIR_EraseFromParent, /*InsnID*/0, |
| 26116 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 26117 | // GIR_Coverage, 271, |
| 26118 | GIR_Done, |
| 26119 | // Label 1435: @65129 |
| 26120 | GIM_Try, /*On fail goto*//*Label 1436*/ 65175, // Rule ID 272 // |
| 26121 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 26122 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26123 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 26124 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26125 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, |
| 26126 | // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) |
| 26127 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi, |
| 26128 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 26129 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26130 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 26131 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26132 | GIR_EraseFromParent, /*InsnID*/0, |
| 26133 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 26134 | // GIR_Coverage, 272, |
| 26135 | GIR_Done, |
| 26136 | // Label 1436: @65175 |
| 26137 | GIM_Try, /*On fail goto*//*Label 1437*/ 65221, // Rule ID 3696 // |
| 26138 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 26139 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26140 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 26141 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26142 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, |
| 26143 | // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>> => (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) |
| 26144 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDRBBui, |
| 26145 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 26146 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26147 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 26148 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26149 | GIR_EraseFromParent, /*InsnID*/0, |
| 26150 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 26151 | // GIR_Coverage, 3696, |
| 26152 | GIR_Done, |
| 26153 | // Label 1437: @65221 |
| 26154 | GIM_Try, /*On fail goto*//*Label 1438*/ 65267, // Rule ID 3728 // |
| 26155 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 26156 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26157 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 26158 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26159 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, |
| 26160 | // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 26161 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURHHi, |
| 26162 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 26163 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26164 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 26165 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26166 | GIR_EraseFromParent, /*InsnID*/0, |
| 26167 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 26168 | // GIR_Coverage, 3728, |
| 26169 | GIR_Done, |
| 26170 | // Label 1438: @65267 |
| 26171 | GIM_Try, /*On fail goto*//*Label 1439*/ 65313, // Rule ID 3729 // |
| 26172 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 26173 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26174 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 26175 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26176 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, |
| 26177 | // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 26178 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi, |
| 26179 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 26180 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26181 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 26182 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26183 | GIR_EraseFromParent, /*InsnID*/0, |
| 26184 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 26185 | // GIR_Coverage, 3729, |
| 26186 | GIR_Done, |
| 26187 | // Label 1439: @65313 |
| 26188 | GIM_Try, /*On fail goto*//*Label 1440*/ 65359, // Rule ID 3730 // |
| 26189 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 26190 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26191 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 26192 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26193 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, |
| 26194 | // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 26195 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDURBBi, |
| 26196 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 26197 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26198 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 26199 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26200 | GIR_EraseFromParent, /*InsnID*/0, |
| 26201 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 26202 | // GIR_Coverage, 3730, |
| 26203 | GIR_Done, |
| 26204 | // Label 1440: @65359 |
| 26205 | GIM_Reject, |
| 26206 | // Label 1425: @65360 |
| 26207 | GIM_Try, /*On fail goto*//*Label 1441*/ 65438, // Rule ID 3644 // |
| 26208 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 26209 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26210 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 26211 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26212 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, |
| 26213 | // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) |
| 26214 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 26215 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroW, |
| 26216 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 26217 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26218 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 26219 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend |
| 26220 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26221 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 26222 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 26223 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 26224 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 26225 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 26226 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 26227 | GIR_EraseFromParent, /*InsnID*/0, |
| 26228 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 26229 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 26230 | // GIR_Coverage, 3644, |
| 26231 | GIR_Done, |
| 26232 | // Label 1441: @65438 |
| 26233 | GIM_Try, /*On fail goto*//*Label 1442*/ 65516, // Rule ID 3645 // |
| 26234 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 26235 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26236 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 26237 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26238 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, |
| 26239 | // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) |
| 26240 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 26241 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroX, |
| 26242 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 26243 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26244 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 26245 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend |
| 26246 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26247 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 26248 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 26249 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 26250 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 26251 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 26252 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 26253 | GIR_EraseFromParent, /*InsnID*/0, |
| 26254 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 26255 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 26256 | // GIR_Coverage, 3645, |
| 26257 | GIR_Done, |
| 26258 | // Label 1442: @65516 |
| 26259 | GIM_Try, /*On fail goto*//*Label 1443*/ 65594, // Rule ID 3646 // |
| 26260 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 26261 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26262 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 26263 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26264 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, |
| 26265 | // (ld:{ *:[i64] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) |
| 26266 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 26267 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRHHroW, |
| 26268 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 26269 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26270 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 26271 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend |
| 26272 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26273 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 26274 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 26275 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 26276 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 26277 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 26278 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 26279 | GIR_EraseFromParent, /*InsnID*/0, |
| 26280 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 26281 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 26282 | // GIR_Coverage, 3646, |
| 26283 | GIR_Done, |
| 26284 | // Label 1443: @65594 |
| 26285 | GIM_Try, /*On fail goto*//*Label 1444*/ 65672, // Rule ID 3647 // |
| 26286 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 26287 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26288 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 26289 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26290 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, |
| 26291 | // (ld:{ *:[i64] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) |
| 26292 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 26293 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRHHroX, |
| 26294 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 26295 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26296 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 26297 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend |
| 26298 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26299 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 26300 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 26301 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 26302 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 26303 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 26304 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 26305 | GIR_EraseFromParent, /*InsnID*/0, |
| 26306 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 26307 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 26308 | // GIR_Coverage, 3647, |
| 26309 | GIR_Done, |
| 26310 | // Label 1444: @65672 |
| 26311 | GIM_Try, /*On fail goto*//*Label 1445*/ 65750, // Rule ID 3648 // |
| 26312 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 26313 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26314 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 26315 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26316 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, |
| 26317 | // (ld:{ *:[i64] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) |
| 26318 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 26319 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRWroW, |
| 26320 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 26321 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26322 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 26323 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend |
| 26324 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26325 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 26326 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 26327 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 26328 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 26329 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 26330 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 26331 | GIR_EraseFromParent, /*InsnID*/0, |
| 26332 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 26333 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 26334 | // GIR_Coverage, 3648, |
| 26335 | GIR_Done, |
| 26336 | // Label 1445: @65750 |
| 26337 | GIM_Try, /*On fail goto*//*Label 1446*/ 65828, // Rule ID 3649 // |
| 26338 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 26339 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26340 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 26341 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26342 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, |
| 26343 | // (ld:{ *:[i64] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) |
| 26344 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 26345 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRWroX, |
| 26346 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 26347 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26348 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 26349 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend |
| 26350 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26351 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 26352 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 26353 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 26354 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 26355 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 26356 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 26357 | GIR_EraseFromParent, /*InsnID*/0, |
| 26358 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 26359 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 26360 | // GIR_Coverage, 3649, |
| 26361 | GIR_Done, |
| 26362 | // Label 1446: @65828 |
| 26363 | GIM_Try, /*On fail goto*//*Label 1447*/ 65906, // Rule ID 3650 // |
| 26364 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 26365 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26366 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 26367 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26368 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, |
| 26369 | // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) |
| 26370 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 26371 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroW, |
| 26372 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 26373 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26374 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 26375 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend |
| 26376 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26377 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 26378 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 26379 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 26380 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 26381 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 26382 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 26383 | GIR_EraseFromParent, /*InsnID*/0, |
| 26384 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 26385 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 26386 | // GIR_Coverage, 3650, |
| 26387 | GIR_Done, |
| 26388 | // Label 1447: @65906 |
| 26389 | GIM_Try, /*On fail goto*//*Label 1448*/ 65984, // Rule ID 3651 // |
| 26390 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 26391 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26392 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 26393 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26394 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, |
| 26395 | // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] }) |
| 26396 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 26397 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBroX, |
| 26398 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 26399 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26400 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 26401 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/2, // extend |
| 26402 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26403 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 26404 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 26405 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 26406 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 26407 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 26408 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 26409 | GIR_EraseFromParent, /*InsnID*/0, |
| 26410 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 26411 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 26412 | // GIR_Coverage, 3651, |
| 26413 | GIR_Done, |
| 26414 | // Label 1448: @65984 |
| 26415 | GIM_Try, /*On fail goto*//*Label 1449*/ 66058, // Rule ID 3694 // |
| 26416 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 26417 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26418 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 26419 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26420 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, |
| 26421 | // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), sub_32:{ *:[i32] }) |
| 26422 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 26423 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBui, |
| 26424 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 26425 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26426 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset |
| 26427 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26428 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 26429 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 26430 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 26431 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 26432 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 26433 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 26434 | GIR_EraseFromParent, /*InsnID*/0, |
| 26435 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 26436 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 26437 | // GIR_Coverage, 3694, |
| 26438 | GIR_Done, |
| 26439 | // Label 1449: @66058 |
| 26440 | GIM_Try, /*On fail goto*//*Label 1450*/ 66132, // Rule ID 3695 // |
| 26441 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 26442 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26443 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 26444 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26445 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, |
| 26446 | // (ld:{ *:[i64] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), sub_32:{ *:[i32] }) |
| 26447 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 26448 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRHHui, |
| 26449 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 26450 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26451 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset |
| 26452 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26453 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 26454 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 26455 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 26456 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 26457 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 26458 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 26459 | GIR_EraseFromParent, /*InsnID*/0, |
| 26460 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 26461 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 26462 | // GIR_Coverage, 3695, |
| 26463 | GIR_Done, |
| 26464 | // Label 1450: @66132 |
| 26465 | GIM_Try, /*On fail goto*//*Label 1451*/ 66206, // Rule ID 3697 // |
| 26466 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 26467 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26468 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 26469 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26470 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, |
| 26471 | // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), sub_32:{ *:[i32] }) |
| 26472 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 26473 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRBBui, |
| 26474 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 26475 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26476 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset |
| 26477 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26478 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 26479 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 26480 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 26481 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 26482 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 26483 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 26484 | GIR_EraseFromParent, /*InsnID*/0, |
| 26485 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 26486 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 26487 | // GIR_Coverage, 3697, |
| 26488 | GIR_Done, |
| 26489 | // Label 1451: @66206 |
| 26490 | GIM_Try, /*On fail goto*//*Label 1452*/ 66280, // Rule ID 3705 // |
| 26491 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 26492 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26493 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 26494 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26495 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, |
| 26496 | // (ld:{ *:[i64] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), sub_32:{ *:[i32] }) |
| 26497 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 26498 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDRWui, |
| 26499 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 26500 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26501 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset |
| 26502 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26503 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 26504 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 26505 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 26506 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 26507 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 26508 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 26509 | GIR_EraseFromParent, /*InsnID*/0, |
| 26510 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 26511 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 26512 | // GIR_Coverage, 3705, |
| 26513 | GIR_Done, |
| 26514 | // Label 1452: @66280 |
| 26515 | GIM_Try, /*On fail goto*//*Label 1453*/ 66354, // Rule ID 3731 // |
| 26516 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 26517 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26518 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 26519 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26520 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, |
| 26521 | // (ld:{ *:[i64] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] }) |
| 26522 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 26523 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURWi, |
| 26524 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 26525 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26526 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset |
| 26527 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26528 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 26529 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 26530 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 26531 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 26532 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 26533 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 26534 | GIR_EraseFromParent, /*InsnID*/0, |
| 26535 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 26536 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 26537 | // GIR_Coverage, 3731, |
| 26538 | GIR_Done, |
| 26539 | // Label 1453: @66354 |
| 26540 | GIM_Try, /*On fail goto*//*Label 1454*/ 66428, // Rule ID 3732 // |
| 26541 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 26542 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26543 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 26544 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26545 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, |
| 26546 | // (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] }) |
| 26547 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 26548 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURHHi, |
| 26549 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 26550 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26551 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset |
| 26552 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26553 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 26554 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 26555 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 26556 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 26557 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 26558 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 26559 | GIR_EraseFromParent, /*InsnID*/0, |
| 26560 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 26561 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 26562 | // GIR_Coverage, 3732, |
| 26563 | GIR_Done, |
| 26564 | // Label 1454: @66428 |
| 26565 | GIM_Try, /*On fail goto*//*Label 1455*/ 66502, // Rule ID 3733 // |
| 26566 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 26567 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26568 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 26569 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26570 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, |
| 26571 | // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] }) |
| 26572 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 26573 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURBBi, |
| 26574 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 26575 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26576 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset |
| 26577 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26578 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 26579 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 26580 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 26581 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 26582 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 26583 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 26584 | GIR_EraseFromParent, /*InsnID*/0, |
| 26585 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 26586 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 26587 | // GIR_Coverage, 3733, |
| 26588 | GIR_Done, |
| 26589 | // Label 1455: @66502 |
| 26590 | GIM_Try, /*On fail goto*//*Label 1456*/ 66576, // Rule ID 3734 // |
| 26591 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 26592 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26593 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 26594 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26595 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, |
| 26596 | // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] }) |
| 26597 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 26598 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURBBi, |
| 26599 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 26600 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26601 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset |
| 26602 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26603 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 26604 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 26605 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 26606 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 26607 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 26608 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 26609 | GIR_EraseFromParent, /*InsnID*/0, |
| 26610 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 26611 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 26612 | // GIR_Coverage, 3734, |
| 26613 | GIR_Done, |
| 26614 | // Label 1456: @66576 |
| 26615 | GIM_Try, /*On fail goto*//*Label 1457*/ 66650, // Rule ID 3735 // |
| 26616 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 26617 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26618 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 26619 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26620 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, |
| 26621 | // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] }) |
| 26622 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 26623 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURBBi, |
| 26624 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 26625 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26626 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset |
| 26627 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26628 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 26629 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 26630 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 26631 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 26632 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 26633 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 26634 | GIR_EraseFromParent, /*InsnID*/0, |
| 26635 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 26636 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 26637 | // GIR_Coverage, 3735, |
| 26638 | GIR_Done, |
| 26639 | // Label 1457: @66650 |
| 26640 | GIM_Try, /*On fail goto*//*Label 1458*/ 66724, // Rule ID 3736 // |
| 26641 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 26642 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26643 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 26644 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26645 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, |
| 26646 | // (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] }) |
| 26647 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 26648 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDURHHi, |
| 26649 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 26650 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26651 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/1, // offset |
| 26652 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26653 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 26654 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 26655 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 26656 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 26657 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 26658 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 26659 | GIR_EraseFromParent, /*InsnID*/0, |
| 26660 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 26661 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 26662 | // GIR_Coverage, 3736, |
| 26663 | GIR_Done, |
| 26664 | // Label 1458: @66724 |
| 26665 | GIM_Reject, |
| 26666 | // Label 1426: @66725 |
| 26667 | GIM_Reject, |
| 26668 | // Label 17: @66726 |
| 26669 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 11, /*)*//*default:*//*Label 1470*/ 72744, |
| 26670 | /*GILLT_s16*//*Label 1459*/ 66743, |
| 26671 | /*GILLT_s32*//*Label 1460*/ 67285, |
| 26672 | /*GILLT_s64*//*Label 1461*/ 68733, |
| 26673 | /*GILLT_s128*//*Label 1462*/ 69913, |
| 26674 | /*GILLT_v2s32*//*Label 1463*/ 70099, |
| 26675 | /*GILLT_v2s64*//*Label 1464*/ 70471, |
| 26676 | /*GILLT_v4s16*//*Label 1465*/ 70884, |
| 26677 | /*GILLT_v4s32*//*Label 1466*/ 71428, |
| 26678 | /*GILLT_v8s8*//*Label 1467*/ 71800, |
| 26679 | /*GILLT_v8s16*//*Label 1468*/ 72000, |
| 26680 | /*GILLT_v16s8*//*Label 1469*/ 72544, |
| 26681 | // Label 1459: @66743 |
| 26682 | GIM_Try, /*On fail goto*//*Label 1471*/ 67284, |
| 26683 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26684 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26685 | GIM_Try, /*On fail goto*//*Label 1472*/ 66820, // Rule ID 4852 // |
| 26686 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 26687 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 26688 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 26689 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 26690 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 26691 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 26692 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 26693 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 26694 | // MIs[2] Operand 1 |
| 26695 | // No operand predicates |
| 26696 | // MIs[0] Rn |
| 26697 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 26698 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 26699 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 26700 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 26701 | // (st (vector_extract:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1i16 VecListOne128:{ *:[v8f16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn) |
| 26702 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i16, |
| 26703 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt |
| 26704 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 26705 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 26706 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, |
| 26707 | GIR_EraseFromParent, /*InsnID*/0, |
| 26708 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 26709 | // GIR_Coverage, 4852, |
| 26710 | GIR_Done, |
| 26711 | // Label 1472: @66820 |
| 26712 | GIM_Try, /*On fail goto*//*Label 1473*/ 66888, // Rule ID 4853 // |
| 26713 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 26714 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 26715 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 26716 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 26717 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 26718 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 26719 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 26720 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 26721 | // MIs[2] Operand 1 |
| 26722 | // No operand predicates |
| 26723 | // MIs[0] Rn |
| 26724 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 26725 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 26726 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 26727 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 26728 | // (st (vector_extract:{ *:[bf16] } VecListOne128:{ *:[v8bf16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1i16 VecListOne128:{ *:[v8bf16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn) |
| 26729 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i16, |
| 26730 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt |
| 26731 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 26732 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 26733 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, |
| 26734 | GIR_EraseFromParent, /*InsnID*/0, |
| 26735 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 26736 | // GIR_Coverage, 4853, |
| 26737 | GIR_Done, |
| 26738 | // Label 1473: @66888 |
| 26739 | GIM_Try, /*On fail goto*//*Label 1474*/ 66984, // Rule ID 4858 // |
| 26740 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 26741 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 26742 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 26743 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 26744 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 26745 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 26746 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 26747 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 26748 | // MIs[2] Operand 1 |
| 26749 | // No operand predicates |
| 26750 | // MIs[0] Rn |
| 26751 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 26752 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 26753 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 26754 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 26755 | // (st (vector_extract:{ *:[f16] } VecListOne64:{ *:[v4f16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1i16 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v4f16] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn) |
| 26756 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 26757 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 26758 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 26759 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 26760 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt |
| 26761 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 26762 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 26763 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 26764 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i16, |
| 26765 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 26766 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 26767 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 26768 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, |
| 26769 | GIR_EraseFromParent, /*InsnID*/0, |
| 26770 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 26771 | // GIR_Coverage, 4858, |
| 26772 | GIR_Done, |
| 26773 | // Label 1474: @66984 |
| 26774 | GIM_Try, /*On fail goto*//*Label 1475*/ 67080, // Rule ID 4859 // |
| 26775 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 26776 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 26777 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 26778 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 26779 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 26780 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 26781 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 26782 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 26783 | // MIs[2] Operand 1 |
| 26784 | // No operand predicates |
| 26785 | // MIs[0] Rn |
| 26786 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 26787 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 26788 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 26789 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 26790 | // (st (vector_extract:{ *:[bf16] } VecListOne64:{ *:[v4bf16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1i16 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v4bf16] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn) |
| 26791 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 26792 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 26793 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 26794 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 26795 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt |
| 26796 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 26797 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 26798 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 26799 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i16, |
| 26800 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 26801 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 26802 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 26803 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, |
| 26804 | GIR_EraseFromParent, /*InsnID*/0, |
| 26805 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 26806 | // GIR_Coverage, 4859, |
| 26807 | GIR_Done, |
| 26808 | // Label 1475: @67080 |
| 26809 | GIM_Try, /*On fail goto*//*Label 1476*/ 67123, // Rule ID 289 // |
| 26810 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 26811 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26812 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, |
| 26813 | // (st FPR16Op:{ *:[f16] }:$Rt, (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRHroW FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend) |
| 26814 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHroW, |
| 26815 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 26816 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26817 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 26818 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 26819 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26820 | GIR_EraseFromParent, /*InsnID*/0, |
| 26821 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 26822 | // GIR_Coverage, 289, |
| 26823 | GIR_Done, |
| 26824 | // Label 1476: @67123 |
| 26825 | GIM_Try, /*On fail goto*//*Label 1477*/ 67166, // Rule ID 290 // |
| 26826 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 26827 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26828 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, |
| 26829 | // (st FPR16Op:{ *:[f16] }:$Rt, (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRHroX FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend) |
| 26830 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHroX, |
| 26831 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 26832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26833 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 26834 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 26835 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26836 | GIR_EraseFromParent, /*InsnID*/0, |
| 26837 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 26838 | // GIR_Coverage, 290, |
| 26839 | GIR_Done, |
| 26840 | // Label 1477: @67166 |
| 26841 | GIM_Try, /*On fail goto*//*Label 1478*/ 67205, // Rule ID 298 // |
| 26842 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 26843 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26844 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, |
| 26845 | // (st FPR16Op:{ *:[f16] }:$Rt, (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRHui FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) |
| 26846 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHui, |
| 26847 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 26848 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 26850 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26851 | GIR_EraseFromParent, /*InsnID*/0, |
| 26852 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 26853 | // GIR_Coverage, 298, |
| 26854 | GIR_Done, |
| 26855 | // Label 1478: @67205 |
| 26856 | GIM_Try, /*On fail goto*//*Label 1479*/ 67244, // Rule ID 306 // |
| 26857 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 26858 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26859 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, |
| 26860 | // (st FPR16Op:{ *:[f16] }:$Rt, (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURHi FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) |
| 26861 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURHi, |
| 26862 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 26863 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26864 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 26865 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26866 | GIR_EraseFromParent, /*InsnID*/0, |
| 26867 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 26868 | // GIR_Coverage, 306, |
| 26869 | GIR_Done, |
| 26870 | // Label 1479: @67244 |
| 26871 | GIM_Try, /*On fail goto*//*Label 1480*/ 67283, // Rule ID 3791 // |
| 26872 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 26873 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26874 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, |
| 26875 | // (st FPR16Op:{ *:[bf16] }:$Rt, (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRHui FPR16:{ *:[bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) |
| 26876 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHui, |
| 26877 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 26878 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 26879 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 26880 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 26881 | GIR_EraseFromParent, /*InsnID*/0, |
| 26882 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 26883 | // GIR_Coverage, 3791, |
| 26884 | GIR_Done, |
| 26885 | // Label 1480: @67283 |
| 26886 | GIM_Reject, |
| 26887 | // Label 1471: @67284 |
| 26888 | GIM_Reject, |
| 26889 | // Label 1460: @67285 |
| 26890 | GIM_Try, /*On fail goto*//*Label 1481*/ 67360, // Rule ID 4848 // |
| 26891 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26892 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26893 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 26894 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 26895 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 26896 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 26897 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 26898 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 26899 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 26900 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 26901 | // MIs[2] Operand 1 |
| 26902 | // No operand predicates |
| 26903 | // MIs[0] Rn |
| 26904 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 26905 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 26906 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 26907 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 26908 | // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1i32 VecListOne128:{ *:[v4i32] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn) |
| 26909 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i32, |
| 26910 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt |
| 26911 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 26912 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 26913 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, |
| 26914 | GIR_EraseFromParent, /*InsnID*/0, |
| 26915 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 26916 | // GIR_Coverage, 4848, |
| 26917 | GIR_Done, |
| 26918 | // Label 1481: @67360 |
| 26919 | GIM_Try, /*On fail goto*//*Label 1482*/ 67435, // Rule ID 4849 // |
| 26920 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26921 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26922 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 26923 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 26924 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 26925 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 26926 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 26927 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 26928 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 26929 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 26930 | // MIs[2] Operand 1 |
| 26931 | // No operand predicates |
| 26932 | // MIs[0] Rn |
| 26933 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 26934 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 26935 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 26936 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 26937 | // (st (vector_extract:{ *:[f32] } VecListOne128:{ *:[v4f32] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1i32 VecListOne128:{ *:[v4f32] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn) |
| 26938 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i32, |
| 26939 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt |
| 26940 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 26941 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 26942 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, |
| 26943 | GIR_EraseFromParent, /*InsnID*/0, |
| 26944 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 26945 | // GIR_Coverage, 4849, |
| 26946 | GIR_Done, |
| 26947 | // Label 1482: @67435 |
| 26948 | GIM_Try, /*On fail goto*//*Label 1483*/ 67538, // Rule ID 4856 // |
| 26949 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26950 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26951 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 26952 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 26953 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 26954 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 26955 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 26956 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 26957 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 26958 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 26959 | // MIs[2] Operand 1 |
| 26960 | // No operand predicates |
| 26961 | // MIs[0] Rn |
| 26962 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 26963 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 26964 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 26965 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 26966 | // (st (vector_extract:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1i32 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v2i32] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn) |
| 26967 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 26968 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 26969 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 26970 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 26971 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt |
| 26972 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 26973 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 26974 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 26975 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i32, |
| 26976 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 26977 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 26978 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 26979 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, |
| 26980 | GIR_EraseFromParent, /*InsnID*/0, |
| 26981 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 26982 | // GIR_Coverage, 4856, |
| 26983 | GIR_Done, |
| 26984 | // Label 1483: @67538 |
| 26985 | GIM_Try, /*On fail goto*//*Label 1484*/ 67641, // Rule ID 4857 // |
| 26986 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26987 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 26988 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 26989 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 26990 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 26991 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 26992 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 26993 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 26994 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 26995 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 26996 | // MIs[2] Operand 1 |
| 26997 | // No operand predicates |
| 26998 | // MIs[0] Rn |
| 26999 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 27000 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 27001 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 27002 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 27003 | // (st (vector_extract:{ *:[f32] } VecListOne64:{ *:[v2f32] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1i32 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v2f32] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn) |
| 27004 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 27005 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 27006 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 27007 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 27008 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt |
| 27009 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 27010 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 27011 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 27012 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i32, |
| 27013 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 27014 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 27015 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 27016 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, |
| 27017 | GIR_EraseFromParent, /*InsnID*/0, |
| 27018 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27019 | // GIR_Coverage, 4857, |
| 27020 | GIR_Done, |
| 27021 | // Label 1484: @67641 |
| 27022 | GIM_Try, /*On fail goto*//*Label 1485*/ 67691, // Rule ID 283 // |
| 27023 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27024 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27025 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 27026 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27027 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, |
| 27028 | // (st GPR32:{ *:[i32] }:$Rt, (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRWroW GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend) |
| 27029 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRWroW, |
| 27030 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27031 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27032 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 27033 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 27034 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27035 | GIR_EraseFromParent, /*InsnID*/0, |
| 27036 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27037 | // GIR_Coverage, 283, |
| 27038 | GIR_Done, |
| 27039 | // Label 1485: @67691 |
| 27040 | GIM_Try, /*On fail goto*//*Label 1486*/ 67741, // Rule ID 284 // |
| 27041 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27042 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27043 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 27044 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27045 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, |
| 27046 | // (st GPR32:{ *:[i32] }:$Rt, (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRWroX GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend) |
| 27047 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRWroX, |
| 27048 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27049 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27050 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 27051 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 27052 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27053 | GIR_EraseFromParent, /*InsnID*/0, |
| 27054 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27055 | // GIR_Coverage, 284, |
| 27056 | GIR_Done, |
| 27057 | // Label 1486: @67741 |
| 27058 | GIM_Try, /*On fail goto*//*Label 1487*/ 67791, // Rule ID 291 // |
| 27059 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27060 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27061 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 27062 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27063 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, |
| 27064 | // (st FPR32Op:{ *:[f32] }:$Rt, (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRSroW FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend) |
| 27065 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRSroW, |
| 27066 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27067 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27068 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 27069 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 27070 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27071 | GIR_EraseFromParent, /*InsnID*/0, |
| 27072 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27073 | // GIR_Coverage, 291, |
| 27074 | GIR_Done, |
| 27075 | // Label 1487: @67791 |
| 27076 | GIM_Try, /*On fail goto*//*Label 1488*/ 67841, // Rule ID 292 // |
| 27077 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27078 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27079 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 27080 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27081 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, |
| 27082 | // (st FPR32Op:{ *:[f32] }:$Rt, (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRSroX FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend) |
| 27083 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRSroX, |
| 27084 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27085 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27086 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 27087 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 27088 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27089 | GIR_EraseFromParent, /*InsnID*/0, |
| 27090 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27091 | // GIR_Coverage, 292, |
| 27092 | GIR_Done, |
| 27093 | // Label 1488: @67841 |
| 27094 | GIM_Try, /*On fail goto*//*Label 1489*/ 67888, // Rule ID 296 // |
| 27095 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27096 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27097 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 27098 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27099 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, |
| 27100 | // (st GPR32z:{ *:[i32] }:$Rt, (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRWui GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) |
| 27101 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRWui, |
| 27102 | GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::WZR, // Rt |
| 27103 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27104 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 27105 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27106 | GIR_EraseFromParent, /*InsnID*/0, |
| 27107 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27108 | // GIR_Coverage, 296, |
| 27109 | GIR_Done, |
| 27110 | // Label 1489: @67888 |
| 27111 | GIM_Try, /*On fail goto*//*Label 1490*/ 67934, // Rule ID 299 // |
| 27112 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27113 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27114 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 27115 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27116 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, |
| 27117 | // (st FPR32Op:{ *:[f32] }:$Rt, (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRSui FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) |
| 27118 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRSui, |
| 27119 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27120 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27121 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 27122 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27123 | GIR_EraseFromParent, /*InsnID*/0, |
| 27124 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27125 | // GIR_Coverage, 299, |
| 27126 | GIR_Done, |
| 27127 | // Label 1490: @67934 |
| 27128 | GIM_Try, /*On fail goto*//*Label 1491*/ 67987, // Rule ID 5389 // |
| 27129 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 27130 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 27131 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 27132 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27133 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 27134 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed8, |
| 27135 | // (atomic_store (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), GPR32:{ *:[i32] }:$val)<<P:Predicate_atomic_store_8>><<P:Predicate_anonymous_7099>> => (STRBBroW GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend) |
| 27136 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRBBroW, |
| 27137 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val |
| 27138 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27139 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 27140 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 27141 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27142 | GIR_EraseFromParent, /*InsnID*/0, |
| 27143 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27144 | // GIR_Coverage, 5389, |
| 27145 | GIR_Done, |
| 27146 | // Label 1491: @67987 |
| 27147 | GIM_Try, /*On fail goto*//*Label 1492*/ 68040, // Rule ID 5390 // |
| 27148 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 27149 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 27150 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 27151 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27152 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 27153 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed8, |
| 27154 | // (atomic_store (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), GPR32:{ *:[i32] }:$val)<<P:Predicate_atomic_store_8>><<P:Predicate_anonymous_7099>> => (STRBBroX GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend) |
| 27155 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRBBroX, |
| 27156 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val |
| 27157 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27158 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 27159 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 27160 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27161 | GIR_EraseFromParent, /*InsnID*/0, |
| 27162 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27163 | // GIR_Coverage, 5390, |
| 27164 | GIR_Done, |
| 27165 | // Label 1492: @68040 |
| 27166 | GIM_Try, /*On fail goto*//*Label 1493*/ 68093, // Rule ID 5394 // |
| 27167 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 27168 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 27169 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 27170 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27171 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 27172 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, |
| 27173 | // (atomic_store (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), GPR32:{ *:[i32] }:$val)<<P:Predicate_atomic_store_16>><<P:Predicate_anonymous_7106>> => (STRHHroW GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend) |
| 27174 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHHroW, |
| 27175 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val |
| 27176 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27177 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 27178 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 27179 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27180 | GIR_EraseFromParent, /*InsnID*/0, |
| 27181 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27182 | // GIR_Coverage, 5394, |
| 27183 | GIR_Done, |
| 27184 | // Label 1493: @68093 |
| 27185 | GIM_Try, /*On fail goto*//*Label 1494*/ 68146, // Rule ID 5395 // |
| 27186 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 27187 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 27188 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 27189 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27190 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 27191 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, |
| 27192 | // (atomic_store (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), GPR32:{ *:[i32] }:$val)<<P:Predicate_atomic_store_16>><<P:Predicate_anonymous_7106>> => (STRHHroX GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend) |
| 27193 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHHroX, |
| 27194 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val |
| 27195 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27196 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 27197 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 27198 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27199 | GIR_EraseFromParent, /*InsnID*/0, |
| 27200 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27201 | // GIR_Coverage, 5395, |
| 27202 | GIR_Done, |
| 27203 | // Label 1494: @68146 |
| 27204 | GIM_Try, /*On fail goto*//*Label 1495*/ 68199, // Rule ID 5399 // |
| 27205 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 27206 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 27207 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 27208 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27209 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 27210 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, |
| 27211 | // (atomic_store (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), GPR32:{ *:[i32] }:$val)<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_7113>> => (STRWroW GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend) |
| 27212 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRWroW, |
| 27213 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val |
| 27214 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27215 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 27216 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 27217 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27218 | GIR_EraseFromParent, /*InsnID*/0, |
| 27219 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27220 | // GIR_Coverage, 5399, |
| 27221 | GIR_Done, |
| 27222 | // Label 1495: @68199 |
| 27223 | GIM_Try, /*On fail goto*//*Label 1496*/ 68252, // Rule ID 5400 // |
| 27224 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 27225 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 27226 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 27227 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27228 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 27229 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, |
| 27230 | // (atomic_store (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), GPR32:{ *:[i32] }:$val)<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_7113>> => (STRWroX GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend) |
| 27231 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRWroX, |
| 27232 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val |
| 27233 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27234 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 27235 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 27236 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27237 | GIR_EraseFromParent, /*InsnID*/0, |
| 27238 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27239 | // GIR_Coverage, 5400, |
| 27240 | GIR_Done, |
| 27241 | // Label 1496: @68252 |
| 27242 | GIM_Try, /*On fail goto*//*Label 1497*/ 68299, // Rule ID 304 // |
| 27243 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27244 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27245 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 27246 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27247 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, |
| 27248 | // (st GPR32z:{ *:[i32] }:$Rt, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURWi GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) |
| 27249 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURWi, |
| 27250 | GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::WZR, // Rt |
| 27251 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27252 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 27253 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27254 | GIR_EraseFromParent, /*InsnID*/0, |
| 27255 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27256 | // GIR_Coverage, 304, |
| 27257 | GIR_Done, |
| 27258 | // Label 1497: @68299 |
| 27259 | GIM_Try, /*On fail goto*//*Label 1498*/ 68345, // Rule ID 307 // |
| 27260 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27261 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27262 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 27263 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27264 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, |
| 27265 | // (st FPR32Op:{ *:[f32] }:$Rt, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURSi FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) |
| 27266 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURSi, |
| 27267 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27268 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27269 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 27270 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27271 | GIR_EraseFromParent, /*InsnID*/0, |
| 27272 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27273 | // GIR_Coverage, 307, |
| 27274 | GIR_Done, |
| 27275 | // Label 1498: @68345 |
| 27276 | GIM_Try, /*On fail goto*//*Label 1499*/ 68394, // Rule ID 5391 // |
| 27277 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 27278 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 27279 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 27280 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27281 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 27282 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed8, |
| 27283 | // (atomic_store (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), GPR32:{ *:[i32] }:$val)<<P:Predicate_atomic_store_8>><<P:Predicate_anonymous_7099>> => (STRBBui GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset) |
| 27284 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRBBui, |
| 27285 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val |
| 27286 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27287 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 27288 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27289 | GIR_EraseFromParent, /*InsnID*/0, |
| 27290 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27291 | // GIR_Coverage, 5391, |
| 27292 | GIR_Done, |
| 27293 | // Label 1499: @68394 |
| 27294 | GIM_Try, /*On fail goto*//*Label 1500*/ 68443, // Rule ID 5392 // |
| 27295 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 27296 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 27297 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 27298 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27299 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 27300 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled8, |
| 27301 | // (atomic_store (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), GPR32:{ *:[i32] }:$val)<<P:Predicate_atomic_store_8>><<P:Predicate_anonymous_7099>> => (STURBBi GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 27302 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURBBi, |
| 27303 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val |
| 27304 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 27306 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27307 | GIR_EraseFromParent, /*InsnID*/0, |
| 27308 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27309 | // GIR_Coverage, 5392, |
| 27310 | GIR_Done, |
| 27311 | // Label 1500: @68443 |
| 27312 | GIM_Try, /*On fail goto*//*Label 1501*/ 68492, // Rule ID 5396 // |
| 27313 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 27314 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 27315 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 27316 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27317 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 27318 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, |
| 27319 | // (atomic_store (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), GPR32:{ *:[i32] }:$val)<<P:Predicate_atomic_store_16>><<P:Predicate_anonymous_7106>> => (STRHHui GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset) |
| 27320 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRHHui, |
| 27321 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val |
| 27322 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 27324 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27325 | GIR_EraseFromParent, /*InsnID*/0, |
| 27326 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27327 | // GIR_Coverage, 5396, |
| 27328 | GIR_Done, |
| 27329 | // Label 1501: @68492 |
| 27330 | GIM_Try, /*On fail goto*//*Label 1502*/ 68541, // Rule ID 5397 // |
| 27331 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 27332 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 27333 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 27334 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27335 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 27336 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, |
| 27337 | // (atomic_store (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), GPR32:{ *:[i32] }:$val)<<P:Predicate_atomic_store_16>><<P:Predicate_anonymous_7106>> => (STURHHi GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 27338 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURHHi, |
| 27339 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val |
| 27340 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27341 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 27342 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27343 | GIR_EraseFromParent, /*InsnID*/0, |
| 27344 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27345 | // GIR_Coverage, 5397, |
| 27346 | GIR_Done, |
| 27347 | // Label 1502: @68541 |
| 27348 | GIM_Try, /*On fail goto*//*Label 1503*/ 68590, // Rule ID 5401 // |
| 27349 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 27350 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 27351 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 27352 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27353 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 27354 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, |
| 27355 | // (atomic_store (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), GPR32:{ *:[i32] }:$val)<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_7113>> => (STRWui GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset) |
| 27356 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRWui, |
| 27357 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val |
| 27358 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27359 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 27360 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27361 | GIR_EraseFromParent, /*InsnID*/0, |
| 27362 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27363 | // GIR_Coverage, 5401, |
| 27364 | GIR_Done, |
| 27365 | // Label 1503: @68590 |
| 27366 | GIM_Try, /*On fail goto*//*Label 1504*/ 68639, // Rule ID 5402 // |
| 27367 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 27368 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 27369 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 27370 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27371 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 27372 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, |
| 27373 | // (atomic_store (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), GPR32:{ *:[i32] }:$val)<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_7113>> => (STURWi GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 27374 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURWi, |
| 27375 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val |
| 27376 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27377 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 27378 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27379 | GIR_EraseFromParent, /*InsnID*/0, |
| 27380 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27381 | // GIR_Coverage, 5402, |
| 27382 | GIR_Done, |
| 27383 | // Label 1504: @68639 |
| 27384 | GIM_Try, /*On fail goto*//*Label 1505*/ 68670, // Rule ID 5388 // |
| 27385 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 27386 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 27387 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 27388 | // MIs[0] ptr |
| 27389 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 27390 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 27391 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 27392 | // (atomic_store GPR64sp:{ *:[i64] }:$ptr, GPR32:{ *:[i32] }:$val)<<P:Predicate_atomic_store_8>><<P:Predicate_anonymous_7097>> => (STLRB GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$ptr) |
| 27393 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::STLRB, |
| 27394 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27395 | // GIR_Coverage, 5388, |
| 27396 | GIR_Done, |
| 27397 | // Label 1505: @68670 |
| 27398 | GIM_Try, /*On fail goto*//*Label 1506*/ 68701, // Rule ID 5393 // |
| 27399 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 27400 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 27401 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 27402 | // MIs[0] ptr |
| 27403 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 27404 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 27405 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 27406 | // (atomic_store GPR64sp:{ *:[i64] }:$ptr, GPR32:{ *:[i32] }:$val)<<P:Predicate_atomic_store_16>><<P:Predicate_anonymous_7104>> => (STLRH GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$ptr) |
| 27407 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::STLRH, |
| 27408 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27409 | // GIR_Coverage, 5393, |
| 27410 | GIR_Done, |
| 27411 | // Label 1506: @68701 |
| 27412 | GIM_Try, /*On fail goto*//*Label 1507*/ 68732, // Rule ID 5398 // |
| 27413 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 27414 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 27415 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 27416 | // MIs[0] ptr |
| 27417 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 27418 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 27419 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 27420 | // (atomic_store GPR64sp:{ *:[i64] }:$ptr, GPR32:{ *:[i32] }:$val)<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_7111>> => (STLRW GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$ptr) |
| 27421 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::STLRW, |
| 27422 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27423 | // GIR_Coverage, 5398, |
| 27424 | GIR_Done, |
| 27425 | // Label 1507: @68732 |
| 27426 | GIM_Reject, |
| 27427 | // Label 1461: @68733 |
| 27428 | GIM_Try, /*On fail goto*//*Label 1508*/ 68808, // Rule ID 4850 // |
| 27429 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27430 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27431 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 27432 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 27433 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 27434 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 27435 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 27436 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 27437 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 27438 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 27439 | // MIs[2] Operand 1 |
| 27440 | // No operand predicates |
| 27441 | // MIs[0] Rn |
| 27442 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 27443 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 27444 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 27445 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 27446 | // (st (vector_extract:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1i64 VecListOne128:{ *:[v2i64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, GPR64sp:{ *:[i64] }:$Rn) |
| 27447 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i64, |
| 27448 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt |
| 27449 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 27450 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 27451 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, |
| 27452 | GIR_EraseFromParent, /*InsnID*/0, |
| 27453 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27454 | // GIR_Coverage, 4850, |
| 27455 | GIR_Done, |
| 27456 | // Label 1508: @68808 |
| 27457 | GIM_Try, /*On fail goto*//*Label 1509*/ 68883, // Rule ID 4851 // |
| 27458 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27459 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27460 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 27461 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 27462 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 27463 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 27464 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 27465 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 27466 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 27467 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 27468 | // MIs[2] Operand 1 |
| 27469 | // No operand predicates |
| 27470 | // MIs[0] Rn |
| 27471 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 27472 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 27473 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 27474 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 27475 | // (st (vector_extract:{ *:[f64] } VecListOne128:{ *:[v2f64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1i64 VecListOne128:{ *:[v2f64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, GPR64sp:{ *:[i64] }:$Rn) |
| 27476 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ST1i64, |
| 27477 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt |
| 27478 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 27479 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 27480 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, |
| 27481 | GIR_EraseFromParent, /*InsnID*/0, |
| 27482 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27483 | // GIR_Coverage, 4851, |
| 27484 | GIR_Done, |
| 27485 | // Label 1509: @68883 |
| 27486 | GIM_Try, /*On fail goto*//*Label 1510*/ 68933, // Rule ID 285 // |
| 27487 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27488 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27489 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 27490 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27491 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, |
| 27492 | // (st GPR64:{ *:[i64] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRXroW GPR64:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) |
| 27493 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRXroW, |
| 27494 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27495 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27496 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 27497 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 27498 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27499 | GIR_EraseFromParent, /*InsnID*/0, |
| 27500 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27501 | // GIR_Coverage, 285, |
| 27502 | GIR_Done, |
| 27503 | // Label 1510: @68933 |
| 27504 | GIM_Try, /*On fail goto*//*Label 1511*/ 68983, // Rule ID 286 // |
| 27505 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27506 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27507 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 27508 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27509 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, |
| 27510 | // (st GPR64:{ *:[i64] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRXroX GPR64:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) |
| 27511 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRXroX, |
| 27512 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27513 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27514 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 27515 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 27516 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27517 | GIR_EraseFromParent, /*InsnID*/0, |
| 27518 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27519 | // GIR_Coverage, 286, |
| 27520 | GIR_Done, |
| 27521 | // Label 1511: @68983 |
| 27522 | GIM_Try, /*On fail goto*//*Label 1512*/ 69033, // Rule ID 293 // |
| 27523 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27524 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27525 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 27526 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27527 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, |
| 27528 | // (st FPR64Op:{ *:[f64] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroW FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) |
| 27529 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, |
| 27530 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27531 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27532 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 27533 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 27534 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27535 | GIR_EraseFromParent, /*InsnID*/0, |
| 27536 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27537 | // GIR_Coverage, 293, |
| 27538 | GIR_Done, |
| 27539 | // Label 1512: @69033 |
| 27540 | GIM_Try, /*On fail goto*//*Label 1513*/ 69083, // Rule ID 294 // |
| 27541 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27542 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27543 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 27544 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27545 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, |
| 27546 | // (st FPR64Op:{ *:[f64] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroX FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) |
| 27547 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, |
| 27548 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27549 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27550 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 27551 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 27552 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27553 | GIR_EraseFromParent, /*InsnID*/0, |
| 27554 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27555 | // GIR_Coverage, 294, |
| 27556 | GIR_Done, |
| 27557 | // Label 1513: @69083 |
| 27558 | GIM_Try, /*On fail goto*//*Label 1514*/ 69133, // Rule ID 3759 // |
| 27559 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27560 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27561 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 27562 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27563 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, |
| 27564 | // (st FPR64:{ *:[v1i64] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroW FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) |
| 27565 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, |
| 27566 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27567 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27568 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 27569 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 27570 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27571 | GIR_EraseFromParent, /*InsnID*/0, |
| 27572 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27573 | // GIR_Coverage, 3759, |
| 27574 | GIR_Done, |
| 27575 | // Label 1514: @69133 |
| 27576 | GIM_Try, /*On fail goto*//*Label 1515*/ 69183, // Rule ID 3760 // |
| 27577 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27578 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27579 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 27580 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27581 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, |
| 27582 | // (st FPR64:{ *:[v1i64] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroX FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) |
| 27583 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, |
| 27584 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27585 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27586 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 27587 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 27588 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27589 | GIR_EraseFromParent, /*InsnID*/0, |
| 27590 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27591 | // GIR_Coverage, 3760, |
| 27592 | GIR_Done, |
| 27593 | // Label 1515: @69183 |
| 27594 | GIM_Try, /*On fail goto*//*Label 1516*/ 69233, // Rule ID 3761 // |
| 27595 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27596 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27597 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 27598 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27599 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, |
| 27600 | // (st FPR64:{ *:[v1f64] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroW FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) |
| 27601 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, |
| 27602 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27604 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 27605 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 27606 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27607 | GIR_EraseFromParent, /*InsnID*/0, |
| 27608 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27609 | // GIR_Coverage, 3761, |
| 27610 | GIR_Done, |
| 27611 | // Label 1516: @69233 |
| 27612 | GIM_Try, /*On fail goto*//*Label 1517*/ 69283, // Rule ID 3762 // |
| 27613 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27614 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27615 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 27616 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27617 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, |
| 27618 | // (st FPR64:{ *:[v1f64] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroX FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) |
| 27619 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, |
| 27620 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27621 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 27623 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 27624 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27625 | GIR_EraseFromParent, /*InsnID*/0, |
| 27626 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27627 | // GIR_Coverage, 3762, |
| 27628 | GIR_Done, |
| 27629 | // Label 1517: @69283 |
| 27630 | GIM_Try, /*On fail goto*//*Label 1518*/ 69330, // Rule ID 295 // |
| 27631 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27632 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27633 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 27634 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27635 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, |
| 27636 | // (st GPR64z:{ *:[i64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRXui GPR64z:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) |
| 27637 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRXui, |
| 27638 | GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::XZR, // Rt |
| 27639 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27640 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 27641 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27642 | GIR_EraseFromParent, /*InsnID*/0, |
| 27643 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27644 | // GIR_Coverage, 295, |
| 27645 | GIR_Done, |
| 27646 | // Label 1518: @69330 |
| 27647 | GIM_Try, /*On fail goto*//*Label 1519*/ 69376, // Rule ID 300 // |
| 27648 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27649 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27650 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 27651 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27652 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, |
| 27653 | // (st FPR64Op:{ *:[f64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) |
| 27654 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, |
| 27655 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27656 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27657 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 27658 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27659 | GIR_EraseFromParent, /*InsnID*/0, |
| 27660 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27661 | // GIR_Coverage, 300, |
| 27662 | GIR_Done, |
| 27663 | // Label 1519: @69376 |
| 27664 | GIM_Try, /*On fail goto*//*Label 1520*/ 69422, // Rule ID 3792 // |
| 27665 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27666 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27667 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 27668 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27669 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, |
| 27670 | // (st FPR64:{ *:[v1i64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) |
| 27671 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, |
| 27672 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27673 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27674 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 27675 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27676 | GIR_EraseFromParent, /*InsnID*/0, |
| 27677 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27678 | // GIR_Coverage, 3792, |
| 27679 | GIR_Done, |
| 27680 | // Label 1520: @69422 |
| 27681 | GIM_Try, /*On fail goto*//*Label 1521*/ 69468, // Rule ID 3793 // |
| 27682 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27683 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27684 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 27685 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27686 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, |
| 27687 | // (st FPR64:{ *:[v1f64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) |
| 27688 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, |
| 27689 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27690 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27691 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 27692 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27693 | GIR_EraseFromParent, /*InsnID*/0, |
| 27694 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27695 | // GIR_Coverage, 3793, |
| 27696 | GIR_Done, |
| 27697 | // Label 1521: @69468 |
| 27698 | GIM_Try, /*On fail goto*//*Label 1522*/ 69521, // Rule ID 5404 // |
| 27699 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, |
| 27700 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 27701 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 27702 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27703 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 27704 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, |
| 27705 | // (atomic_store (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), GPR64:{ *:[i64] }:$val)<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_7120>> => (STRXroW GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) |
| 27706 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRXroW, |
| 27707 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val |
| 27708 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27709 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 27710 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 27711 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27712 | GIR_EraseFromParent, /*InsnID*/0, |
| 27713 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27714 | // GIR_Coverage, 5404, |
| 27715 | GIR_Done, |
| 27716 | // Label 1522: @69521 |
| 27717 | GIM_Try, /*On fail goto*//*Label 1523*/ 69574, // Rule ID 5405 // |
| 27718 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, |
| 27719 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 27720 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 27721 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27722 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 27723 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, |
| 27724 | // (atomic_store (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), GPR64:{ *:[i64] }:$val)<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_7120>> => (STRXroX GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) |
| 27725 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRXroX, |
| 27726 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val |
| 27727 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27728 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 27729 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 27730 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27731 | GIR_EraseFromParent, /*InsnID*/0, |
| 27732 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27733 | // GIR_Coverage, 5405, |
| 27734 | GIR_Done, |
| 27735 | // Label 1523: @69574 |
| 27736 | GIM_Try, /*On fail goto*//*Label 1524*/ 69621, // Rule ID 303 // |
| 27737 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27738 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27739 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 27740 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27741 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, |
| 27742 | // (st GPR64z:{ *:[i64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURXi GPR64z:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) |
| 27743 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURXi, |
| 27744 | GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::XZR, // Rt |
| 27745 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27746 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 27747 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27748 | GIR_EraseFromParent, /*InsnID*/0, |
| 27749 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27750 | // GIR_Coverage, 303, |
| 27751 | GIR_Done, |
| 27752 | // Label 1524: @69621 |
| 27753 | GIM_Try, /*On fail goto*//*Label 1525*/ 69667, // Rule ID 308 // |
| 27754 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27755 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27756 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 27757 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27758 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, |
| 27759 | // (st FPR64Op:{ *:[f64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) |
| 27760 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, |
| 27761 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27762 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27763 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 27764 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27765 | GIR_EraseFromParent, /*InsnID*/0, |
| 27766 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27767 | // GIR_Coverage, 308, |
| 27768 | GIR_Done, |
| 27769 | // Label 1525: @69667 |
| 27770 | GIM_Try, /*On fail goto*//*Label 1526*/ 69716, // Rule ID 5406 // |
| 27771 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, |
| 27772 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 27773 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 27774 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27775 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 27776 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, |
| 27777 | // (atomic_store (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset), GPR64:{ *:[i64] }:$val)<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_7120>> => (STRXui GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) |
| 27778 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRXui, |
| 27779 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val |
| 27780 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27781 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 27782 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27783 | GIR_EraseFromParent, /*InsnID*/0, |
| 27784 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27785 | // GIR_Coverage, 5406, |
| 27786 | GIR_Done, |
| 27787 | // Label 1526: @69716 |
| 27788 | GIM_Try, /*On fail goto*//*Label 1527*/ 69765, // Rule ID 5407 // |
| 27789 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, |
| 27790 | GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 27791 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 27792 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27793 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 27794 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, |
| 27795 | // (atomic_store (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), GPR64:{ *:[i64] }:$val)<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_7120>> => (STURXi GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 27796 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURXi, |
| 27797 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val |
| 27798 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27799 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 27800 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27801 | GIR_EraseFromParent, /*InsnID*/0, |
| 27802 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27803 | // GIR_Coverage, 5407, |
| 27804 | GIR_Done, |
| 27805 | // Label 1527: @69765 |
| 27806 | GIM_Try, /*On fail goto*//*Label 1528*/ 69811, // Rule ID 3818 // |
| 27807 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27808 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27809 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 27810 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27811 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, |
| 27812 | // (st FPR64:{ *:[v1f64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 27813 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, |
| 27814 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27815 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27816 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 27817 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27818 | GIR_EraseFromParent, /*InsnID*/0, |
| 27819 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27820 | // GIR_Coverage, 3818, |
| 27821 | GIR_Done, |
| 27822 | // Label 1528: @69811 |
| 27823 | GIM_Try, /*On fail goto*//*Label 1529*/ 69857, // Rule ID 3819 // |
| 27824 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27825 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27826 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 27827 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27828 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, |
| 27829 | // (st FPR64:{ *:[v1i64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 27830 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, |
| 27831 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27833 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 27834 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27835 | GIR_EraseFromParent, /*InsnID*/0, |
| 27836 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27837 | // GIR_Coverage, 3819, |
| 27838 | GIR_Done, |
| 27839 | // Label 1529: @69857 |
| 27840 | GIM_Try, /*On fail goto*//*Label 1530*/ 69888, // Rule ID 5403 // |
| 27841 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, |
| 27842 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 27843 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, |
| 27844 | // MIs[0] ptr |
| 27845 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 27846 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 27847 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 27848 | // (atomic_store GPR64sp:{ *:[i64] }:$ptr, GPR64:{ *:[i64] }:$val)<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_7118>> => (STLRX GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$ptr) |
| 27849 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::STLRX, |
| 27850 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27851 | // GIR_Coverage, 5403, |
| 27852 | GIR_Done, |
| 27853 | // Label 1530: @69888 |
| 27854 | GIM_Try, /*On fail goto*//*Label 1531*/ 69912, // Rule ID 4815 // |
| 27855 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27856 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27857 | // MIs[0] Rn |
| 27858 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 27859 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 27860 | // (st v1i64:{ *:[v1i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1Onev1d v1i64:{ *:[v1i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) |
| 27861 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev1d, |
| 27862 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27863 | // GIR_Coverage, 4815, |
| 27864 | GIR_Done, |
| 27865 | // Label 1531: @69912 |
| 27866 | GIM_Reject, |
| 27867 | // Label 1462: @69913 |
| 27868 | GIM_Try, /*On fail goto*//*Label 1532*/ 70098, |
| 27869 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27870 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27871 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 27872 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27873 | GIM_Try, /*On fail goto*//*Label 1533*/ 69967, // Rule ID 3739 // |
| 27874 | GIM_CheckFeatures, GIFBS_UseSTRQro, |
| 27875 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, |
| 27876 | // (st FPR128:{ *:[f128] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroW FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) |
| 27877 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroW, |
| 27878 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27879 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27880 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 27881 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 27882 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27883 | GIR_EraseFromParent, /*InsnID*/0, |
| 27884 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27885 | // GIR_Coverage, 3739, |
| 27886 | GIR_Done, |
| 27887 | // Label 1533: @69967 |
| 27888 | GIM_Try, /*On fail goto*//*Label 1534*/ 70004, // Rule ID 3740 // |
| 27889 | GIM_CheckFeatures, GIFBS_UseSTRQro, |
| 27890 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, |
| 27891 | // (st FPR128:{ *:[f128] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroX FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) |
| 27892 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX, |
| 27893 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27894 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27895 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 27896 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 27897 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27898 | GIR_EraseFromParent, /*InsnID*/0, |
| 27899 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27900 | // GIR_Coverage, 3740, |
| 27901 | GIR_Done, |
| 27902 | // Label 1534: @70004 |
| 27903 | GIM_Try, /*On fail goto*//*Label 1535*/ 70035, // Rule ID 3800 // |
| 27904 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, |
| 27905 | // (st FPR128:{ *:[f128] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQui FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) |
| 27906 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, |
| 27907 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27908 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27909 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 27910 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27911 | GIR_EraseFromParent, /*InsnID*/0, |
| 27912 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27913 | // GIR_Coverage, 3800, |
| 27914 | GIR_Done, |
| 27915 | // Label 1535: @70035 |
| 27916 | GIM_Try, /*On fail goto*//*Label 1536*/ 70066, // Rule ID 3826 // |
| 27917 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, |
| 27918 | // (st FPR128:{ *:[f128] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 27919 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, |
| 27920 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27921 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27922 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 27923 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27924 | GIR_EraseFromParent, /*InsnID*/0, |
| 27925 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27926 | // GIR_Coverage, 3826, |
| 27927 | GIR_Done, |
| 27928 | // Label 1536: @70066 |
| 27929 | GIM_Try, /*On fail goto*//*Label 1537*/ 70097, // Rule ID 309 // |
| 27930 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, |
| 27931 | // (st FPR128Op:{ *:[f128] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128Op:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset) |
| 27932 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, |
| 27933 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27934 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27935 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 27936 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27937 | GIR_EraseFromParent, /*InsnID*/0, |
| 27938 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27939 | // GIR_Coverage, 309, |
| 27940 | GIR_Done, |
| 27941 | // Label 1537: @70097 |
| 27942 | GIM_Reject, |
| 27943 | // Label 1532: @70098 |
| 27944 | GIM_Reject, |
| 27945 | // Label 1463: @70099 |
| 27946 | GIM_Try, /*On fail goto*//*Label 1538*/ 70470, |
| 27947 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27948 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 27949 | GIM_Try, /*On fail goto*//*Label 1539*/ 70153, // Rule ID 3747 // |
| 27950 | GIM_CheckFeatures, GIFBS_IsLE, |
| 27951 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 27952 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27953 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, |
| 27954 | // (st FPR64:{ *:[v2i32] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroW FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) |
| 27955 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, |
| 27956 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27957 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 27959 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 27960 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27961 | GIR_EraseFromParent, /*InsnID*/0, |
| 27962 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27963 | // GIR_Coverage, 3747, |
| 27964 | GIR_Done, |
| 27965 | // Label 1539: @70153 |
| 27966 | GIM_Try, /*On fail goto*//*Label 1540*/ 70198, // Rule ID 3748 // |
| 27967 | GIM_CheckFeatures, GIFBS_IsLE, |
| 27968 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 27969 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27970 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, |
| 27971 | // (st FPR64:{ *:[v2i32] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroX FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) |
| 27972 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, |
| 27973 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27974 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27975 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 27976 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 27977 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27978 | GIR_EraseFromParent, /*InsnID*/0, |
| 27979 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27980 | // GIR_Coverage, 3748, |
| 27981 | GIR_Done, |
| 27982 | // Label 1540: @70198 |
| 27983 | GIM_Try, /*On fail goto*//*Label 1541*/ 70243, // Rule ID 3749 // |
| 27984 | GIM_CheckFeatures, GIFBS_IsLE, |
| 27985 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 27986 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27987 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, |
| 27988 | // (st FPR64:{ *:[v2f32] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroW FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) |
| 27989 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, |
| 27990 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 27991 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 27992 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 27993 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 27994 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 27995 | GIR_EraseFromParent, /*InsnID*/0, |
| 27996 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 27997 | // GIR_Coverage, 3749, |
| 27998 | GIR_Done, |
| 27999 | // Label 1541: @70243 |
| 28000 | GIM_Try, /*On fail goto*//*Label 1542*/ 70288, // Rule ID 3750 // |
| 28001 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28002 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 28003 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28004 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, |
| 28005 | // (st FPR64:{ *:[v2f32] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroX FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) |
| 28006 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, |
| 28007 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28008 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28009 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 28010 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 28011 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28012 | GIR_EraseFromParent, /*InsnID*/0, |
| 28013 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28014 | // GIR_Coverage, 3750, |
| 28015 | GIR_Done, |
| 28016 | // Label 1542: @70288 |
| 28017 | GIM_Try, /*On fail goto*//*Label 1543*/ 70329, // Rule ID 3794 // |
| 28018 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28019 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 28020 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28021 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, |
| 28022 | // (st FPR64:{ *:[v2f32] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) |
| 28023 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, |
| 28024 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28025 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28026 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28027 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28028 | GIR_EraseFromParent, /*InsnID*/0, |
| 28029 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28030 | // GIR_Coverage, 3794, |
| 28031 | GIR_Done, |
| 28032 | // Label 1543: @70329 |
| 28033 | GIM_Try, /*On fail goto*//*Label 1544*/ 70370, // Rule ID 3797 // |
| 28034 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28035 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 28036 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28037 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, |
| 28038 | // (st FPR64:{ *:[v2i32] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) |
| 28039 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, |
| 28040 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28041 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28042 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28043 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28044 | GIR_EraseFromParent, /*InsnID*/0, |
| 28045 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28046 | // GIR_Coverage, 3797, |
| 28047 | GIR_Done, |
| 28048 | // Label 1544: @70370 |
| 28049 | GIM_Try, /*On fail goto*//*Label 1545*/ 70411, // Rule ID 3820 // |
| 28050 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28051 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 28052 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28053 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, |
| 28054 | // (st FPR64:{ *:[v2f32] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 28055 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, |
| 28056 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28057 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28058 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28059 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28060 | GIR_EraseFromParent, /*InsnID*/0, |
| 28061 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28062 | // GIR_Coverage, 3820, |
| 28063 | GIR_Done, |
| 28064 | // Label 1545: @70411 |
| 28065 | GIM_Try, /*On fail goto*//*Label 1546*/ 70452, // Rule ID 3823 // |
| 28066 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28067 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 28068 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28069 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, |
| 28070 | // (st FPR64:{ *:[v2i32] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 28071 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, |
| 28072 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28073 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28074 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28075 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28076 | GIR_EraseFromParent, /*InsnID*/0, |
| 28077 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28078 | // GIR_Coverage, 3823, |
| 28079 | GIR_Done, |
| 28080 | // Label 1546: @70452 |
| 28081 | GIM_Try, /*On fail goto*//*Label 1547*/ 70469, // Rule ID 4814 // |
| 28082 | // MIs[0] Rn |
| 28083 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 28084 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 28085 | // (st v2i32:{ *:[v2i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1Onev2s v2i32:{ *:[v2i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) |
| 28086 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev2s, |
| 28087 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28088 | // GIR_Coverage, 4814, |
| 28089 | GIR_Done, |
| 28090 | // Label 1547: @70469 |
| 28091 | GIM_Reject, |
| 28092 | // Label 1538: @70470 |
| 28093 | GIM_Reject, |
| 28094 | // Label 1464: @70471 |
| 28095 | GIM_Try, /*On fail goto*//*Label 1548*/ 70883, |
| 28096 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28097 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 28098 | GIM_Try, /*On fail goto*//*Label 1549*/ 70525, // Rule ID 3763 // |
| 28099 | GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, |
| 28100 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28101 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28102 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, |
| 28103 | // (st FPR128:{ *:[v2i64] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroW FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) |
| 28104 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroW, |
| 28105 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28106 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28107 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 28108 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 28109 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28110 | GIR_EraseFromParent, /*InsnID*/0, |
| 28111 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28112 | // GIR_Coverage, 3763, |
| 28113 | GIR_Done, |
| 28114 | // Label 1549: @70525 |
| 28115 | GIM_Try, /*On fail goto*//*Label 1550*/ 70570, // Rule ID 3764 // |
| 28116 | GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, |
| 28117 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28118 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28119 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, |
| 28120 | // (st FPR128:{ *:[v2i64] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroX FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) |
| 28121 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX, |
| 28122 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28123 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28124 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 28125 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 28126 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28127 | GIR_EraseFromParent, /*InsnID*/0, |
| 28128 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28129 | // GIR_Coverage, 3764, |
| 28130 | GIR_Done, |
| 28131 | // Label 1550: @70570 |
| 28132 | GIM_Try, /*On fail goto*//*Label 1551*/ 70615, // Rule ID 3765 // |
| 28133 | GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, |
| 28134 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28135 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28136 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, |
| 28137 | // (st FPR128:{ *:[v2f64] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroW FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) |
| 28138 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroW, |
| 28139 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28140 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28141 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 28142 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 28143 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28144 | GIR_EraseFromParent, /*InsnID*/0, |
| 28145 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28146 | // GIR_Coverage, 3765, |
| 28147 | GIR_Done, |
| 28148 | // Label 1551: @70615 |
| 28149 | GIM_Try, /*On fail goto*//*Label 1552*/ 70660, // Rule ID 3766 // |
| 28150 | GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, |
| 28151 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28152 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28153 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, |
| 28154 | // (st FPR128:{ *:[v2f64] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroX FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) |
| 28155 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX, |
| 28156 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28157 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28158 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 28159 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 28160 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28161 | GIR_EraseFromParent, /*InsnID*/0, |
| 28162 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28163 | // GIR_Coverage, 3766, |
| 28164 | GIR_Done, |
| 28165 | // Label 1552: @70660 |
| 28166 | GIM_Try, /*On fail goto*//*Label 1553*/ 70701, // Rule ID 3802 // |
| 28167 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28168 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28169 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28170 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, |
| 28171 | // (st FPR128:{ *:[v2f64] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQui FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) |
| 28172 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, |
| 28173 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28174 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28175 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28176 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28177 | GIR_EraseFromParent, /*InsnID*/0, |
| 28178 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28179 | // GIR_Coverage, 3802, |
| 28180 | GIR_Done, |
| 28181 | // Label 1553: @70701 |
| 28182 | GIM_Try, /*On fail goto*//*Label 1554*/ 70742, // Rule ID 3806 // |
| 28183 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28184 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28185 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28186 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, |
| 28187 | // (st FPR128:{ *:[v2i64] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQui FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) |
| 28188 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, |
| 28189 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28190 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28191 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28192 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28193 | GIR_EraseFromParent, /*InsnID*/0, |
| 28194 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28195 | // GIR_Coverage, 3806, |
| 28196 | GIR_Done, |
| 28197 | // Label 1554: @70742 |
| 28198 | GIM_Try, /*On fail goto*//*Label 1555*/ 70783, // Rule ID 3828 // |
| 28199 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28200 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28201 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28202 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, |
| 28203 | // (st FPR128:{ *:[v2f64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 28204 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, |
| 28205 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28206 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28207 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28208 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28209 | GIR_EraseFromParent, /*InsnID*/0, |
| 28210 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28211 | // GIR_Coverage, 3828, |
| 28212 | GIR_Done, |
| 28213 | // Label 1555: @70783 |
| 28214 | GIM_Try, /*On fail goto*//*Label 1556*/ 70824, // Rule ID 3832 // |
| 28215 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28216 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28217 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28218 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, |
| 28219 | // (st FPR128:{ *:[v2i64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 28220 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, |
| 28221 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28222 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28223 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28224 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28225 | GIR_EraseFromParent, /*InsnID*/0, |
| 28226 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28227 | // GIR_Coverage, 3832, |
| 28228 | GIR_Done, |
| 28229 | // Label 1556: @70824 |
| 28230 | GIM_Try, /*On fail goto*//*Label 1557*/ 70865, // Rule ID 3833 // |
| 28231 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28232 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28233 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28234 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, |
| 28235 | // (st FPR128:{ *:[v2f64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 28236 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, |
| 28237 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28238 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28239 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28240 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28241 | GIR_EraseFromParent, /*InsnID*/0, |
| 28242 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28243 | // GIR_Coverage, 3833, |
| 28244 | GIR_Done, |
| 28245 | // Label 1557: @70865 |
| 28246 | GIM_Try, /*On fail goto*//*Label 1558*/ 70882, // Rule ID 4811 // |
| 28247 | // MIs[0] Rn |
| 28248 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 28249 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 28250 | // (st v2i64:{ *:[v2i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1Onev2d v2i64:{ *:[v2i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) |
| 28251 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev2d, |
| 28252 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28253 | // GIR_Coverage, 4811, |
| 28254 | GIR_Done, |
| 28255 | // Label 1558: @70882 |
| 28256 | GIM_Reject, |
| 28257 | // Label 1548: @70883 |
| 28258 | GIM_Reject, |
| 28259 | // Label 1465: @70884 |
| 28260 | GIM_Try, /*On fail goto*//*Label 1559*/ 71427, |
| 28261 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28262 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 28263 | GIM_Try, /*On fail goto*//*Label 1560*/ 70938, // Rule ID 3751 // |
| 28264 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28265 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 28266 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28267 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, |
| 28268 | // (st FPR64:{ *:[v4i16] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroW FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) |
| 28269 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, |
| 28270 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28271 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28272 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 28273 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 28274 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28275 | GIR_EraseFromParent, /*InsnID*/0, |
| 28276 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28277 | // GIR_Coverage, 3751, |
| 28278 | GIR_Done, |
| 28279 | // Label 1560: @70938 |
| 28280 | GIM_Try, /*On fail goto*//*Label 1561*/ 70983, // Rule ID 3752 // |
| 28281 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28282 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 28283 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28284 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, |
| 28285 | // (st FPR64:{ *:[v4i16] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroX FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) |
| 28286 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, |
| 28287 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28288 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28289 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 28290 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 28291 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28292 | GIR_EraseFromParent, /*InsnID*/0, |
| 28293 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28294 | // GIR_Coverage, 3752, |
| 28295 | GIR_Done, |
| 28296 | // Label 1561: @70983 |
| 28297 | GIM_Try, /*On fail goto*//*Label 1562*/ 71028, // Rule ID 3755 // |
| 28298 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28299 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 28300 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28301 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, |
| 28302 | // (st FPR64:{ *:[v4f16] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroW FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) |
| 28303 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, |
| 28304 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28306 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 28307 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 28308 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28309 | GIR_EraseFromParent, /*InsnID*/0, |
| 28310 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28311 | // GIR_Coverage, 3755, |
| 28312 | GIR_Done, |
| 28313 | // Label 1562: @71028 |
| 28314 | GIM_Try, /*On fail goto*//*Label 1563*/ 71073, // Rule ID 3756 // |
| 28315 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28316 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 28317 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28318 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, |
| 28319 | // (st FPR64:{ *:[v4f16] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroX FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) |
| 28320 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, |
| 28321 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28322 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 28324 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 28325 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28326 | GIR_EraseFromParent, /*InsnID*/0, |
| 28327 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28328 | // GIR_Coverage, 3756, |
| 28329 | GIR_Done, |
| 28330 | // Label 1563: @71073 |
| 28331 | GIM_Try, /*On fail goto*//*Label 1564*/ 71118, // Rule ID 3757 // |
| 28332 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28333 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 28334 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28335 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, |
| 28336 | // (st FPR64:{ *:[v4bf16] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroW FPR64:{ *:[v4bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) |
| 28337 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, |
| 28338 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28339 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28340 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 28341 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 28342 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28343 | GIR_EraseFromParent, /*InsnID*/0, |
| 28344 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28345 | // GIR_Coverage, 3757, |
| 28346 | GIR_Done, |
| 28347 | // Label 1564: @71118 |
| 28348 | GIM_Try, /*On fail goto*//*Label 1565*/ 71163, // Rule ID 3758 // |
| 28349 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28350 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 28351 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28352 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, |
| 28353 | // (st FPR64:{ *:[v4bf16] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroX FPR64:{ *:[v4bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) |
| 28354 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, |
| 28355 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28356 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28357 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 28358 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 28359 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28360 | GIR_EraseFromParent, /*InsnID*/0, |
| 28361 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28362 | // GIR_Coverage, 3758, |
| 28363 | GIR_Done, |
| 28364 | // Label 1565: @71163 |
| 28365 | GIM_Try, /*On fail goto*//*Label 1566*/ 71204, // Rule ID 3796 // |
| 28366 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28367 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 28368 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28369 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, |
| 28370 | // (st FPR64:{ *:[v4i16] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) |
| 28371 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, |
| 28372 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28373 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28374 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28375 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28376 | GIR_EraseFromParent, /*InsnID*/0, |
| 28377 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28378 | // GIR_Coverage, 3796, |
| 28379 | GIR_Done, |
| 28380 | // Label 1566: @71204 |
| 28381 | GIM_Try, /*On fail goto*//*Label 1567*/ 71245, // Rule ID 3798 // |
| 28382 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28383 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 28384 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28385 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, |
| 28386 | // (st FPR64:{ *:[v4f16] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) |
| 28387 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, |
| 28388 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28389 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28390 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28391 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28392 | GIR_EraseFromParent, /*InsnID*/0, |
| 28393 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28394 | // GIR_Coverage, 3798, |
| 28395 | GIR_Done, |
| 28396 | // Label 1567: @71245 |
| 28397 | GIM_Try, /*On fail goto*//*Label 1568*/ 71286, // Rule ID 3799 // |
| 28398 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28399 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 28400 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28401 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, |
| 28402 | // (st FPR64:{ *:[v4bf16] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui FPR64:{ *:[v4bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) |
| 28403 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, |
| 28404 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28405 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28406 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28407 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28408 | GIR_EraseFromParent, /*InsnID*/0, |
| 28409 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28410 | // GIR_Coverage, 3799, |
| 28411 | GIR_Done, |
| 28412 | // Label 1568: @71286 |
| 28413 | GIM_Try, /*On fail goto*//*Label 1569*/ 71327, // Rule ID 3822 // |
| 28414 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28415 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 28416 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28417 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, |
| 28418 | // (st FPR64:{ *:[v4i16] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 28419 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, |
| 28420 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28421 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28422 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28423 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28424 | GIR_EraseFromParent, /*InsnID*/0, |
| 28425 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28426 | // GIR_Coverage, 3822, |
| 28427 | GIR_Done, |
| 28428 | // Label 1569: @71327 |
| 28429 | GIM_Try, /*On fail goto*//*Label 1570*/ 71368, // Rule ID 3824 // |
| 28430 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28431 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 28432 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28433 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, |
| 28434 | // (st FPR64:{ *:[v4f16] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 28435 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, |
| 28436 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28437 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28438 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28439 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28440 | GIR_EraseFromParent, /*InsnID*/0, |
| 28441 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28442 | // GIR_Coverage, 3824, |
| 28443 | GIR_Done, |
| 28444 | // Label 1570: @71368 |
| 28445 | GIM_Try, /*On fail goto*//*Label 1571*/ 71409, // Rule ID 3825 // |
| 28446 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28447 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 28448 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28449 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, |
| 28450 | // (st FPR64:{ *:[v4bf16] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi FPR64:{ *:[v4bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 28451 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, |
| 28452 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28453 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28454 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28455 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28456 | GIR_EraseFromParent, /*InsnID*/0, |
| 28457 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28458 | // GIR_Coverage, 3825, |
| 28459 | GIR_Done, |
| 28460 | // Label 1571: @71409 |
| 28461 | GIM_Try, /*On fail goto*//*Label 1572*/ 71426, // Rule ID 4813 // |
| 28462 | // MIs[0] Rn |
| 28463 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 28464 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 28465 | // (st v4i16:{ *:[v4i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1Onev4h v4i16:{ *:[v4i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) |
| 28466 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev4h, |
| 28467 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28468 | // GIR_Coverage, 4813, |
| 28469 | GIR_Done, |
| 28470 | // Label 1572: @71426 |
| 28471 | GIM_Reject, |
| 28472 | // Label 1559: @71427 |
| 28473 | GIM_Reject, |
| 28474 | // Label 1466: @71428 |
| 28475 | GIM_Try, /*On fail goto*//*Label 1573*/ 71799, |
| 28476 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28477 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 28478 | GIM_Try, /*On fail goto*//*Label 1574*/ 71482, // Rule ID 3767 // |
| 28479 | GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, |
| 28480 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28481 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28482 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, |
| 28483 | // (st FPR128:{ *:[v4i32] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroW FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) |
| 28484 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroW, |
| 28485 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28486 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28487 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 28488 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 28489 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28490 | GIR_EraseFromParent, /*InsnID*/0, |
| 28491 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28492 | // GIR_Coverage, 3767, |
| 28493 | GIR_Done, |
| 28494 | // Label 1574: @71482 |
| 28495 | GIM_Try, /*On fail goto*//*Label 1575*/ 71527, // Rule ID 3768 // |
| 28496 | GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, |
| 28497 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28498 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28499 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, |
| 28500 | // (st FPR128:{ *:[v4i32] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroX FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) |
| 28501 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX, |
| 28502 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28503 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28504 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 28505 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 28506 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28507 | GIR_EraseFromParent, /*InsnID*/0, |
| 28508 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28509 | // GIR_Coverage, 3768, |
| 28510 | GIR_Done, |
| 28511 | // Label 1575: @71527 |
| 28512 | GIM_Try, /*On fail goto*//*Label 1576*/ 71572, // Rule ID 3769 // |
| 28513 | GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, |
| 28514 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28515 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28516 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, |
| 28517 | // (st FPR128:{ *:[v4f32] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroW FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) |
| 28518 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroW, |
| 28519 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28520 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28521 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 28522 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 28523 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28524 | GIR_EraseFromParent, /*InsnID*/0, |
| 28525 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28526 | // GIR_Coverage, 3769, |
| 28527 | GIR_Done, |
| 28528 | // Label 1576: @71572 |
| 28529 | GIM_Try, /*On fail goto*//*Label 1577*/ 71617, // Rule ID 3770 // |
| 28530 | GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, |
| 28531 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28532 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28533 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, |
| 28534 | // (st FPR128:{ *:[v4f32] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroX FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) |
| 28535 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX, |
| 28536 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28537 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28538 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 28539 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 28540 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28541 | GIR_EraseFromParent, /*InsnID*/0, |
| 28542 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28543 | // GIR_Coverage, 3770, |
| 28544 | GIR_Done, |
| 28545 | // Label 1577: @71617 |
| 28546 | GIM_Try, /*On fail goto*//*Label 1578*/ 71658, // Rule ID 3801 // |
| 28547 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28548 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28549 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28550 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, |
| 28551 | // (st FPR128:{ *:[v4f32] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQui FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) |
| 28552 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, |
| 28553 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28554 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28555 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28556 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28557 | GIR_EraseFromParent, /*InsnID*/0, |
| 28558 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28559 | // GIR_Coverage, 3801, |
| 28560 | GIR_Done, |
| 28561 | // Label 1578: @71658 |
| 28562 | GIM_Try, /*On fail goto*//*Label 1579*/ 71699, // Rule ID 3805 // |
| 28563 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28564 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28565 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28566 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, |
| 28567 | // (st FPR128:{ *:[v4i32] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQui FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) |
| 28568 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, |
| 28569 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28570 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28571 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28572 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28573 | GIR_EraseFromParent, /*InsnID*/0, |
| 28574 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28575 | // GIR_Coverage, 3805, |
| 28576 | GIR_Done, |
| 28577 | // Label 1579: @71699 |
| 28578 | GIM_Try, /*On fail goto*//*Label 1580*/ 71740, // Rule ID 3827 // |
| 28579 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28580 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28581 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28582 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, |
| 28583 | // (st FPR128:{ *:[v4f32] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 28584 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, |
| 28585 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28586 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28587 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28588 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28589 | GIR_EraseFromParent, /*InsnID*/0, |
| 28590 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28591 | // GIR_Coverage, 3827, |
| 28592 | GIR_Done, |
| 28593 | // Label 1580: @71740 |
| 28594 | GIM_Try, /*On fail goto*//*Label 1581*/ 71781, // Rule ID 3831 // |
| 28595 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28596 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28597 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28598 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, |
| 28599 | // (st FPR128:{ *:[v4i32] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 28600 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, |
| 28601 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28602 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28604 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28605 | GIR_EraseFromParent, /*InsnID*/0, |
| 28606 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28607 | // GIR_Coverage, 3831, |
| 28608 | GIR_Done, |
| 28609 | // Label 1581: @71781 |
| 28610 | GIM_Try, /*On fail goto*//*Label 1582*/ 71798, // Rule ID 4810 // |
| 28611 | // MIs[0] Rn |
| 28612 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 28613 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 28614 | // (st v4i32:{ *:[v4i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1Onev4s v4i32:{ *:[v4i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) |
| 28615 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev4s, |
| 28616 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28617 | // GIR_Coverage, 4810, |
| 28618 | GIR_Done, |
| 28619 | // Label 1582: @71798 |
| 28620 | GIM_Reject, |
| 28621 | // Label 1573: @71799 |
| 28622 | GIM_Reject, |
| 28623 | // Label 1467: @71800 |
| 28624 | GIM_Try, /*On fail goto*//*Label 1583*/ 71999, |
| 28625 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28626 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 28627 | GIM_Try, /*On fail goto*//*Label 1584*/ 71854, // Rule ID 3753 // |
| 28628 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28629 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 28630 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28631 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed64, |
| 28632 | // (st FPR64:{ *:[v8i8] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroW FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend) |
| 28633 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroW, |
| 28634 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28635 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28636 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 28637 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 28638 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28639 | GIR_EraseFromParent, /*InsnID*/0, |
| 28640 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28641 | // GIR_Coverage, 3753, |
| 28642 | GIR_Done, |
| 28643 | // Label 1584: @71854 |
| 28644 | GIM_Try, /*On fail goto*//*Label 1585*/ 71899, // Rule ID 3754 // |
| 28645 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28646 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 28647 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28648 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed64, |
| 28649 | // (st FPR64:{ *:[v8i8] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroX FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend) |
| 28650 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDroX, |
| 28651 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28652 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28653 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 28654 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 28655 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28656 | GIR_EraseFromParent, /*InsnID*/0, |
| 28657 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28658 | // GIR_Coverage, 3754, |
| 28659 | GIR_Done, |
| 28660 | // Label 1585: @71899 |
| 28661 | GIM_Try, /*On fail goto*//*Label 1586*/ 71940, // Rule ID 3795 // |
| 28662 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28663 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 28664 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28665 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed64, |
| 28666 | // (st FPR64:{ *:[v8i8] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset) |
| 28667 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRDui, |
| 28668 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28669 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28670 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28671 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28672 | GIR_EraseFromParent, /*InsnID*/0, |
| 28673 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28674 | // GIR_Coverage, 3795, |
| 28675 | GIR_Done, |
| 28676 | // Label 1586: @71940 |
| 28677 | GIM_Try, /*On fail goto*//*Label 1587*/ 71981, // Rule ID 3821 // |
| 28678 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28679 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 28680 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28681 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled64, |
| 28682 | // (st FPR64:{ *:[v8i8] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 28683 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURDi, |
| 28684 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28685 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28686 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28687 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28688 | GIR_EraseFromParent, /*InsnID*/0, |
| 28689 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28690 | // GIR_Coverage, 3821, |
| 28691 | GIR_Done, |
| 28692 | // Label 1587: @71981 |
| 28693 | GIM_Try, /*On fail goto*//*Label 1588*/ 71998, // Rule ID 4812 // |
| 28694 | // MIs[0] Rn |
| 28695 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 28696 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 28697 | // (st v8i8:{ *:[v8i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1Onev8b v8i8:{ *:[v8i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) |
| 28698 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev8b, |
| 28699 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28700 | // GIR_Coverage, 4812, |
| 28701 | GIR_Done, |
| 28702 | // Label 1588: @71998 |
| 28703 | GIM_Reject, |
| 28704 | // Label 1583: @71999 |
| 28705 | GIM_Reject, |
| 28706 | // Label 1468: @72000 |
| 28707 | GIM_Try, /*On fail goto*//*Label 1589*/ 72543, |
| 28708 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28709 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 28710 | GIM_Try, /*On fail goto*//*Label 1590*/ 72054, // Rule ID 3771 // |
| 28711 | GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, |
| 28712 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28713 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28714 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, |
| 28715 | // (st FPR128:{ *:[v8i16] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroW FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) |
| 28716 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroW, |
| 28717 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28718 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28719 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 28720 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 28721 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28722 | GIR_EraseFromParent, /*InsnID*/0, |
| 28723 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28724 | // GIR_Coverage, 3771, |
| 28725 | GIR_Done, |
| 28726 | // Label 1590: @72054 |
| 28727 | GIM_Try, /*On fail goto*//*Label 1591*/ 72099, // Rule ID 3772 // |
| 28728 | GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, |
| 28729 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28730 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28731 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, |
| 28732 | // (st FPR128:{ *:[v8i16] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroX FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) |
| 28733 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX, |
| 28734 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28735 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28736 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 28737 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 28738 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28739 | GIR_EraseFromParent, /*InsnID*/0, |
| 28740 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28741 | // GIR_Coverage, 3772, |
| 28742 | GIR_Done, |
| 28743 | // Label 1591: @72099 |
| 28744 | GIM_Try, /*On fail goto*//*Label 1592*/ 72144, // Rule ID 3775 // |
| 28745 | GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, |
| 28746 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28747 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28748 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, |
| 28749 | // (st FPR128:{ *:[v8f16] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroW FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) |
| 28750 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroW, |
| 28751 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28752 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28753 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 28754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 28755 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28756 | GIR_EraseFromParent, /*InsnID*/0, |
| 28757 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28758 | // GIR_Coverage, 3775, |
| 28759 | GIR_Done, |
| 28760 | // Label 1592: @72144 |
| 28761 | GIM_Try, /*On fail goto*//*Label 1593*/ 72189, // Rule ID 3776 // |
| 28762 | GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, |
| 28763 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28764 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28765 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, |
| 28766 | // (st FPR128:{ *:[v8f16] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroX FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) |
| 28767 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX, |
| 28768 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28769 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28770 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 28771 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 28772 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28773 | GIR_EraseFromParent, /*InsnID*/0, |
| 28774 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28775 | // GIR_Coverage, 3776, |
| 28776 | GIR_Done, |
| 28777 | // Label 1593: @72189 |
| 28778 | GIM_Try, /*On fail goto*//*Label 1594*/ 72234, // Rule ID 3777 // |
| 28779 | GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, |
| 28780 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28781 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28782 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, |
| 28783 | // (st FPR128:{ *:[v8bf16] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroW FPR128:{ *:[v8bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) |
| 28784 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroW, |
| 28785 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28786 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28787 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 28788 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 28789 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28790 | GIR_EraseFromParent, /*InsnID*/0, |
| 28791 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28792 | // GIR_Coverage, 3777, |
| 28793 | GIR_Done, |
| 28794 | // Label 1594: @72234 |
| 28795 | GIM_Try, /*On fail goto*//*Label 1595*/ 72279, // Rule ID 3778 // |
| 28796 | GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, |
| 28797 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28798 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28799 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, |
| 28800 | // (st FPR128:{ *:[v8bf16] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroX FPR128:{ *:[v8bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) |
| 28801 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX, |
| 28802 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28803 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28804 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 28805 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 28806 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28807 | GIR_EraseFromParent, /*InsnID*/0, |
| 28808 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28809 | // GIR_Coverage, 3778, |
| 28810 | GIR_Done, |
| 28811 | // Label 1595: @72279 |
| 28812 | GIM_Try, /*On fail goto*//*Label 1596*/ 72320, // Rule ID 3804 // |
| 28813 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28814 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28815 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28816 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, |
| 28817 | // (st FPR128:{ *:[v8i16] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQui FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) |
| 28818 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, |
| 28819 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28820 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28821 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28822 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28823 | GIR_EraseFromParent, /*InsnID*/0, |
| 28824 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28825 | // GIR_Coverage, 3804, |
| 28826 | GIR_Done, |
| 28827 | // Label 1596: @72320 |
| 28828 | GIM_Try, /*On fail goto*//*Label 1597*/ 72361, // Rule ID 3807 // |
| 28829 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28830 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28831 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28832 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, |
| 28833 | // (st FPR128:{ *:[v8f16] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQui FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) |
| 28834 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, |
| 28835 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28836 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28837 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28838 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28839 | GIR_EraseFromParent, /*InsnID*/0, |
| 28840 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28841 | // GIR_Coverage, 3807, |
| 28842 | GIR_Done, |
| 28843 | // Label 1597: @72361 |
| 28844 | GIM_Try, /*On fail goto*//*Label 1598*/ 72402, // Rule ID 3808 // |
| 28845 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28846 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28847 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28848 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, |
| 28849 | // (st FPR128:{ *:[v8bf16] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQui FPR128:{ *:[v8bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) |
| 28850 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, |
| 28851 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28852 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28853 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28854 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28855 | GIR_EraseFromParent, /*InsnID*/0, |
| 28856 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28857 | // GIR_Coverage, 3808, |
| 28858 | GIR_Done, |
| 28859 | // Label 1598: @72402 |
| 28860 | GIM_Try, /*On fail goto*//*Label 1599*/ 72443, // Rule ID 3830 // |
| 28861 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28862 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28863 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28864 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, |
| 28865 | // (st FPR128:{ *:[v8i16] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 28866 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, |
| 28867 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28868 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28869 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28870 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28871 | GIR_EraseFromParent, /*InsnID*/0, |
| 28872 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28873 | // GIR_Coverage, 3830, |
| 28874 | GIR_Done, |
| 28875 | // Label 1599: @72443 |
| 28876 | GIM_Try, /*On fail goto*//*Label 1600*/ 72484, // Rule ID 3834 // |
| 28877 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28878 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28879 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28880 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, |
| 28881 | // (st FPR128:{ *:[v8f16] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 28882 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, |
| 28883 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28884 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28885 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28886 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28887 | GIR_EraseFromParent, /*InsnID*/0, |
| 28888 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28889 | // GIR_Coverage, 3834, |
| 28890 | GIR_Done, |
| 28891 | // Label 1600: @72484 |
| 28892 | GIM_Try, /*On fail goto*//*Label 1601*/ 72525, // Rule ID 3835 // |
| 28893 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28894 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28895 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28896 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, |
| 28897 | // (st FPR128:{ *:[v8bf16] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[v8bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 28898 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, |
| 28899 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28900 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28901 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28902 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28903 | GIR_EraseFromParent, /*InsnID*/0, |
| 28904 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28905 | // GIR_Coverage, 3835, |
| 28906 | GIR_Done, |
| 28907 | // Label 1601: @72525 |
| 28908 | GIM_Try, /*On fail goto*//*Label 1602*/ 72542, // Rule ID 4809 // |
| 28909 | // MIs[0] Rn |
| 28910 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 28911 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 28912 | // (st v8i16:{ *:[v8i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1Onev8h v8i16:{ *:[v8i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) |
| 28913 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev8h, |
| 28914 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28915 | // GIR_Coverage, 4809, |
| 28916 | GIR_Done, |
| 28917 | // Label 1602: @72542 |
| 28918 | GIM_Reject, |
| 28919 | // Label 1589: @72543 |
| 28920 | GIM_Reject, |
| 28921 | // Label 1469: @72544 |
| 28922 | GIM_Try, /*On fail goto*//*Label 1603*/ 72743, |
| 28923 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28924 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 28925 | GIM_Try, /*On fail goto*//*Label 1604*/ 72598, // Rule ID 3773 // |
| 28926 | GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, |
| 28927 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28928 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28929 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed128, |
| 28930 | // (st FPR128:{ *:[v16i8] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroW FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend) |
| 28931 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroW, |
| 28932 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28933 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28934 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 28935 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 28936 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28937 | GIR_EraseFromParent, /*InsnID*/0, |
| 28938 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28939 | // GIR_Coverage, 3773, |
| 28940 | GIR_Done, |
| 28941 | // Label 1604: @72598 |
| 28942 | GIM_Try, /*On fail goto*//*Label 1605*/ 72643, // Rule ID 3774 // |
| 28943 | GIM_CheckFeatures, GIFBS_IsLE_UseSTRQro, |
| 28944 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28945 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28946 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed128, |
| 28947 | // (st FPR128:{ *:[v16i8] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroX FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend) |
| 28948 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQroX, |
| 28949 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28950 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28951 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 28952 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // extend |
| 28953 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28954 | GIR_EraseFromParent, /*InsnID*/0, |
| 28955 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28956 | // GIR_Coverage, 3774, |
| 28957 | GIR_Done, |
| 28958 | // Label 1605: @72643 |
| 28959 | GIM_Try, /*On fail goto*//*Label 1606*/ 72684, // Rule ID 3803 // |
| 28960 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28961 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28962 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28963 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed128, |
| 28964 | // (st FPR128:{ *:[v16i8] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQui FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset) |
| 28965 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STRQui, |
| 28966 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28967 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28968 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28969 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28970 | GIR_EraseFromParent, /*InsnID*/0, |
| 28971 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28972 | // GIR_Coverage, 3803, |
| 28973 | GIR_Done, |
| 28974 | // Label 1606: @72684 |
| 28975 | GIM_Try, /*On fail goto*//*Label 1607*/ 72725, // Rule ID 3829 // |
| 28976 | GIM_CheckFeatures, GIFBS_IsLE, |
| 28977 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 28978 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28979 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled128, |
| 28980 | // (st FPR128:{ *:[v16i8] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset) |
| 28981 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STURQi, |
| 28982 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 28983 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 28984 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // offset |
| 28985 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 28986 | GIR_EraseFromParent, /*InsnID*/0, |
| 28987 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28988 | // GIR_Coverage, 3829, |
| 28989 | GIR_Done, |
| 28990 | // Label 1607: @72725 |
| 28991 | GIM_Try, /*On fail goto*//*Label 1608*/ 72742, // Rule ID 4808 // |
| 28992 | // MIs[0] Rn |
| 28993 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 28994 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 28995 | // (st v16i8:{ *:[v16i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1Onev16b v16i8:{ *:[v16i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn) |
| 28996 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ST1Onev16b, |
| 28997 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 28998 | // GIR_Coverage, 4808, |
| 28999 | GIR_Done, |
| 29000 | // Label 1608: @72742 |
| 29001 | GIM_Reject, |
| 29002 | // Label 1603: @72743 |
| 29003 | GIM_Reject, |
| 29004 | // Label 1470: @72744 |
| 29005 | GIM_Reject, |
| 29006 | // Label 18: @72745 |
| 29007 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1611*/ 73941, |
| 29008 | /*GILLT_s32*//*Label 1609*/ 72753, |
| 29009 | /*GILLT_s64*//*Label 1610*/ 73650, |
| 29010 | // Label 1609: @72753 |
| 29011 | GIM_Try, /*On fail goto*//*Label 1612*/ 73649, |
| 29012 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 29013 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 29014 | GIM_Try, /*On fail goto*//*Label 1613*/ 72822, // Rule ID 5618 // |
| 29015 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29016 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 29017 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 29018 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29019 | // MIs[0] Rn |
| 29020 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29021 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29022 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29023 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, |
| 29024 | // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_monotonic>> => (CASW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) |
| 29025 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASW, |
| 29026 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out |
| 29027 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold |
| 29028 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew |
| 29029 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29030 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29031 | GIR_EraseFromParent, /*InsnID*/0, |
| 29032 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29033 | // GIR_Coverage, 5618, |
| 29034 | GIR_Done, |
| 29035 | // Label 1613: @72822 |
| 29036 | GIM_Try, /*On fail goto*//*Label 1614*/ 72881, // Rule ID 5619 // |
| 29037 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29038 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 29039 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 29040 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29041 | // MIs[0] Rn |
| 29042 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29043 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29044 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29045 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, |
| 29046 | // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_acquire>> => (CASAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) |
| 29047 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASAW, |
| 29048 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out |
| 29049 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold |
| 29050 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew |
| 29051 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29052 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29053 | GIR_EraseFromParent, /*InsnID*/0, |
| 29054 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29055 | // GIR_Coverage, 5619, |
| 29056 | GIR_Done, |
| 29057 | // Label 1614: @72881 |
| 29058 | GIM_Try, /*On fail goto*//*Label 1615*/ 72940, // Rule ID 5620 // |
| 29059 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29060 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 29061 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 29062 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29063 | // MIs[0] Rn |
| 29064 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29065 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29066 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29067 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, |
| 29068 | // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_release>> => (CASLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) |
| 29069 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASLW, |
| 29070 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out |
| 29071 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold |
| 29072 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew |
| 29073 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29074 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29075 | GIR_EraseFromParent, /*InsnID*/0, |
| 29076 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29077 | // GIR_Coverage, 5620, |
| 29078 | GIR_Done, |
| 29079 | // Label 1615: @72940 |
| 29080 | GIM_Try, /*On fail goto*//*Label 1616*/ 72999, // Rule ID 5621 // |
| 29081 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29082 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 29083 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 29084 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29085 | // MIs[0] Rn |
| 29086 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29087 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29088 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29089 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, |
| 29090 | // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_acq_rel>> => (CASALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) |
| 29091 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALW, |
| 29092 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out |
| 29093 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold |
| 29094 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew |
| 29095 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29096 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29097 | GIR_EraseFromParent, /*InsnID*/0, |
| 29098 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29099 | // GIR_Coverage, 5621, |
| 29100 | GIR_Done, |
| 29101 | // Label 1616: @72999 |
| 29102 | GIM_Try, /*On fail goto*//*Label 1617*/ 73058, // Rule ID 5622 // |
| 29103 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29104 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 29105 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 29106 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29107 | // MIs[0] Rn |
| 29108 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29109 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29110 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29111 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, |
| 29112 | // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_seq_cst>> => (CASALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) |
| 29113 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALW, |
| 29114 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out |
| 29115 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold |
| 29116 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew |
| 29117 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29118 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29119 | GIR_EraseFromParent, /*InsnID*/0, |
| 29120 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29121 | // GIR_Coverage, 5622, |
| 29122 | GIR_Done, |
| 29123 | // Label 1617: @73058 |
| 29124 | GIM_Try, /*On fail goto*//*Label 1618*/ 73117, // Rule ID 5623 // |
| 29125 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29126 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 29127 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 29128 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29129 | // MIs[0] Rn |
| 29130 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29131 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29132 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29133 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, |
| 29134 | // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_16>><<P:Predicate_atomic_cmp_swap_16_monotonic>> => (CASH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) |
| 29135 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASH, |
| 29136 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out |
| 29137 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold |
| 29138 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew |
| 29139 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29140 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29141 | GIR_EraseFromParent, /*InsnID*/0, |
| 29142 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29143 | // GIR_Coverage, 5623, |
| 29144 | GIR_Done, |
| 29145 | // Label 1618: @73117 |
| 29146 | GIM_Try, /*On fail goto*//*Label 1619*/ 73176, // Rule ID 5624 // |
| 29147 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29148 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 29149 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 29150 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29151 | // MIs[0] Rn |
| 29152 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29153 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29154 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29155 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, |
| 29156 | // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_16>><<P:Predicate_atomic_cmp_swap_16_acquire>> => (CASAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) |
| 29157 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASAH, |
| 29158 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out |
| 29159 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold |
| 29160 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew |
| 29161 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29162 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29163 | GIR_EraseFromParent, /*InsnID*/0, |
| 29164 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29165 | // GIR_Coverage, 5624, |
| 29166 | GIR_Done, |
| 29167 | // Label 1619: @73176 |
| 29168 | GIM_Try, /*On fail goto*//*Label 1620*/ 73235, // Rule ID 5625 // |
| 29169 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29170 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 29171 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 29172 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29173 | // MIs[0] Rn |
| 29174 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29175 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29176 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29177 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, |
| 29178 | // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_16>><<P:Predicate_atomic_cmp_swap_16_release>> => (CASLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) |
| 29179 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASLH, |
| 29180 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out |
| 29181 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold |
| 29182 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew |
| 29183 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29184 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29185 | GIR_EraseFromParent, /*InsnID*/0, |
| 29186 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29187 | // GIR_Coverage, 5625, |
| 29188 | GIR_Done, |
| 29189 | // Label 1620: @73235 |
| 29190 | GIM_Try, /*On fail goto*//*Label 1621*/ 73294, // Rule ID 5626 // |
| 29191 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29192 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 29193 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 29194 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29195 | // MIs[0] Rn |
| 29196 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29197 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29198 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29199 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, |
| 29200 | // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_16>><<P:Predicate_atomic_cmp_swap_16_acq_rel>> => (CASALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) |
| 29201 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALH, |
| 29202 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out |
| 29203 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold |
| 29204 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew |
| 29205 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29206 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29207 | GIR_EraseFromParent, /*InsnID*/0, |
| 29208 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29209 | // GIR_Coverage, 5626, |
| 29210 | GIR_Done, |
| 29211 | // Label 1621: @73294 |
| 29212 | GIM_Try, /*On fail goto*//*Label 1622*/ 73353, // Rule ID 5627 // |
| 29213 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29214 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 29215 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 29216 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29217 | // MIs[0] Rn |
| 29218 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29219 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29220 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29221 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, |
| 29222 | // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_16>><<P:Predicate_atomic_cmp_swap_16_seq_cst>> => (CASALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) |
| 29223 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALH, |
| 29224 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out |
| 29225 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold |
| 29226 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew |
| 29227 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29228 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29229 | GIR_EraseFromParent, /*InsnID*/0, |
| 29230 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29231 | // GIR_Coverage, 5627, |
| 29232 | GIR_Done, |
| 29233 | // Label 1622: @73353 |
| 29234 | GIM_Try, /*On fail goto*//*Label 1623*/ 73412, // Rule ID 5628 // |
| 29235 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29236 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 29237 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 29238 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29239 | // MIs[0] Rn |
| 29240 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29241 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29242 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29243 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, |
| 29244 | // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_8>><<P:Predicate_atomic_cmp_swap_8_monotonic>> => (CASB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) |
| 29245 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASB, |
| 29246 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out |
| 29247 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold |
| 29248 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew |
| 29249 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29250 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29251 | GIR_EraseFromParent, /*InsnID*/0, |
| 29252 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29253 | // GIR_Coverage, 5628, |
| 29254 | GIR_Done, |
| 29255 | // Label 1623: @73412 |
| 29256 | GIM_Try, /*On fail goto*//*Label 1624*/ 73471, // Rule ID 5629 // |
| 29257 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29258 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 29259 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 29260 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29261 | // MIs[0] Rn |
| 29262 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29263 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29264 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29265 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, |
| 29266 | // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_8>><<P:Predicate_atomic_cmp_swap_8_acquire>> => (CASAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) |
| 29267 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASAB, |
| 29268 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out |
| 29269 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold |
| 29270 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew |
| 29271 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29272 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29273 | GIR_EraseFromParent, /*InsnID*/0, |
| 29274 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29275 | // GIR_Coverage, 5629, |
| 29276 | GIR_Done, |
| 29277 | // Label 1624: @73471 |
| 29278 | GIM_Try, /*On fail goto*//*Label 1625*/ 73530, // Rule ID 5630 // |
| 29279 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29280 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 29281 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 29282 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29283 | // MIs[0] Rn |
| 29284 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29285 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29286 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29287 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, |
| 29288 | // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_8>><<P:Predicate_atomic_cmp_swap_8_release>> => (CASLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) |
| 29289 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASLB, |
| 29290 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out |
| 29291 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold |
| 29292 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew |
| 29293 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29294 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29295 | GIR_EraseFromParent, /*InsnID*/0, |
| 29296 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29297 | // GIR_Coverage, 5630, |
| 29298 | GIR_Done, |
| 29299 | // Label 1625: @73530 |
| 29300 | GIM_Try, /*On fail goto*//*Label 1626*/ 73589, // Rule ID 5631 // |
| 29301 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29302 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 29303 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 29304 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29305 | // MIs[0] Rn |
| 29306 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29307 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29308 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29309 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, |
| 29310 | // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_8>><<P:Predicate_atomic_cmp_swap_8_acq_rel>> => (CASALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) |
| 29311 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALB, |
| 29312 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out |
| 29313 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold |
| 29314 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew |
| 29315 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29316 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29317 | GIR_EraseFromParent, /*InsnID*/0, |
| 29318 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29319 | // GIR_Coverage, 5631, |
| 29320 | GIR_Done, |
| 29321 | // Label 1626: @73589 |
| 29322 | GIM_Try, /*On fail goto*//*Label 1627*/ 73648, // Rule ID 5632 // |
| 29323 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29324 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 29325 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 29326 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29327 | // MIs[0] Rn |
| 29328 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29329 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29330 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29331 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, |
| 29332 | // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_8>><<P:Predicate_atomic_cmp_swap_8_seq_cst>> => (CASALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) |
| 29333 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALB, |
| 29334 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out |
| 29335 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold |
| 29336 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew |
| 29337 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29338 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29339 | GIR_EraseFromParent, /*InsnID*/0, |
| 29340 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29341 | // GIR_Coverage, 5632, |
| 29342 | GIR_Done, |
| 29343 | // Label 1627: @73648 |
| 29344 | GIM_Reject, |
| 29345 | // Label 1612: @73649 |
| 29346 | GIM_Reject, |
| 29347 | // Label 1610: @73650 |
| 29348 | GIM_Try, /*On fail goto*//*Label 1628*/ 73940, |
| 29349 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 29350 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 29351 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, |
| 29352 | GIM_Try, /*On fail goto*//*Label 1629*/ 73719, // Rule ID 2747 // |
| 29353 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29354 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 29355 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 29356 | // MIs[0] Rn |
| 29357 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29358 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29359 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 29360 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, |
| 29361 | // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_monotonic>> => (CASX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) |
| 29362 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASX, |
| 29363 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out |
| 29364 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold |
| 29365 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew |
| 29366 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29367 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29368 | GIR_EraseFromParent, /*InsnID*/0, |
| 29369 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29370 | // GIR_Coverage, 2747, |
| 29371 | GIR_Done, |
| 29372 | // Label 1629: @73719 |
| 29373 | GIM_Try, /*On fail goto*//*Label 1630*/ 73774, // Rule ID 2748 // |
| 29374 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29375 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 29376 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 29377 | // MIs[0] Rn |
| 29378 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29379 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29380 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 29381 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, |
| 29382 | // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_acquire>> => (CASAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) |
| 29383 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASAX, |
| 29384 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out |
| 29385 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold |
| 29386 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew |
| 29387 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29388 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29389 | GIR_EraseFromParent, /*InsnID*/0, |
| 29390 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29391 | // GIR_Coverage, 2748, |
| 29392 | GIR_Done, |
| 29393 | // Label 1630: @73774 |
| 29394 | GIM_Try, /*On fail goto*//*Label 1631*/ 73829, // Rule ID 2749 // |
| 29395 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29396 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 29397 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 29398 | // MIs[0] Rn |
| 29399 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29400 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29401 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 29402 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, |
| 29403 | // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_release>> => (CASLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) |
| 29404 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASLX, |
| 29405 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out |
| 29406 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold |
| 29407 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew |
| 29408 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29409 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29410 | GIR_EraseFromParent, /*InsnID*/0, |
| 29411 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29412 | // GIR_Coverage, 2749, |
| 29413 | GIR_Done, |
| 29414 | // Label 1631: @73829 |
| 29415 | GIM_Try, /*On fail goto*//*Label 1632*/ 73884, // Rule ID 2750 // |
| 29416 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29417 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 29418 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 29419 | // MIs[0] Rn |
| 29420 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29421 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29422 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 29423 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, |
| 29424 | // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_acq_rel>> => (CASALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) |
| 29425 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALX, |
| 29426 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out |
| 29427 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold |
| 29428 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew |
| 29429 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29430 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29431 | GIR_EraseFromParent, /*InsnID*/0, |
| 29432 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29433 | // GIR_Coverage, 2750, |
| 29434 | GIR_Done, |
| 29435 | // Label 1632: @73884 |
| 29436 | GIM_Try, /*On fail goto*//*Label 1633*/ 73939, // Rule ID 2751 // |
| 29437 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29438 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 29439 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 29440 | // MIs[0] Rn |
| 29441 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29442 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29443 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 29444 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, |
| 29445 | // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_seq_cst>> => (CASALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn) |
| 29446 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CASALX, |
| 29447 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out |
| 29448 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rold |
| 29449 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rnew |
| 29450 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29451 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29452 | GIR_EraseFromParent, /*InsnID*/0, |
| 29453 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29454 | // GIR_Coverage, 2751, |
| 29455 | GIR_Done, |
| 29456 | // Label 1633: @73939 |
| 29457 | GIM_Reject, |
| 29458 | // Label 1628: @73940 |
| 29459 | GIM_Reject, |
| 29460 | // Label 1611: @73941 |
| 29461 | GIM_Reject, |
| 29462 | // Label 19: @73942 |
| 29463 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1636*/ 74970, |
| 29464 | /*GILLT_s32*//*Label 1634*/ 73950, |
| 29465 | /*GILLT_s64*//*Label 1635*/ 74723, |
| 29466 | // Label 1634: @73950 |
| 29467 | GIM_Try, /*On fail goto*//*Label 1637*/ 74722, |
| 29468 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 29469 | GIM_Try, /*On fail goto*//*Label 1638*/ 74007, // Rule ID 5603 // |
| 29470 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29471 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 29472 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 29473 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29474 | // MIs[0] Rn |
| 29475 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29476 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29477 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29478 | // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_monotonic>> => (SWPW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 29479 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPW, |
| 29480 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 29481 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 29482 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29483 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29484 | GIR_EraseFromParent, /*InsnID*/0, |
| 29485 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29486 | // GIR_Coverage, 5603, |
| 29487 | GIR_Done, |
| 29488 | // Label 1638: @74007 |
| 29489 | GIM_Try, /*On fail goto*//*Label 1639*/ 74058, // Rule ID 5604 // |
| 29490 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29491 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 29492 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 29493 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29494 | // MIs[0] Rn |
| 29495 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29496 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29497 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29498 | // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_acquire>> => (SWPAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 29499 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPAW, |
| 29500 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 29501 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 29502 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29503 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29504 | GIR_EraseFromParent, /*InsnID*/0, |
| 29505 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29506 | // GIR_Coverage, 5604, |
| 29507 | GIR_Done, |
| 29508 | // Label 1639: @74058 |
| 29509 | GIM_Try, /*On fail goto*//*Label 1640*/ 74109, // Rule ID 5605 // |
| 29510 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29511 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 29512 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 29513 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29514 | // MIs[0] Rn |
| 29515 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29516 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29517 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29518 | // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_release>> => (SWPLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 29519 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPLW, |
| 29520 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 29521 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 29522 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29523 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29524 | GIR_EraseFromParent, /*InsnID*/0, |
| 29525 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29526 | // GIR_Coverage, 5605, |
| 29527 | GIR_Done, |
| 29528 | // Label 1640: @74109 |
| 29529 | GIM_Try, /*On fail goto*//*Label 1641*/ 74160, // Rule ID 5606 // |
| 29530 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29531 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 29532 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 29533 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29534 | // MIs[0] Rn |
| 29535 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29536 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29537 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29538 | // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_acq_rel>> => (SWPALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 29539 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALW, |
| 29540 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 29541 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 29542 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29543 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29544 | GIR_EraseFromParent, /*InsnID*/0, |
| 29545 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29546 | // GIR_Coverage, 5606, |
| 29547 | GIR_Done, |
| 29548 | // Label 1641: @74160 |
| 29549 | GIM_Try, /*On fail goto*//*Label 1642*/ 74211, // Rule ID 5607 // |
| 29550 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29551 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 29552 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 29553 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29554 | // MIs[0] Rn |
| 29555 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29556 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29557 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29558 | // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_seq_cst>> => (SWPALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 29559 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALW, |
| 29560 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 29561 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 29562 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29563 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29564 | GIR_EraseFromParent, /*InsnID*/0, |
| 29565 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29566 | // GIR_Coverage, 5607, |
| 29567 | GIR_Done, |
| 29568 | // Label 1642: @74211 |
| 29569 | GIM_Try, /*On fail goto*//*Label 1643*/ 74262, // Rule ID 5608 // |
| 29570 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29571 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 29572 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 29573 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29574 | // MIs[0] Rn |
| 29575 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29576 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29577 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29578 | // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_16>><<P:Predicate_atomic_swap_16_monotonic>> => (SWPH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 29579 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPH, |
| 29580 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 29581 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 29582 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29583 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29584 | GIR_EraseFromParent, /*InsnID*/0, |
| 29585 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29586 | // GIR_Coverage, 5608, |
| 29587 | GIR_Done, |
| 29588 | // Label 1643: @74262 |
| 29589 | GIM_Try, /*On fail goto*//*Label 1644*/ 74313, // Rule ID 5609 // |
| 29590 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29591 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 29592 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 29593 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29594 | // MIs[0] Rn |
| 29595 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29596 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29597 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29598 | // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_16>><<P:Predicate_atomic_swap_16_acquire>> => (SWPAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 29599 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPAH, |
| 29600 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 29601 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 29602 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29603 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29604 | GIR_EraseFromParent, /*InsnID*/0, |
| 29605 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29606 | // GIR_Coverage, 5609, |
| 29607 | GIR_Done, |
| 29608 | // Label 1644: @74313 |
| 29609 | GIM_Try, /*On fail goto*//*Label 1645*/ 74364, // Rule ID 5610 // |
| 29610 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29611 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 29612 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 29613 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29614 | // MIs[0] Rn |
| 29615 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29616 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29617 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29618 | // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_16>><<P:Predicate_atomic_swap_16_release>> => (SWPLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 29619 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPLH, |
| 29620 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 29621 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 29622 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29623 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29624 | GIR_EraseFromParent, /*InsnID*/0, |
| 29625 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29626 | // GIR_Coverage, 5610, |
| 29627 | GIR_Done, |
| 29628 | // Label 1645: @74364 |
| 29629 | GIM_Try, /*On fail goto*//*Label 1646*/ 74415, // Rule ID 5611 // |
| 29630 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29631 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 29632 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 29633 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29634 | // MIs[0] Rn |
| 29635 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29636 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29637 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29638 | // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_16>><<P:Predicate_atomic_swap_16_acq_rel>> => (SWPALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 29639 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALH, |
| 29640 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 29641 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 29642 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29643 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29644 | GIR_EraseFromParent, /*InsnID*/0, |
| 29645 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29646 | // GIR_Coverage, 5611, |
| 29647 | GIR_Done, |
| 29648 | // Label 1646: @74415 |
| 29649 | GIM_Try, /*On fail goto*//*Label 1647*/ 74466, // Rule ID 5612 // |
| 29650 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29651 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 29652 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 29653 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29654 | // MIs[0] Rn |
| 29655 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29656 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29657 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29658 | // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_16>><<P:Predicate_atomic_swap_16_seq_cst>> => (SWPALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 29659 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALH, |
| 29660 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 29661 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 29662 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29663 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29664 | GIR_EraseFromParent, /*InsnID*/0, |
| 29665 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29666 | // GIR_Coverage, 5612, |
| 29667 | GIR_Done, |
| 29668 | // Label 1647: @74466 |
| 29669 | GIM_Try, /*On fail goto*//*Label 1648*/ 74517, // Rule ID 5613 // |
| 29670 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29671 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 29672 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 29673 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29674 | // MIs[0] Rn |
| 29675 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29676 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29677 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29678 | // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_8>><<P:Predicate_atomic_swap_8_monotonic>> => (SWPB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 29679 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPB, |
| 29680 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 29681 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 29682 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29683 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29684 | GIR_EraseFromParent, /*InsnID*/0, |
| 29685 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29686 | // GIR_Coverage, 5613, |
| 29687 | GIR_Done, |
| 29688 | // Label 1648: @74517 |
| 29689 | GIM_Try, /*On fail goto*//*Label 1649*/ 74568, // Rule ID 5614 // |
| 29690 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29691 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 29692 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 29693 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29694 | // MIs[0] Rn |
| 29695 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29696 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29697 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29698 | // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_8>><<P:Predicate_atomic_swap_8_acquire>> => (SWPAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 29699 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPAB, |
| 29700 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 29701 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 29702 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29703 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29704 | GIR_EraseFromParent, /*InsnID*/0, |
| 29705 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29706 | // GIR_Coverage, 5614, |
| 29707 | GIR_Done, |
| 29708 | // Label 1649: @74568 |
| 29709 | GIM_Try, /*On fail goto*//*Label 1650*/ 74619, // Rule ID 5615 // |
| 29710 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29711 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 29712 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 29713 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29714 | // MIs[0] Rn |
| 29715 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29716 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29717 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29718 | // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_8>><<P:Predicate_atomic_swap_8_release>> => (SWPLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 29719 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPLB, |
| 29720 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 29721 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 29722 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29723 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29724 | GIR_EraseFromParent, /*InsnID*/0, |
| 29725 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29726 | // GIR_Coverage, 5615, |
| 29727 | GIR_Done, |
| 29728 | // Label 1650: @74619 |
| 29729 | GIM_Try, /*On fail goto*//*Label 1651*/ 74670, // Rule ID 5616 // |
| 29730 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29731 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 29732 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 29733 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29734 | // MIs[0] Rn |
| 29735 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29736 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29737 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29738 | // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_8>><<P:Predicate_atomic_swap_8_acq_rel>> => (SWPALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 29739 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALB, |
| 29740 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 29741 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 29742 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29743 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29744 | GIR_EraseFromParent, /*InsnID*/0, |
| 29745 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29746 | // GIR_Coverage, 5616, |
| 29747 | GIR_Done, |
| 29748 | // Label 1651: @74670 |
| 29749 | GIM_Try, /*On fail goto*//*Label 1652*/ 74721, // Rule ID 5617 // |
| 29750 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29751 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 29752 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 29753 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29754 | // MIs[0] Rn |
| 29755 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29756 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29757 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29758 | // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_8>><<P:Predicate_atomic_swap_8_seq_cst>> => (SWPALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 29759 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALB, |
| 29760 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 29761 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 29762 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29763 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29764 | GIR_EraseFromParent, /*InsnID*/0, |
| 29765 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29766 | // GIR_Coverage, 5617, |
| 29767 | GIR_Done, |
| 29768 | // Label 1652: @74721 |
| 29769 | GIM_Reject, |
| 29770 | // Label 1637: @74722 |
| 29771 | GIM_Reject, |
| 29772 | // Label 1635: @74723 |
| 29773 | GIM_Try, /*On fail goto*//*Label 1653*/ 74969, |
| 29774 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 29775 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, |
| 29776 | GIM_Try, /*On fail goto*//*Label 1654*/ 74780, // Rule ID 5598 // |
| 29777 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29778 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 29779 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 29780 | // MIs[0] Rn |
| 29781 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29782 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29783 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 29784 | // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_monotonic>> => (SWPX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 29785 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPX, |
| 29786 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 29787 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 29788 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29789 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29790 | GIR_EraseFromParent, /*InsnID*/0, |
| 29791 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29792 | // GIR_Coverage, 5598, |
| 29793 | GIR_Done, |
| 29794 | // Label 1654: @74780 |
| 29795 | GIM_Try, /*On fail goto*//*Label 1655*/ 74827, // Rule ID 5599 // |
| 29796 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29797 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 29798 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 29799 | // MIs[0] Rn |
| 29800 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29801 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29802 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 29803 | // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_acquire>> => (SWPAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 29804 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPAX, |
| 29805 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 29806 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 29807 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29808 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29809 | GIR_EraseFromParent, /*InsnID*/0, |
| 29810 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29811 | // GIR_Coverage, 5599, |
| 29812 | GIR_Done, |
| 29813 | // Label 1655: @74827 |
| 29814 | GIM_Try, /*On fail goto*//*Label 1656*/ 74874, // Rule ID 5600 // |
| 29815 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29816 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 29817 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 29818 | // MIs[0] Rn |
| 29819 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29820 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29821 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 29822 | // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_release>> => (SWPLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 29823 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPLX, |
| 29824 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 29825 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 29826 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29827 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29828 | GIR_EraseFromParent, /*InsnID*/0, |
| 29829 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29830 | // GIR_Coverage, 5600, |
| 29831 | GIR_Done, |
| 29832 | // Label 1656: @74874 |
| 29833 | GIM_Try, /*On fail goto*//*Label 1657*/ 74921, // Rule ID 5601 // |
| 29834 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29835 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 29836 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 29837 | // MIs[0] Rn |
| 29838 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29839 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29840 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 29841 | // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_acq_rel>> => (SWPALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 29842 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALX, |
| 29843 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 29844 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 29845 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29846 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29847 | GIR_EraseFromParent, /*InsnID*/0, |
| 29848 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29849 | // GIR_Coverage, 5601, |
| 29850 | GIR_Done, |
| 29851 | // Label 1657: @74921 |
| 29852 | GIM_Try, /*On fail goto*//*Label 1658*/ 74968, // Rule ID 5602 // |
| 29853 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29854 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 29855 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 29856 | // MIs[0] Rn |
| 29857 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29858 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29859 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 29860 | // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_seq_cst>> => (SWPALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 29861 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SWPALX, |
| 29862 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 29863 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 29864 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29865 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29866 | GIR_EraseFromParent, /*InsnID*/0, |
| 29867 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29868 | // GIR_Coverage, 5602, |
| 29869 | GIR_Done, |
| 29870 | // Label 1658: @74968 |
| 29871 | GIM_Reject, |
| 29872 | // Label 1653: @74969 |
| 29873 | GIM_Reject, |
| 29874 | // Label 1636: @74970 |
| 29875 | GIM_Reject, |
| 29876 | // Label 20: @74971 |
| 29877 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1661*/ 75999, |
| 29878 | /*GILLT_s32*//*Label 1659*/ 74979, |
| 29879 | /*GILLT_s64*//*Label 1660*/ 75752, |
| 29880 | // Label 1659: @74979 |
| 29881 | GIM_Try, /*On fail goto*//*Label 1662*/ 75751, |
| 29882 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 29883 | GIM_Try, /*On fail goto*//*Label 1663*/ 75036, // Rule ID 5443 // |
| 29884 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29885 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 29886 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 29887 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29888 | // MIs[0] Rn |
| 29889 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29890 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29891 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29892 | // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_monotonic>> => (LDADDW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 29893 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDW, |
| 29894 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 29895 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 29896 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29897 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29898 | GIR_EraseFromParent, /*InsnID*/0, |
| 29899 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29900 | // GIR_Coverage, 5443, |
| 29901 | GIR_Done, |
| 29902 | // Label 1663: @75036 |
| 29903 | GIM_Try, /*On fail goto*//*Label 1664*/ 75087, // Rule ID 5444 // |
| 29904 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29905 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 29906 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 29907 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29908 | // MIs[0] Rn |
| 29909 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29910 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29911 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29912 | // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_acquire>> => (LDADDAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 29913 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAW, |
| 29914 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 29915 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 29916 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29917 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29918 | GIR_EraseFromParent, /*InsnID*/0, |
| 29919 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29920 | // GIR_Coverage, 5444, |
| 29921 | GIR_Done, |
| 29922 | // Label 1664: @75087 |
| 29923 | GIM_Try, /*On fail goto*//*Label 1665*/ 75138, // Rule ID 5445 // |
| 29924 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29925 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 29926 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 29927 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29928 | // MIs[0] Rn |
| 29929 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29930 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29931 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29932 | // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_release>> => (LDADDLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 29933 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLW, |
| 29934 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 29935 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 29936 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29937 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29938 | GIR_EraseFromParent, /*InsnID*/0, |
| 29939 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29940 | // GIR_Coverage, 5445, |
| 29941 | GIR_Done, |
| 29942 | // Label 1665: @75138 |
| 29943 | GIM_Try, /*On fail goto*//*Label 1666*/ 75189, // Rule ID 5446 // |
| 29944 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29945 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 29946 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 29947 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29948 | // MIs[0] Rn |
| 29949 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29950 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29951 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29952 | // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_acq_rel>> => (LDADDALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 29953 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALW, |
| 29954 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 29955 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 29956 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29957 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29958 | GIR_EraseFromParent, /*InsnID*/0, |
| 29959 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29960 | // GIR_Coverage, 5446, |
| 29961 | GIR_Done, |
| 29962 | // Label 1666: @75189 |
| 29963 | GIM_Try, /*On fail goto*//*Label 1667*/ 75240, // Rule ID 5447 // |
| 29964 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29965 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 29966 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 29967 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29968 | // MIs[0] Rn |
| 29969 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29970 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29971 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29972 | // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_seq_cst>> => (LDADDALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 29973 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALW, |
| 29974 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 29975 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 29976 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29977 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29978 | GIR_EraseFromParent, /*InsnID*/0, |
| 29979 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 29980 | // GIR_Coverage, 5447, |
| 29981 | GIR_Done, |
| 29982 | // Label 1667: @75240 |
| 29983 | GIM_Try, /*On fail goto*//*Label 1668*/ 75291, // Rule ID 5448 // |
| 29984 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 29985 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 29986 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 29987 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 29988 | // MIs[0] Rn |
| 29989 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29990 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 29991 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 29992 | // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_16>><<P:Predicate_atomic_load_add_16_monotonic>> => (LDADDH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 29993 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDH, |
| 29994 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 29995 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 29996 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 29997 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 29998 | GIR_EraseFromParent, /*InsnID*/0, |
| 29999 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30000 | // GIR_Coverage, 5448, |
| 30001 | GIR_Done, |
| 30002 | // Label 1668: @75291 |
| 30003 | GIM_Try, /*On fail goto*//*Label 1669*/ 75342, // Rule ID 5449 // |
| 30004 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30005 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 30006 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 30007 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30008 | // MIs[0] Rn |
| 30009 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30010 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30011 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30012 | // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_16>><<P:Predicate_atomic_load_add_16_acquire>> => (LDADDAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 30013 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAH, |
| 30014 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30015 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30016 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30017 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30018 | GIR_EraseFromParent, /*InsnID*/0, |
| 30019 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30020 | // GIR_Coverage, 5449, |
| 30021 | GIR_Done, |
| 30022 | // Label 1669: @75342 |
| 30023 | GIM_Try, /*On fail goto*//*Label 1670*/ 75393, // Rule ID 5450 // |
| 30024 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30025 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 30026 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 30027 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30028 | // MIs[0] Rn |
| 30029 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30030 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30031 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30032 | // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_16>><<P:Predicate_atomic_load_add_16_release>> => (LDADDLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 30033 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLH, |
| 30034 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30035 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30036 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30037 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30038 | GIR_EraseFromParent, /*InsnID*/0, |
| 30039 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30040 | // GIR_Coverage, 5450, |
| 30041 | GIR_Done, |
| 30042 | // Label 1670: @75393 |
| 30043 | GIM_Try, /*On fail goto*//*Label 1671*/ 75444, // Rule ID 5451 // |
| 30044 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30045 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 30046 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 30047 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30048 | // MIs[0] Rn |
| 30049 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30050 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30051 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30052 | // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_16>><<P:Predicate_atomic_load_add_16_acq_rel>> => (LDADDALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 30053 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALH, |
| 30054 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30055 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30056 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30057 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30058 | GIR_EraseFromParent, /*InsnID*/0, |
| 30059 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30060 | // GIR_Coverage, 5451, |
| 30061 | GIR_Done, |
| 30062 | // Label 1671: @75444 |
| 30063 | GIM_Try, /*On fail goto*//*Label 1672*/ 75495, // Rule ID 5452 // |
| 30064 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30065 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 30066 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 30067 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30068 | // MIs[0] Rn |
| 30069 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30070 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30071 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30072 | // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_16>><<P:Predicate_atomic_load_add_16_seq_cst>> => (LDADDALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 30073 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALH, |
| 30074 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30075 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30076 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30077 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30078 | GIR_EraseFromParent, /*InsnID*/0, |
| 30079 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30080 | // GIR_Coverage, 5452, |
| 30081 | GIR_Done, |
| 30082 | // Label 1672: @75495 |
| 30083 | GIM_Try, /*On fail goto*//*Label 1673*/ 75546, // Rule ID 5453 // |
| 30084 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30085 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 30086 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 30087 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30088 | // MIs[0] Rn |
| 30089 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30090 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30091 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30092 | // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_8>><<P:Predicate_atomic_load_add_8_monotonic>> => (LDADDB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 30093 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDB, |
| 30094 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30095 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30096 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30097 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30098 | GIR_EraseFromParent, /*InsnID*/0, |
| 30099 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30100 | // GIR_Coverage, 5453, |
| 30101 | GIR_Done, |
| 30102 | // Label 1673: @75546 |
| 30103 | GIM_Try, /*On fail goto*//*Label 1674*/ 75597, // Rule ID 5454 // |
| 30104 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30105 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 30106 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 30107 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30108 | // MIs[0] Rn |
| 30109 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30110 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30111 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30112 | // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_8>><<P:Predicate_atomic_load_add_8_acquire>> => (LDADDAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 30113 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAB, |
| 30114 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30115 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30116 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30117 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30118 | GIR_EraseFromParent, /*InsnID*/0, |
| 30119 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30120 | // GIR_Coverage, 5454, |
| 30121 | GIR_Done, |
| 30122 | // Label 1674: @75597 |
| 30123 | GIM_Try, /*On fail goto*//*Label 1675*/ 75648, // Rule ID 5455 // |
| 30124 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30125 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 30126 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 30127 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30128 | // MIs[0] Rn |
| 30129 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30130 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30131 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30132 | // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_8>><<P:Predicate_atomic_load_add_8_release>> => (LDADDLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 30133 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLB, |
| 30134 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30135 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30136 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30137 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30138 | GIR_EraseFromParent, /*InsnID*/0, |
| 30139 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30140 | // GIR_Coverage, 5455, |
| 30141 | GIR_Done, |
| 30142 | // Label 1675: @75648 |
| 30143 | GIM_Try, /*On fail goto*//*Label 1676*/ 75699, // Rule ID 5456 // |
| 30144 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30145 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 30146 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 30147 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30148 | // MIs[0] Rn |
| 30149 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30150 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30151 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30152 | // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_8>><<P:Predicate_atomic_load_add_8_acq_rel>> => (LDADDALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 30153 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALB, |
| 30154 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30155 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30156 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30157 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30158 | GIR_EraseFromParent, /*InsnID*/0, |
| 30159 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30160 | // GIR_Coverage, 5456, |
| 30161 | GIR_Done, |
| 30162 | // Label 1676: @75699 |
| 30163 | GIM_Try, /*On fail goto*//*Label 1677*/ 75750, // Rule ID 5457 // |
| 30164 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30165 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 30166 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 30167 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30168 | // MIs[0] Rn |
| 30169 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30170 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30171 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30172 | // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_8>><<P:Predicate_atomic_load_add_8_seq_cst>> => (LDADDALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 30173 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALB, |
| 30174 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30175 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30176 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30177 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30178 | GIR_EraseFromParent, /*InsnID*/0, |
| 30179 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30180 | // GIR_Coverage, 5457, |
| 30181 | GIR_Done, |
| 30182 | // Label 1677: @75750 |
| 30183 | GIM_Reject, |
| 30184 | // Label 1662: @75751 |
| 30185 | GIM_Reject, |
| 30186 | // Label 1660: @75752 |
| 30187 | GIM_Try, /*On fail goto*//*Label 1678*/ 75998, |
| 30188 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 30189 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, |
| 30190 | GIM_Try, /*On fail goto*//*Label 1679*/ 75809, // Rule ID 2742 // |
| 30191 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30192 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 30193 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 30194 | // MIs[0] Rn |
| 30195 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30196 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30197 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 30198 | // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_monotonic>> => (LDADDX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 30199 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDX, |
| 30200 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30201 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30202 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30203 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30204 | GIR_EraseFromParent, /*InsnID*/0, |
| 30205 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30206 | // GIR_Coverage, 2742, |
| 30207 | GIR_Done, |
| 30208 | // Label 1679: @75809 |
| 30209 | GIM_Try, /*On fail goto*//*Label 1680*/ 75856, // Rule ID 2743 // |
| 30210 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30211 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 30212 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 30213 | // MIs[0] Rn |
| 30214 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30215 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30216 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 30217 | // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_acquire>> => (LDADDAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 30218 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAX, |
| 30219 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30220 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30221 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30222 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30223 | GIR_EraseFromParent, /*InsnID*/0, |
| 30224 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30225 | // GIR_Coverage, 2743, |
| 30226 | GIR_Done, |
| 30227 | // Label 1680: @75856 |
| 30228 | GIM_Try, /*On fail goto*//*Label 1681*/ 75903, // Rule ID 2744 // |
| 30229 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30230 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 30231 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 30232 | // MIs[0] Rn |
| 30233 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30234 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30235 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 30236 | // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_release>> => (LDADDLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 30237 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLX, |
| 30238 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30239 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30240 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30241 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30242 | GIR_EraseFromParent, /*InsnID*/0, |
| 30243 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30244 | // GIR_Coverage, 2744, |
| 30245 | GIR_Done, |
| 30246 | // Label 1681: @75903 |
| 30247 | GIM_Try, /*On fail goto*//*Label 1682*/ 75950, // Rule ID 2745 // |
| 30248 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30249 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 30250 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 30251 | // MIs[0] Rn |
| 30252 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30253 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30254 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 30255 | // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_acq_rel>> => (LDADDALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 30256 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALX, |
| 30257 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30258 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30259 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30260 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30261 | GIR_EraseFromParent, /*InsnID*/0, |
| 30262 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30263 | // GIR_Coverage, 2745, |
| 30264 | GIR_Done, |
| 30265 | // Label 1682: @75950 |
| 30266 | GIM_Try, /*On fail goto*//*Label 1683*/ 75997, // Rule ID 2746 // |
| 30267 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30268 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 30269 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 30270 | // MIs[0] Rn |
| 30271 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30272 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30273 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 30274 | // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_seq_cst>> => (LDADDALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 30275 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALX, |
| 30276 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30277 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30278 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30279 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30280 | GIR_EraseFromParent, /*InsnID*/0, |
| 30281 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30282 | // GIR_Coverage, 2746, |
| 30283 | GIR_Done, |
| 30284 | // Label 1683: @75997 |
| 30285 | GIM_Reject, |
| 30286 | // Label 1678: @75998 |
| 30287 | GIM_Reject, |
| 30288 | // Label 1661: @75999 |
| 30289 | GIM_Reject, |
| 30290 | // Label 21: @76000 |
| 30291 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1686*/ 77428, |
| 30292 | /*GILLT_s32*//*Label 1684*/ 76008, |
| 30293 | /*GILLT_s64*//*Label 1685*/ 77081, |
| 30294 | // Label 1684: @76008 |
| 30295 | GIM_Try, /*On fail goto*//*Label 1687*/ 77080, |
| 30296 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 30297 | GIM_Try, /*On fail goto*//*Label 1688*/ 76085, // Rule ID 5638 // |
| 30298 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30299 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 30300 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 30301 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30302 | // MIs[0] Rn |
| 30303 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30304 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30305 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30306 | // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_monotonic>> => (LDADDW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30307 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 30308 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, |
| 30309 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 30310 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 30311 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30312 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30313 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDW, |
| 30314 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30315 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 30316 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30317 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30318 | GIR_EraseFromParent, /*InsnID*/0, |
| 30319 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30320 | // GIR_Coverage, 5638, |
| 30321 | GIR_Done, |
| 30322 | // Label 1688: @76085 |
| 30323 | GIM_Try, /*On fail goto*//*Label 1689*/ 76156, // Rule ID 5639 // |
| 30324 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30325 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 30326 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 30327 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30328 | // MIs[0] Rn |
| 30329 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30330 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30331 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30332 | // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_acquire>> => (LDADDAW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30333 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 30334 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, |
| 30335 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 30336 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 30337 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30338 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30339 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAW, |
| 30340 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30341 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 30342 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30343 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30344 | GIR_EraseFromParent, /*InsnID*/0, |
| 30345 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30346 | // GIR_Coverage, 5639, |
| 30347 | GIR_Done, |
| 30348 | // Label 1689: @76156 |
| 30349 | GIM_Try, /*On fail goto*//*Label 1690*/ 76227, // Rule ID 5640 // |
| 30350 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30351 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 30352 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 30353 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30354 | // MIs[0] Rn |
| 30355 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30356 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30357 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30358 | // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_release>> => (LDADDLW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30359 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 30360 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, |
| 30361 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 30362 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 30363 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30364 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30365 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLW, |
| 30366 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30367 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 30368 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30369 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30370 | GIR_EraseFromParent, /*InsnID*/0, |
| 30371 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30372 | // GIR_Coverage, 5640, |
| 30373 | GIR_Done, |
| 30374 | // Label 1690: @76227 |
| 30375 | GIM_Try, /*On fail goto*//*Label 1691*/ 76298, // Rule ID 5641 // |
| 30376 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30377 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 30378 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 30379 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30380 | // MIs[0] Rn |
| 30381 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30382 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30383 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30384 | // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_acq_rel>> => (LDADDALW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30385 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 30386 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, |
| 30387 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 30388 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 30389 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30390 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30391 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALW, |
| 30392 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30393 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 30394 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30395 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30396 | GIR_EraseFromParent, /*InsnID*/0, |
| 30397 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30398 | // GIR_Coverage, 5641, |
| 30399 | GIR_Done, |
| 30400 | // Label 1691: @76298 |
| 30401 | GIM_Try, /*On fail goto*//*Label 1692*/ 76369, // Rule ID 5642 // |
| 30402 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30403 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 30404 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 30405 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30406 | // MIs[0] Rn |
| 30407 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30408 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30409 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30410 | // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_seq_cst>> => (LDADDALW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30411 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 30412 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, |
| 30413 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 30414 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 30415 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30416 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30417 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALW, |
| 30418 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30419 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 30420 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30421 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30422 | GIR_EraseFromParent, /*InsnID*/0, |
| 30423 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30424 | // GIR_Coverage, 5642, |
| 30425 | GIR_Done, |
| 30426 | // Label 1692: @76369 |
| 30427 | GIM_Try, /*On fail goto*//*Label 1693*/ 76440, // Rule ID 5643 // |
| 30428 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30429 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 30430 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 30431 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30432 | // MIs[0] Rn |
| 30433 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30434 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30435 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30436 | // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_16>><<P:Predicate_atomic_load_sub_16_monotonic>> => (LDADDH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30437 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 30438 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, |
| 30439 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 30440 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 30441 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30442 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30443 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDH, |
| 30444 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30445 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 30446 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30447 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30448 | GIR_EraseFromParent, /*InsnID*/0, |
| 30449 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30450 | // GIR_Coverage, 5643, |
| 30451 | GIR_Done, |
| 30452 | // Label 1693: @76440 |
| 30453 | GIM_Try, /*On fail goto*//*Label 1694*/ 76511, // Rule ID 5644 // |
| 30454 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30455 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 30456 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 30457 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30458 | // MIs[0] Rn |
| 30459 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30460 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30461 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30462 | // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_16>><<P:Predicate_atomic_load_sub_16_acquire>> => (LDADDAH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30463 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 30464 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, |
| 30465 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 30466 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 30467 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30468 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30469 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAH, |
| 30470 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30471 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 30472 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30473 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30474 | GIR_EraseFromParent, /*InsnID*/0, |
| 30475 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30476 | // GIR_Coverage, 5644, |
| 30477 | GIR_Done, |
| 30478 | // Label 1694: @76511 |
| 30479 | GIM_Try, /*On fail goto*//*Label 1695*/ 76582, // Rule ID 5645 // |
| 30480 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30481 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 30482 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 30483 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30484 | // MIs[0] Rn |
| 30485 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30486 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30487 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30488 | // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_16>><<P:Predicate_atomic_load_sub_16_release>> => (LDADDLH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30489 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 30490 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, |
| 30491 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 30492 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 30493 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30494 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30495 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLH, |
| 30496 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30497 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 30498 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30499 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30500 | GIR_EraseFromParent, /*InsnID*/0, |
| 30501 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30502 | // GIR_Coverage, 5645, |
| 30503 | GIR_Done, |
| 30504 | // Label 1695: @76582 |
| 30505 | GIM_Try, /*On fail goto*//*Label 1696*/ 76653, // Rule ID 5646 // |
| 30506 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30507 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 30508 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 30509 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30510 | // MIs[0] Rn |
| 30511 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30512 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30513 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30514 | // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_16>><<P:Predicate_atomic_load_sub_16_acq_rel>> => (LDADDALH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30515 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 30516 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, |
| 30517 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 30518 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 30519 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30520 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30521 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALH, |
| 30522 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30523 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 30524 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30525 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30526 | GIR_EraseFromParent, /*InsnID*/0, |
| 30527 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30528 | // GIR_Coverage, 5646, |
| 30529 | GIR_Done, |
| 30530 | // Label 1696: @76653 |
| 30531 | GIM_Try, /*On fail goto*//*Label 1697*/ 76724, // Rule ID 5647 // |
| 30532 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30533 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 30534 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 30535 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30536 | // MIs[0] Rn |
| 30537 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30538 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30539 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30540 | // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_16>><<P:Predicate_atomic_load_sub_16_seq_cst>> => (LDADDALH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30541 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 30542 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, |
| 30543 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 30544 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 30545 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30546 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30547 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALH, |
| 30548 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30549 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 30550 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30551 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30552 | GIR_EraseFromParent, /*InsnID*/0, |
| 30553 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30554 | // GIR_Coverage, 5647, |
| 30555 | GIR_Done, |
| 30556 | // Label 1697: @76724 |
| 30557 | GIM_Try, /*On fail goto*//*Label 1698*/ 76795, // Rule ID 5648 // |
| 30558 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30559 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 30560 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 30561 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30562 | // MIs[0] Rn |
| 30563 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30564 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30565 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30566 | // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_8>><<P:Predicate_atomic_load_sub_8_monotonic>> => (LDADDB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30567 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 30568 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, |
| 30569 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 30570 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 30571 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30572 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30573 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDB, |
| 30574 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30575 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 30576 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30577 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30578 | GIR_EraseFromParent, /*InsnID*/0, |
| 30579 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30580 | // GIR_Coverage, 5648, |
| 30581 | GIR_Done, |
| 30582 | // Label 1698: @76795 |
| 30583 | GIM_Try, /*On fail goto*//*Label 1699*/ 76866, // Rule ID 5649 // |
| 30584 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30585 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 30586 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 30587 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30588 | // MIs[0] Rn |
| 30589 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30590 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30591 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30592 | // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_8>><<P:Predicate_atomic_load_sub_8_acquire>> => (LDADDAB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30593 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 30594 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, |
| 30595 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 30596 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 30597 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30598 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30599 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAB, |
| 30600 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30601 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 30602 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30603 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30604 | GIR_EraseFromParent, /*InsnID*/0, |
| 30605 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30606 | // GIR_Coverage, 5649, |
| 30607 | GIR_Done, |
| 30608 | // Label 1699: @76866 |
| 30609 | GIM_Try, /*On fail goto*//*Label 1700*/ 76937, // Rule ID 5650 // |
| 30610 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30611 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 30612 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 30613 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30614 | // MIs[0] Rn |
| 30615 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30616 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30617 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30618 | // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_8>><<P:Predicate_atomic_load_sub_8_release>> => (LDADDLB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30619 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 30620 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, |
| 30621 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 30622 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 30623 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30624 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30625 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLB, |
| 30626 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30627 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 30628 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30629 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30630 | GIR_EraseFromParent, /*InsnID*/0, |
| 30631 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30632 | // GIR_Coverage, 5650, |
| 30633 | GIR_Done, |
| 30634 | // Label 1700: @76937 |
| 30635 | GIM_Try, /*On fail goto*//*Label 1701*/ 77008, // Rule ID 5651 // |
| 30636 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30637 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 30638 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 30639 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30640 | // MIs[0] Rn |
| 30641 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30642 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30643 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30644 | // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_8>><<P:Predicate_atomic_load_sub_8_acq_rel>> => (LDADDALB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30645 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 30646 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, |
| 30647 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 30648 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 30649 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30650 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30651 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALB, |
| 30652 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30653 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 30654 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30655 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30656 | GIR_EraseFromParent, /*InsnID*/0, |
| 30657 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30658 | // GIR_Coverage, 5651, |
| 30659 | GIR_Done, |
| 30660 | // Label 1701: @77008 |
| 30661 | GIM_Try, /*On fail goto*//*Label 1702*/ 77079, // Rule ID 5652 // |
| 30662 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30663 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 30664 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 30665 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30666 | // MIs[0] Rn |
| 30667 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30668 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30669 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30670 | // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_8>><<P:Predicate_atomic_load_sub_8_seq_cst>> => (LDADDALB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30671 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 30672 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr, |
| 30673 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 30674 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 30675 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30676 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30677 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALB, |
| 30678 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30679 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 30680 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30681 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30682 | GIR_EraseFromParent, /*InsnID*/0, |
| 30683 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30684 | // GIR_Coverage, 5652, |
| 30685 | GIR_Done, |
| 30686 | // Label 1702: @77079 |
| 30687 | GIM_Reject, |
| 30688 | // Label 1687: @77080 |
| 30689 | GIM_Reject, |
| 30690 | // Label 1685: @77081 |
| 30691 | GIM_Try, /*On fail goto*//*Label 1703*/ 77427, |
| 30692 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 30693 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, |
| 30694 | GIM_Try, /*On fail goto*//*Label 1704*/ 77158, // Rule ID 5633 // |
| 30695 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30696 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 30697 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 30698 | // MIs[0] Rn |
| 30699 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30700 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30701 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 30702 | // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_monotonic>> => (LDADDX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30703 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 30704 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBXrr, |
| 30705 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 30706 | GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, |
| 30707 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30708 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30709 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDX, |
| 30710 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30711 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 30712 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30713 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30714 | GIR_EraseFromParent, /*InsnID*/0, |
| 30715 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30716 | // GIR_Coverage, 5633, |
| 30717 | GIR_Done, |
| 30718 | // Label 1704: @77158 |
| 30719 | GIM_Try, /*On fail goto*//*Label 1705*/ 77225, // Rule ID 5634 // |
| 30720 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30721 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 30722 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 30723 | // MIs[0] Rn |
| 30724 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30725 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30726 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 30727 | // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_acquire>> => (LDADDAX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30728 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 30729 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBXrr, |
| 30730 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 30731 | GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, |
| 30732 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30733 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30734 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDAX, |
| 30735 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30736 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 30737 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30738 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30739 | GIR_EraseFromParent, /*InsnID*/0, |
| 30740 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30741 | // GIR_Coverage, 5634, |
| 30742 | GIR_Done, |
| 30743 | // Label 1705: @77225 |
| 30744 | GIM_Try, /*On fail goto*//*Label 1706*/ 77292, // Rule ID 5635 // |
| 30745 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30746 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 30747 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 30748 | // MIs[0] Rn |
| 30749 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30750 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30751 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 30752 | // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_release>> => (LDADDLX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30753 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 30754 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBXrr, |
| 30755 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 30756 | GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, |
| 30757 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30758 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30759 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDLX, |
| 30760 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30761 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 30762 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30763 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30764 | GIR_EraseFromParent, /*InsnID*/0, |
| 30765 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30766 | // GIR_Coverage, 5635, |
| 30767 | GIR_Done, |
| 30768 | // Label 1706: @77292 |
| 30769 | GIM_Try, /*On fail goto*//*Label 1707*/ 77359, // Rule ID 5636 // |
| 30770 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30771 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 30772 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 30773 | // MIs[0] Rn |
| 30774 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30775 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30776 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 30777 | // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_acq_rel>> => (LDADDALX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30778 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 30779 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBXrr, |
| 30780 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 30781 | GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, |
| 30782 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30783 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30784 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALX, |
| 30785 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30786 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 30787 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30788 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30789 | GIR_EraseFromParent, /*InsnID*/0, |
| 30790 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30791 | // GIR_Coverage, 5636, |
| 30792 | GIR_Done, |
| 30793 | // Label 1707: @77359 |
| 30794 | GIM_Try, /*On fail goto*//*Label 1708*/ 77426, // Rule ID 5637 // |
| 30795 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30796 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 30797 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 30798 | // MIs[0] Rn |
| 30799 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30800 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30801 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 30802 | // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_seq_cst>> => (LDADDALX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30803 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 30804 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBXrr, |
| 30805 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 30806 | GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, |
| 30807 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30808 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30809 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDADDALX, |
| 30810 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30811 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 30812 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30813 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30814 | GIR_EraseFromParent, /*InsnID*/0, |
| 30815 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30816 | // GIR_Coverage, 5637, |
| 30817 | GIR_Done, |
| 30818 | // Label 1708: @77426 |
| 30819 | GIM_Reject, |
| 30820 | // Label 1703: @77427 |
| 30821 | GIM_Reject, |
| 30822 | // Label 1686: @77428 |
| 30823 | GIM_Reject, |
| 30824 | // Label 22: @77429 |
| 30825 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1711*/ 78857, |
| 30826 | /*GILLT_s32*//*Label 1709*/ 77437, |
| 30827 | /*GILLT_s64*//*Label 1710*/ 78510, |
| 30828 | // Label 1709: @77437 |
| 30829 | GIM_Try, /*On fail goto*//*Label 1712*/ 78509, |
| 30830 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 30831 | GIM_Try, /*On fail goto*//*Label 1713*/ 77514, // Rule ID 5658 // |
| 30832 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30833 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 30834 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 30835 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30836 | // MIs[0] Rn |
| 30837 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30838 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30839 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30840 | // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_monotonic>> => (LDCLRW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30841 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 30842 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, |
| 30843 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 30844 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 30845 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30846 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30847 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRW, |
| 30848 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30849 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 30850 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30851 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30852 | GIR_EraseFromParent, /*InsnID*/0, |
| 30853 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30854 | // GIR_Coverage, 5658, |
| 30855 | GIR_Done, |
| 30856 | // Label 1713: @77514 |
| 30857 | GIM_Try, /*On fail goto*//*Label 1714*/ 77585, // Rule ID 5659 // |
| 30858 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30859 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 30860 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 30861 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30862 | // MIs[0] Rn |
| 30863 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30864 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30865 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30866 | // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_acquire>> => (LDCLRAW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30867 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 30868 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, |
| 30869 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 30870 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 30871 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30872 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30873 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRAW, |
| 30874 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30875 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 30876 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30877 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30878 | GIR_EraseFromParent, /*InsnID*/0, |
| 30879 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30880 | // GIR_Coverage, 5659, |
| 30881 | GIR_Done, |
| 30882 | // Label 1714: @77585 |
| 30883 | GIM_Try, /*On fail goto*//*Label 1715*/ 77656, // Rule ID 5660 // |
| 30884 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30885 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 30886 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 30887 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30888 | // MIs[0] Rn |
| 30889 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30890 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30891 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30892 | // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_release>> => (LDCLRLW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30893 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 30894 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, |
| 30895 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 30896 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 30897 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30898 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30899 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRLW, |
| 30900 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30901 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 30902 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30903 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30904 | GIR_EraseFromParent, /*InsnID*/0, |
| 30905 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30906 | // GIR_Coverage, 5660, |
| 30907 | GIR_Done, |
| 30908 | // Label 1715: @77656 |
| 30909 | GIM_Try, /*On fail goto*//*Label 1716*/ 77727, // Rule ID 5661 // |
| 30910 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30911 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 30912 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 30913 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30914 | // MIs[0] Rn |
| 30915 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30916 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30917 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30918 | // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_acq_rel>> => (LDCLRALW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30919 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 30920 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, |
| 30921 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 30922 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 30923 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30924 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30925 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALW, |
| 30926 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30927 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 30928 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30929 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30930 | GIR_EraseFromParent, /*InsnID*/0, |
| 30931 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30932 | // GIR_Coverage, 5661, |
| 30933 | GIR_Done, |
| 30934 | // Label 1716: @77727 |
| 30935 | GIM_Try, /*On fail goto*//*Label 1717*/ 77798, // Rule ID 5662 // |
| 30936 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30937 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 30938 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 30939 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30940 | // MIs[0] Rn |
| 30941 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30942 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30943 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30944 | // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_seq_cst>> => (LDCLRALW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30945 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 30946 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, |
| 30947 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 30948 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 30949 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30950 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30951 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALW, |
| 30952 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30953 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 30954 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30955 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30956 | GIR_EraseFromParent, /*InsnID*/0, |
| 30957 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30958 | // GIR_Coverage, 5662, |
| 30959 | GIR_Done, |
| 30960 | // Label 1717: @77798 |
| 30961 | GIM_Try, /*On fail goto*//*Label 1718*/ 77869, // Rule ID 5663 // |
| 30962 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30963 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 30964 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 30965 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30966 | // MIs[0] Rn |
| 30967 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30968 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30969 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30970 | // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_16>><<P:Predicate_atomic_load_and_16_monotonic>> => (LDCLRH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30971 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 30972 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, |
| 30973 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 30974 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 30975 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 30976 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30977 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRH, |
| 30978 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 30979 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 30980 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 30981 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 30982 | GIR_EraseFromParent, /*InsnID*/0, |
| 30983 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 30984 | // GIR_Coverage, 5663, |
| 30985 | GIR_Done, |
| 30986 | // Label 1718: @77869 |
| 30987 | GIM_Try, /*On fail goto*//*Label 1719*/ 77940, // Rule ID 5664 // |
| 30988 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 30989 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 30990 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 30991 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 30992 | // MIs[0] Rn |
| 30993 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30994 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 30995 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 30996 | // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_16>><<P:Predicate_atomic_load_and_16_acquire>> => (LDCLRAH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 30997 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 30998 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, |
| 30999 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 31000 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 31001 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31002 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 31003 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRAH, |
| 31004 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31005 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 31006 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31007 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31008 | GIR_EraseFromParent, /*InsnID*/0, |
| 31009 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31010 | // GIR_Coverage, 5664, |
| 31011 | GIR_Done, |
| 31012 | // Label 1719: @77940 |
| 31013 | GIM_Try, /*On fail goto*//*Label 1720*/ 78011, // Rule ID 5665 // |
| 31014 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31015 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 31016 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 31017 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31018 | // MIs[0] Rn |
| 31019 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31020 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31021 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31022 | // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_16>><<P:Predicate_atomic_load_and_16_release>> => (LDCLRLH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 31023 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 31024 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, |
| 31025 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 31026 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 31027 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31028 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 31029 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRLH, |
| 31030 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31031 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 31032 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31033 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31034 | GIR_EraseFromParent, /*InsnID*/0, |
| 31035 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31036 | // GIR_Coverage, 5665, |
| 31037 | GIR_Done, |
| 31038 | // Label 1720: @78011 |
| 31039 | GIM_Try, /*On fail goto*//*Label 1721*/ 78082, // Rule ID 5666 // |
| 31040 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31041 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 31042 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 31043 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31044 | // MIs[0] Rn |
| 31045 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31046 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31047 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31048 | // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_16>><<P:Predicate_atomic_load_and_16_acq_rel>> => (LDCLRALH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 31049 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 31050 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, |
| 31051 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 31052 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 31053 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31054 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 31055 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALH, |
| 31056 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31057 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 31058 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31059 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31060 | GIR_EraseFromParent, /*InsnID*/0, |
| 31061 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31062 | // GIR_Coverage, 5666, |
| 31063 | GIR_Done, |
| 31064 | // Label 1721: @78082 |
| 31065 | GIM_Try, /*On fail goto*//*Label 1722*/ 78153, // Rule ID 5667 // |
| 31066 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31067 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 31068 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 31069 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31070 | // MIs[0] Rn |
| 31071 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31072 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31073 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31074 | // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_16>><<P:Predicate_atomic_load_and_16_seq_cst>> => (LDCLRALH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 31075 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 31076 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, |
| 31077 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 31078 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 31079 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31080 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 31081 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALH, |
| 31082 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31083 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 31084 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31085 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31086 | GIR_EraseFromParent, /*InsnID*/0, |
| 31087 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31088 | // GIR_Coverage, 5667, |
| 31089 | GIR_Done, |
| 31090 | // Label 1722: @78153 |
| 31091 | GIM_Try, /*On fail goto*//*Label 1723*/ 78224, // Rule ID 5668 // |
| 31092 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31093 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 31094 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 31095 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31096 | // MIs[0] Rn |
| 31097 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31098 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31099 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31100 | // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_8>><<P:Predicate_atomic_load_and_8_monotonic>> => (LDCLRB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 31101 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 31102 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, |
| 31103 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 31104 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 31105 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31106 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 31107 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRB, |
| 31108 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31109 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 31110 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31111 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31112 | GIR_EraseFromParent, /*InsnID*/0, |
| 31113 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31114 | // GIR_Coverage, 5668, |
| 31115 | GIR_Done, |
| 31116 | // Label 1723: @78224 |
| 31117 | GIM_Try, /*On fail goto*//*Label 1724*/ 78295, // Rule ID 5669 // |
| 31118 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31119 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 31120 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 31121 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31122 | // MIs[0] Rn |
| 31123 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31124 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31125 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31126 | // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_8>><<P:Predicate_atomic_load_and_8_acquire>> => (LDCLRAB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 31127 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 31128 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, |
| 31129 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 31130 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 31131 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31132 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 31133 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRAB, |
| 31134 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31135 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 31136 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31137 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31138 | GIR_EraseFromParent, /*InsnID*/0, |
| 31139 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31140 | // GIR_Coverage, 5669, |
| 31141 | GIR_Done, |
| 31142 | // Label 1724: @78295 |
| 31143 | GIM_Try, /*On fail goto*//*Label 1725*/ 78366, // Rule ID 5670 // |
| 31144 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31145 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 31146 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 31147 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31148 | // MIs[0] Rn |
| 31149 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31150 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31151 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31152 | // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_8>><<P:Predicate_atomic_load_and_8_release>> => (LDCLRLB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 31153 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 31154 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, |
| 31155 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 31156 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 31157 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31158 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 31159 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRLB, |
| 31160 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31161 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 31162 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31163 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31164 | GIR_EraseFromParent, /*InsnID*/0, |
| 31165 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31166 | // GIR_Coverage, 5670, |
| 31167 | GIR_Done, |
| 31168 | // Label 1725: @78366 |
| 31169 | GIM_Try, /*On fail goto*//*Label 1726*/ 78437, // Rule ID 5671 // |
| 31170 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31171 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 31172 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 31173 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31174 | // MIs[0] Rn |
| 31175 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31176 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31177 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31178 | // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_8>><<P:Predicate_atomic_load_and_8_acq_rel>> => (LDCLRALB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 31179 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 31180 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, |
| 31181 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 31182 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 31183 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31184 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 31185 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALB, |
| 31186 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31187 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 31188 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31189 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31190 | GIR_EraseFromParent, /*InsnID*/0, |
| 31191 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31192 | // GIR_Coverage, 5671, |
| 31193 | GIR_Done, |
| 31194 | // Label 1726: @78437 |
| 31195 | GIM_Try, /*On fail goto*//*Label 1727*/ 78508, // Rule ID 5672 // |
| 31196 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31197 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 31198 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 31199 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31200 | // MIs[0] Rn |
| 31201 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31202 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31203 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31204 | // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_8>><<P:Predicate_atomic_load_and_8_seq_cst>> => (LDCLRALB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 31205 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 31206 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr, |
| 31207 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 31208 | GIR_AddRegister, /*InsnID*/1, AArch64::WZR, /*AddRegisterRegFlags*/0, |
| 31209 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31210 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 31211 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALB, |
| 31212 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31213 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 31214 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31215 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31216 | GIR_EraseFromParent, /*InsnID*/0, |
| 31217 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31218 | // GIR_Coverage, 5672, |
| 31219 | GIR_Done, |
| 31220 | // Label 1727: @78508 |
| 31221 | GIM_Reject, |
| 31222 | // Label 1712: @78509 |
| 31223 | GIM_Reject, |
| 31224 | // Label 1710: @78510 |
| 31225 | GIM_Try, /*On fail goto*//*Label 1728*/ 78856, |
| 31226 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 31227 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, |
| 31228 | GIM_Try, /*On fail goto*//*Label 1729*/ 78587, // Rule ID 5653 // |
| 31229 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31230 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 31231 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 31232 | // MIs[0] Rn |
| 31233 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31234 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31235 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 31236 | // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_monotonic>> => (LDCLRX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 31237 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 31238 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNXrr, |
| 31239 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 31240 | GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, |
| 31241 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31242 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 31243 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRX, |
| 31244 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31245 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 31246 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31247 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31248 | GIR_EraseFromParent, /*InsnID*/0, |
| 31249 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31250 | // GIR_Coverage, 5653, |
| 31251 | GIR_Done, |
| 31252 | // Label 1729: @78587 |
| 31253 | GIM_Try, /*On fail goto*//*Label 1730*/ 78654, // Rule ID 5654 // |
| 31254 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31255 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 31256 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 31257 | // MIs[0] Rn |
| 31258 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31259 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31260 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 31261 | // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_acquire>> => (LDCLRAX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 31262 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 31263 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNXrr, |
| 31264 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 31265 | GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, |
| 31266 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31267 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 31268 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRAX, |
| 31269 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31270 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 31271 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31272 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31273 | GIR_EraseFromParent, /*InsnID*/0, |
| 31274 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31275 | // GIR_Coverage, 5654, |
| 31276 | GIR_Done, |
| 31277 | // Label 1730: @78654 |
| 31278 | GIM_Try, /*On fail goto*//*Label 1731*/ 78721, // Rule ID 5655 // |
| 31279 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31280 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 31281 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 31282 | // MIs[0] Rn |
| 31283 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31284 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31285 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 31286 | // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_release>> => (LDCLRLX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 31287 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 31288 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNXrr, |
| 31289 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 31290 | GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, |
| 31291 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31292 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 31293 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRLX, |
| 31294 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31295 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 31296 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31297 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31298 | GIR_EraseFromParent, /*InsnID*/0, |
| 31299 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31300 | // GIR_Coverage, 5655, |
| 31301 | GIR_Done, |
| 31302 | // Label 1731: @78721 |
| 31303 | GIM_Try, /*On fail goto*//*Label 1732*/ 78788, // Rule ID 5656 // |
| 31304 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31305 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 31306 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 31307 | // MIs[0] Rn |
| 31308 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31309 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31310 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 31311 | // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_acq_rel>> => (LDCLRALX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 31312 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 31313 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNXrr, |
| 31314 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 31315 | GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, |
| 31316 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31317 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 31318 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALX, |
| 31319 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31320 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 31321 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31322 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31323 | GIR_EraseFromParent, /*InsnID*/0, |
| 31324 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31325 | // GIR_Coverage, 5656, |
| 31326 | GIR_Done, |
| 31327 | // Label 1732: @78788 |
| 31328 | GIM_Try, /*On fail goto*//*Label 1733*/ 78855, // Rule ID 5657 // |
| 31329 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31330 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 31331 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 31332 | // MIs[0] Rn |
| 31333 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31334 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31335 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 31336 | // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_seq_cst>> => (LDCLRALX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn) |
| 31337 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 31338 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNXrr, |
| 31339 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 31340 | GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0, |
| 31341 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31342 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 31343 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDCLRALX, |
| 31344 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31345 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 31346 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31347 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31348 | GIR_EraseFromParent, /*InsnID*/0, |
| 31349 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31350 | // GIR_Coverage, 5657, |
| 31351 | GIR_Done, |
| 31352 | // Label 1733: @78855 |
| 31353 | GIM_Reject, |
| 31354 | // Label 1728: @78856 |
| 31355 | GIM_Reject, |
| 31356 | // Label 1711: @78857 |
| 31357 | GIM_Reject, |
| 31358 | // Label 23: @78858 |
| 31359 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1736*/ 79886, |
| 31360 | /*GILLT_s32*//*Label 1734*/ 78866, |
| 31361 | /*GILLT_s64*//*Label 1735*/ 79639, |
| 31362 | // Label 1734: @78866 |
| 31363 | GIM_Try, /*On fail goto*//*Label 1737*/ 79638, |
| 31364 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 31365 | GIM_Try, /*On fail goto*//*Label 1738*/ 78923, // Rule ID 5463 // |
| 31366 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31367 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 31368 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 31369 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31370 | // MIs[0] Rn |
| 31371 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31372 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31373 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31374 | // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_monotonic>> => (LDSETW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31375 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETW, |
| 31376 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31377 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31378 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31379 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31380 | GIR_EraseFromParent, /*InsnID*/0, |
| 31381 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31382 | // GIR_Coverage, 5463, |
| 31383 | GIR_Done, |
| 31384 | // Label 1738: @78923 |
| 31385 | GIM_Try, /*On fail goto*//*Label 1739*/ 78974, // Rule ID 5464 // |
| 31386 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31387 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 31388 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 31389 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31390 | // MIs[0] Rn |
| 31391 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31392 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31393 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31394 | // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_acquire>> => (LDSETAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31395 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETAW, |
| 31396 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31397 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31398 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31399 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31400 | GIR_EraseFromParent, /*InsnID*/0, |
| 31401 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31402 | // GIR_Coverage, 5464, |
| 31403 | GIR_Done, |
| 31404 | // Label 1739: @78974 |
| 31405 | GIM_Try, /*On fail goto*//*Label 1740*/ 79025, // Rule ID 5465 // |
| 31406 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31407 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 31408 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 31409 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31410 | // MIs[0] Rn |
| 31411 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31412 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31413 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31414 | // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_release>> => (LDSETLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31415 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETLW, |
| 31416 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31417 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31418 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31419 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31420 | GIR_EraseFromParent, /*InsnID*/0, |
| 31421 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31422 | // GIR_Coverage, 5465, |
| 31423 | GIR_Done, |
| 31424 | // Label 1740: @79025 |
| 31425 | GIM_Try, /*On fail goto*//*Label 1741*/ 79076, // Rule ID 5466 // |
| 31426 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31427 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 31428 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 31429 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31430 | // MIs[0] Rn |
| 31431 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31432 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31433 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31434 | // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_acq_rel>> => (LDSETALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31435 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALW, |
| 31436 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31437 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31438 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31439 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31440 | GIR_EraseFromParent, /*InsnID*/0, |
| 31441 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31442 | // GIR_Coverage, 5466, |
| 31443 | GIR_Done, |
| 31444 | // Label 1741: @79076 |
| 31445 | GIM_Try, /*On fail goto*//*Label 1742*/ 79127, // Rule ID 5467 // |
| 31446 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31447 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 31448 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 31449 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31450 | // MIs[0] Rn |
| 31451 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31452 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31453 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31454 | // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_seq_cst>> => (LDSETALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31455 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALW, |
| 31456 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31457 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31458 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31459 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31460 | GIR_EraseFromParent, /*InsnID*/0, |
| 31461 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31462 | // GIR_Coverage, 5467, |
| 31463 | GIR_Done, |
| 31464 | // Label 1742: @79127 |
| 31465 | GIM_Try, /*On fail goto*//*Label 1743*/ 79178, // Rule ID 5468 // |
| 31466 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31467 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 31468 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 31469 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31470 | // MIs[0] Rn |
| 31471 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31472 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31473 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31474 | // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_16>><<P:Predicate_atomic_load_or_16_monotonic>> => (LDSETH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31475 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETH, |
| 31476 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31477 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31478 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31479 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31480 | GIR_EraseFromParent, /*InsnID*/0, |
| 31481 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31482 | // GIR_Coverage, 5468, |
| 31483 | GIR_Done, |
| 31484 | // Label 1743: @79178 |
| 31485 | GIM_Try, /*On fail goto*//*Label 1744*/ 79229, // Rule ID 5469 // |
| 31486 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31487 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 31488 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 31489 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31490 | // MIs[0] Rn |
| 31491 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31492 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31493 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31494 | // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_16>><<P:Predicate_atomic_load_or_16_acquire>> => (LDSETAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31495 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETAH, |
| 31496 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31497 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31498 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31499 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31500 | GIR_EraseFromParent, /*InsnID*/0, |
| 31501 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31502 | // GIR_Coverage, 5469, |
| 31503 | GIR_Done, |
| 31504 | // Label 1744: @79229 |
| 31505 | GIM_Try, /*On fail goto*//*Label 1745*/ 79280, // Rule ID 5470 // |
| 31506 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31507 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 31508 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 31509 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31510 | // MIs[0] Rn |
| 31511 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31512 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31513 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31514 | // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_16>><<P:Predicate_atomic_load_or_16_release>> => (LDSETLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31515 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETLH, |
| 31516 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31517 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31518 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31519 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31520 | GIR_EraseFromParent, /*InsnID*/0, |
| 31521 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31522 | // GIR_Coverage, 5470, |
| 31523 | GIR_Done, |
| 31524 | // Label 1745: @79280 |
| 31525 | GIM_Try, /*On fail goto*//*Label 1746*/ 79331, // Rule ID 5471 // |
| 31526 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31527 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 31528 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 31529 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31530 | // MIs[0] Rn |
| 31531 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31532 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31533 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31534 | // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_16>><<P:Predicate_atomic_load_or_16_acq_rel>> => (LDSETALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31535 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALH, |
| 31536 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31537 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31538 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31539 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31540 | GIR_EraseFromParent, /*InsnID*/0, |
| 31541 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31542 | // GIR_Coverage, 5471, |
| 31543 | GIR_Done, |
| 31544 | // Label 1746: @79331 |
| 31545 | GIM_Try, /*On fail goto*//*Label 1747*/ 79382, // Rule ID 5472 // |
| 31546 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31547 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 31548 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 31549 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31550 | // MIs[0] Rn |
| 31551 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31552 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31553 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31554 | // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_16>><<P:Predicate_atomic_load_or_16_seq_cst>> => (LDSETALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31555 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALH, |
| 31556 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31557 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31558 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31559 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31560 | GIR_EraseFromParent, /*InsnID*/0, |
| 31561 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31562 | // GIR_Coverage, 5472, |
| 31563 | GIR_Done, |
| 31564 | // Label 1747: @79382 |
| 31565 | GIM_Try, /*On fail goto*//*Label 1748*/ 79433, // Rule ID 5473 // |
| 31566 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31567 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 31568 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 31569 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31570 | // MIs[0] Rn |
| 31571 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31572 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31573 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31574 | // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_8>><<P:Predicate_atomic_load_or_8_monotonic>> => (LDSETB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31575 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETB, |
| 31576 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31577 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31578 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31579 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31580 | GIR_EraseFromParent, /*InsnID*/0, |
| 31581 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31582 | // GIR_Coverage, 5473, |
| 31583 | GIR_Done, |
| 31584 | // Label 1748: @79433 |
| 31585 | GIM_Try, /*On fail goto*//*Label 1749*/ 79484, // Rule ID 5474 // |
| 31586 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31587 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 31588 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 31589 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31590 | // MIs[0] Rn |
| 31591 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31592 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31593 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31594 | // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_8>><<P:Predicate_atomic_load_or_8_acquire>> => (LDSETAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31595 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETAB, |
| 31596 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31597 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31598 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31599 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31600 | GIR_EraseFromParent, /*InsnID*/0, |
| 31601 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31602 | // GIR_Coverage, 5474, |
| 31603 | GIR_Done, |
| 31604 | // Label 1749: @79484 |
| 31605 | GIM_Try, /*On fail goto*//*Label 1750*/ 79535, // Rule ID 5475 // |
| 31606 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31607 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 31608 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 31609 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31610 | // MIs[0] Rn |
| 31611 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31612 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31613 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31614 | // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_8>><<P:Predicate_atomic_load_or_8_release>> => (LDSETLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31615 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETLB, |
| 31616 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31617 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31618 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31619 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31620 | GIR_EraseFromParent, /*InsnID*/0, |
| 31621 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31622 | // GIR_Coverage, 5475, |
| 31623 | GIR_Done, |
| 31624 | // Label 1750: @79535 |
| 31625 | GIM_Try, /*On fail goto*//*Label 1751*/ 79586, // Rule ID 5476 // |
| 31626 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31627 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 31628 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 31629 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31630 | // MIs[0] Rn |
| 31631 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31632 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31633 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31634 | // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_8>><<P:Predicate_atomic_load_or_8_acq_rel>> => (LDSETALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31635 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALB, |
| 31636 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31637 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31638 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31639 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31640 | GIR_EraseFromParent, /*InsnID*/0, |
| 31641 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31642 | // GIR_Coverage, 5476, |
| 31643 | GIR_Done, |
| 31644 | // Label 1751: @79586 |
| 31645 | GIM_Try, /*On fail goto*//*Label 1752*/ 79637, // Rule ID 5477 // |
| 31646 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31647 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 31648 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 31649 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31650 | // MIs[0] Rn |
| 31651 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31652 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31653 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31654 | // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_8>><<P:Predicate_atomic_load_or_8_seq_cst>> => (LDSETALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31655 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALB, |
| 31656 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31657 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31658 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31659 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31660 | GIR_EraseFromParent, /*InsnID*/0, |
| 31661 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31662 | // GIR_Coverage, 5477, |
| 31663 | GIR_Done, |
| 31664 | // Label 1752: @79637 |
| 31665 | GIM_Reject, |
| 31666 | // Label 1737: @79638 |
| 31667 | GIM_Reject, |
| 31668 | // Label 1735: @79639 |
| 31669 | GIM_Try, /*On fail goto*//*Label 1753*/ 79885, |
| 31670 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 31671 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, |
| 31672 | GIM_Try, /*On fail goto*//*Label 1754*/ 79696, // Rule ID 5458 // |
| 31673 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31674 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 31675 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 31676 | // MIs[0] Rn |
| 31677 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31678 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31679 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 31680 | // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_monotonic>> => (LDSETX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31681 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETX, |
| 31682 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31683 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31684 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31685 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31686 | GIR_EraseFromParent, /*InsnID*/0, |
| 31687 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31688 | // GIR_Coverage, 5458, |
| 31689 | GIR_Done, |
| 31690 | // Label 1754: @79696 |
| 31691 | GIM_Try, /*On fail goto*//*Label 1755*/ 79743, // Rule ID 5459 // |
| 31692 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31693 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 31694 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 31695 | // MIs[0] Rn |
| 31696 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31697 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31698 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 31699 | // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_acquire>> => (LDSETAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31700 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETAX, |
| 31701 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31702 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31703 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31704 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31705 | GIR_EraseFromParent, /*InsnID*/0, |
| 31706 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31707 | // GIR_Coverage, 5459, |
| 31708 | GIR_Done, |
| 31709 | // Label 1755: @79743 |
| 31710 | GIM_Try, /*On fail goto*//*Label 1756*/ 79790, // Rule ID 5460 // |
| 31711 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31712 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 31713 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 31714 | // MIs[0] Rn |
| 31715 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31716 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31717 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 31718 | // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_release>> => (LDSETLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31719 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETLX, |
| 31720 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31721 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31722 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31723 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31724 | GIR_EraseFromParent, /*InsnID*/0, |
| 31725 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31726 | // GIR_Coverage, 5460, |
| 31727 | GIR_Done, |
| 31728 | // Label 1756: @79790 |
| 31729 | GIM_Try, /*On fail goto*//*Label 1757*/ 79837, // Rule ID 5461 // |
| 31730 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31731 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 31732 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 31733 | // MIs[0] Rn |
| 31734 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31735 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31736 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 31737 | // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_acq_rel>> => (LDSETALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31738 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALX, |
| 31739 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31740 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31741 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31742 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31743 | GIR_EraseFromParent, /*InsnID*/0, |
| 31744 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31745 | // GIR_Coverage, 5461, |
| 31746 | GIR_Done, |
| 31747 | // Label 1757: @79837 |
| 31748 | GIM_Try, /*On fail goto*//*Label 1758*/ 79884, // Rule ID 5462 // |
| 31749 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31750 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 31751 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 31752 | // MIs[0] Rn |
| 31753 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31754 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31755 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 31756 | // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_seq_cst>> => (LDSETALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31757 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSETALX, |
| 31758 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31759 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31760 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31761 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31762 | GIR_EraseFromParent, /*InsnID*/0, |
| 31763 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31764 | // GIR_Coverage, 5462, |
| 31765 | GIR_Done, |
| 31766 | // Label 1758: @79884 |
| 31767 | GIM_Reject, |
| 31768 | // Label 1753: @79885 |
| 31769 | GIM_Reject, |
| 31770 | // Label 1736: @79886 |
| 31771 | GIM_Reject, |
| 31772 | // Label 24: @79887 |
| 31773 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1761*/ 80915, |
| 31774 | /*GILLT_s32*//*Label 1759*/ 79895, |
| 31775 | /*GILLT_s64*//*Label 1760*/ 80668, |
| 31776 | // Label 1759: @79895 |
| 31777 | GIM_Try, /*On fail goto*//*Label 1762*/ 80667, |
| 31778 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 31779 | GIM_Try, /*On fail goto*//*Label 1763*/ 79952, // Rule ID 5483 // |
| 31780 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31781 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 31782 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 31783 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31784 | // MIs[0] Rn |
| 31785 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31786 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31787 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31788 | // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_monotonic>> => (LDEORW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31789 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORW, |
| 31790 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31791 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31792 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31793 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31794 | GIR_EraseFromParent, /*InsnID*/0, |
| 31795 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31796 | // GIR_Coverage, 5483, |
| 31797 | GIR_Done, |
| 31798 | // Label 1763: @79952 |
| 31799 | GIM_Try, /*On fail goto*//*Label 1764*/ 80003, // Rule ID 5484 // |
| 31800 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31801 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 31802 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 31803 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31804 | // MIs[0] Rn |
| 31805 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31806 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31807 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31808 | // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_acquire>> => (LDEORAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31809 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORAW, |
| 31810 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31811 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31812 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31813 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31814 | GIR_EraseFromParent, /*InsnID*/0, |
| 31815 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31816 | // GIR_Coverage, 5484, |
| 31817 | GIR_Done, |
| 31818 | // Label 1764: @80003 |
| 31819 | GIM_Try, /*On fail goto*//*Label 1765*/ 80054, // Rule ID 5485 // |
| 31820 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31821 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 31822 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 31823 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31824 | // MIs[0] Rn |
| 31825 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31826 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31827 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31828 | // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_release>> => (LDEORLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31829 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORLW, |
| 31830 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31831 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31832 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31833 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31834 | GIR_EraseFromParent, /*InsnID*/0, |
| 31835 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31836 | // GIR_Coverage, 5485, |
| 31837 | GIR_Done, |
| 31838 | // Label 1765: @80054 |
| 31839 | GIM_Try, /*On fail goto*//*Label 1766*/ 80105, // Rule ID 5486 // |
| 31840 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31841 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 31842 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 31843 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31844 | // MIs[0] Rn |
| 31845 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31846 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31847 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31848 | // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_acq_rel>> => (LDEORALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31849 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALW, |
| 31850 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31851 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31852 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31853 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31854 | GIR_EraseFromParent, /*InsnID*/0, |
| 31855 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31856 | // GIR_Coverage, 5486, |
| 31857 | GIR_Done, |
| 31858 | // Label 1766: @80105 |
| 31859 | GIM_Try, /*On fail goto*//*Label 1767*/ 80156, // Rule ID 5487 // |
| 31860 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31861 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 31862 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 31863 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31864 | // MIs[0] Rn |
| 31865 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31866 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31867 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31868 | // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_seq_cst>> => (LDEORALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31869 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALW, |
| 31870 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31871 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31872 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31873 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31874 | GIR_EraseFromParent, /*InsnID*/0, |
| 31875 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31876 | // GIR_Coverage, 5487, |
| 31877 | GIR_Done, |
| 31878 | // Label 1767: @80156 |
| 31879 | GIM_Try, /*On fail goto*//*Label 1768*/ 80207, // Rule ID 5488 // |
| 31880 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31881 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 31882 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 31883 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31884 | // MIs[0] Rn |
| 31885 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31886 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31887 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31888 | // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_16>><<P:Predicate_atomic_load_xor_16_monotonic>> => (LDEORH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31889 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORH, |
| 31890 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31891 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31892 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31893 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31894 | GIR_EraseFromParent, /*InsnID*/0, |
| 31895 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31896 | // GIR_Coverage, 5488, |
| 31897 | GIR_Done, |
| 31898 | // Label 1768: @80207 |
| 31899 | GIM_Try, /*On fail goto*//*Label 1769*/ 80258, // Rule ID 5489 // |
| 31900 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31901 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 31902 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 31903 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31904 | // MIs[0] Rn |
| 31905 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31906 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31907 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31908 | // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_16>><<P:Predicate_atomic_load_xor_16_acquire>> => (LDEORAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31909 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORAH, |
| 31910 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31911 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31912 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31913 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31914 | GIR_EraseFromParent, /*InsnID*/0, |
| 31915 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31916 | // GIR_Coverage, 5489, |
| 31917 | GIR_Done, |
| 31918 | // Label 1769: @80258 |
| 31919 | GIM_Try, /*On fail goto*//*Label 1770*/ 80309, // Rule ID 5490 // |
| 31920 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31921 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 31922 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 31923 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31924 | // MIs[0] Rn |
| 31925 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31926 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31927 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31928 | // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_16>><<P:Predicate_atomic_load_xor_16_release>> => (LDEORLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31929 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORLH, |
| 31930 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31931 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31932 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31933 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31934 | GIR_EraseFromParent, /*InsnID*/0, |
| 31935 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31936 | // GIR_Coverage, 5490, |
| 31937 | GIR_Done, |
| 31938 | // Label 1770: @80309 |
| 31939 | GIM_Try, /*On fail goto*//*Label 1771*/ 80360, // Rule ID 5491 // |
| 31940 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31941 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 31942 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 31943 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31944 | // MIs[0] Rn |
| 31945 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31946 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31947 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31948 | // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_16>><<P:Predicate_atomic_load_xor_16_acq_rel>> => (LDEORALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31949 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALH, |
| 31950 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31951 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31952 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31953 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31954 | GIR_EraseFromParent, /*InsnID*/0, |
| 31955 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31956 | // GIR_Coverage, 5491, |
| 31957 | GIR_Done, |
| 31958 | // Label 1771: @80360 |
| 31959 | GIM_Try, /*On fail goto*//*Label 1772*/ 80411, // Rule ID 5492 // |
| 31960 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31961 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 31962 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 31963 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31964 | // MIs[0] Rn |
| 31965 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31966 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31967 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31968 | // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_16>><<P:Predicate_atomic_load_xor_16_seq_cst>> => (LDEORALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31969 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALH, |
| 31970 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31971 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31972 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31973 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31974 | GIR_EraseFromParent, /*InsnID*/0, |
| 31975 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31976 | // GIR_Coverage, 5492, |
| 31977 | GIR_Done, |
| 31978 | // Label 1772: @80411 |
| 31979 | GIM_Try, /*On fail goto*//*Label 1773*/ 80462, // Rule ID 5493 // |
| 31980 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 31981 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 31982 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 31983 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 31984 | // MIs[0] Rn |
| 31985 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 31986 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 31987 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 31988 | // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_8>><<P:Predicate_atomic_load_xor_8_monotonic>> => (LDEORB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 31989 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORB, |
| 31990 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 31991 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 31992 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 31993 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 31994 | GIR_EraseFromParent, /*InsnID*/0, |
| 31995 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 31996 | // GIR_Coverage, 5493, |
| 31997 | GIR_Done, |
| 31998 | // Label 1773: @80462 |
| 31999 | GIM_Try, /*On fail goto*//*Label 1774*/ 80513, // Rule ID 5494 // |
| 32000 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32001 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 32002 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 32003 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32004 | // MIs[0] Rn |
| 32005 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32006 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32007 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32008 | // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_8>><<P:Predicate_atomic_load_xor_8_acquire>> => (LDEORAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32009 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORAB, |
| 32010 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32011 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32012 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32013 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32014 | GIR_EraseFromParent, /*InsnID*/0, |
| 32015 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32016 | // GIR_Coverage, 5494, |
| 32017 | GIR_Done, |
| 32018 | // Label 1774: @80513 |
| 32019 | GIM_Try, /*On fail goto*//*Label 1775*/ 80564, // Rule ID 5495 // |
| 32020 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32021 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 32022 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 32023 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32024 | // MIs[0] Rn |
| 32025 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32026 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32027 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32028 | // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_8>><<P:Predicate_atomic_load_xor_8_release>> => (LDEORLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32029 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORLB, |
| 32030 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32031 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32032 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32033 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32034 | GIR_EraseFromParent, /*InsnID*/0, |
| 32035 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32036 | // GIR_Coverage, 5495, |
| 32037 | GIR_Done, |
| 32038 | // Label 1775: @80564 |
| 32039 | GIM_Try, /*On fail goto*//*Label 1776*/ 80615, // Rule ID 5496 // |
| 32040 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32041 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 32042 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 32043 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32044 | // MIs[0] Rn |
| 32045 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32046 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32047 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32048 | // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_8>><<P:Predicate_atomic_load_xor_8_acq_rel>> => (LDEORALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32049 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALB, |
| 32050 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32051 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32052 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32053 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32054 | GIR_EraseFromParent, /*InsnID*/0, |
| 32055 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32056 | // GIR_Coverage, 5496, |
| 32057 | GIR_Done, |
| 32058 | // Label 1776: @80615 |
| 32059 | GIM_Try, /*On fail goto*//*Label 1777*/ 80666, // Rule ID 5497 // |
| 32060 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32061 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 32062 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 32063 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32064 | // MIs[0] Rn |
| 32065 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32066 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32067 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32068 | // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_8>><<P:Predicate_atomic_load_xor_8_seq_cst>> => (LDEORALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32069 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALB, |
| 32070 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32071 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32072 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32073 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32074 | GIR_EraseFromParent, /*InsnID*/0, |
| 32075 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32076 | // GIR_Coverage, 5497, |
| 32077 | GIR_Done, |
| 32078 | // Label 1777: @80666 |
| 32079 | GIM_Reject, |
| 32080 | // Label 1762: @80667 |
| 32081 | GIM_Reject, |
| 32082 | // Label 1760: @80668 |
| 32083 | GIM_Try, /*On fail goto*//*Label 1778*/ 80914, |
| 32084 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 32085 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, |
| 32086 | GIM_Try, /*On fail goto*//*Label 1779*/ 80725, // Rule ID 5478 // |
| 32087 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32088 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 32089 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 32090 | // MIs[0] Rn |
| 32091 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32092 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32093 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 32094 | // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_monotonic>> => (LDEORX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32095 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORX, |
| 32096 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32097 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32098 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32099 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32100 | GIR_EraseFromParent, /*InsnID*/0, |
| 32101 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32102 | // GIR_Coverage, 5478, |
| 32103 | GIR_Done, |
| 32104 | // Label 1779: @80725 |
| 32105 | GIM_Try, /*On fail goto*//*Label 1780*/ 80772, // Rule ID 5479 // |
| 32106 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32107 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 32108 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 32109 | // MIs[0] Rn |
| 32110 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32111 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32112 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 32113 | // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_acquire>> => (LDEORAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32114 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORAX, |
| 32115 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32116 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32117 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32118 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32119 | GIR_EraseFromParent, /*InsnID*/0, |
| 32120 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32121 | // GIR_Coverage, 5479, |
| 32122 | GIR_Done, |
| 32123 | // Label 1780: @80772 |
| 32124 | GIM_Try, /*On fail goto*//*Label 1781*/ 80819, // Rule ID 5480 // |
| 32125 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32126 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 32127 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 32128 | // MIs[0] Rn |
| 32129 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32130 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32131 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 32132 | // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_release>> => (LDEORLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32133 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORLX, |
| 32134 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32135 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32136 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32137 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32138 | GIR_EraseFromParent, /*InsnID*/0, |
| 32139 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32140 | // GIR_Coverage, 5480, |
| 32141 | GIR_Done, |
| 32142 | // Label 1781: @80819 |
| 32143 | GIM_Try, /*On fail goto*//*Label 1782*/ 80866, // Rule ID 5481 // |
| 32144 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32145 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 32146 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 32147 | // MIs[0] Rn |
| 32148 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32149 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32150 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 32151 | // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_acq_rel>> => (LDEORALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32152 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALX, |
| 32153 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32154 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32155 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32156 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32157 | GIR_EraseFromParent, /*InsnID*/0, |
| 32158 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32159 | // GIR_Coverage, 5481, |
| 32160 | GIR_Done, |
| 32161 | // Label 1782: @80866 |
| 32162 | GIM_Try, /*On fail goto*//*Label 1783*/ 80913, // Rule ID 5482 // |
| 32163 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32164 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 32165 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 32166 | // MIs[0] Rn |
| 32167 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32168 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32169 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 32170 | // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_seq_cst>> => (LDEORALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32171 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDEORALX, |
| 32172 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32173 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32174 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32175 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32176 | GIR_EraseFromParent, /*InsnID*/0, |
| 32177 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32178 | // GIR_Coverage, 5482, |
| 32179 | GIR_Done, |
| 32180 | // Label 1783: @80913 |
| 32181 | GIM_Reject, |
| 32182 | // Label 1778: @80914 |
| 32183 | GIM_Reject, |
| 32184 | // Label 1761: @80915 |
| 32185 | GIM_Reject, |
| 32186 | // Label 25: @80916 |
| 32187 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1786*/ 81944, |
| 32188 | /*GILLT_s32*//*Label 1784*/ 80924, |
| 32189 | /*GILLT_s64*//*Label 1785*/ 81697, |
| 32190 | // Label 1784: @80924 |
| 32191 | GIM_Try, /*On fail goto*//*Label 1787*/ 81696, |
| 32192 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 32193 | GIM_Try, /*On fail goto*//*Label 1788*/ 80981, // Rule ID 5523 // |
| 32194 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32195 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 32196 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 32197 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32198 | // MIs[0] Rn |
| 32199 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32200 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32201 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32202 | // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_monotonic>> => (LDSMAXW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32203 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXW, |
| 32204 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32205 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32206 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32207 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32208 | GIR_EraseFromParent, /*InsnID*/0, |
| 32209 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32210 | // GIR_Coverage, 5523, |
| 32211 | GIR_Done, |
| 32212 | // Label 1788: @80981 |
| 32213 | GIM_Try, /*On fail goto*//*Label 1789*/ 81032, // Rule ID 5524 // |
| 32214 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32215 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 32216 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 32217 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32218 | // MIs[0] Rn |
| 32219 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32220 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32221 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32222 | // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_acquire>> => (LDSMAXAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32223 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXAW, |
| 32224 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32225 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32226 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32227 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32228 | GIR_EraseFromParent, /*InsnID*/0, |
| 32229 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32230 | // GIR_Coverage, 5524, |
| 32231 | GIR_Done, |
| 32232 | // Label 1789: @81032 |
| 32233 | GIM_Try, /*On fail goto*//*Label 1790*/ 81083, // Rule ID 5525 // |
| 32234 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32235 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 32236 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 32237 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32238 | // MIs[0] Rn |
| 32239 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32240 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32241 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32242 | // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_release>> => (LDSMAXLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32243 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXLW, |
| 32244 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32245 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32246 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32247 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32248 | GIR_EraseFromParent, /*InsnID*/0, |
| 32249 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32250 | // GIR_Coverage, 5525, |
| 32251 | GIR_Done, |
| 32252 | // Label 1790: @81083 |
| 32253 | GIM_Try, /*On fail goto*//*Label 1791*/ 81134, // Rule ID 5526 // |
| 32254 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32255 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 32256 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 32257 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32258 | // MIs[0] Rn |
| 32259 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32260 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32261 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32262 | // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_acq_rel>> => (LDSMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32263 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALW, |
| 32264 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32265 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32266 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32267 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32268 | GIR_EraseFromParent, /*InsnID*/0, |
| 32269 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32270 | // GIR_Coverage, 5526, |
| 32271 | GIR_Done, |
| 32272 | // Label 1791: @81134 |
| 32273 | GIM_Try, /*On fail goto*//*Label 1792*/ 81185, // Rule ID 5527 // |
| 32274 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32275 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 32276 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 32277 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32278 | // MIs[0] Rn |
| 32279 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32280 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32281 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32282 | // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_seq_cst>> => (LDSMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32283 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALW, |
| 32284 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32285 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32286 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32287 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32288 | GIR_EraseFromParent, /*InsnID*/0, |
| 32289 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32290 | // GIR_Coverage, 5527, |
| 32291 | GIR_Done, |
| 32292 | // Label 1792: @81185 |
| 32293 | GIM_Try, /*On fail goto*//*Label 1793*/ 81236, // Rule ID 5528 // |
| 32294 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32295 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 32296 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 32297 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32298 | // MIs[0] Rn |
| 32299 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32300 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32301 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32302 | // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_16>><<P:Predicate_atomic_load_max_16_monotonic>> => (LDSMAXH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32303 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXH, |
| 32304 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32305 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32306 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32307 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32308 | GIR_EraseFromParent, /*InsnID*/0, |
| 32309 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32310 | // GIR_Coverage, 5528, |
| 32311 | GIR_Done, |
| 32312 | // Label 1793: @81236 |
| 32313 | GIM_Try, /*On fail goto*//*Label 1794*/ 81287, // Rule ID 5529 // |
| 32314 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32315 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 32316 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 32317 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32318 | // MIs[0] Rn |
| 32319 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32320 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32321 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32322 | // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_16>><<P:Predicate_atomic_load_max_16_acquire>> => (LDSMAXAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32323 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXAH, |
| 32324 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32325 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32326 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32327 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32328 | GIR_EraseFromParent, /*InsnID*/0, |
| 32329 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32330 | // GIR_Coverage, 5529, |
| 32331 | GIR_Done, |
| 32332 | // Label 1794: @81287 |
| 32333 | GIM_Try, /*On fail goto*//*Label 1795*/ 81338, // Rule ID 5530 // |
| 32334 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32335 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 32336 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 32337 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32338 | // MIs[0] Rn |
| 32339 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32340 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32341 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32342 | // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_16>><<P:Predicate_atomic_load_max_16_release>> => (LDSMAXLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32343 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXLH, |
| 32344 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32345 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32346 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32347 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32348 | GIR_EraseFromParent, /*InsnID*/0, |
| 32349 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32350 | // GIR_Coverage, 5530, |
| 32351 | GIR_Done, |
| 32352 | // Label 1795: @81338 |
| 32353 | GIM_Try, /*On fail goto*//*Label 1796*/ 81389, // Rule ID 5531 // |
| 32354 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32355 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 32356 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 32357 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32358 | // MIs[0] Rn |
| 32359 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32360 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32361 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32362 | // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_16>><<P:Predicate_atomic_load_max_16_acq_rel>> => (LDSMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32363 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALH, |
| 32364 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32365 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32366 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32367 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32368 | GIR_EraseFromParent, /*InsnID*/0, |
| 32369 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32370 | // GIR_Coverage, 5531, |
| 32371 | GIR_Done, |
| 32372 | // Label 1796: @81389 |
| 32373 | GIM_Try, /*On fail goto*//*Label 1797*/ 81440, // Rule ID 5532 // |
| 32374 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32375 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 32376 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 32377 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32378 | // MIs[0] Rn |
| 32379 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32380 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32381 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32382 | // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_16>><<P:Predicate_atomic_load_max_16_seq_cst>> => (LDSMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32383 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALH, |
| 32384 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32385 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32386 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32387 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32388 | GIR_EraseFromParent, /*InsnID*/0, |
| 32389 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32390 | // GIR_Coverage, 5532, |
| 32391 | GIR_Done, |
| 32392 | // Label 1797: @81440 |
| 32393 | GIM_Try, /*On fail goto*//*Label 1798*/ 81491, // Rule ID 5533 // |
| 32394 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32395 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 32396 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 32397 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32398 | // MIs[0] Rn |
| 32399 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32400 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32401 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32402 | // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_8>><<P:Predicate_atomic_load_max_8_monotonic>> => (LDSMAXB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32403 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXB, |
| 32404 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32405 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32406 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32407 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32408 | GIR_EraseFromParent, /*InsnID*/0, |
| 32409 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32410 | // GIR_Coverage, 5533, |
| 32411 | GIR_Done, |
| 32412 | // Label 1798: @81491 |
| 32413 | GIM_Try, /*On fail goto*//*Label 1799*/ 81542, // Rule ID 5534 // |
| 32414 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32415 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 32416 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 32417 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32418 | // MIs[0] Rn |
| 32419 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32420 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32421 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32422 | // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_8>><<P:Predicate_atomic_load_max_8_acquire>> => (LDSMAXAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32423 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXAB, |
| 32424 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32425 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32426 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32427 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32428 | GIR_EraseFromParent, /*InsnID*/0, |
| 32429 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32430 | // GIR_Coverage, 5534, |
| 32431 | GIR_Done, |
| 32432 | // Label 1799: @81542 |
| 32433 | GIM_Try, /*On fail goto*//*Label 1800*/ 81593, // Rule ID 5535 // |
| 32434 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32435 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 32436 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 32437 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32438 | // MIs[0] Rn |
| 32439 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32440 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32441 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32442 | // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_8>><<P:Predicate_atomic_load_max_8_release>> => (LDSMAXLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32443 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXLB, |
| 32444 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32445 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32446 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32447 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32448 | GIR_EraseFromParent, /*InsnID*/0, |
| 32449 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32450 | // GIR_Coverage, 5535, |
| 32451 | GIR_Done, |
| 32452 | // Label 1800: @81593 |
| 32453 | GIM_Try, /*On fail goto*//*Label 1801*/ 81644, // Rule ID 5536 // |
| 32454 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32455 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 32456 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 32457 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32458 | // MIs[0] Rn |
| 32459 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32460 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32461 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32462 | // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_8>><<P:Predicate_atomic_load_max_8_acq_rel>> => (LDSMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32463 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALB, |
| 32464 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32465 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32466 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32467 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32468 | GIR_EraseFromParent, /*InsnID*/0, |
| 32469 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32470 | // GIR_Coverage, 5536, |
| 32471 | GIR_Done, |
| 32472 | // Label 1801: @81644 |
| 32473 | GIM_Try, /*On fail goto*//*Label 1802*/ 81695, // Rule ID 5537 // |
| 32474 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32475 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 32476 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 32477 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32478 | // MIs[0] Rn |
| 32479 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32480 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32481 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32482 | // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_8>><<P:Predicate_atomic_load_max_8_seq_cst>> => (LDSMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32483 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALB, |
| 32484 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32485 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32486 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32487 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32488 | GIR_EraseFromParent, /*InsnID*/0, |
| 32489 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32490 | // GIR_Coverage, 5537, |
| 32491 | GIR_Done, |
| 32492 | // Label 1802: @81695 |
| 32493 | GIM_Reject, |
| 32494 | // Label 1787: @81696 |
| 32495 | GIM_Reject, |
| 32496 | // Label 1785: @81697 |
| 32497 | GIM_Try, /*On fail goto*//*Label 1803*/ 81943, |
| 32498 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 32499 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, |
| 32500 | GIM_Try, /*On fail goto*//*Label 1804*/ 81754, // Rule ID 5518 // |
| 32501 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32502 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 32503 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 32504 | // MIs[0] Rn |
| 32505 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32506 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32507 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 32508 | // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_monotonic>> => (LDSMAXX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32509 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXX, |
| 32510 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32511 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32512 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32513 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32514 | GIR_EraseFromParent, /*InsnID*/0, |
| 32515 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32516 | // GIR_Coverage, 5518, |
| 32517 | GIR_Done, |
| 32518 | // Label 1804: @81754 |
| 32519 | GIM_Try, /*On fail goto*//*Label 1805*/ 81801, // Rule ID 5519 // |
| 32520 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32521 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 32522 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 32523 | // MIs[0] Rn |
| 32524 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32525 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32526 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 32527 | // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_acquire>> => (LDSMAXAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32528 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXAX, |
| 32529 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32530 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32531 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32532 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32533 | GIR_EraseFromParent, /*InsnID*/0, |
| 32534 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32535 | // GIR_Coverage, 5519, |
| 32536 | GIR_Done, |
| 32537 | // Label 1805: @81801 |
| 32538 | GIM_Try, /*On fail goto*//*Label 1806*/ 81848, // Rule ID 5520 // |
| 32539 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32540 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 32541 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 32542 | // MIs[0] Rn |
| 32543 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32544 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32545 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 32546 | // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_release>> => (LDSMAXLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32547 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXLX, |
| 32548 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32549 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32550 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32551 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32552 | GIR_EraseFromParent, /*InsnID*/0, |
| 32553 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32554 | // GIR_Coverage, 5520, |
| 32555 | GIR_Done, |
| 32556 | // Label 1806: @81848 |
| 32557 | GIM_Try, /*On fail goto*//*Label 1807*/ 81895, // Rule ID 5521 // |
| 32558 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32559 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 32560 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 32561 | // MIs[0] Rn |
| 32562 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32563 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32564 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 32565 | // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_acq_rel>> => (LDSMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32566 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALX, |
| 32567 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32568 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32569 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32570 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32571 | GIR_EraseFromParent, /*InsnID*/0, |
| 32572 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32573 | // GIR_Coverage, 5521, |
| 32574 | GIR_Done, |
| 32575 | // Label 1807: @81895 |
| 32576 | GIM_Try, /*On fail goto*//*Label 1808*/ 81942, // Rule ID 5522 // |
| 32577 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32578 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 32579 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 32580 | // MIs[0] Rn |
| 32581 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32582 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32583 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 32584 | // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_seq_cst>> => (LDSMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32585 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMAXALX, |
| 32586 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32587 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32588 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32589 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32590 | GIR_EraseFromParent, /*InsnID*/0, |
| 32591 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32592 | // GIR_Coverage, 5522, |
| 32593 | GIR_Done, |
| 32594 | // Label 1808: @81942 |
| 32595 | GIM_Reject, |
| 32596 | // Label 1803: @81943 |
| 32597 | GIM_Reject, |
| 32598 | // Label 1786: @81944 |
| 32599 | GIM_Reject, |
| 32600 | // Label 26: @81945 |
| 32601 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1811*/ 82973, |
| 32602 | /*GILLT_s32*//*Label 1809*/ 81953, |
| 32603 | /*GILLT_s64*//*Label 1810*/ 82726, |
| 32604 | // Label 1809: @81953 |
| 32605 | GIM_Try, /*On fail goto*//*Label 1812*/ 82725, |
| 32606 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 32607 | GIM_Try, /*On fail goto*//*Label 1813*/ 82010, // Rule ID 5543 // |
| 32608 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32609 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 32610 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 32611 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32612 | // MIs[0] Rn |
| 32613 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32614 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32615 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32616 | // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_monotonic>> => (LDSMINW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32617 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINW, |
| 32618 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32619 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32620 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32621 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32622 | GIR_EraseFromParent, /*InsnID*/0, |
| 32623 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32624 | // GIR_Coverage, 5543, |
| 32625 | GIR_Done, |
| 32626 | // Label 1813: @82010 |
| 32627 | GIM_Try, /*On fail goto*//*Label 1814*/ 82061, // Rule ID 5544 // |
| 32628 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32629 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 32630 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 32631 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32632 | // MIs[0] Rn |
| 32633 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32634 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32635 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32636 | // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_acquire>> => (LDSMINAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32637 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINAW, |
| 32638 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32639 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32640 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32641 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32642 | GIR_EraseFromParent, /*InsnID*/0, |
| 32643 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32644 | // GIR_Coverage, 5544, |
| 32645 | GIR_Done, |
| 32646 | // Label 1814: @82061 |
| 32647 | GIM_Try, /*On fail goto*//*Label 1815*/ 82112, // Rule ID 5545 // |
| 32648 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32649 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 32650 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 32651 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32652 | // MIs[0] Rn |
| 32653 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32654 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32655 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32656 | // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_release>> => (LDSMINLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32657 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINLW, |
| 32658 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32659 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32660 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32661 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32662 | GIR_EraseFromParent, /*InsnID*/0, |
| 32663 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32664 | // GIR_Coverage, 5545, |
| 32665 | GIR_Done, |
| 32666 | // Label 1815: @82112 |
| 32667 | GIM_Try, /*On fail goto*//*Label 1816*/ 82163, // Rule ID 5546 // |
| 32668 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32669 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 32670 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 32671 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32672 | // MIs[0] Rn |
| 32673 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32674 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32675 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32676 | // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_acq_rel>> => (LDSMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32677 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALW, |
| 32678 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32679 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32680 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32681 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32682 | GIR_EraseFromParent, /*InsnID*/0, |
| 32683 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32684 | // GIR_Coverage, 5546, |
| 32685 | GIR_Done, |
| 32686 | // Label 1816: @82163 |
| 32687 | GIM_Try, /*On fail goto*//*Label 1817*/ 82214, // Rule ID 5547 // |
| 32688 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32689 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 32690 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 32691 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32692 | // MIs[0] Rn |
| 32693 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32694 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32695 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32696 | // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_seq_cst>> => (LDSMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32697 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALW, |
| 32698 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32699 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32700 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32701 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32702 | GIR_EraseFromParent, /*InsnID*/0, |
| 32703 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32704 | // GIR_Coverage, 5547, |
| 32705 | GIR_Done, |
| 32706 | // Label 1817: @82214 |
| 32707 | GIM_Try, /*On fail goto*//*Label 1818*/ 82265, // Rule ID 5548 // |
| 32708 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32709 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 32710 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 32711 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32712 | // MIs[0] Rn |
| 32713 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32714 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32715 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32716 | // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_16>><<P:Predicate_atomic_load_min_16_monotonic>> => (LDSMINH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32717 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINH, |
| 32718 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32719 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32720 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32721 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32722 | GIR_EraseFromParent, /*InsnID*/0, |
| 32723 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32724 | // GIR_Coverage, 5548, |
| 32725 | GIR_Done, |
| 32726 | // Label 1818: @82265 |
| 32727 | GIM_Try, /*On fail goto*//*Label 1819*/ 82316, // Rule ID 5549 // |
| 32728 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32729 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 32730 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 32731 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32732 | // MIs[0] Rn |
| 32733 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32734 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32735 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32736 | // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_16>><<P:Predicate_atomic_load_min_16_acquire>> => (LDSMINAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32737 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINAH, |
| 32738 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32739 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32740 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32741 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32742 | GIR_EraseFromParent, /*InsnID*/0, |
| 32743 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32744 | // GIR_Coverage, 5549, |
| 32745 | GIR_Done, |
| 32746 | // Label 1819: @82316 |
| 32747 | GIM_Try, /*On fail goto*//*Label 1820*/ 82367, // Rule ID 5550 // |
| 32748 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32749 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 32750 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 32751 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32752 | // MIs[0] Rn |
| 32753 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32754 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32755 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32756 | // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_16>><<P:Predicate_atomic_load_min_16_release>> => (LDSMINLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32757 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINLH, |
| 32758 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32759 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32760 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32761 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32762 | GIR_EraseFromParent, /*InsnID*/0, |
| 32763 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32764 | // GIR_Coverage, 5550, |
| 32765 | GIR_Done, |
| 32766 | // Label 1820: @82367 |
| 32767 | GIM_Try, /*On fail goto*//*Label 1821*/ 82418, // Rule ID 5551 // |
| 32768 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32769 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 32770 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 32771 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32772 | // MIs[0] Rn |
| 32773 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32774 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32775 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32776 | // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_16>><<P:Predicate_atomic_load_min_16_acq_rel>> => (LDSMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32777 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALH, |
| 32778 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32779 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32780 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32781 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32782 | GIR_EraseFromParent, /*InsnID*/0, |
| 32783 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32784 | // GIR_Coverage, 5551, |
| 32785 | GIR_Done, |
| 32786 | // Label 1821: @82418 |
| 32787 | GIM_Try, /*On fail goto*//*Label 1822*/ 82469, // Rule ID 5552 // |
| 32788 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32789 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 32790 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 32791 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32792 | // MIs[0] Rn |
| 32793 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32794 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32795 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32796 | // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_16>><<P:Predicate_atomic_load_min_16_seq_cst>> => (LDSMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32797 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALH, |
| 32798 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32799 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32800 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32801 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32802 | GIR_EraseFromParent, /*InsnID*/0, |
| 32803 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32804 | // GIR_Coverage, 5552, |
| 32805 | GIR_Done, |
| 32806 | // Label 1822: @82469 |
| 32807 | GIM_Try, /*On fail goto*//*Label 1823*/ 82520, // Rule ID 5553 // |
| 32808 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32809 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 32810 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 32811 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32812 | // MIs[0] Rn |
| 32813 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32814 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32815 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32816 | // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_8>><<P:Predicate_atomic_load_min_8_monotonic>> => (LDSMINB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32817 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINB, |
| 32818 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32819 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32820 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32821 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32822 | GIR_EraseFromParent, /*InsnID*/0, |
| 32823 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32824 | // GIR_Coverage, 5553, |
| 32825 | GIR_Done, |
| 32826 | // Label 1823: @82520 |
| 32827 | GIM_Try, /*On fail goto*//*Label 1824*/ 82571, // Rule ID 5554 // |
| 32828 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32829 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 32830 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 32831 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32832 | // MIs[0] Rn |
| 32833 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32834 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32835 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32836 | // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_8>><<P:Predicate_atomic_load_min_8_acquire>> => (LDSMINAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32837 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINAB, |
| 32838 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32839 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32840 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32841 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32842 | GIR_EraseFromParent, /*InsnID*/0, |
| 32843 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32844 | // GIR_Coverage, 5554, |
| 32845 | GIR_Done, |
| 32846 | // Label 1824: @82571 |
| 32847 | GIM_Try, /*On fail goto*//*Label 1825*/ 82622, // Rule ID 5555 // |
| 32848 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32849 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 32850 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 32851 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32852 | // MIs[0] Rn |
| 32853 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32854 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32855 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32856 | // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_8>><<P:Predicate_atomic_load_min_8_release>> => (LDSMINLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32857 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINLB, |
| 32858 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32859 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32860 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32861 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32862 | GIR_EraseFromParent, /*InsnID*/0, |
| 32863 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32864 | // GIR_Coverage, 5555, |
| 32865 | GIR_Done, |
| 32866 | // Label 1825: @82622 |
| 32867 | GIM_Try, /*On fail goto*//*Label 1826*/ 82673, // Rule ID 5556 // |
| 32868 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32869 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 32870 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 32871 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32872 | // MIs[0] Rn |
| 32873 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32874 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32875 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32876 | // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_8>><<P:Predicate_atomic_load_min_8_acq_rel>> => (LDSMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32877 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALB, |
| 32878 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32879 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32880 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32881 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32882 | GIR_EraseFromParent, /*InsnID*/0, |
| 32883 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32884 | // GIR_Coverage, 5556, |
| 32885 | GIR_Done, |
| 32886 | // Label 1826: @82673 |
| 32887 | GIM_Try, /*On fail goto*//*Label 1827*/ 82724, // Rule ID 5557 // |
| 32888 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32889 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 32890 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 32891 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 32892 | // MIs[0] Rn |
| 32893 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32894 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32895 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 32896 | // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_8>><<P:Predicate_atomic_load_min_8_seq_cst>> => (LDSMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32897 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALB, |
| 32898 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32899 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32900 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32901 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32902 | GIR_EraseFromParent, /*InsnID*/0, |
| 32903 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32904 | // GIR_Coverage, 5557, |
| 32905 | GIR_Done, |
| 32906 | // Label 1827: @82724 |
| 32907 | GIM_Reject, |
| 32908 | // Label 1812: @82725 |
| 32909 | GIM_Reject, |
| 32910 | // Label 1810: @82726 |
| 32911 | GIM_Try, /*On fail goto*//*Label 1828*/ 82972, |
| 32912 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 32913 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, |
| 32914 | GIM_Try, /*On fail goto*//*Label 1829*/ 82783, // Rule ID 5538 // |
| 32915 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32916 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 32917 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 32918 | // MIs[0] Rn |
| 32919 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32920 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32921 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 32922 | // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_monotonic>> => (LDSMINX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32923 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINX, |
| 32924 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32925 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32926 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32927 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32928 | GIR_EraseFromParent, /*InsnID*/0, |
| 32929 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32930 | // GIR_Coverage, 5538, |
| 32931 | GIR_Done, |
| 32932 | // Label 1829: @82783 |
| 32933 | GIM_Try, /*On fail goto*//*Label 1830*/ 82830, // Rule ID 5539 // |
| 32934 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32935 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 32936 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 32937 | // MIs[0] Rn |
| 32938 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32939 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32940 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 32941 | // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_acquire>> => (LDSMINAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32942 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINAX, |
| 32943 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32944 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32945 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32946 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32947 | GIR_EraseFromParent, /*InsnID*/0, |
| 32948 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32949 | // GIR_Coverage, 5539, |
| 32950 | GIR_Done, |
| 32951 | // Label 1830: @82830 |
| 32952 | GIM_Try, /*On fail goto*//*Label 1831*/ 82877, // Rule ID 5540 // |
| 32953 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32954 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 32955 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 32956 | // MIs[0] Rn |
| 32957 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32958 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32959 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 32960 | // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_release>> => (LDSMINLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32961 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINLX, |
| 32962 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32963 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32964 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32965 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32966 | GIR_EraseFromParent, /*InsnID*/0, |
| 32967 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32968 | // GIR_Coverage, 5540, |
| 32969 | GIR_Done, |
| 32970 | // Label 1831: @82877 |
| 32971 | GIM_Try, /*On fail goto*//*Label 1832*/ 82924, // Rule ID 5541 // |
| 32972 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32973 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 32974 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 32975 | // MIs[0] Rn |
| 32976 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32977 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32978 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 32979 | // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_acq_rel>> => (LDSMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32980 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALX, |
| 32981 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 32982 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 32983 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 32984 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 32985 | GIR_EraseFromParent, /*InsnID*/0, |
| 32986 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 32987 | // GIR_Coverage, 5541, |
| 32988 | GIR_Done, |
| 32989 | // Label 1832: @82924 |
| 32990 | GIM_Try, /*On fail goto*//*Label 1833*/ 82971, // Rule ID 5542 // |
| 32991 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 32992 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 32993 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 32994 | // MIs[0] Rn |
| 32995 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32996 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 32997 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 32998 | // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_seq_cst>> => (LDSMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 32999 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDSMINALX, |
| 33000 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33001 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33002 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33003 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33004 | GIR_EraseFromParent, /*InsnID*/0, |
| 33005 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33006 | // GIR_Coverage, 5542, |
| 33007 | GIR_Done, |
| 33008 | // Label 1833: @82971 |
| 33009 | GIM_Reject, |
| 33010 | // Label 1828: @82972 |
| 33011 | GIM_Reject, |
| 33012 | // Label 1811: @82973 |
| 33013 | GIM_Reject, |
| 33014 | // Label 27: @82974 |
| 33015 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1836*/ 84002, |
| 33016 | /*GILLT_s32*//*Label 1834*/ 82982, |
| 33017 | /*GILLT_s64*//*Label 1835*/ 83755, |
| 33018 | // Label 1834: @82982 |
| 33019 | GIM_Try, /*On fail goto*//*Label 1837*/ 83754, |
| 33020 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 33021 | GIM_Try, /*On fail goto*//*Label 1838*/ 83039, // Rule ID 5563 // |
| 33022 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33023 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 33024 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 33025 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33026 | // MIs[0] Rn |
| 33027 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33028 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33029 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33030 | // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_monotonic>> => (LDUMAXW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33031 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXW, |
| 33032 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33033 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33034 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33035 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33036 | GIR_EraseFromParent, /*InsnID*/0, |
| 33037 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33038 | // GIR_Coverage, 5563, |
| 33039 | GIR_Done, |
| 33040 | // Label 1838: @83039 |
| 33041 | GIM_Try, /*On fail goto*//*Label 1839*/ 83090, // Rule ID 5564 // |
| 33042 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33043 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 33044 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 33045 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33046 | // MIs[0] Rn |
| 33047 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33048 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33049 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33050 | // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_acquire>> => (LDUMAXAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33051 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXAW, |
| 33052 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33053 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33054 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33055 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33056 | GIR_EraseFromParent, /*InsnID*/0, |
| 33057 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33058 | // GIR_Coverage, 5564, |
| 33059 | GIR_Done, |
| 33060 | // Label 1839: @83090 |
| 33061 | GIM_Try, /*On fail goto*//*Label 1840*/ 83141, // Rule ID 5565 // |
| 33062 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33063 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 33064 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 33065 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33066 | // MIs[0] Rn |
| 33067 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33068 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33069 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33070 | // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_release>> => (LDUMAXLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33071 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXLW, |
| 33072 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33073 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33074 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33075 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33076 | GIR_EraseFromParent, /*InsnID*/0, |
| 33077 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33078 | // GIR_Coverage, 5565, |
| 33079 | GIR_Done, |
| 33080 | // Label 1840: @83141 |
| 33081 | GIM_Try, /*On fail goto*//*Label 1841*/ 83192, // Rule ID 5566 // |
| 33082 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33083 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 33084 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 33085 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33086 | // MIs[0] Rn |
| 33087 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33088 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33089 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33090 | // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_acq_rel>> => (LDUMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33091 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALW, |
| 33092 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33093 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33094 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33095 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33096 | GIR_EraseFromParent, /*InsnID*/0, |
| 33097 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33098 | // GIR_Coverage, 5566, |
| 33099 | GIR_Done, |
| 33100 | // Label 1841: @83192 |
| 33101 | GIM_Try, /*On fail goto*//*Label 1842*/ 83243, // Rule ID 5567 // |
| 33102 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33103 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 33104 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 33105 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33106 | // MIs[0] Rn |
| 33107 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33108 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33109 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33110 | // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_seq_cst>> => (LDUMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33111 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALW, |
| 33112 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33113 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33114 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33115 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33116 | GIR_EraseFromParent, /*InsnID*/0, |
| 33117 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33118 | // GIR_Coverage, 5567, |
| 33119 | GIR_Done, |
| 33120 | // Label 1842: @83243 |
| 33121 | GIM_Try, /*On fail goto*//*Label 1843*/ 83294, // Rule ID 5568 // |
| 33122 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33123 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 33124 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 33125 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33126 | // MIs[0] Rn |
| 33127 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33128 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33129 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33130 | // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_16>><<P:Predicate_atomic_load_umax_16_monotonic>> => (LDUMAXH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33131 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXH, |
| 33132 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33133 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33134 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33135 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33136 | GIR_EraseFromParent, /*InsnID*/0, |
| 33137 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33138 | // GIR_Coverage, 5568, |
| 33139 | GIR_Done, |
| 33140 | // Label 1843: @83294 |
| 33141 | GIM_Try, /*On fail goto*//*Label 1844*/ 83345, // Rule ID 5569 // |
| 33142 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33143 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 33144 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 33145 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33146 | // MIs[0] Rn |
| 33147 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33148 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33149 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33150 | // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_16>><<P:Predicate_atomic_load_umax_16_acquire>> => (LDUMAXAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33151 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXAH, |
| 33152 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33153 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33154 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33155 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33156 | GIR_EraseFromParent, /*InsnID*/0, |
| 33157 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33158 | // GIR_Coverage, 5569, |
| 33159 | GIR_Done, |
| 33160 | // Label 1844: @83345 |
| 33161 | GIM_Try, /*On fail goto*//*Label 1845*/ 83396, // Rule ID 5570 // |
| 33162 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33163 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 33164 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 33165 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33166 | // MIs[0] Rn |
| 33167 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33168 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33169 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33170 | // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_16>><<P:Predicate_atomic_load_umax_16_release>> => (LDUMAXLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33171 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXLH, |
| 33172 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33173 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33174 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33175 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33176 | GIR_EraseFromParent, /*InsnID*/0, |
| 33177 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33178 | // GIR_Coverage, 5570, |
| 33179 | GIR_Done, |
| 33180 | // Label 1845: @83396 |
| 33181 | GIM_Try, /*On fail goto*//*Label 1846*/ 83447, // Rule ID 5571 // |
| 33182 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33183 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 33184 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 33185 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33186 | // MIs[0] Rn |
| 33187 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33188 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33189 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33190 | // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_16>><<P:Predicate_atomic_load_umax_16_acq_rel>> => (LDUMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33191 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALH, |
| 33192 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33193 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33194 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33195 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33196 | GIR_EraseFromParent, /*InsnID*/0, |
| 33197 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33198 | // GIR_Coverage, 5571, |
| 33199 | GIR_Done, |
| 33200 | // Label 1846: @83447 |
| 33201 | GIM_Try, /*On fail goto*//*Label 1847*/ 83498, // Rule ID 5572 // |
| 33202 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33203 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 33204 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 33205 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33206 | // MIs[0] Rn |
| 33207 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33208 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33209 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33210 | // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_16>><<P:Predicate_atomic_load_umax_16_seq_cst>> => (LDUMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33211 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALH, |
| 33212 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33213 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33214 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33215 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33216 | GIR_EraseFromParent, /*InsnID*/0, |
| 33217 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33218 | // GIR_Coverage, 5572, |
| 33219 | GIR_Done, |
| 33220 | // Label 1847: @83498 |
| 33221 | GIM_Try, /*On fail goto*//*Label 1848*/ 83549, // Rule ID 5573 // |
| 33222 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33223 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 33224 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 33225 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33226 | // MIs[0] Rn |
| 33227 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33228 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33229 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33230 | // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_8>><<P:Predicate_atomic_load_umax_8_monotonic>> => (LDUMAXB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33231 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXB, |
| 33232 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33233 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33234 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33235 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33236 | GIR_EraseFromParent, /*InsnID*/0, |
| 33237 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33238 | // GIR_Coverage, 5573, |
| 33239 | GIR_Done, |
| 33240 | // Label 1848: @83549 |
| 33241 | GIM_Try, /*On fail goto*//*Label 1849*/ 83600, // Rule ID 5574 // |
| 33242 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33243 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 33244 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 33245 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33246 | // MIs[0] Rn |
| 33247 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33248 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33249 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33250 | // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_8>><<P:Predicate_atomic_load_umax_8_acquire>> => (LDUMAXAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33251 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXAB, |
| 33252 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33253 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33254 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33255 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33256 | GIR_EraseFromParent, /*InsnID*/0, |
| 33257 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33258 | // GIR_Coverage, 5574, |
| 33259 | GIR_Done, |
| 33260 | // Label 1849: @83600 |
| 33261 | GIM_Try, /*On fail goto*//*Label 1850*/ 83651, // Rule ID 5575 // |
| 33262 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33263 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 33264 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 33265 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33266 | // MIs[0] Rn |
| 33267 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33268 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33269 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33270 | // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_8>><<P:Predicate_atomic_load_umax_8_release>> => (LDUMAXLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33271 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXLB, |
| 33272 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33273 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33274 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33275 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33276 | GIR_EraseFromParent, /*InsnID*/0, |
| 33277 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33278 | // GIR_Coverage, 5575, |
| 33279 | GIR_Done, |
| 33280 | // Label 1850: @83651 |
| 33281 | GIM_Try, /*On fail goto*//*Label 1851*/ 83702, // Rule ID 5576 // |
| 33282 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33283 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 33284 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 33285 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33286 | // MIs[0] Rn |
| 33287 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33288 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33289 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33290 | // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_8>><<P:Predicate_atomic_load_umax_8_acq_rel>> => (LDUMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33291 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALB, |
| 33292 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33293 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33294 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33295 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33296 | GIR_EraseFromParent, /*InsnID*/0, |
| 33297 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33298 | // GIR_Coverage, 5576, |
| 33299 | GIR_Done, |
| 33300 | // Label 1851: @83702 |
| 33301 | GIM_Try, /*On fail goto*//*Label 1852*/ 83753, // Rule ID 5577 // |
| 33302 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33303 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 33304 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 33305 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33306 | // MIs[0] Rn |
| 33307 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33308 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33309 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33310 | // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_8>><<P:Predicate_atomic_load_umax_8_seq_cst>> => (LDUMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33311 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALB, |
| 33312 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33313 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33314 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33315 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33316 | GIR_EraseFromParent, /*InsnID*/0, |
| 33317 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33318 | // GIR_Coverage, 5577, |
| 33319 | GIR_Done, |
| 33320 | // Label 1852: @83753 |
| 33321 | GIM_Reject, |
| 33322 | // Label 1837: @83754 |
| 33323 | GIM_Reject, |
| 33324 | // Label 1835: @83755 |
| 33325 | GIM_Try, /*On fail goto*//*Label 1853*/ 84001, |
| 33326 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 33327 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, |
| 33328 | GIM_Try, /*On fail goto*//*Label 1854*/ 83812, // Rule ID 5558 // |
| 33329 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33330 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 33331 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 33332 | // MIs[0] Rn |
| 33333 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33334 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33335 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 33336 | // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_monotonic>> => (LDUMAXX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33337 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXX, |
| 33338 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33339 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33340 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33341 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33342 | GIR_EraseFromParent, /*InsnID*/0, |
| 33343 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33344 | // GIR_Coverage, 5558, |
| 33345 | GIR_Done, |
| 33346 | // Label 1854: @83812 |
| 33347 | GIM_Try, /*On fail goto*//*Label 1855*/ 83859, // Rule ID 5559 // |
| 33348 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33349 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 33350 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 33351 | // MIs[0] Rn |
| 33352 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33353 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33354 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 33355 | // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_acquire>> => (LDUMAXAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33356 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXAX, |
| 33357 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33358 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33359 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33360 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33361 | GIR_EraseFromParent, /*InsnID*/0, |
| 33362 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33363 | // GIR_Coverage, 5559, |
| 33364 | GIR_Done, |
| 33365 | // Label 1855: @83859 |
| 33366 | GIM_Try, /*On fail goto*//*Label 1856*/ 83906, // Rule ID 5560 // |
| 33367 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33368 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 33369 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 33370 | // MIs[0] Rn |
| 33371 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33372 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33373 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 33374 | // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_release>> => (LDUMAXLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33375 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXLX, |
| 33376 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33377 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33378 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33379 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33380 | GIR_EraseFromParent, /*InsnID*/0, |
| 33381 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33382 | // GIR_Coverage, 5560, |
| 33383 | GIR_Done, |
| 33384 | // Label 1856: @83906 |
| 33385 | GIM_Try, /*On fail goto*//*Label 1857*/ 83953, // Rule ID 5561 // |
| 33386 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33387 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 33388 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 33389 | // MIs[0] Rn |
| 33390 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33391 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33392 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 33393 | // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_acq_rel>> => (LDUMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33394 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALX, |
| 33395 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33396 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33397 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33398 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33399 | GIR_EraseFromParent, /*InsnID*/0, |
| 33400 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33401 | // GIR_Coverage, 5561, |
| 33402 | GIR_Done, |
| 33403 | // Label 1857: @83953 |
| 33404 | GIM_Try, /*On fail goto*//*Label 1858*/ 84000, // Rule ID 5562 // |
| 33405 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33406 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 33407 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 33408 | // MIs[0] Rn |
| 33409 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33410 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33411 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 33412 | // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_seq_cst>> => (LDUMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33413 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMAXALX, |
| 33414 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33415 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33416 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33417 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33418 | GIR_EraseFromParent, /*InsnID*/0, |
| 33419 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33420 | // GIR_Coverage, 5562, |
| 33421 | GIR_Done, |
| 33422 | // Label 1858: @84000 |
| 33423 | GIM_Reject, |
| 33424 | // Label 1853: @84001 |
| 33425 | GIM_Reject, |
| 33426 | // Label 1836: @84002 |
| 33427 | GIM_Reject, |
| 33428 | // Label 28: @84003 |
| 33429 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1861*/ 85031, |
| 33430 | /*GILLT_s32*//*Label 1859*/ 84011, |
| 33431 | /*GILLT_s64*//*Label 1860*/ 84784, |
| 33432 | // Label 1859: @84011 |
| 33433 | GIM_Try, /*On fail goto*//*Label 1862*/ 84783, |
| 33434 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 33435 | GIM_Try, /*On fail goto*//*Label 1863*/ 84068, // Rule ID 5583 // |
| 33436 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33437 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 33438 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 33439 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33440 | // MIs[0] Rn |
| 33441 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33442 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33443 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33444 | // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_monotonic>> => (LDUMINW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33445 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINW, |
| 33446 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33447 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33448 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33449 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33450 | GIR_EraseFromParent, /*InsnID*/0, |
| 33451 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33452 | // GIR_Coverage, 5583, |
| 33453 | GIR_Done, |
| 33454 | // Label 1863: @84068 |
| 33455 | GIM_Try, /*On fail goto*//*Label 1864*/ 84119, // Rule ID 5584 // |
| 33456 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33457 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 33458 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 33459 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33460 | // MIs[0] Rn |
| 33461 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33462 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33463 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33464 | // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_acquire>> => (LDUMINAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33465 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINAW, |
| 33466 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33467 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33468 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33469 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33470 | GIR_EraseFromParent, /*InsnID*/0, |
| 33471 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33472 | // GIR_Coverage, 5584, |
| 33473 | GIR_Done, |
| 33474 | // Label 1864: @84119 |
| 33475 | GIM_Try, /*On fail goto*//*Label 1865*/ 84170, // Rule ID 5585 // |
| 33476 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33477 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 33478 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 33479 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33480 | // MIs[0] Rn |
| 33481 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33482 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33483 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33484 | // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_release>> => (LDUMINLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33485 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINLW, |
| 33486 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33487 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33488 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33489 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33490 | GIR_EraseFromParent, /*InsnID*/0, |
| 33491 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33492 | // GIR_Coverage, 5585, |
| 33493 | GIR_Done, |
| 33494 | // Label 1865: @84170 |
| 33495 | GIM_Try, /*On fail goto*//*Label 1866*/ 84221, // Rule ID 5586 // |
| 33496 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33497 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 33498 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 33499 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33500 | // MIs[0] Rn |
| 33501 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33502 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33503 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33504 | // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_acq_rel>> => (LDUMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33505 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALW, |
| 33506 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33507 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33508 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33509 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33510 | GIR_EraseFromParent, /*InsnID*/0, |
| 33511 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33512 | // GIR_Coverage, 5586, |
| 33513 | GIR_Done, |
| 33514 | // Label 1866: @84221 |
| 33515 | GIM_Try, /*On fail goto*//*Label 1867*/ 84272, // Rule ID 5587 // |
| 33516 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33517 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, |
| 33518 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 33519 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33520 | // MIs[0] Rn |
| 33521 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33522 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33523 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33524 | // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_seq_cst>> => (LDUMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33525 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALW, |
| 33526 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33527 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33528 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33529 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33530 | GIR_EraseFromParent, /*InsnID*/0, |
| 33531 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33532 | // GIR_Coverage, 5587, |
| 33533 | GIR_Done, |
| 33534 | // Label 1867: @84272 |
| 33535 | GIM_Try, /*On fail goto*//*Label 1868*/ 84323, // Rule ID 5588 // |
| 33536 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33537 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 33538 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 33539 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33540 | // MIs[0] Rn |
| 33541 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33542 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33543 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33544 | // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_16>><<P:Predicate_atomic_load_umin_16_monotonic>> => (LDUMINH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33545 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINH, |
| 33546 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33547 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33548 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33549 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33550 | GIR_EraseFromParent, /*InsnID*/0, |
| 33551 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33552 | // GIR_Coverage, 5588, |
| 33553 | GIR_Done, |
| 33554 | // Label 1868: @84323 |
| 33555 | GIM_Try, /*On fail goto*//*Label 1869*/ 84374, // Rule ID 5589 // |
| 33556 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33557 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 33558 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 33559 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33560 | // MIs[0] Rn |
| 33561 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33562 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33563 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33564 | // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_16>><<P:Predicate_atomic_load_umin_16_acquire>> => (LDUMINAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33565 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINAH, |
| 33566 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33567 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33568 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33569 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33570 | GIR_EraseFromParent, /*InsnID*/0, |
| 33571 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33572 | // GIR_Coverage, 5589, |
| 33573 | GIR_Done, |
| 33574 | // Label 1869: @84374 |
| 33575 | GIM_Try, /*On fail goto*//*Label 1870*/ 84425, // Rule ID 5590 // |
| 33576 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33577 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 33578 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 33579 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33580 | // MIs[0] Rn |
| 33581 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33582 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33583 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33584 | // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_16>><<P:Predicate_atomic_load_umin_16_release>> => (LDUMINLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33585 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINLH, |
| 33586 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33587 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33588 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33589 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33590 | GIR_EraseFromParent, /*InsnID*/0, |
| 33591 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33592 | // GIR_Coverage, 5590, |
| 33593 | GIR_Done, |
| 33594 | // Label 1870: @84425 |
| 33595 | GIM_Try, /*On fail goto*//*Label 1871*/ 84476, // Rule ID 5591 // |
| 33596 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33597 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 33598 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 33599 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33600 | // MIs[0] Rn |
| 33601 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33602 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33603 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33604 | // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_16>><<P:Predicate_atomic_load_umin_16_acq_rel>> => (LDUMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33605 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALH, |
| 33606 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33607 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33608 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33609 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33610 | GIR_EraseFromParent, /*InsnID*/0, |
| 33611 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33612 | // GIR_Coverage, 5591, |
| 33613 | GIR_Done, |
| 33614 | // Label 1871: @84476 |
| 33615 | GIM_Try, /*On fail goto*//*Label 1872*/ 84527, // Rule ID 5592 // |
| 33616 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33617 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 33618 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 33619 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33620 | // MIs[0] Rn |
| 33621 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33622 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33623 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33624 | // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_16>><<P:Predicate_atomic_load_umin_16_seq_cst>> => (LDUMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33625 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALH, |
| 33626 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33627 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33628 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33629 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33630 | GIR_EraseFromParent, /*InsnID*/0, |
| 33631 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33632 | // GIR_Coverage, 5592, |
| 33633 | GIR_Done, |
| 33634 | // Label 1872: @84527 |
| 33635 | GIM_Try, /*On fail goto*//*Label 1873*/ 84578, // Rule ID 5593 // |
| 33636 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33637 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 33638 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 33639 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33640 | // MIs[0] Rn |
| 33641 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33642 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33643 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33644 | // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_8>><<P:Predicate_atomic_load_umin_8_monotonic>> => (LDUMINB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33645 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINB, |
| 33646 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33647 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33648 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33649 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33650 | GIR_EraseFromParent, /*InsnID*/0, |
| 33651 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33652 | // GIR_Coverage, 5593, |
| 33653 | GIR_Done, |
| 33654 | // Label 1873: @84578 |
| 33655 | GIM_Try, /*On fail goto*//*Label 1874*/ 84629, // Rule ID 5594 // |
| 33656 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33657 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 33658 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 33659 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33660 | // MIs[0] Rn |
| 33661 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33662 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33663 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33664 | // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_8>><<P:Predicate_atomic_load_umin_8_acquire>> => (LDUMINAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33665 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINAB, |
| 33666 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33667 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33668 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33669 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33670 | GIR_EraseFromParent, /*InsnID*/0, |
| 33671 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33672 | // GIR_Coverage, 5594, |
| 33673 | GIR_Done, |
| 33674 | // Label 1874: @84629 |
| 33675 | GIM_Try, /*On fail goto*//*Label 1875*/ 84680, // Rule ID 5595 // |
| 33676 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33677 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 33678 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 33679 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33680 | // MIs[0] Rn |
| 33681 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33682 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33683 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33684 | // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_8>><<P:Predicate_atomic_load_umin_8_release>> => (LDUMINLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33685 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINLB, |
| 33686 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33687 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33688 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33689 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33690 | GIR_EraseFromParent, /*InsnID*/0, |
| 33691 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33692 | // GIR_Coverage, 5595, |
| 33693 | GIR_Done, |
| 33694 | // Label 1875: @84680 |
| 33695 | GIM_Try, /*On fail goto*//*Label 1876*/ 84731, // Rule ID 5596 // |
| 33696 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33697 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 33698 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 33699 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33700 | // MIs[0] Rn |
| 33701 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33702 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33703 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33704 | // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_8>><<P:Predicate_atomic_load_umin_8_acq_rel>> => (LDUMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33705 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALB, |
| 33706 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33707 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33708 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33709 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33710 | GIR_EraseFromParent, /*InsnID*/0, |
| 33711 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33712 | // GIR_Coverage, 5596, |
| 33713 | GIR_Done, |
| 33714 | // Label 1876: @84731 |
| 33715 | GIM_Try, /*On fail goto*//*Label 1877*/ 84782, // Rule ID 5597 // |
| 33716 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33717 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 33718 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 33719 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 33720 | // MIs[0] Rn |
| 33721 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33722 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33723 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 33724 | // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_8>><<P:Predicate_atomic_load_umin_8_seq_cst>> => (LDUMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33725 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALB, |
| 33726 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33727 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33728 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33729 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33730 | GIR_EraseFromParent, /*InsnID*/0, |
| 33731 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33732 | // GIR_Coverage, 5597, |
| 33733 | GIR_Done, |
| 33734 | // Label 1877: @84782 |
| 33735 | GIM_Reject, |
| 33736 | // Label 1862: @84783 |
| 33737 | GIM_Reject, |
| 33738 | // Label 1860: @84784 |
| 33739 | GIM_Try, /*On fail goto*//*Label 1878*/ 85030, |
| 33740 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 33741 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, |
| 33742 | GIM_Try, /*On fail goto*//*Label 1879*/ 84841, // Rule ID 5578 // |
| 33743 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33744 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, |
| 33745 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 33746 | // MIs[0] Rn |
| 33747 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33748 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33749 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 33750 | // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_monotonic>> => (LDUMINX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33751 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINX, |
| 33752 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33753 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33754 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33755 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33756 | GIR_EraseFromParent, /*InsnID*/0, |
| 33757 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33758 | // GIR_Coverage, 5578, |
| 33759 | GIR_Done, |
| 33760 | // Label 1879: @84841 |
| 33761 | GIM_Try, /*On fail goto*//*Label 1880*/ 84888, // Rule ID 5579 // |
| 33762 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33763 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, |
| 33764 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 33765 | // MIs[0] Rn |
| 33766 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33767 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33768 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 33769 | // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_acquire>> => (LDUMINAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33770 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINAX, |
| 33771 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33772 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33773 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33774 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33775 | GIR_EraseFromParent, /*InsnID*/0, |
| 33776 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33777 | // GIR_Coverage, 5579, |
| 33778 | GIR_Done, |
| 33779 | // Label 1880: @84888 |
| 33780 | GIM_Try, /*On fail goto*//*Label 1881*/ 84935, // Rule ID 5580 // |
| 33781 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33782 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, |
| 33783 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 33784 | // MIs[0] Rn |
| 33785 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33786 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33787 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 33788 | // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_release>> => (LDUMINLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33789 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINLX, |
| 33790 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33791 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33792 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33793 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33794 | GIR_EraseFromParent, /*InsnID*/0, |
| 33795 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33796 | // GIR_Coverage, 5580, |
| 33797 | GIR_Done, |
| 33798 | // Label 1881: @84935 |
| 33799 | GIM_Try, /*On fail goto*//*Label 1882*/ 84982, // Rule ID 5581 // |
| 33800 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33801 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, |
| 33802 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 33803 | // MIs[0] Rn |
| 33804 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33805 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33806 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 33807 | // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_acq_rel>> => (LDUMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33808 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALX, |
| 33809 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33810 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33811 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33812 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33813 | GIR_EraseFromParent, /*InsnID*/0, |
| 33814 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33815 | // GIR_Coverage, 5581, |
| 33816 | GIR_Done, |
| 33817 | // Label 1882: @84982 |
| 33818 | GIM_Try, /*On fail goto*//*Label 1883*/ 85029, // Rule ID 5582 // |
| 33819 | GIM_CheckFeatures, GIFBS_HasLSE, |
| 33820 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, |
| 33821 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 33822 | // MIs[0] Rn |
| 33823 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33824 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 33825 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 33826 | // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_seq_cst>> => (LDUMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn) |
| 33827 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDUMINALX, |
| 33828 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 33829 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 33830 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 33831 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33832 | GIR_EraseFromParent, /*InsnID*/0, |
| 33833 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33834 | // GIR_Coverage, 5582, |
| 33835 | GIR_Done, |
| 33836 | // Label 1883: @85029 |
| 33837 | GIM_Reject, |
| 33838 | // Label 1878: @85030 |
| 33839 | GIM_Reject, |
| 33840 | // Label 1861: @85031 |
| 33841 | GIM_Reject, |
| 33842 | // Label 29: @85032 |
| 33843 | GIM_Try, /*On fail goto*//*Label 1884*/ 85060, // Rule ID 5366 // |
| 33844 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 33845 | GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 4, |
| 33846 | // MIs[0] Operand 1 |
| 33847 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 33848 | // (atomic_fence 4:{ *:[i64] }, (timm:{ *:[i64] })) => (DMB 9:{ *:[i32] }) |
| 33849 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DMB, |
| 33850 | GIR_AddImm, /*InsnID*/0, /*Imm*/9, |
| 33851 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33852 | GIR_EraseFromParent, /*InsnID*/0, |
| 33853 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33854 | // GIR_Coverage, 5366, |
| 33855 | GIR_Done, |
| 33856 | // Label 1884: @85060 |
| 33857 | GIM_Try, /*On fail goto*//*Label 1885*/ 85083, // Rule ID 5367 // |
| 33858 | // MIs[0] Operand 0 |
| 33859 | GIM_CheckIsImm, /*MI*/0, /*Op*/0, |
| 33860 | // MIs[0] Operand 1 |
| 33861 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 33862 | // (atomic_fence (timm:{ *:[iPTR] }), (timm:{ *:[iPTR] })) => (DMB 11:{ *:[i32] }) |
| 33863 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DMB, |
| 33864 | GIR_AddImm, /*InsnID*/0, /*Imm*/11, |
| 33865 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 33866 | GIR_EraseFromParent, /*InsnID*/0, |
| 33867 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33868 | // GIR_Coverage, 5367, |
| 33869 | GIR_Done, |
| 33870 | // Label 1885: @85083 |
| 33871 | GIM_Reject, |
| 33872 | // Label 30: @85084 |
| 33873 | GIM_Try, /*On fail goto*//*Label 1886*/ 95434, |
| 33874 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 33875 | GIM_Try, /*On fail goto*//*Label 1887*/ 85177, // Rule ID 4892 // |
| 33876 | GIM_CheckFeatures, GIFBS_HasFuseAES, |
| 33877 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aesmc, |
| 33878 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 33879 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 33880 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 33881 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 33882 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 33883 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 33884 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_crypto_aese, |
| 33885 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 33886 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, |
| 33887 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 33888 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 33889 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 33890 | // (intrinsic_wo_chain:{ *:[v16i8] } 331:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[v16i8] } 329:{ *:[iPTR] }, V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2)) => (AESMCrrTied:{ *:[v16i8] } (AESErr:{ *:[v16i8] } V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2)) |
| 33891 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 33892 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::AESErr, |
| 33893 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 33894 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 33895 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // src2 |
| 33896 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 33897 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESMCrrTied, |
| 33898 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 33899 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 33900 | GIR_EraseFromParent, /*InsnID*/0, |
| 33901 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33902 | // GIR_Coverage, 4892, |
| 33903 | GIR_Done, |
| 33904 | // Label 1887: @85177 |
| 33905 | GIM_Try, /*On fail goto*//*Label 1888*/ 85265, // Rule ID 4893 // |
| 33906 | GIM_CheckFeatures, GIFBS_HasFuseAES, |
| 33907 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aesimc, |
| 33908 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 33909 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 33910 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 33911 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 33912 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 33913 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 33914 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_crypto_aesd, |
| 33915 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 33916 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, |
| 33917 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 33918 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 33919 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 33920 | // (intrinsic_wo_chain:{ *:[v16i8] } 330:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[v16i8] } 328:{ *:[iPTR] }, V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2)) => (AESIMCrrTied:{ *:[v16i8] } (AESDrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2)) |
| 33921 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 33922 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::AESDrr, |
| 33923 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 33924 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 33925 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // src2 |
| 33926 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 33927 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESIMCrrTied, |
| 33928 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 33929 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 33930 | GIR_EraseFromParent, /*InsnID*/0, |
| 33931 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33932 | // GIR_Coverage, 4893, |
| 33933 | GIR_Done, |
| 33934 | // Label 1888: @85265 |
| 33935 | GIM_Try, /*On fail goto*//*Label 1889*/ 85303, // Rule ID 2782 // |
| 33936 | GIM_CheckFeatures, GIFBS_HasSVE, |
| 33937 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_cntb, |
| 33938 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 33939 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 33940 | // MIs[0] pattern |
| 33941 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 33942 | // (intrinsic_wo_chain:{ *:[i64] } 624:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern) => (CNTB_XPiI:{ *:[i64] } (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }) |
| 33943 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CNTB_XPiI, |
| 33944 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 33945 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // pattern |
| 33946 | GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 33947 | GIR_EraseFromParent, /*InsnID*/0, |
| 33948 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33949 | // GIR_Coverage, 2782, |
| 33950 | GIR_Done, |
| 33951 | // Label 1889: @85303 |
| 33952 | GIM_Try, /*On fail goto*//*Label 1890*/ 85341, // Rule ID 6724 // |
| 33953 | GIM_CheckFeatures, GIFBS_HasSVE, |
| 33954 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_cnth, |
| 33955 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 33956 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 33957 | // MIs[0] pattern |
| 33958 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 33959 | // (intrinsic_wo_chain:{ *:[i64] } 626:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern) => (CNTH_XPiI:{ *:[i64] } (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }) |
| 33960 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CNTH_XPiI, |
| 33961 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 33962 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // pattern |
| 33963 | GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 33964 | GIR_EraseFromParent, /*InsnID*/0, |
| 33965 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33966 | // GIR_Coverage, 6724, |
| 33967 | GIR_Done, |
| 33968 | // Label 1890: @85341 |
| 33969 | GIM_Try, /*On fail goto*//*Label 1891*/ 85379, // Rule ID 6727 // |
| 33970 | GIM_CheckFeatures, GIFBS_HasSVE, |
| 33971 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_cntw, |
| 33972 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 33973 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 33974 | // MIs[0] pattern |
| 33975 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 33976 | // (intrinsic_wo_chain:{ *:[i64] } 628:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern) => (CNTW_XPiI:{ *:[i64] } (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }) |
| 33977 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CNTW_XPiI, |
| 33978 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 33979 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // pattern |
| 33980 | GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 33981 | GIR_EraseFromParent, /*InsnID*/0, |
| 33982 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 33983 | // GIR_Coverage, 6727, |
| 33984 | GIR_Done, |
| 33985 | // Label 1891: @85379 |
| 33986 | GIM_Try, /*On fail goto*//*Label 1892*/ 85417, // Rule ID 6730 // |
| 33987 | GIM_CheckFeatures, GIFBS_HasSVE, |
| 33988 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sve_cntd, |
| 33989 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 33990 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 33991 | // MIs[0] pattern |
| 33992 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 33993 | // (intrinsic_wo_chain:{ *:[i64] } 625:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern) => (CNTD_XPiI:{ *:[i64] } (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }) |
| 33994 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CNTD_XPiI, |
| 33995 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 33996 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // pattern |
| 33997 | GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 33998 | GIR_EraseFromParent, /*InsnID*/0, |
| 33999 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34000 | // GIR_Coverage, 6730, |
| 34001 | GIR_Done, |
| 34002 | // Label 1892: @85417 |
| 34003 | GIM_Try, /*On fail goto*//*Label 1893*/ 85457, // Rule ID 36 // |
| 34004 | GIM_CheckFeatures, GIFBS_HasBF16, |
| 34005 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_bfcvtn, |
| 34006 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34007 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 34008 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 34009 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 34010 | // (intrinsic_wo_chain:{ *:[v8bf16] } 361:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (BFCVTN:{ *:[v8bf16] } V128:{ *:[v4f32] }:$Rn) |
| 34011 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BFCVTN, |
| 34012 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34013 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34014 | GIR_EraseFromParent, /*InsnID*/0, |
| 34015 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34016 | // GIR_Coverage, 36, |
| 34017 | GIR_Done, |
| 34018 | // Label 1893: @85457 |
| 34019 | GIM_Try, /*On fail goto*//*Label 1894*/ 85497, // Rule ID 38 // |
| 34020 | GIM_CheckFeatures, GIFBS_HasBF16, |
| 34021 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_bfcvt, |
| 34022 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, |
| 34023 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 34024 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 34025 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 34026 | // (intrinsic_wo_chain:{ *:[bf16] } 360:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (BFCVT:{ *:[bf16] } FPR32:{ *:[f32] }:$Rn) |
| 34027 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BFCVT, |
| 34028 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34029 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34030 | GIR_EraseFromParent, /*InsnID*/0, |
| 34031 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34032 | // GIR_Coverage, 38, |
| 34033 | GIR_Done, |
| 34034 | // Label 1894: @85497 |
| 34035 | GIM_Try, /*On fail goto*//*Label 1895*/ 85537, // Rule ID 64 // |
| 34036 | GIM_CheckFeatures, GIFBS_HasFPARMv8_HasJS, |
| 34037 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_fjcvtzs, |
| 34038 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 34039 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 34040 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 34041 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 34042 | // (intrinsic_wo_chain:{ *:[i32] } 344:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FJCVTZS:{ *:[i32] }:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) |
| 34043 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FJCVTZS, |
| 34044 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34045 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34046 | GIR_EraseFromParent, /*InsnID*/0, |
| 34047 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34048 | // GIR_Coverage, 64, |
| 34049 | GIR_Done, |
| 34050 | // Label 1895: @85537 |
| 34051 | GIM_Try, /*On fail goto*//*Label 1896*/ 85577, // Rule ID 330 // |
| 34052 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 34053 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, |
| 34054 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 34055 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 34056 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 34057 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 34058 | // (intrinsic_wo_chain:{ *:[i32] } 373:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTASUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) |
| 34059 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUWHr, |
| 34060 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34061 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34062 | GIR_EraseFromParent, /*InsnID*/0, |
| 34063 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34064 | // GIR_Coverage, 330, |
| 34065 | GIR_Done, |
| 34066 | // Label 1896: @85577 |
| 34067 | GIM_Try, /*On fail goto*//*Label 1897*/ 85617, // Rule ID 331 // |
| 34068 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 34069 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, |
| 34070 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 34071 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 34072 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 34073 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 34074 | // (intrinsic_wo_chain:{ *:[i64] } 373:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTASUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) |
| 34075 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUXHr, |
| 34076 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34077 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34078 | GIR_EraseFromParent, /*InsnID*/0, |
| 34079 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34080 | // GIR_Coverage, 331, |
| 34081 | GIR_Done, |
| 34082 | // Label 1897: @85617 |
| 34083 | GIM_Try, /*On fail goto*//*Label 1898*/ 85657, // Rule ID 332 // |
| 34084 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34085 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, |
| 34086 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 34087 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 34088 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 34089 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 34090 | // (intrinsic_wo_chain:{ *:[i32] } 373:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTASUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) |
| 34091 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUWSr, |
| 34092 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34093 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34094 | GIR_EraseFromParent, /*InsnID*/0, |
| 34095 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34096 | // GIR_Coverage, 332, |
| 34097 | GIR_Done, |
| 34098 | // Label 1898: @85657 |
| 34099 | GIM_Try, /*On fail goto*//*Label 1899*/ 85697, // Rule ID 333 // |
| 34100 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34101 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, |
| 34102 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 34103 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 34104 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 34105 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 34106 | // (intrinsic_wo_chain:{ *:[i64] } 373:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTASUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) |
| 34107 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUXSr, |
| 34108 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34109 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34110 | GIR_EraseFromParent, /*InsnID*/0, |
| 34111 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34112 | // GIR_Coverage, 333, |
| 34113 | GIR_Done, |
| 34114 | // Label 1899: @85697 |
| 34115 | GIM_Try, /*On fail goto*//*Label 1900*/ 85737, // Rule ID 334 // |
| 34116 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34117 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, |
| 34118 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 34119 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 34120 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 34121 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 34122 | // (intrinsic_wo_chain:{ *:[i32] } 373:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTASUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) |
| 34123 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUWDr, |
| 34124 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34125 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34126 | GIR_EraseFromParent, /*InsnID*/0, |
| 34127 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34128 | // GIR_Coverage, 334, |
| 34129 | GIR_Done, |
| 34130 | // Label 1900: @85737 |
| 34131 | GIM_Try, /*On fail goto*//*Label 1901*/ 85777, // Rule ID 335 // |
| 34132 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34133 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, |
| 34134 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 34135 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 34136 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 34137 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 34138 | // (intrinsic_wo_chain:{ *:[i64] } 373:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTASUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) |
| 34139 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUXDr, |
| 34140 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34141 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34142 | GIR_EraseFromParent, /*InsnID*/0, |
| 34143 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34144 | // GIR_Coverage, 335, |
| 34145 | GIR_Done, |
| 34146 | // Label 1901: @85777 |
| 34147 | GIM_Try, /*On fail goto*//*Label 1902*/ 85817, // Rule ID 336 // |
| 34148 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 34149 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, |
| 34150 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 34151 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 34152 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 34153 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 34154 | // (intrinsic_wo_chain:{ *:[i32] } 374:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTAUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) |
| 34155 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUWHr, |
| 34156 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34157 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34158 | GIR_EraseFromParent, /*InsnID*/0, |
| 34159 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34160 | // GIR_Coverage, 336, |
| 34161 | GIR_Done, |
| 34162 | // Label 1902: @85817 |
| 34163 | GIM_Try, /*On fail goto*//*Label 1903*/ 85857, // Rule ID 337 // |
| 34164 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 34165 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, |
| 34166 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 34167 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 34168 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 34169 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 34170 | // (intrinsic_wo_chain:{ *:[i64] } 374:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTAUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) |
| 34171 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUXHr, |
| 34172 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34173 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34174 | GIR_EraseFromParent, /*InsnID*/0, |
| 34175 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34176 | // GIR_Coverage, 337, |
| 34177 | GIR_Done, |
| 34178 | // Label 1903: @85857 |
| 34179 | GIM_Try, /*On fail goto*//*Label 1904*/ 85897, // Rule ID 338 // |
| 34180 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34181 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, |
| 34182 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 34183 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 34184 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 34185 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 34186 | // (intrinsic_wo_chain:{ *:[i32] } 374:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTAUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) |
| 34187 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUWSr, |
| 34188 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34189 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34190 | GIR_EraseFromParent, /*InsnID*/0, |
| 34191 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34192 | // GIR_Coverage, 338, |
| 34193 | GIR_Done, |
| 34194 | // Label 1904: @85897 |
| 34195 | GIM_Try, /*On fail goto*//*Label 1905*/ 85937, // Rule ID 339 // |
| 34196 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34197 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, |
| 34198 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 34199 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 34200 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 34201 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 34202 | // (intrinsic_wo_chain:{ *:[i64] } 374:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTAUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) |
| 34203 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUXSr, |
| 34204 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34205 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34206 | GIR_EraseFromParent, /*InsnID*/0, |
| 34207 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34208 | // GIR_Coverage, 339, |
| 34209 | GIR_Done, |
| 34210 | // Label 1905: @85937 |
| 34211 | GIM_Try, /*On fail goto*//*Label 1906*/ 85977, // Rule ID 340 // |
| 34212 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34213 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, |
| 34214 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 34215 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 34216 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 34217 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 34218 | // (intrinsic_wo_chain:{ *:[i32] } 374:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTAUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) |
| 34219 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUWDr, |
| 34220 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34221 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34222 | GIR_EraseFromParent, /*InsnID*/0, |
| 34223 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34224 | // GIR_Coverage, 340, |
| 34225 | GIR_Done, |
| 34226 | // Label 1906: @85977 |
| 34227 | GIM_Try, /*On fail goto*//*Label 1907*/ 86017, // Rule ID 341 // |
| 34228 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34229 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, |
| 34230 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 34231 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 34232 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 34233 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 34234 | // (intrinsic_wo_chain:{ *:[i64] } 374:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTAUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) |
| 34235 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUXDr, |
| 34236 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34237 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34238 | GIR_EraseFromParent, /*InsnID*/0, |
| 34239 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34240 | // GIR_Coverage, 341, |
| 34241 | GIR_Done, |
| 34242 | // Label 1907: @86017 |
| 34243 | GIM_Try, /*On fail goto*//*Label 1908*/ 86057, // Rule ID 342 // |
| 34244 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 34245 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, |
| 34246 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 34247 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 34248 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 34249 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 34250 | // (intrinsic_wo_chain:{ *:[i32] } 375:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTMSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) |
| 34251 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUWHr, |
| 34252 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34253 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34254 | GIR_EraseFromParent, /*InsnID*/0, |
| 34255 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34256 | // GIR_Coverage, 342, |
| 34257 | GIR_Done, |
| 34258 | // Label 1908: @86057 |
| 34259 | GIM_Try, /*On fail goto*//*Label 1909*/ 86097, // Rule ID 343 // |
| 34260 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 34261 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, |
| 34262 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 34263 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 34264 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 34265 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 34266 | // (intrinsic_wo_chain:{ *:[i64] } 375:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTMSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) |
| 34267 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUXHr, |
| 34268 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34269 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34270 | GIR_EraseFromParent, /*InsnID*/0, |
| 34271 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34272 | // GIR_Coverage, 343, |
| 34273 | GIR_Done, |
| 34274 | // Label 1909: @86097 |
| 34275 | GIM_Try, /*On fail goto*//*Label 1910*/ 86137, // Rule ID 344 // |
| 34276 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34277 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, |
| 34278 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 34279 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 34280 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 34281 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 34282 | // (intrinsic_wo_chain:{ *:[i32] } 375:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTMSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) |
| 34283 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUWSr, |
| 34284 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34285 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34286 | GIR_EraseFromParent, /*InsnID*/0, |
| 34287 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34288 | // GIR_Coverage, 344, |
| 34289 | GIR_Done, |
| 34290 | // Label 1910: @86137 |
| 34291 | GIM_Try, /*On fail goto*//*Label 1911*/ 86177, // Rule ID 345 // |
| 34292 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34293 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, |
| 34294 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 34295 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 34296 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 34297 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 34298 | // (intrinsic_wo_chain:{ *:[i64] } 375:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTMSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) |
| 34299 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUXSr, |
| 34300 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34301 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34302 | GIR_EraseFromParent, /*InsnID*/0, |
| 34303 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34304 | // GIR_Coverage, 345, |
| 34305 | GIR_Done, |
| 34306 | // Label 1911: @86177 |
| 34307 | GIM_Try, /*On fail goto*//*Label 1912*/ 86217, // Rule ID 346 // |
| 34308 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34309 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, |
| 34310 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 34311 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 34312 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 34313 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 34314 | // (intrinsic_wo_chain:{ *:[i32] } 375:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTMSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) |
| 34315 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUWDr, |
| 34316 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34317 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34318 | GIR_EraseFromParent, /*InsnID*/0, |
| 34319 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34320 | // GIR_Coverage, 346, |
| 34321 | GIR_Done, |
| 34322 | // Label 1912: @86217 |
| 34323 | GIM_Try, /*On fail goto*//*Label 1913*/ 86257, // Rule ID 347 // |
| 34324 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34325 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, |
| 34326 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 34327 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 34328 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 34329 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 34330 | // (intrinsic_wo_chain:{ *:[i64] } 375:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTMSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) |
| 34331 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUXDr, |
| 34332 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34333 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34334 | GIR_EraseFromParent, /*InsnID*/0, |
| 34335 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34336 | // GIR_Coverage, 347, |
| 34337 | GIR_Done, |
| 34338 | // Label 1913: @86257 |
| 34339 | GIM_Try, /*On fail goto*//*Label 1914*/ 86297, // Rule ID 348 // |
| 34340 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 34341 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, |
| 34342 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 34343 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 34344 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 34345 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 34346 | // (intrinsic_wo_chain:{ *:[i32] } 376:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTMUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) |
| 34347 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUWHr, |
| 34348 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34349 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34350 | GIR_EraseFromParent, /*InsnID*/0, |
| 34351 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34352 | // GIR_Coverage, 348, |
| 34353 | GIR_Done, |
| 34354 | // Label 1914: @86297 |
| 34355 | GIM_Try, /*On fail goto*//*Label 1915*/ 86337, // Rule ID 349 // |
| 34356 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 34357 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, |
| 34358 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 34359 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 34360 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 34361 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 34362 | // (intrinsic_wo_chain:{ *:[i64] } 376:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTMUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) |
| 34363 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUXHr, |
| 34364 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34365 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34366 | GIR_EraseFromParent, /*InsnID*/0, |
| 34367 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34368 | // GIR_Coverage, 349, |
| 34369 | GIR_Done, |
| 34370 | // Label 1915: @86337 |
| 34371 | GIM_Try, /*On fail goto*//*Label 1916*/ 86377, // Rule ID 350 // |
| 34372 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34373 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, |
| 34374 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 34375 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 34376 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 34377 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 34378 | // (intrinsic_wo_chain:{ *:[i32] } 376:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTMUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) |
| 34379 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUWSr, |
| 34380 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34381 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34382 | GIR_EraseFromParent, /*InsnID*/0, |
| 34383 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34384 | // GIR_Coverage, 350, |
| 34385 | GIR_Done, |
| 34386 | // Label 1916: @86377 |
| 34387 | GIM_Try, /*On fail goto*//*Label 1917*/ 86417, // Rule ID 351 // |
| 34388 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34389 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, |
| 34390 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 34391 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 34392 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 34393 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 34394 | // (intrinsic_wo_chain:{ *:[i64] } 376:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTMUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) |
| 34395 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUXSr, |
| 34396 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34397 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34398 | GIR_EraseFromParent, /*InsnID*/0, |
| 34399 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34400 | // GIR_Coverage, 351, |
| 34401 | GIR_Done, |
| 34402 | // Label 1917: @86417 |
| 34403 | GIM_Try, /*On fail goto*//*Label 1918*/ 86457, // Rule ID 352 // |
| 34404 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34405 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, |
| 34406 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 34407 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 34408 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 34409 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 34410 | // (intrinsic_wo_chain:{ *:[i32] } 376:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTMUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) |
| 34411 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUWDr, |
| 34412 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34413 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34414 | GIR_EraseFromParent, /*InsnID*/0, |
| 34415 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34416 | // GIR_Coverage, 352, |
| 34417 | GIR_Done, |
| 34418 | // Label 1918: @86457 |
| 34419 | GIM_Try, /*On fail goto*//*Label 1919*/ 86497, // Rule ID 353 // |
| 34420 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34421 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, |
| 34422 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 34423 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 34424 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 34425 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 34426 | // (intrinsic_wo_chain:{ *:[i64] } 376:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTMUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) |
| 34427 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUXDr, |
| 34428 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34429 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34430 | GIR_EraseFromParent, /*InsnID*/0, |
| 34431 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34432 | // GIR_Coverage, 353, |
| 34433 | GIR_Done, |
| 34434 | // Label 1919: @86497 |
| 34435 | GIM_Try, /*On fail goto*//*Label 1920*/ 86537, // Rule ID 354 // |
| 34436 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 34437 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, |
| 34438 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 34439 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 34440 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 34441 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 34442 | // (intrinsic_wo_chain:{ *:[i32] } 377:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTNSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) |
| 34443 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUWHr, |
| 34444 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34445 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34446 | GIR_EraseFromParent, /*InsnID*/0, |
| 34447 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34448 | // GIR_Coverage, 354, |
| 34449 | GIR_Done, |
| 34450 | // Label 1920: @86537 |
| 34451 | GIM_Try, /*On fail goto*//*Label 1921*/ 86577, // Rule ID 355 // |
| 34452 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 34453 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, |
| 34454 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 34455 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 34456 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 34457 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 34458 | // (intrinsic_wo_chain:{ *:[i64] } 377:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTNSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) |
| 34459 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUXHr, |
| 34460 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34461 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34462 | GIR_EraseFromParent, /*InsnID*/0, |
| 34463 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34464 | // GIR_Coverage, 355, |
| 34465 | GIR_Done, |
| 34466 | // Label 1921: @86577 |
| 34467 | GIM_Try, /*On fail goto*//*Label 1922*/ 86617, // Rule ID 356 // |
| 34468 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34469 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, |
| 34470 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 34471 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 34472 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 34473 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 34474 | // (intrinsic_wo_chain:{ *:[i32] } 377:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTNSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) |
| 34475 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUWSr, |
| 34476 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34477 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34478 | GIR_EraseFromParent, /*InsnID*/0, |
| 34479 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34480 | // GIR_Coverage, 356, |
| 34481 | GIR_Done, |
| 34482 | // Label 1922: @86617 |
| 34483 | GIM_Try, /*On fail goto*//*Label 1923*/ 86657, // Rule ID 357 // |
| 34484 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34485 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, |
| 34486 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 34487 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 34488 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 34489 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 34490 | // (intrinsic_wo_chain:{ *:[i64] } 377:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTNSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) |
| 34491 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUXSr, |
| 34492 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34493 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34494 | GIR_EraseFromParent, /*InsnID*/0, |
| 34495 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34496 | // GIR_Coverage, 357, |
| 34497 | GIR_Done, |
| 34498 | // Label 1923: @86657 |
| 34499 | GIM_Try, /*On fail goto*//*Label 1924*/ 86697, // Rule ID 358 // |
| 34500 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34501 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, |
| 34502 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 34503 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 34504 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 34505 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 34506 | // (intrinsic_wo_chain:{ *:[i32] } 377:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTNSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) |
| 34507 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUWDr, |
| 34508 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34509 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34510 | GIR_EraseFromParent, /*InsnID*/0, |
| 34511 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34512 | // GIR_Coverage, 358, |
| 34513 | GIR_Done, |
| 34514 | // Label 1924: @86697 |
| 34515 | GIM_Try, /*On fail goto*//*Label 1925*/ 86737, // Rule ID 359 // |
| 34516 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34517 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, |
| 34518 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 34519 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 34520 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 34521 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 34522 | // (intrinsic_wo_chain:{ *:[i64] } 377:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTNSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) |
| 34523 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSUXDr, |
| 34524 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34525 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34526 | GIR_EraseFromParent, /*InsnID*/0, |
| 34527 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34528 | // GIR_Coverage, 359, |
| 34529 | GIR_Done, |
| 34530 | // Label 1925: @86737 |
| 34531 | GIM_Try, /*On fail goto*//*Label 1926*/ 86777, // Rule ID 360 // |
| 34532 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 34533 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, |
| 34534 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 34535 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 34536 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 34537 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 34538 | // (intrinsic_wo_chain:{ *:[i32] } 378:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTNUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) |
| 34539 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUWHr, |
| 34540 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34541 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34542 | GIR_EraseFromParent, /*InsnID*/0, |
| 34543 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34544 | // GIR_Coverage, 360, |
| 34545 | GIR_Done, |
| 34546 | // Label 1926: @86777 |
| 34547 | GIM_Try, /*On fail goto*//*Label 1927*/ 86817, // Rule ID 361 // |
| 34548 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 34549 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, |
| 34550 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 34551 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 34552 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 34553 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 34554 | // (intrinsic_wo_chain:{ *:[i64] } 378:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTNUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) |
| 34555 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUXHr, |
| 34556 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34557 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34558 | GIR_EraseFromParent, /*InsnID*/0, |
| 34559 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34560 | // GIR_Coverage, 361, |
| 34561 | GIR_Done, |
| 34562 | // Label 1927: @86817 |
| 34563 | GIM_Try, /*On fail goto*//*Label 1928*/ 86857, // Rule ID 362 // |
| 34564 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34565 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, |
| 34566 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 34567 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 34568 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 34569 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 34570 | // (intrinsic_wo_chain:{ *:[i32] } 378:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTNUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) |
| 34571 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUWSr, |
| 34572 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34573 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34574 | GIR_EraseFromParent, /*InsnID*/0, |
| 34575 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34576 | // GIR_Coverage, 362, |
| 34577 | GIR_Done, |
| 34578 | // Label 1928: @86857 |
| 34579 | GIM_Try, /*On fail goto*//*Label 1929*/ 86897, // Rule ID 363 // |
| 34580 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34581 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, |
| 34582 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 34583 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 34584 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 34585 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 34586 | // (intrinsic_wo_chain:{ *:[i64] } 378:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTNUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) |
| 34587 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUXSr, |
| 34588 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34589 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34590 | GIR_EraseFromParent, /*InsnID*/0, |
| 34591 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34592 | // GIR_Coverage, 363, |
| 34593 | GIR_Done, |
| 34594 | // Label 1929: @86897 |
| 34595 | GIM_Try, /*On fail goto*//*Label 1930*/ 86937, // Rule ID 364 // |
| 34596 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34597 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, |
| 34598 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 34599 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 34600 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 34601 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 34602 | // (intrinsic_wo_chain:{ *:[i32] } 378:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTNUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) |
| 34603 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUWDr, |
| 34604 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34605 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34606 | GIR_EraseFromParent, /*InsnID*/0, |
| 34607 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34608 | // GIR_Coverage, 364, |
| 34609 | GIR_Done, |
| 34610 | // Label 1930: @86937 |
| 34611 | GIM_Try, /*On fail goto*//*Label 1931*/ 86977, // Rule ID 365 // |
| 34612 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34613 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, |
| 34614 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 34615 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 34616 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 34617 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 34618 | // (intrinsic_wo_chain:{ *:[i64] } 378:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTNUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) |
| 34619 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUUXDr, |
| 34620 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34621 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34622 | GIR_EraseFromParent, /*InsnID*/0, |
| 34623 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34624 | // GIR_Coverage, 365, |
| 34625 | GIR_Done, |
| 34626 | // Label 1931: @86977 |
| 34627 | GIM_Try, /*On fail goto*//*Label 1932*/ 87017, // Rule ID 366 // |
| 34628 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 34629 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, |
| 34630 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 34631 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 34632 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 34633 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 34634 | // (intrinsic_wo_chain:{ *:[i32] } 379:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTPSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) |
| 34635 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUWHr, |
| 34636 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34637 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34638 | GIR_EraseFromParent, /*InsnID*/0, |
| 34639 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34640 | // GIR_Coverage, 366, |
| 34641 | GIR_Done, |
| 34642 | // Label 1932: @87017 |
| 34643 | GIM_Try, /*On fail goto*//*Label 1933*/ 87057, // Rule ID 367 // |
| 34644 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 34645 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, |
| 34646 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 34647 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 34648 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 34649 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 34650 | // (intrinsic_wo_chain:{ *:[i64] } 379:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTPSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) |
| 34651 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUXHr, |
| 34652 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34653 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34654 | GIR_EraseFromParent, /*InsnID*/0, |
| 34655 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34656 | // GIR_Coverage, 367, |
| 34657 | GIR_Done, |
| 34658 | // Label 1933: @87057 |
| 34659 | GIM_Try, /*On fail goto*//*Label 1934*/ 87097, // Rule ID 368 // |
| 34660 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34661 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, |
| 34662 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 34663 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 34664 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 34665 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 34666 | // (intrinsic_wo_chain:{ *:[i32] } 379:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTPSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) |
| 34667 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUWSr, |
| 34668 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34669 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34670 | GIR_EraseFromParent, /*InsnID*/0, |
| 34671 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34672 | // GIR_Coverage, 368, |
| 34673 | GIR_Done, |
| 34674 | // Label 1934: @87097 |
| 34675 | GIM_Try, /*On fail goto*//*Label 1935*/ 87137, // Rule ID 369 // |
| 34676 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34677 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, |
| 34678 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 34679 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 34680 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 34681 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 34682 | // (intrinsic_wo_chain:{ *:[i64] } 379:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTPSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) |
| 34683 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUXSr, |
| 34684 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34685 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34686 | GIR_EraseFromParent, /*InsnID*/0, |
| 34687 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34688 | // GIR_Coverage, 369, |
| 34689 | GIR_Done, |
| 34690 | // Label 1935: @87137 |
| 34691 | GIM_Try, /*On fail goto*//*Label 1936*/ 87177, // Rule ID 370 // |
| 34692 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34693 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, |
| 34694 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 34695 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 34696 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 34697 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 34698 | // (intrinsic_wo_chain:{ *:[i32] } 379:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTPSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) |
| 34699 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUWDr, |
| 34700 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34701 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34702 | GIR_EraseFromParent, /*InsnID*/0, |
| 34703 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34704 | // GIR_Coverage, 370, |
| 34705 | GIR_Done, |
| 34706 | // Label 1936: @87177 |
| 34707 | GIM_Try, /*On fail goto*//*Label 1937*/ 87217, // Rule ID 371 // |
| 34708 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34709 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, |
| 34710 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 34711 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 34712 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 34713 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 34714 | // (intrinsic_wo_chain:{ *:[i64] } 379:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTPSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) |
| 34715 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUXDr, |
| 34716 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34717 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34718 | GIR_EraseFromParent, /*InsnID*/0, |
| 34719 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34720 | // GIR_Coverage, 371, |
| 34721 | GIR_Done, |
| 34722 | // Label 1937: @87217 |
| 34723 | GIM_Try, /*On fail goto*//*Label 1938*/ 87257, // Rule ID 372 // |
| 34724 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 34725 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, |
| 34726 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 34727 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 34728 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 34729 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 34730 | // (intrinsic_wo_chain:{ *:[i32] } 380:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTPUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) |
| 34731 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUWHr, |
| 34732 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34733 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34734 | GIR_EraseFromParent, /*InsnID*/0, |
| 34735 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34736 | // GIR_Coverage, 372, |
| 34737 | GIR_Done, |
| 34738 | // Label 1938: @87257 |
| 34739 | GIM_Try, /*On fail goto*//*Label 1939*/ 87297, // Rule ID 373 // |
| 34740 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 34741 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, |
| 34742 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 34743 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 34744 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 34745 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 34746 | // (intrinsic_wo_chain:{ *:[i64] } 380:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTPUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) |
| 34747 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUXHr, |
| 34748 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34749 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34750 | GIR_EraseFromParent, /*InsnID*/0, |
| 34751 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34752 | // GIR_Coverage, 373, |
| 34753 | GIR_Done, |
| 34754 | // Label 1939: @87297 |
| 34755 | GIM_Try, /*On fail goto*//*Label 1940*/ 87337, // Rule ID 374 // |
| 34756 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34757 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, |
| 34758 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 34759 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 34760 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 34761 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 34762 | // (intrinsic_wo_chain:{ *:[i32] } 380:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTPUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) |
| 34763 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUWSr, |
| 34764 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34765 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34766 | GIR_EraseFromParent, /*InsnID*/0, |
| 34767 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34768 | // GIR_Coverage, 374, |
| 34769 | GIR_Done, |
| 34770 | // Label 1940: @87337 |
| 34771 | GIM_Try, /*On fail goto*//*Label 1941*/ 87377, // Rule ID 375 // |
| 34772 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34773 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, |
| 34774 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 34775 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 34776 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 34777 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 34778 | // (intrinsic_wo_chain:{ *:[i64] } 380:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTPUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) |
| 34779 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUXSr, |
| 34780 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34781 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34782 | GIR_EraseFromParent, /*InsnID*/0, |
| 34783 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34784 | // GIR_Coverage, 375, |
| 34785 | GIR_Done, |
| 34786 | // Label 1941: @87377 |
| 34787 | GIM_Try, /*On fail goto*//*Label 1942*/ 87417, // Rule ID 376 // |
| 34788 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34789 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, |
| 34790 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 34791 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 34792 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 34793 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 34794 | // (intrinsic_wo_chain:{ *:[i32] } 380:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTPUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) |
| 34795 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUWDr, |
| 34796 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34797 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34798 | GIR_EraseFromParent, /*InsnID*/0, |
| 34799 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34800 | // GIR_Coverage, 376, |
| 34801 | GIR_Done, |
| 34802 | // Label 1942: @87417 |
| 34803 | GIM_Try, /*On fail goto*//*Label 1943*/ 87457, // Rule ID 377 // |
| 34804 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34805 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, |
| 34806 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 34807 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 34808 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 34809 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 34810 | // (intrinsic_wo_chain:{ *:[i64] } 380:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTPUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) |
| 34811 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUXDr, |
| 34812 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34813 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34814 | GIR_EraseFromParent, /*InsnID*/0, |
| 34815 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34816 | // GIR_Coverage, 377, |
| 34817 | GIR_Done, |
| 34818 | // Label 1943: @87457 |
| 34819 | GIM_Try, /*On fail goto*//*Label 1944*/ 87497, // Rule ID 501 // |
| 34820 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 34821 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, |
| 34822 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, |
| 34823 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 34824 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 34825 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 34826 | // (intrinsic_wo_chain:{ *:[f16] } 404:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FRINTNHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) |
| 34827 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNHr, |
| 34828 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34829 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34830 | GIR_EraseFromParent, /*InsnID*/0, |
| 34831 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34832 | // GIR_Coverage, 501, |
| 34833 | GIR_Done, |
| 34834 | // Label 1944: @87497 |
| 34835 | GIM_Try, /*On fail goto*//*Label 1945*/ 87537, // Rule ID 502 // |
| 34836 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34837 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, |
| 34838 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 34839 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 34840 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 34841 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 34842 | // (intrinsic_wo_chain:{ *:[f32] } 404:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FRINTNSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) |
| 34843 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNSr, |
| 34844 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34845 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34846 | GIR_EraseFromParent, /*InsnID*/0, |
| 34847 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34848 | // GIR_Coverage, 502, |
| 34849 | GIR_Done, |
| 34850 | // Label 1945: @87537 |
| 34851 | GIM_Try, /*On fail goto*//*Label 1946*/ 87577, // Rule ID 503 // |
| 34852 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 34853 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, |
| 34854 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 34855 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 34856 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 34857 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 34858 | // (intrinsic_wo_chain:{ *:[f64] } 404:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FRINTNDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) |
| 34859 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNDr, |
| 34860 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34861 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34862 | GIR_EraseFromParent, /*InsnID*/0, |
| 34863 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34864 | // GIR_Coverage, 503, |
| 34865 | GIR_Done, |
| 34866 | // Label 1946: @87577 |
| 34867 | GIM_Try, /*On fail goto*//*Label 1947*/ 87617, // Rule ID 604 // |
| 34868 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 34869 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_cls, |
| 34870 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 34871 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 34872 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 34873 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 34874 | // (intrinsic_wo_chain:{ *:[v8i8] } 367:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (CLSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) |
| 34875 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv8i8, |
| 34876 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34877 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34878 | GIR_EraseFromParent, /*InsnID*/0, |
| 34879 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34880 | // GIR_Coverage, 604, |
| 34881 | GIR_Done, |
| 34882 | // Label 1947: @87617 |
| 34883 | GIM_Try, /*On fail goto*//*Label 1948*/ 87657, // Rule ID 605 // |
| 34884 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 34885 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_cls, |
| 34886 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 34887 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 34888 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 34889 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 34890 | // (intrinsic_wo_chain:{ *:[v16i8] } 367:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (CLSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) |
| 34891 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv16i8, |
| 34892 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34893 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34894 | GIR_EraseFromParent, /*InsnID*/0, |
| 34895 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34896 | // GIR_Coverage, 605, |
| 34897 | GIR_Done, |
| 34898 | // Label 1948: @87657 |
| 34899 | GIM_Try, /*On fail goto*//*Label 1949*/ 87697, // Rule ID 606 // |
| 34900 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 34901 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_cls, |
| 34902 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 34903 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 34904 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 34905 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 34906 | // (intrinsic_wo_chain:{ *:[v4i16] } 367:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (CLSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) |
| 34907 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv4i16, |
| 34908 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34909 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34910 | GIR_EraseFromParent, /*InsnID*/0, |
| 34911 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34912 | // GIR_Coverage, 606, |
| 34913 | GIR_Done, |
| 34914 | // Label 1949: @87697 |
| 34915 | GIM_Try, /*On fail goto*//*Label 1950*/ 87737, // Rule ID 607 // |
| 34916 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 34917 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_cls, |
| 34918 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34919 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 34920 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 34921 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 34922 | // (intrinsic_wo_chain:{ *:[v8i16] } 367:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (CLSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) |
| 34923 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv8i16, |
| 34924 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34925 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34926 | GIR_EraseFromParent, /*InsnID*/0, |
| 34927 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34928 | // GIR_Coverage, 607, |
| 34929 | GIR_Done, |
| 34930 | // Label 1950: @87737 |
| 34931 | GIM_Try, /*On fail goto*//*Label 1951*/ 87777, // Rule ID 608 // |
| 34932 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 34933 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_cls, |
| 34934 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 34935 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 34936 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 34937 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 34938 | // (intrinsic_wo_chain:{ *:[v2i32] } 367:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (CLSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) |
| 34939 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv2i32, |
| 34940 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34941 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34942 | GIR_EraseFromParent, /*InsnID*/0, |
| 34943 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34944 | // GIR_Coverage, 608, |
| 34945 | GIR_Done, |
| 34946 | // Label 1951: @87777 |
| 34947 | GIM_Try, /*On fail goto*//*Label 1952*/ 87817, // Rule ID 609 // |
| 34948 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 34949 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_cls, |
| 34950 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 34951 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 34952 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 34953 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 34954 | // (intrinsic_wo_chain:{ *:[v4i32] } 367:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (CLSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) |
| 34955 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSv4i32, |
| 34956 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34957 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34958 | GIR_EraseFromParent, /*InsnID*/0, |
| 34959 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34960 | // GIR_Coverage, 609, |
| 34961 | GIR_Done, |
| 34962 | // Label 1952: @87817 |
| 34963 | GIM_Try, /*On fail goto*//*Label 1953*/ 87857, // Rule ID 683 // |
| 34964 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 34965 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, |
| 34966 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 34967 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 34968 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 34969 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 34970 | // (intrinsic_wo_chain:{ *:[v4i16] } 373:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTASv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) |
| 34971 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv4f16, |
| 34972 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34973 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34974 | GIR_EraseFromParent, /*InsnID*/0, |
| 34975 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34976 | // GIR_Coverage, 683, |
| 34977 | GIR_Done, |
| 34978 | // Label 1953: @87857 |
| 34979 | GIM_Try, /*On fail goto*//*Label 1954*/ 87897, // Rule ID 684 // |
| 34980 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 34981 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, |
| 34982 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 34983 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 34984 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 34985 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 34986 | // (intrinsic_wo_chain:{ *:[v8i16] } 373:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTASv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) |
| 34987 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv8f16, |
| 34988 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 34989 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 34990 | GIR_EraseFromParent, /*InsnID*/0, |
| 34991 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 34992 | // GIR_Coverage, 684, |
| 34993 | GIR_Done, |
| 34994 | // Label 1954: @87897 |
| 34995 | GIM_Try, /*On fail goto*//*Label 1955*/ 87937, // Rule ID 685 // |
| 34996 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 34997 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, |
| 34998 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 34999 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 35000 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35001 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 35002 | // (intrinsic_wo_chain:{ *:[v2i32] } 373:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTASv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) |
| 35003 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv2f32, |
| 35004 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35005 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35006 | GIR_EraseFromParent, /*InsnID*/0, |
| 35007 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35008 | // GIR_Coverage, 685, |
| 35009 | GIR_Done, |
| 35010 | // Label 1955: @87937 |
| 35011 | GIM_Try, /*On fail goto*//*Label 1956*/ 87977, // Rule ID 686 // |
| 35012 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35013 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, |
| 35014 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 35015 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 35016 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35017 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35018 | // (intrinsic_wo_chain:{ *:[v4i32] } 373:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTASv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) |
| 35019 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv4f32, |
| 35020 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35021 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35022 | GIR_EraseFromParent, /*InsnID*/0, |
| 35023 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35024 | // GIR_Coverage, 686, |
| 35025 | GIR_Done, |
| 35026 | // Label 1956: @87977 |
| 35027 | GIM_Try, /*On fail goto*//*Label 1957*/ 88017, // Rule ID 687 // |
| 35028 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35029 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, |
| 35030 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 35031 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 35032 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35033 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35034 | // (intrinsic_wo_chain:{ *:[v2i64] } 373:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTASv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) |
| 35035 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv2f64, |
| 35036 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35037 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35038 | GIR_EraseFromParent, /*InsnID*/0, |
| 35039 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35040 | // GIR_Coverage, 687, |
| 35041 | GIR_Done, |
| 35042 | // Label 1957: @88017 |
| 35043 | GIM_Try, /*On fail goto*//*Label 1958*/ 88057, // Rule ID 688 // |
| 35044 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 35045 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, |
| 35046 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 35047 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 35048 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35049 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 35050 | // (intrinsic_wo_chain:{ *:[v4i16] } 374:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTAUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) |
| 35051 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv4f16, |
| 35052 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35053 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35054 | GIR_EraseFromParent, /*InsnID*/0, |
| 35055 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35056 | // GIR_Coverage, 688, |
| 35057 | GIR_Done, |
| 35058 | // Label 1958: @88057 |
| 35059 | GIM_Try, /*On fail goto*//*Label 1959*/ 88097, // Rule ID 689 // |
| 35060 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 35061 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, |
| 35062 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 35063 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 35064 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35065 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35066 | // (intrinsic_wo_chain:{ *:[v8i16] } 374:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTAUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) |
| 35067 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv8f16, |
| 35068 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35069 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35070 | GIR_EraseFromParent, /*InsnID*/0, |
| 35071 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35072 | // GIR_Coverage, 689, |
| 35073 | GIR_Done, |
| 35074 | // Label 1959: @88097 |
| 35075 | GIM_Try, /*On fail goto*//*Label 1960*/ 88137, // Rule ID 690 // |
| 35076 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35077 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, |
| 35078 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 35079 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 35080 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35081 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 35082 | // (intrinsic_wo_chain:{ *:[v2i32] } 374:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTAUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) |
| 35083 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv2f32, |
| 35084 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35085 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35086 | GIR_EraseFromParent, /*InsnID*/0, |
| 35087 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35088 | // GIR_Coverage, 690, |
| 35089 | GIR_Done, |
| 35090 | // Label 1960: @88137 |
| 35091 | GIM_Try, /*On fail goto*//*Label 1961*/ 88177, // Rule ID 691 // |
| 35092 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35093 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, |
| 35094 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 35095 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 35096 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35097 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35098 | // (intrinsic_wo_chain:{ *:[v4i32] } 374:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTAUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) |
| 35099 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv4f32, |
| 35100 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35101 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35102 | GIR_EraseFromParent, /*InsnID*/0, |
| 35103 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35104 | // GIR_Coverage, 691, |
| 35105 | GIR_Done, |
| 35106 | // Label 1961: @88177 |
| 35107 | GIM_Try, /*On fail goto*//*Label 1962*/ 88217, // Rule ID 692 // |
| 35108 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35109 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, |
| 35110 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 35111 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 35112 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35113 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35114 | // (intrinsic_wo_chain:{ *:[v2i64] } 374:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTAUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) |
| 35115 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv2f64, |
| 35116 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35117 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35118 | GIR_EraseFromParent, /*InsnID*/0, |
| 35119 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35120 | // GIR_Coverage, 692, |
| 35121 | GIR_Done, |
| 35122 | // Label 1962: @88217 |
| 35123 | GIM_Try, /*On fail goto*//*Label 1963*/ 88257, // Rule ID 693 // |
| 35124 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 35125 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, |
| 35126 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 35127 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 35128 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35129 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 35130 | // (intrinsic_wo_chain:{ *:[v4i16] } 375:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTMSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) |
| 35131 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv4f16, |
| 35132 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35133 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35134 | GIR_EraseFromParent, /*InsnID*/0, |
| 35135 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35136 | // GIR_Coverage, 693, |
| 35137 | GIR_Done, |
| 35138 | // Label 1963: @88257 |
| 35139 | GIM_Try, /*On fail goto*//*Label 1964*/ 88297, // Rule ID 694 // |
| 35140 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 35141 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, |
| 35142 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 35143 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 35144 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35145 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35146 | // (intrinsic_wo_chain:{ *:[v8i16] } 375:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTMSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) |
| 35147 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv8f16, |
| 35148 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35149 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35150 | GIR_EraseFromParent, /*InsnID*/0, |
| 35151 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35152 | // GIR_Coverage, 694, |
| 35153 | GIR_Done, |
| 35154 | // Label 1964: @88297 |
| 35155 | GIM_Try, /*On fail goto*//*Label 1965*/ 88337, // Rule ID 695 // |
| 35156 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35157 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, |
| 35158 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 35159 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 35160 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35161 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 35162 | // (intrinsic_wo_chain:{ *:[v2i32] } 375:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTMSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) |
| 35163 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv2f32, |
| 35164 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35165 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35166 | GIR_EraseFromParent, /*InsnID*/0, |
| 35167 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35168 | // GIR_Coverage, 695, |
| 35169 | GIR_Done, |
| 35170 | // Label 1965: @88337 |
| 35171 | GIM_Try, /*On fail goto*//*Label 1966*/ 88377, // Rule ID 696 // |
| 35172 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35173 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, |
| 35174 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 35175 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 35176 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35177 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35178 | // (intrinsic_wo_chain:{ *:[v4i32] } 375:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTMSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) |
| 35179 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv4f32, |
| 35180 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35181 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35182 | GIR_EraseFromParent, /*InsnID*/0, |
| 35183 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35184 | // GIR_Coverage, 696, |
| 35185 | GIR_Done, |
| 35186 | // Label 1966: @88377 |
| 35187 | GIM_Try, /*On fail goto*//*Label 1967*/ 88417, // Rule ID 697 // |
| 35188 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35189 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, |
| 35190 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 35191 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 35192 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35193 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35194 | // (intrinsic_wo_chain:{ *:[v2i64] } 375:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTMSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) |
| 35195 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv2f64, |
| 35196 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35197 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35198 | GIR_EraseFromParent, /*InsnID*/0, |
| 35199 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35200 | // GIR_Coverage, 697, |
| 35201 | GIR_Done, |
| 35202 | // Label 1967: @88417 |
| 35203 | GIM_Try, /*On fail goto*//*Label 1968*/ 88457, // Rule ID 698 // |
| 35204 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 35205 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, |
| 35206 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 35207 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 35208 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35209 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 35210 | // (intrinsic_wo_chain:{ *:[v4i16] } 376:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTMUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) |
| 35211 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv4f16, |
| 35212 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35213 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35214 | GIR_EraseFromParent, /*InsnID*/0, |
| 35215 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35216 | // GIR_Coverage, 698, |
| 35217 | GIR_Done, |
| 35218 | // Label 1968: @88457 |
| 35219 | GIM_Try, /*On fail goto*//*Label 1969*/ 88497, // Rule ID 699 // |
| 35220 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 35221 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, |
| 35222 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 35223 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 35224 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35225 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35226 | // (intrinsic_wo_chain:{ *:[v8i16] } 376:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTMUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) |
| 35227 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv8f16, |
| 35228 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35229 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35230 | GIR_EraseFromParent, /*InsnID*/0, |
| 35231 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35232 | // GIR_Coverage, 699, |
| 35233 | GIR_Done, |
| 35234 | // Label 1969: @88497 |
| 35235 | GIM_Try, /*On fail goto*//*Label 1970*/ 88537, // Rule ID 700 // |
| 35236 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35237 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, |
| 35238 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 35239 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 35240 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35241 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 35242 | // (intrinsic_wo_chain:{ *:[v2i32] } 376:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTMUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) |
| 35243 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv2f32, |
| 35244 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35245 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35246 | GIR_EraseFromParent, /*InsnID*/0, |
| 35247 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35248 | // GIR_Coverage, 700, |
| 35249 | GIR_Done, |
| 35250 | // Label 1970: @88537 |
| 35251 | GIM_Try, /*On fail goto*//*Label 1971*/ 88577, // Rule ID 701 // |
| 35252 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35253 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, |
| 35254 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 35255 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 35256 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35257 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35258 | // (intrinsic_wo_chain:{ *:[v4i32] } 376:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTMUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) |
| 35259 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv4f32, |
| 35260 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35261 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35262 | GIR_EraseFromParent, /*InsnID*/0, |
| 35263 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35264 | // GIR_Coverage, 701, |
| 35265 | GIR_Done, |
| 35266 | // Label 1971: @88577 |
| 35267 | GIM_Try, /*On fail goto*//*Label 1972*/ 88617, // Rule ID 702 // |
| 35268 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35269 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, |
| 35270 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 35271 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 35272 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35273 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35274 | // (intrinsic_wo_chain:{ *:[v2i64] } 376:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTMUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) |
| 35275 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv2f64, |
| 35276 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35277 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35278 | GIR_EraseFromParent, /*InsnID*/0, |
| 35279 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35280 | // GIR_Coverage, 702, |
| 35281 | GIR_Done, |
| 35282 | // Label 1972: @88617 |
| 35283 | GIM_Try, /*On fail goto*//*Label 1973*/ 88657, // Rule ID 703 // |
| 35284 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 35285 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, |
| 35286 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 35287 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 35288 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35289 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 35290 | // (intrinsic_wo_chain:{ *:[v4i16] } 377:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTNSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) |
| 35291 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv4f16, |
| 35292 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35293 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35294 | GIR_EraseFromParent, /*InsnID*/0, |
| 35295 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35296 | // GIR_Coverage, 703, |
| 35297 | GIR_Done, |
| 35298 | // Label 1973: @88657 |
| 35299 | GIM_Try, /*On fail goto*//*Label 1974*/ 88697, // Rule ID 704 // |
| 35300 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 35301 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, |
| 35302 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 35303 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 35304 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35305 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35306 | // (intrinsic_wo_chain:{ *:[v8i16] } 377:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTNSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) |
| 35307 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv8f16, |
| 35308 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35309 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35310 | GIR_EraseFromParent, /*InsnID*/0, |
| 35311 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35312 | // GIR_Coverage, 704, |
| 35313 | GIR_Done, |
| 35314 | // Label 1974: @88697 |
| 35315 | GIM_Try, /*On fail goto*//*Label 1975*/ 88737, // Rule ID 705 // |
| 35316 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35317 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, |
| 35318 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 35319 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 35320 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35321 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 35322 | // (intrinsic_wo_chain:{ *:[v2i32] } 377:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTNSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) |
| 35323 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv2f32, |
| 35324 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35325 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35326 | GIR_EraseFromParent, /*InsnID*/0, |
| 35327 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35328 | // GIR_Coverage, 705, |
| 35329 | GIR_Done, |
| 35330 | // Label 1975: @88737 |
| 35331 | GIM_Try, /*On fail goto*//*Label 1976*/ 88777, // Rule ID 706 // |
| 35332 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35333 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, |
| 35334 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 35335 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 35336 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35337 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35338 | // (intrinsic_wo_chain:{ *:[v4i32] } 377:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTNSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) |
| 35339 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv4f32, |
| 35340 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35341 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35342 | GIR_EraseFromParent, /*InsnID*/0, |
| 35343 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35344 | // GIR_Coverage, 706, |
| 35345 | GIR_Done, |
| 35346 | // Label 1976: @88777 |
| 35347 | GIM_Try, /*On fail goto*//*Label 1977*/ 88817, // Rule ID 707 // |
| 35348 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35349 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, |
| 35350 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 35351 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 35352 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35353 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35354 | // (intrinsic_wo_chain:{ *:[v2i64] } 377:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTNSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) |
| 35355 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv2f64, |
| 35356 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35357 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35358 | GIR_EraseFromParent, /*InsnID*/0, |
| 35359 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35360 | // GIR_Coverage, 707, |
| 35361 | GIR_Done, |
| 35362 | // Label 1977: @88817 |
| 35363 | GIM_Try, /*On fail goto*//*Label 1978*/ 88857, // Rule ID 708 // |
| 35364 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 35365 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, |
| 35366 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 35367 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 35368 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35369 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 35370 | // (intrinsic_wo_chain:{ *:[v4i16] } 378:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTNUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) |
| 35371 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv4f16, |
| 35372 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35373 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35374 | GIR_EraseFromParent, /*InsnID*/0, |
| 35375 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35376 | // GIR_Coverage, 708, |
| 35377 | GIR_Done, |
| 35378 | // Label 1978: @88857 |
| 35379 | GIM_Try, /*On fail goto*//*Label 1979*/ 88897, // Rule ID 709 // |
| 35380 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 35381 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, |
| 35382 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 35383 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 35384 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35385 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35386 | // (intrinsic_wo_chain:{ *:[v8i16] } 378:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTNUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) |
| 35387 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv8f16, |
| 35388 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35389 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35390 | GIR_EraseFromParent, /*InsnID*/0, |
| 35391 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35392 | // GIR_Coverage, 709, |
| 35393 | GIR_Done, |
| 35394 | // Label 1979: @88897 |
| 35395 | GIM_Try, /*On fail goto*//*Label 1980*/ 88937, // Rule ID 710 // |
| 35396 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35397 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, |
| 35398 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 35399 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 35400 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35401 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 35402 | // (intrinsic_wo_chain:{ *:[v2i32] } 378:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTNUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) |
| 35403 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv2f32, |
| 35404 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35405 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35406 | GIR_EraseFromParent, /*InsnID*/0, |
| 35407 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35408 | // GIR_Coverage, 710, |
| 35409 | GIR_Done, |
| 35410 | // Label 1980: @88937 |
| 35411 | GIM_Try, /*On fail goto*//*Label 1981*/ 88977, // Rule ID 711 // |
| 35412 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35413 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, |
| 35414 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 35415 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 35416 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35417 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35418 | // (intrinsic_wo_chain:{ *:[v4i32] } 378:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTNUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) |
| 35419 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv4f32, |
| 35420 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35421 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35422 | GIR_EraseFromParent, /*InsnID*/0, |
| 35423 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35424 | // GIR_Coverage, 711, |
| 35425 | GIR_Done, |
| 35426 | // Label 1981: @88977 |
| 35427 | GIM_Try, /*On fail goto*//*Label 1982*/ 89017, // Rule ID 712 // |
| 35428 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35429 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, |
| 35430 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 35431 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 35432 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35433 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35434 | // (intrinsic_wo_chain:{ *:[v2i64] } 378:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTNUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) |
| 35435 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv2f64, |
| 35436 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35437 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35438 | GIR_EraseFromParent, /*InsnID*/0, |
| 35439 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35440 | // GIR_Coverage, 712, |
| 35441 | GIR_Done, |
| 35442 | // Label 1982: @89017 |
| 35443 | GIM_Try, /*On fail goto*//*Label 1983*/ 89057, // Rule ID 713 // |
| 35444 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 35445 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, |
| 35446 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 35447 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 35448 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35449 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 35450 | // (intrinsic_wo_chain:{ *:[v4i16] } 379:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTPSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) |
| 35451 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv4f16, |
| 35452 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35453 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35454 | GIR_EraseFromParent, /*InsnID*/0, |
| 35455 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35456 | // GIR_Coverage, 713, |
| 35457 | GIR_Done, |
| 35458 | // Label 1983: @89057 |
| 35459 | GIM_Try, /*On fail goto*//*Label 1984*/ 89097, // Rule ID 714 // |
| 35460 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 35461 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, |
| 35462 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 35463 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 35464 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35465 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35466 | // (intrinsic_wo_chain:{ *:[v8i16] } 379:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTPSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) |
| 35467 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv8f16, |
| 35468 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35469 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35470 | GIR_EraseFromParent, /*InsnID*/0, |
| 35471 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35472 | // GIR_Coverage, 714, |
| 35473 | GIR_Done, |
| 35474 | // Label 1984: @89097 |
| 35475 | GIM_Try, /*On fail goto*//*Label 1985*/ 89137, // Rule ID 715 // |
| 35476 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35477 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, |
| 35478 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 35479 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 35480 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35481 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 35482 | // (intrinsic_wo_chain:{ *:[v2i32] } 379:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTPSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) |
| 35483 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv2f32, |
| 35484 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35485 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35486 | GIR_EraseFromParent, /*InsnID*/0, |
| 35487 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35488 | // GIR_Coverage, 715, |
| 35489 | GIR_Done, |
| 35490 | // Label 1985: @89137 |
| 35491 | GIM_Try, /*On fail goto*//*Label 1986*/ 89177, // Rule ID 716 // |
| 35492 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35493 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, |
| 35494 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 35495 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 35496 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35497 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35498 | // (intrinsic_wo_chain:{ *:[v4i32] } 379:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTPSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) |
| 35499 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv4f32, |
| 35500 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35501 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35502 | GIR_EraseFromParent, /*InsnID*/0, |
| 35503 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35504 | // GIR_Coverage, 716, |
| 35505 | GIR_Done, |
| 35506 | // Label 1986: @89177 |
| 35507 | GIM_Try, /*On fail goto*//*Label 1987*/ 89217, // Rule ID 717 // |
| 35508 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35509 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, |
| 35510 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 35511 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 35512 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35513 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35514 | // (intrinsic_wo_chain:{ *:[v2i64] } 379:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTPSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) |
| 35515 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv2f64, |
| 35516 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35517 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35518 | GIR_EraseFromParent, /*InsnID*/0, |
| 35519 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35520 | // GIR_Coverage, 717, |
| 35521 | GIR_Done, |
| 35522 | // Label 1987: @89217 |
| 35523 | GIM_Try, /*On fail goto*//*Label 1988*/ 89257, // Rule ID 718 // |
| 35524 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 35525 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, |
| 35526 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 35527 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 35528 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35529 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 35530 | // (intrinsic_wo_chain:{ *:[v4i16] } 380:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTPUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) |
| 35531 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv4f16, |
| 35532 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35533 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35534 | GIR_EraseFromParent, /*InsnID*/0, |
| 35535 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35536 | // GIR_Coverage, 718, |
| 35537 | GIR_Done, |
| 35538 | // Label 1988: @89257 |
| 35539 | GIM_Try, /*On fail goto*//*Label 1989*/ 89297, // Rule ID 719 // |
| 35540 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 35541 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, |
| 35542 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 35543 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 35544 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35545 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35546 | // (intrinsic_wo_chain:{ *:[v8i16] } 380:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTPUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) |
| 35547 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv8f16, |
| 35548 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35549 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35550 | GIR_EraseFromParent, /*InsnID*/0, |
| 35551 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35552 | // GIR_Coverage, 719, |
| 35553 | GIR_Done, |
| 35554 | // Label 1989: @89297 |
| 35555 | GIM_Try, /*On fail goto*//*Label 1990*/ 89337, // Rule ID 720 // |
| 35556 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35557 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, |
| 35558 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 35559 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 35560 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35561 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 35562 | // (intrinsic_wo_chain:{ *:[v2i32] } 380:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTPUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) |
| 35563 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv2f32, |
| 35564 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35565 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35566 | GIR_EraseFromParent, /*InsnID*/0, |
| 35567 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35568 | // GIR_Coverage, 720, |
| 35569 | GIR_Done, |
| 35570 | // Label 1990: @89337 |
| 35571 | GIM_Try, /*On fail goto*//*Label 1991*/ 89377, // Rule ID 721 // |
| 35572 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35573 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, |
| 35574 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 35575 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 35576 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35577 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35578 | // (intrinsic_wo_chain:{ *:[v4i32] } 380:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTPUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) |
| 35579 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv4f32, |
| 35580 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35581 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35582 | GIR_EraseFromParent, /*InsnID*/0, |
| 35583 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35584 | // GIR_Coverage, 721, |
| 35585 | GIR_Done, |
| 35586 | // Label 1991: @89377 |
| 35587 | GIM_Try, /*On fail goto*//*Label 1992*/ 89417, // Rule ID 722 // |
| 35588 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35589 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, |
| 35590 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 35591 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 35592 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35593 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35594 | // (intrinsic_wo_chain:{ *:[v2i64] } 380:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTPUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) |
| 35595 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv2f64, |
| 35596 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35597 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35598 | GIR_EraseFromParent, /*InsnID*/0, |
| 35599 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35600 | // GIR_Coverage, 722, |
| 35601 | GIR_Done, |
| 35602 | // Label 1992: @89417 |
| 35603 | GIM_Try, /*On fail goto*//*Label 1993*/ 89457, // Rule ID 723 // |
| 35604 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35605 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtxn, |
| 35606 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 35607 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 35608 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35609 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35610 | // (intrinsic_wo_chain:{ *:[v2f32] } 381:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTXNv2f32:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn) |
| 35611 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTXNv2f32, |
| 35612 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35613 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35614 | GIR_EraseFromParent, /*InsnID*/0, |
| 35615 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35616 | // GIR_Coverage, 723, |
| 35617 | GIR_Done, |
| 35618 | // Label 1993: @89457 |
| 35619 | GIM_Try, /*On fail goto*//*Label 1994*/ 89497, // Rule ID 739 // |
| 35620 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 35621 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, |
| 35622 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 35623 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 35624 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35625 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 35626 | // (intrinsic_wo_chain:{ *:[v4f16] } 401:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FRECPEv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) |
| 35627 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv4f16, |
| 35628 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35629 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35630 | GIR_EraseFromParent, /*InsnID*/0, |
| 35631 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35632 | // GIR_Coverage, 739, |
| 35633 | GIR_Done, |
| 35634 | // Label 1994: @89497 |
| 35635 | GIM_Try, /*On fail goto*//*Label 1995*/ 89537, // Rule ID 740 // |
| 35636 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 35637 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, |
| 35638 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 35639 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 35640 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35641 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35642 | // (intrinsic_wo_chain:{ *:[v8f16] } 401:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FRECPEv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) |
| 35643 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv8f16, |
| 35644 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35645 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35646 | GIR_EraseFromParent, /*InsnID*/0, |
| 35647 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35648 | // GIR_Coverage, 740, |
| 35649 | GIR_Done, |
| 35650 | // Label 1995: @89537 |
| 35651 | GIM_Try, /*On fail goto*//*Label 1996*/ 89577, // Rule ID 741 // |
| 35652 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35653 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, |
| 35654 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 35655 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 35656 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35657 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 35658 | // (intrinsic_wo_chain:{ *:[v2f32] } 401:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FRECPEv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) |
| 35659 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv2f32, |
| 35660 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35661 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35662 | GIR_EraseFromParent, /*InsnID*/0, |
| 35663 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35664 | // GIR_Coverage, 741, |
| 35665 | GIR_Done, |
| 35666 | // Label 1996: @89577 |
| 35667 | GIM_Try, /*On fail goto*//*Label 1997*/ 89617, // Rule ID 742 // |
| 35668 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35669 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, |
| 35670 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 35671 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 35672 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35673 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35674 | // (intrinsic_wo_chain:{ *:[v4f32] } 401:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FRECPEv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) |
| 35675 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv4f32, |
| 35676 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35677 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35678 | GIR_EraseFromParent, /*InsnID*/0, |
| 35679 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35680 | // GIR_Coverage, 742, |
| 35681 | GIR_Done, |
| 35682 | // Label 1997: @89617 |
| 35683 | GIM_Try, /*On fail goto*//*Label 1998*/ 89657, // Rule ID 743 // |
| 35684 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35685 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, |
| 35686 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 35687 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 35688 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35689 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35690 | // (intrinsic_wo_chain:{ *:[v2f64] } 401:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FRECPEv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) |
| 35691 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv2f64, |
| 35692 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35693 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35694 | GIR_EraseFromParent, /*InsnID*/0, |
| 35695 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35696 | // GIR_Coverage, 743, |
| 35697 | GIR_Done, |
| 35698 | // Label 1998: @89657 |
| 35699 | GIM_Try, /*On fail goto*//*Label 1999*/ 89697, // Rule ID 759 // |
| 35700 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 35701 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, |
| 35702 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 35703 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 35704 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35705 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 35706 | // (intrinsic_wo_chain:{ *:[v4f16] } 404:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FRINTNv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) |
| 35707 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNv4f16, |
| 35708 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35709 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35710 | GIR_EraseFromParent, /*InsnID*/0, |
| 35711 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35712 | // GIR_Coverage, 759, |
| 35713 | GIR_Done, |
| 35714 | // Label 1999: @89697 |
| 35715 | GIM_Try, /*On fail goto*//*Label 2000*/ 89737, // Rule ID 760 // |
| 35716 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 35717 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, |
| 35718 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 35719 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 35720 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35721 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35722 | // (intrinsic_wo_chain:{ *:[v8f16] } 404:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FRINTNv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) |
| 35723 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNv8f16, |
| 35724 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35725 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35726 | GIR_EraseFromParent, /*InsnID*/0, |
| 35727 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35728 | // GIR_Coverage, 760, |
| 35729 | GIR_Done, |
| 35730 | // Label 2000: @89737 |
| 35731 | GIM_Try, /*On fail goto*//*Label 2001*/ 89777, // Rule ID 761 // |
| 35732 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35733 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, |
| 35734 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 35735 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 35736 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35737 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 35738 | // (intrinsic_wo_chain:{ *:[v2f32] } 404:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FRINTNv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) |
| 35739 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNv2f32, |
| 35740 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35741 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35742 | GIR_EraseFromParent, /*InsnID*/0, |
| 35743 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35744 | // GIR_Coverage, 761, |
| 35745 | GIR_Done, |
| 35746 | // Label 2001: @89777 |
| 35747 | GIM_Try, /*On fail goto*//*Label 2002*/ 89817, // Rule ID 762 // |
| 35748 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35749 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, |
| 35750 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 35751 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 35752 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35753 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35754 | // (intrinsic_wo_chain:{ *:[v4f32] } 404:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FRINTNv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) |
| 35755 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNv4f32, |
| 35756 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35757 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35758 | GIR_EraseFromParent, /*InsnID*/0, |
| 35759 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35760 | // GIR_Coverage, 762, |
| 35761 | GIR_Done, |
| 35762 | // Label 2002: @89817 |
| 35763 | GIM_Try, /*On fail goto*//*Label 2003*/ 89857, // Rule ID 763 // |
| 35764 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35765 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, |
| 35766 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 35767 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 35768 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35769 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35770 | // (intrinsic_wo_chain:{ *:[v2f64] } 404:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FRINTNv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) |
| 35771 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNv2f64, |
| 35772 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35773 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35774 | GIR_EraseFromParent, /*InsnID*/0, |
| 35775 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35776 | // GIR_Coverage, 763, |
| 35777 | GIR_Done, |
| 35778 | // Label 2003: @89857 |
| 35779 | GIM_Try, /*On fail goto*//*Label 2004*/ 89897, // Rule ID 779 // |
| 35780 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 35781 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, |
| 35782 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 35783 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 35784 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35785 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 35786 | // (intrinsic_wo_chain:{ *:[v4f16] } 405:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FRSQRTEv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) |
| 35787 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv4f16, |
| 35788 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35789 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35790 | GIR_EraseFromParent, /*InsnID*/0, |
| 35791 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35792 | // GIR_Coverage, 779, |
| 35793 | GIR_Done, |
| 35794 | // Label 2004: @89897 |
| 35795 | GIM_Try, /*On fail goto*//*Label 2005*/ 89937, // Rule ID 780 // |
| 35796 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 35797 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, |
| 35798 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 35799 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 35800 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35801 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35802 | // (intrinsic_wo_chain:{ *:[v8f16] } 405:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FRSQRTEv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) |
| 35803 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv8f16, |
| 35804 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35805 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35806 | GIR_EraseFromParent, /*InsnID*/0, |
| 35807 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35808 | // GIR_Coverage, 780, |
| 35809 | GIR_Done, |
| 35810 | // Label 2005: @89937 |
| 35811 | GIM_Try, /*On fail goto*//*Label 2006*/ 89977, // Rule ID 781 // |
| 35812 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35813 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, |
| 35814 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 35815 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 35816 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35817 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 35818 | // (intrinsic_wo_chain:{ *:[v2f32] } 405:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FRSQRTEv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) |
| 35819 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv2f32, |
| 35820 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35821 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35822 | GIR_EraseFromParent, /*InsnID*/0, |
| 35823 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35824 | // GIR_Coverage, 781, |
| 35825 | GIR_Done, |
| 35826 | // Label 2006: @89977 |
| 35827 | GIM_Try, /*On fail goto*//*Label 2007*/ 90017, // Rule ID 782 // |
| 35828 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35829 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, |
| 35830 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 35831 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 35832 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35833 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35834 | // (intrinsic_wo_chain:{ *:[v4f32] } 405:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FRSQRTEv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) |
| 35835 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv4f32, |
| 35836 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35837 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35838 | GIR_EraseFromParent, /*InsnID*/0, |
| 35839 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35840 | // GIR_Coverage, 782, |
| 35841 | GIR_Done, |
| 35842 | // Label 2007: @90017 |
| 35843 | GIM_Try, /*On fail goto*//*Label 2008*/ 90057, // Rule ID 783 // |
| 35844 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35845 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, |
| 35846 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 35847 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 35848 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35849 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35850 | // (intrinsic_wo_chain:{ *:[v2f64] } 405:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FRSQRTEv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) |
| 35851 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv2f64, |
| 35852 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35853 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35854 | GIR_EraseFromParent, /*InsnID*/0, |
| 35855 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35856 | // GIR_Coverage, 783, |
| 35857 | GIR_Done, |
| 35858 | // Label 2008: @90057 |
| 35859 | GIM_Try, /*On fail goto*//*Label 2009*/ 90097, // Rule ID 798 // |
| 35860 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35861 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rbit, |
| 35862 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 35863 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 35864 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35865 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 35866 | // (intrinsic_wo_chain:{ *:[v8i8] } 423:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (RBITv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) |
| 35867 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RBITv8i8, |
| 35868 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35869 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35870 | GIR_EraseFromParent, /*InsnID*/0, |
| 35871 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35872 | // GIR_Coverage, 798, |
| 35873 | GIR_Done, |
| 35874 | // Label 2009: @90097 |
| 35875 | GIM_Try, /*On fail goto*//*Label 2010*/ 90137, // Rule ID 799 // |
| 35876 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35877 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rbit, |
| 35878 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 35879 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 35880 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35881 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35882 | // (intrinsic_wo_chain:{ *:[v16i8] } 423:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (RBITv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) |
| 35883 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RBITv16i8, |
| 35884 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35885 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35886 | GIR_EraseFromParent, /*InsnID*/0, |
| 35887 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35888 | // GIR_Coverage, 799, |
| 35889 | GIR_Done, |
| 35890 | // Label 2010: @90137 |
| 35891 | GIM_Try, /*On fail goto*//*Label 2011*/ 90177, // Rule ID 818 // |
| 35892 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35893 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlp, |
| 35894 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 35895 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 35896 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35897 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 35898 | // (intrinsic_wo_chain:{ *:[v4i16] } 427:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (SADDLPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn) |
| 35899 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv8i8_v4i16, |
| 35900 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35901 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35902 | GIR_EraseFromParent, /*InsnID*/0, |
| 35903 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35904 | // GIR_Coverage, 818, |
| 35905 | GIR_Done, |
| 35906 | // Label 2011: @90177 |
| 35907 | GIM_Try, /*On fail goto*//*Label 2012*/ 90217, // Rule ID 819 // |
| 35908 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35909 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlp, |
| 35910 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 35911 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 35912 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35913 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35914 | // (intrinsic_wo_chain:{ *:[v8i16] } 427:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (SADDLPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn) |
| 35915 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv16i8_v8i16, |
| 35916 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35917 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35918 | GIR_EraseFromParent, /*InsnID*/0, |
| 35919 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35920 | // GIR_Coverage, 819, |
| 35921 | GIR_Done, |
| 35922 | // Label 2012: @90217 |
| 35923 | GIM_Try, /*On fail goto*//*Label 2013*/ 90257, // Rule ID 820 // |
| 35924 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35925 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlp, |
| 35926 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 35927 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 35928 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35929 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 35930 | // (intrinsic_wo_chain:{ *:[v2i32] } 427:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (SADDLPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn) |
| 35931 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv4i16_v2i32, |
| 35932 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35933 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35934 | GIR_EraseFromParent, /*InsnID*/0, |
| 35935 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35936 | // GIR_Coverage, 820, |
| 35937 | GIR_Done, |
| 35938 | // Label 2013: @90257 |
| 35939 | GIM_Try, /*On fail goto*//*Label 2014*/ 90297, // Rule ID 821 // |
| 35940 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35941 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlp, |
| 35942 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 35943 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 35944 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35945 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35946 | // (intrinsic_wo_chain:{ *:[v4i32] } 427:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SADDLPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn) |
| 35947 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv8i16_v4i32, |
| 35948 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35949 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35950 | GIR_EraseFromParent, /*InsnID*/0, |
| 35951 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35952 | // GIR_Coverage, 821, |
| 35953 | GIR_Done, |
| 35954 | // Label 2014: @90297 |
| 35955 | GIM_Try, /*On fail goto*//*Label 2015*/ 90337, // Rule ID 822 // |
| 35956 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35957 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlp, |
| 35958 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 35959 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 35960 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35961 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 35962 | // (intrinsic_wo_chain:{ *:[v1i64] } 427:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (SADDLPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn) |
| 35963 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv2i32_v1i64, |
| 35964 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35965 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35966 | GIR_EraseFromParent, /*InsnID*/0, |
| 35967 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35968 | // GIR_Coverage, 822, |
| 35969 | GIR_Done, |
| 35970 | // Label 2015: @90337 |
| 35971 | GIM_Try, /*On fail goto*//*Label 2016*/ 90377, // Rule ID 823 // |
| 35972 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35973 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlp, |
| 35974 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 35975 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 35976 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 35977 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 35978 | // (intrinsic_wo_chain:{ *:[v2i64] } 427:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (SADDLPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn) |
| 35979 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SADDLPv4i32_v2i64, |
| 35980 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35981 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35982 | GIR_EraseFromParent, /*InsnID*/0, |
| 35983 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 35984 | // GIR_Coverage, 823, |
| 35985 | GIR_Done, |
| 35986 | // Label 2016: @90377 |
| 35987 | GIM_Try, /*On fail goto*//*Label 2017*/ 90417, // Rule ID 829 // |
| 35988 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 35989 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, |
| 35990 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 35991 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 35992 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 35993 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 35994 | // (intrinsic_wo_chain:{ *:[v8i8] } 445:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (SQABSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) |
| 35995 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv8i8, |
| 35996 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 35997 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 35998 | GIR_EraseFromParent, /*InsnID*/0, |
| 35999 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36000 | // GIR_Coverage, 829, |
| 36001 | GIR_Done, |
| 36002 | // Label 2017: @90417 |
| 36003 | GIM_Try, /*On fail goto*//*Label 2018*/ 90457, // Rule ID 830 // |
| 36004 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36005 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, |
| 36006 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 36007 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 36008 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 36009 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36010 | // (intrinsic_wo_chain:{ *:[v16i8] } 445:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (SQABSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) |
| 36011 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv16i8, |
| 36012 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36013 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36014 | GIR_EraseFromParent, /*InsnID*/0, |
| 36015 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36016 | // GIR_Coverage, 830, |
| 36017 | GIR_Done, |
| 36018 | // Label 2018: @90457 |
| 36019 | GIM_Try, /*On fail goto*//*Label 2019*/ 90497, // Rule ID 831 // |
| 36020 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36021 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, |
| 36022 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 36023 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 36024 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 36025 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 36026 | // (intrinsic_wo_chain:{ *:[v4i16] } 445:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (SQABSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) |
| 36027 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv4i16, |
| 36028 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36029 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36030 | GIR_EraseFromParent, /*InsnID*/0, |
| 36031 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36032 | // GIR_Coverage, 831, |
| 36033 | GIR_Done, |
| 36034 | // Label 2019: @90497 |
| 36035 | GIM_Try, /*On fail goto*//*Label 2020*/ 90537, // Rule ID 832 // |
| 36036 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36037 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, |
| 36038 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 36039 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36040 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 36041 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36042 | // (intrinsic_wo_chain:{ *:[v8i16] } 445:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SQABSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) |
| 36043 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv8i16, |
| 36044 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36045 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36046 | GIR_EraseFromParent, /*InsnID*/0, |
| 36047 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36048 | // GIR_Coverage, 832, |
| 36049 | GIR_Done, |
| 36050 | // Label 2020: @90537 |
| 36051 | GIM_Try, /*On fail goto*//*Label 2021*/ 90577, // Rule ID 833 // |
| 36052 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36053 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, |
| 36054 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 36055 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 36056 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 36057 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 36058 | // (intrinsic_wo_chain:{ *:[v2i32] } 445:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (SQABSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) |
| 36059 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv2i32, |
| 36060 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36061 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36062 | GIR_EraseFromParent, /*InsnID*/0, |
| 36063 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36064 | // GIR_Coverage, 833, |
| 36065 | GIR_Done, |
| 36066 | // Label 2021: @90577 |
| 36067 | GIM_Try, /*On fail goto*//*Label 2022*/ 90617, // Rule ID 834 // |
| 36068 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36069 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, |
| 36070 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 36071 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36072 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 36073 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36074 | // (intrinsic_wo_chain:{ *:[v4i32] } 445:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (SQABSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) |
| 36075 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv4i32, |
| 36076 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36077 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36078 | GIR_EraseFromParent, /*InsnID*/0, |
| 36079 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36080 | // GIR_Coverage, 834, |
| 36081 | GIR_Done, |
| 36082 | // Label 2022: @90617 |
| 36083 | GIM_Try, /*On fail goto*//*Label 2023*/ 90657, // Rule ID 835 // |
| 36084 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36085 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, |
| 36086 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 36087 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 36088 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 36089 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36090 | // (intrinsic_wo_chain:{ *:[v2i64] } 445:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (SQABSv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn) |
| 36091 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv2i64, |
| 36092 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36093 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36094 | GIR_EraseFromParent, /*InsnID*/0, |
| 36095 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36096 | // GIR_Coverage, 835, |
| 36097 | GIR_Done, |
| 36098 | // Label 2023: @90657 |
| 36099 | GIM_Try, /*On fail goto*//*Label 2024*/ 90697, // Rule ID 836 // |
| 36100 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36101 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, |
| 36102 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 36103 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 36104 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 36105 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 36106 | // (intrinsic_wo_chain:{ *:[v8i8] } 452:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (SQNEGv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) |
| 36107 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv8i8, |
| 36108 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36109 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36110 | GIR_EraseFromParent, /*InsnID*/0, |
| 36111 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36112 | // GIR_Coverage, 836, |
| 36113 | GIR_Done, |
| 36114 | // Label 2024: @90697 |
| 36115 | GIM_Try, /*On fail goto*//*Label 2025*/ 90737, // Rule ID 837 // |
| 36116 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36117 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, |
| 36118 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 36119 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 36120 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 36121 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36122 | // (intrinsic_wo_chain:{ *:[v16i8] } 452:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (SQNEGv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) |
| 36123 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv16i8, |
| 36124 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36125 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36126 | GIR_EraseFromParent, /*InsnID*/0, |
| 36127 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36128 | // GIR_Coverage, 837, |
| 36129 | GIR_Done, |
| 36130 | // Label 2025: @90737 |
| 36131 | GIM_Try, /*On fail goto*//*Label 2026*/ 90777, // Rule ID 838 // |
| 36132 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36133 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, |
| 36134 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 36135 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 36136 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 36137 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 36138 | // (intrinsic_wo_chain:{ *:[v4i16] } 452:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (SQNEGv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) |
| 36139 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv4i16, |
| 36140 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36141 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36142 | GIR_EraseFromParent, /*InsnID*/0, |
| 36143 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36144 | // GIR_Coverage, 838, |
| 36145 | GIR_Done, |
| 36146 | // Label 2026: @90777 |
| 36147 | GIM_Try, /*On fail goto*//*Label 2027*/ 90817, // Rule ID 839 // |
| 36148 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36149 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, |
| 36150 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 36151 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36152 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 36153 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36154 | // (intrinsic_wo_chain:{ *:[v8i16] } 452:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SQNEGv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) |
| 36155 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv8i16, |
| 36156 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36157 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36158 | GIR_EraseFromParent, /*InsnID*/0, |
| 36159 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36160 | // GIR_Coverage, 839, |
| 36161 | GIR_Done, |
| 36162 | // Label 2027: @90817 |
| 36163 | GIM_Try, /*On fail goto*//*Label 2028*/ 90857, // Rule ID 840 // |
| 36164 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36165 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, |
| 36166 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 36167 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 36168 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 36169 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 36170 | // (intrinsic_wo_chain:{ *:[v2i32] } 452:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (SQNEGv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) |
| 36171 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv2i32, |
| 36172 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36173 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36174 | GIR_EraseFromParent, /*InsnID*/0, |
| 36175 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36176 | // GIR_Coverage, 840, |
| 36177 | GIR_Done, |
| 36178 | // Label 2028: @90857 |
| 36179 | GIM_Try, /*On fail goto*//*Label 2029*/ 90897, // Rule ID 841 // |
| 36180 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36181 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, |
| 36182 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 36183 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36184 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 36185 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36186 | // (intrinsic_wo_chain:{ *:[v4i32] } 452:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (SQNEGv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) |
| 36187 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv4i32, |
| 36188 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36189 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36190 | GIR_EraseFromParent, /*InsnID*/0, |
| 36191 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36192 | // GIR_Coverage, 841, |
| 36193 | GIR_Done, |
| 36194 | // Label 2029: @90897 |
| 36195 | GIM_Try, /*On fail goto*//*Label 2030*/ 90937, // Rule ID 842 // |
| 36196 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36197 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, |
| 36198 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 36199 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 36200 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 36201 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36202 | // (intrinsic_wo_chain:{ *:[v2i64] } 452:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (SQNEGv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn) |
| 36203 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv2i64, |
| 36204 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36205 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36206 | GIR_EraseFromParent, /*InsnID*/0, |
| 36207 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36208 | // GIR_Coverage, 842, |
| 36209 | GIR_Done, |
| 36210 | // Label 2030: @90937 |
| 36211 | GIM_Try, /*On fail goto*//*Label 2031*/ 90977, // Rule ID 843 // |
| 36212 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36213 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqxtn, |
| 36214 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 36215 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36216 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 36217 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36218 | // (intrinsic_wo_chain:{ *:[v8i8] } 464:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SQXTNv8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn) |
| 36219 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv8i8, |
| 36220 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36221 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36222 | GIR_EraseFromParent, /*InsnID*/0, |
| 36223 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36224 | // GIR_Coverage, 843, |
| 36225 | GIR_Done, |
| 36226 | // Label 2031: @90977 |
| 36227 | GIM_Try, /*On fail goto*//*Label 2032*/ 91017, // Rule ID 844 // |
| 36228 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36229 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqxtn, |
| 36230 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 36231 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36232 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 36233 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36234 | // (intrinsic_wo_chain:{ *:[v4i16] } 464:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (SQXTNv4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn) |
| 36235 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv4i16, |
| 36236 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36237 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36238 | GIR_EraseFromParent, /*InsnID*/0, |
| 36239 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36240 | // GIR_Coverage, 844, |
| 36241 | GIR_Done, |
| 36242 | // Label 2032: @91017 |
| 36243 | GIM_Try, /*On fail goto*//*Label 2033*/ 91057, // Rule ID 845 // |
| 36244 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36245 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqxtn, |
| 36246 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 36247 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 36248 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 36249 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36250 | // (intrinsic_wo_chain:{ *:[v2i32] } 464:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (SQXTNv2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn) |
| 36251 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv2i32, |
| 36252 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36253 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36254 | GIR_EraseFromParent, /*InsnID*/0, |
| 36255 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36256 | // GIR_Coverage, 845, |
| 36257 | GIR_Done, |
| 36258 | // Label 2033: @91057 |
| 36259 | GIM_Try, /*On fail goto*//*Label 2034*/ 91097, // Rule ID 846 // |
| 36260 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36261 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqxtun, |
| 36262 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 36263 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36264 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 36265 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36266 | // (intrinsic_wo_chain:{ *:[v8i8] } 465:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SQXTUNv8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn) |
| 36267 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv8i8, |
| 36268 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36269 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36270 | GIR_EraseFromParent, /*InsnID*/0, |
| 36271 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36272 | // GIR_Coverage, 846, |
| 36273 | GIR_Done, |
| 36274 | // Label 2034: @91097 |
| 36275 | GIM_Try, /*On fail goto*//*Label 2035*/ 91137, // Rule ID 847 // |
| 36276 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36277 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqxtun, |
| 36278 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 36279 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36280 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 36281 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36282 | // (intrinsic_wo_chain:{ *:[v4i16] } 465:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (SQXTUNv4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn) |
| 36283 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv4i16, |
| 36284 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36285 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36286 | GIR_EraseFromParent, /*InsnID*/0, |
| 36287 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36288 | // GIR_Coverage, 847, |
| 36289 | GIR_Done, |
| 36290 | // Label 2035: @91137 |
| 36291 | GIM_Try, /*On fail goto*//*Label 2036*/ 91177, // Rule ID 848 // |
| 36292 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36293 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqxtun, |
| 36294 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 36295 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 36296 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 36297 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36298 | // (intrinsic_wo_chain:{ *:[v2i32] } 465:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (SQXTUNv2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn) |
| 36299 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv2i32, |
| 36300 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36301 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36302 | GIR_EraseFromParent, /*InsnID*/0, |
| 36303 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36304 | // GIR_Coverage, 848, |
| 36305 | GIR_Done, |
| 36306 | // Label 2036: @91177 |
| 36307 | GIM_Try, /*On fail goto*//*Label 2037*/ 91217, // Rule ID 862 // |
| 36308 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36309 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, |
| 36310 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 36311 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 36312 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 36313 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 36314 | // (intrinsic_wo_chain:{ *:[v4i16] } 490:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (UADDLPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn) |
| 36315 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv8i8_v4i16, |
| 36316 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36317 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36318 | GIR_EraseFromParent, /*InsnID*/0, |
| 36319 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36320 | // GIR_Coverage, 862, |
| 36321 | GIR_Done, |
| 36322 | // Label 2037: @91217 |
| 36323 | GIM_Try, /*On fail goto*//*Label 2038*/ 91257, // Rule ID 863 // |
| 36324 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36325 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, |
| 36326 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 36327 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 36328 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 36329 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36330 | // (intrinsic_wo_chain:{ *:[v8i16] } 490:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (UADDLPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn) |
| 36331 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv16i8_v8i16, |
| 36332 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36333 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36334 | GIR_EraseFromParent, /*InsnID*/0, |
| 36335 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36336 | // GIR_Coverage, 863, |
| 36337 | GIR_Done, |
| 36338 | // Label 2038: @91257 |
| 36339 | GIM_Try, /*On fail goto*//*Label 2039*/ 91297, // Rule ID 864 // |
| 36340 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36341 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, |
| 36342 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 36343 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 36344 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 36345 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 36346 | // (intrinsic_wo_chain:{ *:[v2i32] } 490:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (UADDLPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn) |
| 36347 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv4i16_v2i32, |
| 36348 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36349 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36350 | GIR_EraseFromParent, /*InsnID*/0, |
| 36351 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36352 | // GIR_Coverage, 864, |
| 36353 | GIR_Done, |
| 36354 | // Label 2039: @91297 |
| 36355 | GIM_Try, /*On fail goto*//*Label 2040*/ 91337, // Rule ID 865 // |
| 36356 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36357 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, |
| 36358 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 36359 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36360 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 36361 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36362 | // (intrinsic_wo_chain:{ *:[v4i32] } 490:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (UADDLPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn) |
| 36363 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv8i16_v4i32, |
| 36364 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36365 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36366 | GIR_EraseFromParent, /*InsnID*/0, |
| 36367 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36368 | // GIR_Coverage, 865, |
| 36369 | GIR_Done, |
| 36370 | // Label 2040: @91337 |
| 36371 | GIM_Try, /*On fail goto*//*Label 2041*/ 91377, // Rule ID 866 // |
| 36372 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36373 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, |
| 36374 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 36375 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 36376 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 36377 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 36378 | // (intrinsic_wo_chain:{ *:[v1i64] } 490:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (UADDLPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn) |
| 36379 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv2i32_v1i64, |
| 36380 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36381 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36382 | GIR_EraseFromParent, /*InsnID*/0, |
| 36383 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36384 | // GIR_Coverage, 866, |
| 36385 | GIR_Done, |
| 36386 | // Label 2041: @91377 |
| 36387 | GIM_Try, /*On fail goto*//*Label 2042*/ 91417, // Rule ID 867 // |
| 36388 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36389 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlp, |
| 36390 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 36391 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36392 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 36393 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36394 | // (intrinsic_wo_chain:{ *:[v2i64] } 490:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (UADDLPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn) |
| 36395 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UADDLPv4i32_v2i64, |
| 36396 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36397 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36398 | GIR_EraseFromParent, /*InsnID*/0, |
| 36399 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36400 | // GIR_Coverage, 867, |
| 36401 | GIR_Done, |
| 36402 | // Label 2042: @91417 |
| 36403 | GIM_Try, /*On fail goto*//*Label 2043*/ 91457, // Rule ID 873 // |
| 36404 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36405 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqxtn, |
| 36406 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 36407 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36408 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 36409 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36410 | // (intrinsic_wo_chain:{ *:[v8i8] } 510:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (UQXTNv8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn) |
| 36411 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv8i8, |
| 36412 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36413 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36414 | GIR_EraseFromParent, /*InsnID*/0, |
| 36415 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36416 | // GIR_Coverage, 873, |
| 36417 | GIR_Done, |
| 36418 | // Label 2043: @91457 |
| 36419 | GIM_Try, /*On fail goto*//*Label 2044*/ 91497, // Rule ID 874 // |
| 36420 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36421 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqxtn, |
| 36422 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 36423 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36424 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 36425 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36426 | // (intrinsic_wo_chain:{ *:[v4i16] } 510:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (UQXTNv4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn) |
| 36427 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv4i16, |
| 36428 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36429 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36430 | GIR_EraseFromParent, /*InsnID*/0, |
| 36431 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36432 | // GIR_Coverage, 874, |
| 36433 | GIR_Done, |
| 36434 | // Label 2044: @91497 |
| 36435 | GIM_Try, /*On fail goto*//*Label 2045*/ 91537, // Rule ID 875 // |
| 36436 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36437 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqxtn, |
| 36438 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 36439 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 36440 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 36441 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36442 | // (intrinsic_wo_chain:{ *:[v2i32] } 510:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (UQXTNv2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn) |
| 36443 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv2i32, |
| 36444 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36445 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36446 | GIR_EraseFromParent, /*InsnID*/0, |
| 36447 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36448 | // GIR_Coverage, 875, |
| 36449 | GIR_Done, |
| 36450 | // Label 2045: @91537 |
| 36451 | GIM_Try, /*On fail goto*//*Label 2046*/ 91577, // Rule ID 876 // |
| 36452 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36453 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urecpe, |
| 36454 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 36455 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 36456 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 36457 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 36458 | // (intrinsic_wo_chain:{ *:[v2i32] } 511:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (URECPEv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) |
| 36459 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URECPEv2i32, |
| 36460 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36461 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36462 | GIR_EraseFromParent, /*InsnID*/0, |
| 36463 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36464 | // GIR_Coverage, 876, |
| 36465 | GIR_Done, |
| 36466 | // Label 2046: @91577 |
| 36467 | GIM_Try, /*On fail goto*//*Label 2047*/ 91617, // Rule ID 877 // |
| 36468 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36469 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urecpe, |
| 36470 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 36471 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36472 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 36473 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36474 | // (intrinsic_wo_chain:{ *:[v4i32] } 511:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (URECPEv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) |
| 36475 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URECPEv4i32, |
| 36476 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36477 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36478 | GIR_EraseFromParent, /*InsnID*/0, |
| 36479 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36480 | // GIR_Coverage, 877, |
| 36481 | GIR_Done, |
| 36482 | // Label 2047: @91617 |
| 36483 | GIM_Try, /*On fail goto*//*Label 2048*/ 91657, // Rule ID 878 // |
| 36484 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36485 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ursqrte, |
| 36486 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 36487 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 36488 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 36489 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 36490 | // (intrinsic_wo_chain:{ *:[v2i32] } 514:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (URSQRTEv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) |
| 36491 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSQRTEv2i32, |
| 36492 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36493 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36494 | GIR_EraseFromParent, /*InsnID*/0, |
| 36495 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36496 | // GIR_Coverage, 878, |
| 36497 | GIR_Done, |
| 36498 | // Label 2048: @91657 |
| 36499 | GIM_Try, /*On fail goto*//*Label 2049*/ 91697, // Rule ID 879 // |
| 36500 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36501 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ursqrte, |
| 36502 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 36503 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36504 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 36505 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36506 | // (intrinsic_wo_chain:{ *:[v4i32] } 514:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (URSQRTEv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) |
| 36507 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSQRTEv4i32, |
| 36508 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36509 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36510 | GIR_EraseFromParent, /*InsnID*/0, |
| 36511 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36512 | // GIR_Coverage, 879, |
| 36513 | GIR_Done, |
| 36514 | // Label 2049: @91697 |
| 36515 | GIM_Try, /*On fail goto*//*Label 2050*/ 91737, // Rule ID 1373 // |
| 36516 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36517 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sisd_fcvtxn, |
| 36518 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 36519 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 36520 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 36521 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 36522 | // (intrinsic_wo_chain:{ *:[f32] } 539:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTXNv1i64:{ *:[f32] } FPR64:{ *:[f64] }:$Rn) |
| 36523 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTXNv1i64, |
| 36524 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36525 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36526 | GIR_EraseFromParent, /*InsnID*/0, |
| 36527 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36528 | // GIR_Coverage, 1373, |
| 36529 | GIR_Done, |
| 36530 | // Label 2050: @91737 |
| 36531 | GIM_Try, /*On fail goto*//*Label 2051*/ 91777, // Rule ID 1378 // |
| 36532 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36533 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, |
| 36534 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 36535 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 36536 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 36537 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 36538 | // (intrinsic_wo_chain:{ *:[i64] } 445:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn) => (SQABSv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn) |
| 36539 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv1i64, |
| 36540 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36541 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36542 | GIR_EraseFromParent, /*InsnID*/0, |
| 36543 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36544 | // GIR_Coverage, 1378, |
| 36545 | GIR_Done, |
| 36546 | // Label 2051: @91777 |
| 36547 | GIM_Try, /*On fail goto*//*Label 2052*/ 91817, // Rule ID 1379 // |
| 36548 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36549 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, |
| 36550 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 36551 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 36552 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 36553 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 36554 | // (intrinsic_wo_chain:{ *:[i32] } 445:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn) => (SQABSv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn) |
| 36555 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv1i32, |
| 36556 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36557 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36558 | GIR_EraseFromParent, /*InsnID*/0, |
| 36559 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36560 | // GIR_Coverage, 1379, |
| 36561 | GIR_Done, |
| 36562 | // Label 2052: @91817 |
| 36563 | GIM_Try, /*On fail goto*//*Label 2053*/ 91857, // Rule ID 1380 // |
| 36564 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36565 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, |
| 36566 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 36567 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 36568 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 36569 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 36570 | // (intrinsic_wo_chain:{ *:[i64] } 452:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn) => (SQNEGv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn) |
| 36571 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv1i64, |
| 36572 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36573 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36574 | GIR_EraseFromParent, /*InsnID*/0, |
| 36575 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36576 | // GIR_Coverage, 1380, |
| 36577 | GIR_Done, |
| 36578 | // Label 2053: @91857 |
| 36579 | GIM_Try, /*On fail goto*//*Label 2054*/ 91897, // Rule ID 1381 // |
| 36580 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36581 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, |
| 36582 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 36583 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 36584 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 36585 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 36586 | // (intrinsic_wo_chain:{ *:[i32] } 452:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn) => (SQNEGv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn) |
| 36587 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv1i32, |
| 36588 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36589 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36590 | GIR_EraseFromParent, /*InsnID*/0, |
| 36591 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36592 | // GIR_Coverage, 1381, |
| 36593 | GIR_Done, |
| 36594 | // Label 2054: @91897 |
| 36595 | GIM_Try, /*On fail goto*//*Label 2055*/ 91937, // Rule ID 1382 // |
| 36596 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36597 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_scalar_sqxtn, |
| 36598 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 36599 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 36600 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 36601 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 36602 | // (intrinsic_wo_chain:{ *:[i32] } 430:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn) => (SQXTNv1i32:{ *:[i32] } FPR64:{ *:[i64] }:$Rn) |
| 36603 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTNv1i32, |
| 36604 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36605 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36606 | GIR_EraseFromParent, /*InsnID*/0, |
| 36607 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36608 | // GIR_Coverage, 1382, |
| 36609 | GIR_Done, |
| 36610 | // Label 2055: @91937 |
| 36611 | GIM_Try, /*On fail goto*//*Label 2056*/ 91977, // Rule ID 1383 // |
| 36612 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36613 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_scalar_sqxtun, |
| 36614 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 36615 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 36616 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 36617 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 36618 | // (intrinsic_wo_chain:{ *:[i32] } 431:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn) => (SQXTUNv1i32:{ *:[i32] } FPR64:{ *:[i64] }:$Rn) |
| 36619 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQXTUNv1i32, |
| 36620 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36621 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36622 | GIR_EraseFromParent, /*InsnID*/0, |
| 36623 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36624 | // GIR_Coverage, 1383, |
| 36625 | GIR_Done, |
| 36626 | // Label 2056: @91977 |
| 36627 | GIM_Try, /*On fail goto*//*Label 2057*/ 92017, // Rule ID 1389 // |
| 36628 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36629 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_scalar_uqxtn, |
| 36630 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 36631 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 36632 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 36633 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 36634 | // (intrinsic_wo_chain:{ *:[i32] } 432:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn) => (UQXTNv1i32:{ *:[i32] } FPR64:{ *:[i64] }:$Rn) |
| 36635 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQXTNv1i32, |
| 36636 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36637 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36638 | GIR_EraseFromParent, /*InsnID*/0, |
| 36639 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36640 | // GIR_Coverage, 1389, |
| 36641 | GIR_Done, |
| 36642 | // Label 2057: @92017 |
| 36643 | GIM_Try, /*On fail goto*//*Label 2058*/ 92057, // Rule ID 1655 // |
| 36644 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 36645 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmv, |
| 36646 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, |
| 36647 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 36648 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 36649 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 36650 | // (intrinsic_wo_chain:{ *:[f16] } 387:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FMAXNMVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn) |
| 36651 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMVv4i16v, |
| 36652 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36653 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36654 | GIR_EraseFromParent, /*InsnID*/0, |
| 36655 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36656 | // GIR_Coverage, 1655, |
| 36657 | GIR_Done, |
| 36658 | // Label 2058: @92057 |
| 36659 | GIM_Try, /*On fail goto*//*Label 2059*/ 92097, // Rule ID 1656 // |
| 36660 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 36661 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmv, |
| 36662 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, |
| 36663 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36664 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 36665 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36666 | // (intrinsic_wo_chain:{ *:[f16] } 387:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FMAXNMVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn) |
| 36667 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMVv8i16v, |
| 36668 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36669 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36670 | GIR_EraseFromParent, /*InsnID*/0, |
| 36671 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36672 | // GIR_Coverage, 1656, |
| 36673 | GIR_Done, |
| 36674 | // Label 2059: @92097 |
| 36675 | GIM_Try, /*On fail goto*//*Label 2060*/ 92137, // Rule ID 1657 // |
| 36676 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36677 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmv, |
| 36678 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 36679 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36680 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 36681 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36682 | // (intrinsic_wo_chain:{ *:[f32] } 387:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FMAXNMVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn) |
| 36683 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMVv4i32v, |
| 36684 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36685 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36686 | GIR_EraseFromParent, /*InsnID*/0, |
| 36687 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36688 | // GIR_Coverage, 1657, |
| 36689 | GIR_Done, |
| 36690 | // Label 2060: @92137 |
| 36691 | GIM_Try, /*On fail goto*//*Label 2061*/ 92177, // Rule ID 1658 // |
| 36692 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 36693 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxv, |
| 36694 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, |
| 36695 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 36696 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 36697 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 36698 | // (intrinsic_wo_chain:{ *:[f16] } 389:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FMAXVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn) |
| 36699 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXVv4i16v, |
| 36700 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36701 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36702 | GIR_EraseFromParent, /*InsnID*/0, |
| 36703 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36704 | // GIR_Coverage, 1658, |
| 36705 | GIR_Done, |
| 36706 | // Label 2061: @92177 |
| 36707 | GIM_Try, /*On fail goto*//*Label 2062*/ 92217, // Rule ID 1659 // |
| 36708 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 36709 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxv, |
| 36710 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, |
| 36711 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36712 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 36713 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36714 | // (intrinsic_wo_chain:{ *:[f16] } 389:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FMAXVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn) |
| 36715 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXVv8i16v, |
| 36716 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36717 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36718 | GIR_EraseFromParent, /*InsnID*/0, |
| 36719 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36720 | // GIR_Coverage, 1659, |
| 36721 | GIR_Done, |
| 36722 | // Label 2062: @92217 |
| 36723 | GIM_Try, /*On fail goto*//*Label 2063*/ 92257, // Rule ID 1660 // |
| 36724 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36725 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxv, |
| 36726 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 36727 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36728 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 36729 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36730 | // (intrinsic_wo_chain:{ *:[f32] } 389:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FMAXVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn) |
| 36731 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXVv4i32v, |
| 36732 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36733 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36734 | GIR_EraseFromParent, /*InsnID*/0, |
| 36735 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36736 | // GIR_Coverage, 1660, |
| 36737 | GIR_Done, |
| 36738 | // Label 2063: @92257 |
| 36739 | GIM_Try, /*On fail goto*//*Label 2064*/ 92297, // Rule ID 1661 // |
| 36740 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 36741 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmv, |
| 36742 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, |
| 36743 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 36744 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 36745 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 36746 | // (intrinsic_wo_chain:{ *:[f16] } 393:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FMINNMVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn) |
| 36747 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMVv4i16v, |
| 36748 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36749 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36750 | GIR_EraseFromParent, /*InsnID*/0, |
| 36751 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36752 | // GIR_Coverage, 1661, |
| 36753 | GIR_Done, |
| 36754 | // Label 2064: @92297 |
| 36755 | GIM_Try, /*On fail goto*//*Label 2065*/ 92337, // Rule ID 1662 // |
| 36756 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 36757 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmv, |
| 36758 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, |
| 36759 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36760 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 36761 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36762 | // (intrinsic_wo_chain:{ *:[f16] } 393:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FMINNMVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn) |
| 36763 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMVv8i16v, |
| 36764 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36765 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36766 | GIR_EraseFromParent, /*InsnID*/0, |
| 36767 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36768 | // GIR_Coverage, 1662, |
| 36769 | GIR_Done, |
| 36770 | // Label 2065: @92337 |
| 36771 | GIM_Try, /*On fail goto*//*Label 2066*/ 92377, // Rule ID 1663 // |
| 36772 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36773 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmv, |
| 36774 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 36775 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36776 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 36777 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36778 | // (intrinsic_wo_chain:{ *:[f32] } 393:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FMINNMVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn) |
| 36779 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMVv4i32v, |
| 36780 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36781 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36782 | GIR_EraseFromParent, /*InsnID*/0, |
| 36783 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36784 | // GIR_Coverage, 1663, |
| 36785 | GIR_Done, |
| 36786 | // Label 2066: @92377 |
| 36787 | GIM_Try, /*On fail goto*//*Label 2067*/ 92417, // Rule ID 1664 // |
| 36788 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 36789 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminv, |
| 36790 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, |
| 36791 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 36792 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 36793 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 36794 | // (intrinsic_wo_chain:{ *:[f16] } 395:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FMINVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn) |
| 36795 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINVv4i16v, |
| 36796 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36797 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36798 | GIR_EraseFromParent, /*InsnID*/0, |
| 36799 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36800 | // GIR_Coverage, 1664, |
| 36801 | GIR_Done, |
| 36802 | // Label 2067: @92417 |
| 36803 | GIM_Try, /*On fail goto*//*Label 2068*/ 92457, // Rule ID 1665 // |
| 36804 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 36805 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminv, |
| 36806 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, |
| 36807 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36808 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 36809 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36810 | // (intrinsic_wo_chain:{ *:[f16] } 395:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FMINVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn) |
| 36811 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINVv8i16v, |
| 36812 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36813 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36814 | GIR_EraseFromParent, /*InsnID*/0, |
| 36815 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36816 | // GIR_Coverage, 1665, |
| 36817 | GIR_Done, |
| 36818 | // Label 2068: @92457 |
| 36819 | GIM_Try, /*On fail goto*//*Label 2069*/ 92497, // Rule ID 1666 // |
| 36820 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36821 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminv, |
| 36822 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 36823 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36824 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 36825 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36826 | // (intrinsic_wo_chain:{ *:[f32] } 395:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FMINVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn) |
| 36827 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINVv4i32v, |
| 36828 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36829 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36830 | GIR_EraseFromParent, /*InsnID*/0, |
| 36831 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36832 | // GIR_Coverage, 1666, |
| 36833 | GIR_Done, |
| 36834 | // Label 2069: @92497 |
| 36835 | GIM_Try, /*On fail goto*//*Label 2070*/ 92537, // Rule ID 1943 // |
| 36836 | GIM_CheckFeatures, GIFBS_HasAES, |
| 36837 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aesmc, |
| 36838 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 36839 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 36840 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 36841 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36842 | // (intrinsic_wo_chain:{ *:[v16i8] } 331:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (AESMCrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) |
| 36843 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESMCrr, |
| 36844 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36845 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36846 | GIR_EraseFromParent, /*InsnID*/0, |
| 36847 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36848 | // GIR_Coverage, 1943, |
| 36849 | GIR_Done, |
| 36850 | // Label 2070: @92537 |
| 36851 | GIM_Try, /*On fail goto*//*Label 2071*/ 92577, // Rule ID 1944 // |
| 36852 | GIM_CheckFeatures, GIFBS_HasAES, |
| 36853 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aesimc, |
| 36854 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 36855 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 36856 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 36857 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36858 | // (intrinsic_wo_chain:{ *:[v16i8] } 330:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (AESIMCrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) |
| 36859 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESIMCrr, |
| 36860 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36861 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36862 | GIR_EraseFromParent, /*InsnID*/0, |
| 36863 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36864 | // GIR_Coverage, 1944, |
| 36865 | GIR_Done, |
| 36866 | // Label 2071: @92577 |
| 36867 | GIM_Try, /*On fail goto*//*Label 2072*/ 92617, // Rule ID 1952 // |
| 36868 | GIM_CheckFeatures, GIFBS_HasSHA2, |
| 36869 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha1h, |
| 36870 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 36871 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 36872 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 36873 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 36874 | // (intrinsic_wo_chain:{ *:[i32] } 333:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn) => (SHA1Hrr:{ *:[i32] } FPR32:{ *:[i32] }:$Rn) |
| 36875 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1Hrr, |
| 36876 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36877 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36878 | GIR_EraseFromParent, /*InsnID*/0, |
| 36879 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36880 | // GIR_Coverage, 1952, |
| 36881 | GIR_Done, |
| 36882 | // Label 2072: @92617 |
| 36883 | GIM_Try, /*On fail goto*//*Label 2073*/ 92657, // Rule ID 2710 // |
| 36884 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36885 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqabs, |
| 36886 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 36887 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 36888 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 36889 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 36890 | // (intrinsic_wo_chain:{ *:[v1i64] } 445:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn) => (SQABSv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn) |
| 36891 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQABSv1i64, |
| 36892 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36893 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36894 | GIR_EraseFromParent, /*InsnID*/0, |
| 36895 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36896 | // GIR_Coverage, 2710, |
| 36897 | GIR_Done, |
| 36898 | // Label 2073: @92657 |
| 36899 | GIM_Try, /*On fail goto*//*Label 2074*/ 92695, // Rule ID 3538 // |
| 36900 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_cls, |
| 36901 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 36902 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 36903 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 36904 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 36905 | // (intrinsic_wo_chain:{ *:[i32] } 318:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn) => (CLSWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) |
| 36906 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSWr, |
| 36907 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36908 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36909 | GIR_EraseFromParent, /*InsnID*/0, |
| 36910 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36911 | // GIR_Coverage, 3538, |
| 36912 | GIR_Done, |
| 36913 | // Label 2074: @92695 |
| 36914 | GIM_Try, /*On fail goto*//*Label 2075*/ 92756, // Rule ID 3539 // |
| 36915 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_cls64, |
| 36916 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 36917 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 36918 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 36919 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 36920 | // (intrinsic_wo_chain:{ *:[i32] } 319:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rm) => (EXTRACT_SUBREG:{ *:[i32] } (CLSXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rm), sub_32:{ *:[i32] }) |
| 36921 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 36922 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::CLSXr, |
| 36923 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 36924 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 36925 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 36926 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 36927 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 36928 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::sub_32, |
| 36929 | GIR_EraseFromParent, /*InsnID*/0, |
| 36930 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR32RegClassID, |
| 36931 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::GPR64RegClassID, |
| 36932 | // GIR_Coverage, 3539, |
| 36933 | GIR_Done, |
| 36934 | // Label 2075: @92756 |
| 36935 | GIM_Try, /*On fail goto*//*Label 2076*/ 92794, // Rule ID 3944 // |
| 36936 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frintn, |
| 36937 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 36938 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 36939 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 36940 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 36941 | // (intrinsic_wo_chain:{ *:[v1f64] } 404:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FRINTNDr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn) |
| 36942 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRINTNDr, |
| 36943 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36944 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36945 | GIR_EraseFromParent, /*InsnID*/0, |
| 36946 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36947 | // GIR_Coverage, 3944, |
| 36948 | GIR_Done, |
| 36949 | // Label 2076: @92794 |
| 36950 | GIM_Try, /*On fail goto*//*Label 2077*/ 92832, // Rule ID 3972 // |
| 36951 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvthf2fp, |
| 36952 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 36953 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 36954 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 36955 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 36956 | // (intrinsic_wo_chain:{ *:[v4f32] } 532:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (FCVTLv4i16:{ *:[v4f32] } V64:{ *:[v4i16] }:$Rn) |
| 36957 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTLv4i16, |
| 36958 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36959 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36960 | GIR_EraseFromParent, /*InsnID*/0, |
| 36961 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36962 | // GIR_Coverage, 3972, |
| 36963 | GIR_Done, |
| 36964 | // Label 2077: @92832 |
| 36965 | GIM_Try, /*On fail goto*//*Label 2078*/ 92870, // Rule ID 3976 // |
| 36966 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2hf, |
| 36967 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 36968 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36969 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 36970 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 36971 | // (intrinsic_wo_chain:{ *:[v4i16] } 529:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTNv4i16:{ *:[v4i16] } V128:{ *:[v4f32] }:$Rn) |
| 36972 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNv4i16, |
| 36973 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36974 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36975 | GIR_EraseFromParent, /*InsnID*/0, |
| 36976 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36977 | // GIR_Coverage, 3976, |
| 36978 | GIR_Done, |
| 36979 | // Label 2078: @92870 |
| 36980 | GIM_Try, /*On fail goto*//*Label 2079*/ 92910, // Rule ID 4143 // |
| 36981 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 36982 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqneg, |
| 36983 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 36984 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 36985 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 36986 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 36987 | // (intrinsic_wo_chain:{ *:[v1i64] } 452:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn) => (SQNEGv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn) |
| 36988 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQNEGv1i64, |
| 36989 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 36990 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 36991 | GIR_EraseFromParent, /*InsnID*/0, |
| 36992 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 36993 | // GIR_Coverage, 4143, |
| 36994 | GIR_Done, |
| 36995 | // Label 2079: @92910 |
| 36996 | GIM_Try, /*On fail goto*//*Label 2080*/ 92948, // Rule ID 4146 // |
| 36997 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtas, |
| 36998 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 36999 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 37000 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 37001 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37002 | // (intrinsic_wo_chain:{ *:[v1i64] } 373:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTASv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) |
| 37003 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASv1i64, |
| 37004 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37005 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37006 | GIR_EraseFromParent, /*InsnID*/0, |
| 37007 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37008 | // GIR_Coverage, 4146, |
| 37009 | GIR_Done, |
| 37010 | // Label 2080: @92948 |
| 37011 | GIM_Try, /*On fail goto*//*Label 2081*/ 92986, // Rule ID 4147 // |
| 37012 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtau, |
| 37013 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 37014 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 37015 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 37016 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37017 | // (intrinsic_wo_chain:{ *:[v1i64] } 374:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTAUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) |
| 37018 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUv1i64, |
| 37019 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37020 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37021 | GIR_EraseFromParent, /*InsnID*/0, |
| 37022 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37023 | // GIR_Coverage, 4147, |
| 37024 | GIR_Done, |
| 37025 | // Label 2081: @92986 |
| 37026 | GIM_Try, /*On fail goto*//*Label 2082*/ 93024, // Rule ID 4148 // |
| 37027 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtms, |
| 37028 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 37029 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 37030 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 37031 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37032 | // (intrinsic_wo_chain:{ *:[v1i64] } 375:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTMSv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) |
| 37033 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSv1i64, |
| 37034 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37035 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37036 | GIR_EraseFromParent, /*InsnID*/0, |
| 37037 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37038 | // GIR_Coverage, 4148, |
| 37039 | GIR_Done, |
| 37040 | // Label 2082: @93024 |
| 37041 | GIM_Try, /*On fail goto*//*Label 2083*/ 93062, // Rule ID 4149 // |
| 37042 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtmu, |
| 37043 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 37044 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 37045 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 37046 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37047 | // (intrinsic_wo_chain:{ *:[v1i64] } 376:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTMUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) |
| 37048 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUv1i64, |
| 37049 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37050 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37051 | GIR_EraseFromParent, /*InsnID*/0, |
| 37052 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37053 | // GIR_Coverage, 4149, |
| 37054 | GIR_Done, |
| 37055 | // Label 2083: @93062 |
| 37056 | GIM_Try, /*On fail goto*//*Label 2084*/ 93100, // Rule ID 4150 // |
| 37057 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtns, |
| 37058 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 37059 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 37060 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 37061 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37062 | // (intrinsic_wo_chain:{ *:[v1i64] } 377:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTNSv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) |
| 37063 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNSv1i64, |
| 37064 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37065 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37066 | GIR_EraseFromParent, /*InsnID*/0, |
| 37067 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37068 | // GIR_Coverage, 4150, |
| 37069 | GIR_Done, |
| 37070 | // Label 2084: @93100 |
| 37071 | GIM_Try, /*On fail goto*//*Label 2085*/ 93138, // Rule ID 4151 // |
| 37072 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtnu, |
| 37073 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 37074 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 37075 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 37076 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37077 | // (intrinsic_wo_chain:{ *:[v1i64] } 378:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTNUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) |
| 37078 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTNUv1i64, |
| 37079 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37080 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37081 | GIR_EraseFromParent, /*InsnID*/0, |
| 37082 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37083 | // GIR_Coverage, 4151, |
| 37084 | GIR_Done, |
| 37085 | // Label 2085: @93138 |
| 37086 | GIM_Try, /*On fail goto*//*Label 2086*/ 93176, // Rule ID 4152 // |
| 37087 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtps, |
| 37088 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 37089 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 37090 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 37091 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37092 | // (intrinsic_wo_chain:{ *:[v1i64] } 379:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTPSv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) |
| 37093 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSv1i64, |
| 37094 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37095 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37096 | GIR_EraseFromParent, /*InsnID*/0, |
| 37097 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37098 | // GIR_Coverage, 4152, |
| 37099 | GIR_Done, |
| 37100 | // Label 2086: @93176 |
| 37101 | GIM_Try, /*On fail goto*//*Label 2087*/ 93214, // Rule ID 4153 // |
| 37102 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtpu, |
| 37103 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 37104 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 37105 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 37106 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37107 | // (intrinsic_wo_chain:{ *:[v1i64] } 380:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTPUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) |
| 37108 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUv1i64, |
| 37109 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37110 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37111 | GIR_EraseFromParent, /*InsnID*/0, |
| 37112 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37113 | // GIR_Coverage, 4153, |
| 37114 | GIR_Done, |
| 37115 | // Label 2087: @93214 |
| 37116 | GIM_Try, /*On fail goto*//*Label 2088*/ 93252, // Rule ID 4154 // |
| 37117 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtzs, |
| 37118 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 37119 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 37120 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 37121 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37122 | // (intrinsic_wo_chain:{ *:[v1i64] } 382:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTZSv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) |
| 37123 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv1i64, |
| 37124 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37125 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37126 | GIR_EraseFromParent, /*InsnID*/0, |
| 37127 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37128 | // GIR_Coverage, 4154, |
| 37129 | GIR_Done, |
| 37130 | // Label 2088: @93252 |
| 37131 | GIM_Try, /*On fail goto*//*Label 2089*/ 93290, // Rule ID 4155 // |
| 37132 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fcvtzu, |
| 37133 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 37134 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 37135 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 37136 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37137 | // (intrinsic_wo_chain:{ *:[v1i64] } 383:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTZUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) |
| 37138 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv1i64, |
| 37139 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37140 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37141 | GIR_EraseFromParent, /*InsnID*/0, |
| 37142 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37143 | // GIR_Coverage, 4155, |
| 37144 | GIR_Done, |
| 37145 | // Label 2089: @93290 |
| 37146 | GIM_Try, /*On fail goto*//*Label 2090*/ 93328, // Rule ID 4156 // |
| 37147 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, |
| 37148 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, |
| 37149 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 37150 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 37151 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 37152 | // (intrinsic_wo_chain:{ *:[f16] } 401:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FRECPEv1f16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) |
| 37153 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv1f16, |
| 37154 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37155 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37156 | GIR_EraseFromParent, /*InsnID*/0, |
| 37157 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37158 | // GIR_Coverage, 4156, |
| 37159 | GIR_Done, |
| 37160 | // Label 2090: @93328 |
| 37161 | GIM_Try, /*On fail goto*//*Label 2091*/ 93366, // Rule ID 4157 // |
| 37162 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, |
| 37163 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 37164 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 37165 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 37166 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 37167 | // (intrinsic_wo_chain:{ *:[f32] } 401:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FRECPEv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) |
| 37168 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv1i32, |
| 37169 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37170 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37171 | GIR_EraseFromParent, /*InsnID*/0, |
| 37172 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37173 | // GIR_Coverage, 4157, |
| 37174 | GIR_Done, |
| 37175 | // Label 2091: @93366 |
| 37176 | GIM_Try, /*On fail goto*//*Label 2092*/ 93404, // Rule ID 4158 // |
| 37177 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, |
| 37178 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 37179 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 37180 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 37181 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37182 | // (intrinsic_wo_chain:{ *:[f64] } 401:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FRECPEv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) |
| 37183 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv1i64, |
| 37184 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37185 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37186 | GIR_EraseFromParent, /*InsnID*/0, |
| 37187 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37188 | // GIR_Coverage, 4158, |
| 37189 | GIR_Done, |
| 37190 | // Label 2092: @93404 |
| 37191 | GIM_Try, /*On fail goto*//*Label 2093*/ 93442, // Rule ID 4159 // |
| 37192 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpe, |
| 37193 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 37194 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 37195 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 37196 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37197 | // (intrinsic_wo_chain:{ *:[v1f64] } 401:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FRECPEv1i64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn) |
| 37198 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPEv1i64, |
| 37199 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37200 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37201 | GIR_EraseFromParent, /*InsnID*/0, |
| 37202 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37203 | // GIR_Coverage, 4159, |
| 37204 | GIR_Done, |
| 37205 | // Label 2093: @93442 |
| 37206 | GIM_Try, /*On fail goto*//*Label 2094*/ 93480, // Rule ID 4171 // |
| 37207 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpx, |
| 37208 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, |
| 37209 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 37210 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 37211 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 37212 | // (intrinsic_wo_chain:{ *:[f16] } 403:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FRECPXv1f16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) |
| 37213 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPXv1f16, |
| 37214 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37215 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37216 | GIR_EraseFromParent, /*InsnID*/0, |
| 37217 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37218 | // GIR_Coverage, 4171, |
| 37219 | GIR_Done, |
| 37220 | // Label 2094: @93480 |
| 37221 | GIM_Try, /*On fail goto*//*Label 2095*/ 93518, // Rule ID 4172 // |
| 37222 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpx, |
| 37223 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 37224 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 37225 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 37226 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 37227 | // (intrinsic_wo_chain:{ *:[f32] } 403:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FRECPXv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) |
| 37228 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPXv1i32, |
| 37229 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37230 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37231 | GIR_EraseFromParent, /*InsnID*/0, |
| 37232 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37233 | // GIR_Coverage, 4172, |
| 37234 | GIR_Done, |
| 37235 | // Label 2095: @93518 |
| 37236 | GIM_Try, /*On fail goto*//*Label 2096*/ 93556, // Rule ID 4173 // |
| 37237 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecpx, |
| 37238 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 37239 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 37240 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 37241 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37242 | // (intrinsic_wo_chain:{ *:[f64] } 403:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FRECPXv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) |
| 37243 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPXv1i64, |
| 37244 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37245 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37246 | GIR_EraseFromParent, /*InsnID*/0, |
| 37247 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37248 | // GIR_Coverage, 4173, |
| 37249 | GIR_Done, |
| 37250 | // Label 2096: @93556 |
| 37251 | GIM_Try, /*On fail goto*//*Label 2097*/ 93594, // Rule ID 4174 // |
| 37252 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, |
| 37253 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, |
| 37254 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 37255 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 37256 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 37257 | // (intrinsic_wo_chain:{ *:[f16] } 405:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FRSQRTEv1f16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) |
| 37258 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv1f16, |
| 37259 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37260 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37261 | GIR_EraseFromParent, /*InsnID*/0, |
| 37262 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37263 | // GIR_Coverage, 4174, |
| 37264 | GIR_Done, |
| 37265 | // Label 2097: @93594 |
| 37266 | GIM_Try, /*On fail goto*//*Label 2098*/ 93632, // Rule ID 4175 // |
| 37267 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, |
| 37268 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 37269 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 37270 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 37271 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 37272 | // (intrinsic_wo_chain:{ *:[f32] } 405:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FRSQRTEv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) |
| 37273 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv1i32, |
| 37274 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37275 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37276 | GIR_EraseFromParent, /*InsnID*/0, |
| 37277 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37278 | // GIR_Coverage, 4175, |
| 37279 | GIR_Done, |
| 37280 | // Label 2098: @93632 |
| 37281 | GIM_Try, /*On fail goto*//*Label 2099*/ 93670, // Rule ID 4176 // |
| 37282 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, |
| 37283 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 37284 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 37285 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 37286 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37287 | // (intrinsic_wo_chain:{ *:[f64] } 405:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FRSQRTEv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) |
| 37288 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv1i64, |
| 37289 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37290 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37291 | GIR_EraseFromParent, /*InsnID*/0, |
| 37292 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37293 | // GIR_Coverage, 4176, |
| 37294 | GIR_Done, |
| 37295 | // Label 2099: @93670 |
| 37296 | GIM_Try, /*On fail goto*//*Label 2100*/ 93708, // Rule ID 4177 // |
| 37297 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrte, |
| 37298 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 37299 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 37300 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 37301 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37302 | // (intrinsic_wo_chain:{ *:[v1f64] } 405:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FRSQRTEv1i64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn) |
| 37303 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTEv1i64, |
| 37304 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37305 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37306 | GIR_EraseFromParent, /*InsnID*/0, |
| 37307 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37308 | // GIR_Coverage, 4177, |
| 37309 | GIR_Done, |
| 37310 | // Label 2100: @93708 |
| 37311 | GIM_Try, /*On fail goto*//*Label 2101*/ 93746, // Rule ID 4344 // |
| 37312 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_faddv, |
| 37313 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 37314 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 37315 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 37316 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37317 | // (intrinsic_wo_chain:{ *:[f32] } 372:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FADDPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn) |
| 37318 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i32p, |
| 37319 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37320 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37321 | GIR_EraseFromParent, /*InsnID*/0, |
| 37322 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37323 | // GIR_Coverage, 4344, |
| 37324 | GIR_Done, |
| 37325 | // Label 2101: @93746 |
| 37326 | GIM_Try, /*On fail goto*//*Label 2102*/ 93827, // Rule ID 4345 // |
| 37327 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_faddv, |
| 37328 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 37329 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 37330 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 37331 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 37332 | // (intrinsic_wo_chain:{ *:[f32] } 372:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } (FADDPv4f32:{ *:[f128] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rn), dsub:{ *:[i32] })) |
| 37333 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 37334 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 37335 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::FADDPv4f32, |
| 37336 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 37337 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37338 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37339 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 37340 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 37341 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 37342 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, AArch64::dsub, |
| 37343 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, |
| 37344 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 37345 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i32p, |
| 37346 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37347 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 37348 | GIR_EraseFromParent, /*InsnID*/0, |
| 37349 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37350 | // GIR_Coverage, 4345, |
| 37351 | GIR_Done, |
| 37352 | // Label 2102: @93827 |
| 37353 | GIM_Try, /*On fail goto*//*Label 2103*/ 93865, // Rule ID 4346 // |
| 37354 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_faddv, |
| 37355 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 37356 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 37357 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 37358 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 37359 | // (intrinsic_wo_chain:{ *:[f64] } 372:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FADDPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn) |
| 37360 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i64p, |
| 37361 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37362 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37363 | GIR_EraseFromParent, /*InsnID*/0, |
| 37364 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37365 | // GIR_Coverage, 4346, |
| 37366 | GIR_Done, |
| 37367 | // Label 2103: @93865 |
| 37368 | GIM_Try, /*On fail goto*//*Label 2104*/ 93903, // Rule ID 4347 // |
| 37369 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmv, |
| 37370 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 37371 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 37372 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 37373 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37374 | // (intrinsic_wo_chain:{ *:[f32] } 387:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FMAXNMPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn) |
| 37375 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv2i32p, |
| 37376 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37377 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37378 | GIR_EraseFromParent, /*InsnID*/0, |
| 37379 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37380 | // GIR_Coverage, 4347, |
| 37381 | GIR_Done, |
| 37382 | // Label 2104: @93903 |
| 37383 | GIM_Try, /*On fail goto*//*Label 2105*/ 93941, // Rule ID 4348 // |
| 37384 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmv, |
| 37385 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 37386 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 37387 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 37388 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 37389 | // (intrinsic_wo_chain:{ *:[f64] } 387:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FMAXNMPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn) |
| 37390 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv2i64p, |
| 37391 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37392 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37393 | GIR_EraseFromParent, /*InsnID*/0, |
| 37394 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37395 | // GIR_Coverage, 4348, |
| 37396 | GIR_Done, |
| 37397 | // Label 2105: @93941 |
| 37398 | GIM_Try, /*On fail goto*//*Label 2106*/ 93979, // Rule ID 4349 // |
| 37399 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxv, |
| 37400 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 37401 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 37402 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 37403 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37404 | // (intrinsic_wo_chain:{ *:[f32] } 389:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FMAXPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn) |
| 37405 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv2i32p, |
| 37406 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37407 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37408 | GIR_EraseFromParent, /*InsnID*/0, |
| 37409 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37410 | // GIR_Coverage, 4349, |
| 37411 | GIR_Done, |
| 37412 | // Label 2106: @93979 |
| 37413 | GIM_Try, /*On fail goto*//*Label 2107*/ 94017, // Rule ID 4350 // |
| 37414 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxv, |
| 37415 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 37416 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 37417 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 37418 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 37419 | // (intrinsic_wo_chain:{ *:[f64] } 389:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FMAXPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn) |
| 37420 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv2i64p, |
| 37421 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37422 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37423 | GIR_EraseFromParent, /*InsnID*/0, |
| 37424 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37425 | // GIR_Coverage, 4350, |
| 37426 | GIR_Done, |
| 37427 | // Label 2107: @94017 |
| 37428 | GIM_Try, /*On fail goto*//*Label 2108*/ 94055, // Rule ID 4351 // |
| 37429 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmv, |
| 37430 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 37431 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 37432 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 37433 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37434 | // (intrinsic_wo_chain:{ *:[f32] } 393:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FMINNMPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn) |
| 37435 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv2i32p, |
| 37436 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37437 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37438 | GIR_EraseFromParent, /*InsnID*/0, |
| 37439 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37440 | // GIR_Coverage, 4351, |
| 37441 | GIR_Done, |
| 37442 | // Label 2108: @94055 |
| 37443 | GIM_Try, /*On fail goto*//*Label 2109*/ 94093, // Rule ID 4352 // |
| 37444 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmv, |
| 37445 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 37446 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 37447 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 37448 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 37449 | // (intrinsic_wo_chain:{ *:[f64] } 393:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FMINNMPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn) |
| 37450 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv2i64p, |
| 37451 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37452 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37453 | GIR_EraseFromParent, /*InsnID*/0, |
| 37454 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37455 | // GIR_Coverage, 4352, |
| 37456 | GIR_Done, |
| 37457 | // Label 2109: @94093 |
| 37458 | GIM_Try, /*On fail goto*//*Label 2110*/ 94131, // Rule ID 4353 // |
| 37459 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminv, |
| 37460 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 37461 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 37462 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 37463 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37464 | // (intrinsic_wo_chain:{ *:[f32] } 395:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FMINPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn) |
| 37465 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv2i32p, |
| 37466 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37467 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37468 | GIR_EraseFromParent, /*InsnID*/0, |
| 37469 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37470 | // GIR_Coverage, 4353, |
| 37471 | GIR_Done, |
| 37472 | // Label 2110: @94131 |
| 37473 | GIM_Try, /*On fail goto*//*Label 2111*/ 94169, // Rule ID 4354 // |
| 37474 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminv, |
| 37475 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 37476 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 37477 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 37478 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 37479 | // (intrinsic_wo_chain:{ *:[f64] } 395:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FMINPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn) |
| 37480 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv2i64p, |
| 37481 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37482 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37483 | GIR_EraseFromParent, /*InsnID*/0, |
| 37484 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37485 | // GIR_Coverage, 4354, |
| 37486 | GIR_Done, |
| 37487 | // Label 2111: @94169 |
| 37488 | GIM_Try, /*On fail goto*//*Label 2112*/ 94271, // Rule ID 4565 // |
| 37489 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlv, |
| 37490 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 37491 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 37492 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 37493 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37494 | // (intrinsic_wo_chain:{ *:[i32] } 428:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (SMOVvi16to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SADDLVv8i8v:{ *:[bf16] } V64:{ *:[v8i8] }:$Rn), hsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 37495 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 37496 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 37497 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 37498 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::SADDLVv8i8v, |
| 37499 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 37500 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37501 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 37502 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 37503 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 37504 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 37505 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 37506 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 37507 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 37508 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 37509 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 37510 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 37511 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 37512 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, |
| 37513 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMOVvi16to32, |
| 37514 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37515 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 37516 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 37517 | GIR_EraseFromParent, /*InsnID*/0, |
| 37518 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37519 | // GIR_Coverage, 4565, |
| 37520 | GIR_Done, |
| 37521 | // Label 2112: @94271 |
| 37522 | GIM_Try, /*On fail goto*//*Label 2113*/ 94373, // Rule ID 4566 // |
| 37523 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlv, |
| 37524 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 37525 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 37526 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 37527 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 37528 | // (intrinsic_wo_chain:{ *:[i32] } 428:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (SMOVvi16to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SADDLVv16i8v:{ *:[bf16] } V128:{ *:[v16i8] }:$Rn), hsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 37529 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 37530 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 37531 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 37532 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::SADDLVv16i8v, |
| 37533 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 37534 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37535 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 37536 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 37537 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 37538 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 37539 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 37540 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 37541 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 37542 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 37543 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 37544 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 37545 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 37546 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, |
| 37547 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMOVvi16to32, |
| 37548 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 37549 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 37550 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 37551 | GIR_EraseFromParent, /*InsnID*/0, |
| 37552 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 37553 | // GIR_Coverage, 4566, |
| 37554 | GIR_Done, |
| 37555 | // Label 2113: @94373 |
| 37556 | GIM_Try, /*On fail goto*//*Label 2114*/ 94479, // Rule ID 4567 // |
| 37557 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlv, |
| 37558 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 37559 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 37560 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 37561 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37562 | // (intrinsic_wo_chain:{ *:[i32] } 428:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SADDLVv4i16v:{ *:[i32] } V64:{ *:[v4i16] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] }) |
| 37563 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 37564 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 37565 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 37566 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::SADDLVv4i16v, |
| 37567 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 37568 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37569 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 37570 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 37571 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 37572 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 37573 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 37574 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 37575 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 37576 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 37577 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 37578 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 37579 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 37580 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 37581 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 37582 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 37583 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::ssub, |
| 37584 | GIR_EraseFromParent, /*InsnID*/0, |
| 37585 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, |
| 37586 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, |
| 37587 | // GIR_Coverage, 4567, |
| 37588 | GIR_Done, |
| 37589 | // Label 2114: @94479 |
| 37590 | GIM_Try, /*On fail goto*//*Label 2115*/ 94585, // Rule ID 4568 // |
| 37591 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlv, |
| 37592 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 37593 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 37594 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 37595 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 37596 | // (intrinsic_wo_chain:{ *:[i32] } 428:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] }) |
| 37597 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 37598 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 37599 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 37600 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::SADDLVv8i16v, |
| 37601 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 37602 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37603 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 37604 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 37605 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 37606 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 37607 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 37608 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 37609 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 37610 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 37611 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 37612 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 37613 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 37614 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 37615 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 37616 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 37617 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::ssub, |
| 37618 | GIR_EraseFromParent, /*InsnID*/0, |
| 37619 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, |
| 37620 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, |
| 37621 | // GIR_Coverage, 4568, |
| 37622 | GIR_Done, |
| 37623 | // Label 2115: @94585 |
| 37624 | GIM_Try, /*On fail goto*//*Label 2116*/ 94691, // Rule ID 4569 // |
| 37625 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlv, |
| 37626 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 37627 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 37628 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 37629 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 37630 | // (intrinsic_wo_chain:{ *:[i64] } 428:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i64] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SADDLVv4i32v:{ *:[i64] } V128:{ *:[v4i32] }:$Rn), dsub:{ *:[i32] }), dsub:{ *:[i32] }) |
| 37631 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 37632 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 37633 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 37634 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::SADDLVv4i32v, |
| 37635 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 37636 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37637 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 37638 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 37639 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 37640 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 37641 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 37642 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 37643 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 37644 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 37645 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 37646 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 37647 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 37648 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 37649 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 37650 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 37651 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::dsub, |
| 37652 | GIR_EraseFromParent, /*InsnID*/0, |
| 37653 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 37654 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, |
| 37655 | // GIR_Coverage, 4569, |
| 37656 | GIR_Done, |
| 37657 | // Label 2116: @94691 |
| 37658 | GIM_Try, /*On fail goto*//*Label 2117*/ 94797, // Rule ID 4570 // |
| 37659 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlv, |
| 37660 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 37661 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 37662 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 37663 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37664 | // (intrinsic_wo_chain:{ *:[i32] } 491:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UADDLVv8i8v:{ *:[bf16] } V64:{ *:[v8i8] }:$Rn), hsub:{ *:[i32] }), ssub:{ *:[i32] }) |
| 37665 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 37666 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 37667 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 37668 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::UADDLVv8i8v, |
| 37669 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 37670 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37671 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 37672 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 37673 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 37674 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 37675 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 37676 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 37677 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 37678 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 37679 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 37680 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 37681 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 37682 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, |
| 37683 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 37684 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 37685 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::ssub, |
| 37686 | GIR_EraseFromParent, /*InsnID*/0, |
| 37687 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, |
| 37688 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, |
| 37689 | // GIR_Coverage, 4570, |
| 37690 | GIR_Done, |
| 37691 | // Label 2117: @94797 |
| 37692 | GIM_Try, /*On fail goto*//*Label 2118*/ 94903, // Rule ID 4571 // |
| 37693 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlv, |
| 37694 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 37695 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 37696 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 37697 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 37698 | // (intrinsic_wo_chain:{ *:[i32] } 491:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UADDLVv16i8v:{ *:[bf16] } V128:{ *:[v16i8] }:$Rn), hsub:{ *:[i32] }), ssub:{ *:[i32] }) |
| 37699 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 37700 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 37701 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 37702 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::UADDLVv16i8v, |
| 37703 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 37704 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37705 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 37706 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 37707 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 37708 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 37709 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 37710 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 37711 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 37712 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 37713 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 37714 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 37715 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 37716 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, |
| 37717 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 37718 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 37719 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::ssub, |
| 37720 | GIR_EraseFromParent, /*InsnID*/0, |
| 37721 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, |
| 37722 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, |
| 37723 | // GIR_Coverage, 4571, |
| 37724 | GIR_Done, |
| 37725 | // Label 2118: @94903 |
| 37726 | GIM_Try, /*On fail goto*//*Label 2119*/ 95009, // Rule ID 4572 // |
| 37727 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlv, |
| 37728 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 37729 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 37730 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 37731 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37732 | // (intrinsic_wo_chain:{ *:[i32] } 491:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UADDLVv4i16v:{ *:[i32] } V64:{ *:[v4i16] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] }) |
| 37733 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 37734 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 37735 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 37736 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::UADDLVv4i16v, |
| 37737 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 37738 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37739 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 37740 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 37741 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 37742 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 37743 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 37744 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 37745 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 37746 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 37747 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 37748 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 37749 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 37750 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 37751 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 37752 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 37753 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::ssub, |
| 37754 | GIR_EraseFromParent, /*InsnID*/0, |
| 37755 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, |
| 37756 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, |
| 37757 | // GIR_Coverage, 4572, |
| 37758 | GIR_Done, |
| 37759 | // Label 2119: @95009 |
| 37760 | GIM_Try, /*On fail goto*//*Label 2120*/ 95115, // Rule ID 4573 // |
| 37761 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlv, |
| 37762 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 37763 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 37764 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 37765 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 37766 | // (intrinsic_wo_chain:{ *:[i32] } 491:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] }) |
| 37767 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 37768 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 37769 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 37770 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::UADDLVv8i16v, |
| 37771 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 37772 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37773 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 37774 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 37775 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 37776 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 37777 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 37778 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 37779 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 37780 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 37781 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 37782 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 37783 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 37784 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 37785 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 37786 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 37787 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::ssub, |
| 37788 | GIR_EraseFromParent, /*InsnID*/0, |
| 37789 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, |
| 37790 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, |
| 37791 | // GIR_Coverage, 4573, |
| 37792 | GIR_Done, |
| 37793 | // Label 2120: @95115 |
| 37794 | GIM_Try, /*On fail goto*//*Label 2121*/ 95221, // Rule ID 4574 // |
| 37795 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlv, |
| 37796 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 37797 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 37798 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 37799 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 37800 | // (intrinsic_wo_chain:{ *:[i64] } 491:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i64] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UADDLVv4i32v:{ *:[i64] } V128:{ *:[v4i32] }:$Rn), dsub:{ *:[i32] }), dsub:{ *:[i32] }) |
| 37801 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 37802 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 37803 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 37804 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::UADDLVv4i32v, |
| 37805 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 37806 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37807 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 37808 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 37809 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 37810 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 37811 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 37812 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 37813 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 37814 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 37815 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 37816 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 37817 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 37818 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 37819 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 37820 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 37821 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::dsub, |
| 37822 | GIR_EraseFromParent, /*InsnID*/0, |
| 37823 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 37824 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, |
| 37825 | // GIR_Coverage, 4574, |
| 37826 | GIR_Done, |
| 37827 | // Label 2121: @95221 |
| 37828 | GIM_Try, /*On fail goto*//*Label 2122*/ 95327, // Rule ID 4575 // |
| 37829 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_saddlv, |
| 37830 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 37831 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 37832 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 37833 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37834 | // (intrinsic_wo_chain:{ *:[i64] } 428:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i64] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SADDLPv2i32_v1i64:{ *:[i64] } V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] }), dsub:{ *:[i32] }) |
| 37835 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 37836 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 37837 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 37838 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::SADDLPv2i32_v1i64, |
| 37839 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 37840 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37841 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 37842 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 37843 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 37844 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 37845 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 37846 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 37847 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 37848 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 37849 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 37850 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 37851 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 37852 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 37853 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 37854 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 37855 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::dsub, |
| 37856 | GIR_EraseFromParent, /*InsnID*/0, |
| 37857 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 37858 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, |
| 37859 | // GIR_Coverage, 4575, |
| 37860 | GIR_Done, |
| 37861 | // Label 2122: @95327 |
| 37862 | GIM_Try, /*On fail goto*//*Label 2123*/ 95433, // Rule ID 4576 // |
| 37863 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uaddlv, |
| 37864 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 37865 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 37866 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 37867 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37868 | // (intrinsic_wo_chain:{ *:[i64] } 491:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i64] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UADDLPv2i32_v1i64:{ *:[i64] } V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] }), dsub:{ *:[i32] }) |
| 37869 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 37870 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 37871 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 37872 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::UADDLPv2i32_v1i64, |
| 37873 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 37874 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 37875 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 37876 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 37877 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 37878 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 37879 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 37880 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 37881 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 37882 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 37883 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 37884 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 37885 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 37886 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 37887 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 37888 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 37889 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::dsub, |
| 37890 | GIR_EraseFromParent, /*InsnID*/0, |
| 37891 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 37892 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, |
| 37893 | // GIR_Coverage, 4576, |
| 37894 | GIR_Done, |
| 37895 | // Label 2123: @95433 |
| 37896 | GIM_Reject, |
| 37897 | // Label 1886: @95434 |
| 37898 | GIM_Try, /*On fail goto*//*Label 2124*/ 124126, |
| 37899 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, |
| 37900 | GIM_Try, /*On fail goto*//*Label 2125*/ 95627, // Rule ID 2734 // |
| 37901 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 37902 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 37903 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 37904 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 37905 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 37906 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 37907 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 37908 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 37909 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 37910 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 37911 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 37912 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 37913 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, |
| 37914 | GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, |
| 37915 | GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, |
| 37916 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 37917 | GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16, |
| 37918 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37919 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/3, // MIs[3] |
| 37920 | GIM_CheckOpcode, /*MI*/3, AArch64::G_DUPLANE16, |
| 37921 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16, |
| 37922 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64, |
| 37923 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 37924 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 37925 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
| 37926 | GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 37927 | // MIs[4] Operand 1 |
| 37928 | // No operand predicates |
| 37929 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 0, |
| 37930 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 37931 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 37932 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 37933 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 37934 | // (intrinsic_wo_chain:{ *:[i32] } 446:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (vector_extract:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 450:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), 0:{ *:[i64] })) => (EXTRACT_SUBREG:{ *:[i32] } (SQDMLALv4i16_indexed:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[i32] }:$Rd, ssub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), ssub:{ *:[i32] }) |
| 37935 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 37936 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 37937 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 37938 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 37939 | GIR_AddImm, /*InsnID*/2, /*Imm*/0, |
| 37940 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 37941 | GIR_AddImm, /*InsnID*/2, /*Imm*/14, |
| 37942 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::FPR128RegClassID, |
| 37943 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, AArch64::FPR32RegClassID, |
| 37944 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SQDMLALv4i16_indexed, |
| 37945 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 37946 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 37947 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rn |
| 37948 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 37949 | GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/4, // idx |
| 37950 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 37951 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 37952 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 37953 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::ssub, |
| 37954 | GIR_EraseFromParent, /*InsnID*/0, |
| 37955 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, |
| 37956 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, |
| 37957 | // GIR_Coverage, 2734, |
| 37958 | GIR_Done, |
| 37959 | // Label 2125: @95627 |
| 37960 | GIM_Try, /*On fail goto*//*Label 2126*/ 95815, // Rule ID 4700 // |
| 37961 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 37962 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 37963 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 37964 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 37965 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 37966 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 37967 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 37968 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 37969 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 37970 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 37971 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 37972 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 37973 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, |
| 37974 | GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, |
| 37975 | GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, |
| 37976 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 37977 | GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16, |
| 37978 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 37979 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/3, // MIs[3] |
| 37980 | GIM_CheckOpcode, /*MI*/3, AArch64::G_DUPLANE16, |
| 37981 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16, |
| 37982 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64, |
| 37983 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 37984 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 37985 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
| 37986 | GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 37987 | // MIs[4] Operand 1 |
| 37988 | // No operand predicates |
| 37989 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 0, |
| 37990 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 37991 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 37992 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 37993 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 37994 | // (intrinsic_wo_chain:{ *:[i32] } 463:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (vector_extract:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 450:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), 0:{ *:[i64] })) => (EXTRACT_SUBREG:{ *:[i32] } (SQDMLSLv4i16_indexed:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[i32] }:$Rd, ssub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), ssub:{ *:[i32] }) |
| 37995 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 37996 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 37997 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 37998 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 37999 | GIR_AddImm, /*InsnID*/2, /*Imm*/0, |
| 38000 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 38001 | GIR_AddImm, /*InsnID*/2, /*Imm*/14, |
| 38002 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::FPR128RegClassID, |
| 38003 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, AArch64::FPR32RegClassID, |
| 38004 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SQDMLSLv4i16_indexed, |
| 38005 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 38006 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 38007 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rn |
| 38008 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 38009 | GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/4, // idx |
| 38010 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 38011 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 38012 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 38013 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::ssub, |
| 38014 | GIR_EraseFromParent, /*InsnID*/0, |
| 38015 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, |
| 38016 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, |
| 38017 | // GIR_Coverage, 4700, |
| 38018 | GIR_Done, |
| 38019 | // Label 2126: @95815 |
| 38020 | GIM_Try, /*On fail goto*//*Label 2127*/ 96020, // Rule ID 2741 // |
| 38021 | GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, |
| 38022 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 38023 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 38024 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 38025 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 38026 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 38027 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 38028 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 38029 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 38030 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 38031 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 38032 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 38033 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, |
| 38034 | GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, |
| 38035 | GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 38036 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 38037 | GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s32, |
| 38038 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 38039 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/3, // MIs[3] |
| 38040 | GIM_CheckOpcode, /*MI*/3, AArch64::G_DUPLANE32, |
| 38041 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32, |
| 38042 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64, |
| 38043 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 38044 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 38045 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
| 38046 | GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 38047 | // MIs[4] Operand 1 |
| 38048 | // No operand predicates |
| 38049 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 0, |
| 38050 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 38051 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 38052 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 38053 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 38054 | // (intrinsic_wo_chain:{ *:[i32] } 446:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (vector_extract:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 453:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), 0:{ *:[i64] })) => (EXTRACT_SUBREG:{ *:[i32] } (SQRDMLAHv4i32_indexed:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32Op:{ *:[i32] }:$Rd, ssub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), ssub:{ *:[i32] }) |
| 38055 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 38056 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 38057 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32, |
| 38058 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 38059 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 38060 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 38061 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 38062 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 38063 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, |
| 38064 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 38065 | GIR_AddImm, /*InsnID*/2, /*Imm*/14, |
| 38066 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::FPR128RegClassID, |
| 38067 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::FPR128RegClassID, |
| 38068 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, AArch64::FPR32RegClassID, |
| 38069 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SQRDMLAHv4i32_indexed, |
| 38070 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 38071 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 38072 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rn |
| 38073 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 38074 | GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/4, // idx |
| 38075 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 38076 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 38077 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 38078 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::ssub, |
| 38079 | GIR_EraseFromParent, /*InsnID*/0, |
| 38080 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, |
| 38081 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, |
| 38082 | // GIR_Coverage, 2741, |
| 38083 | GIR_Done, |
| 38084 | // Label 2127: @96020 |
| 38085 | GIM_Try, /*On fail goto*//*Label 2128*/ 96225, // Rule ID 4702 // |
| 38086 | GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, |
| 38087 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 38088 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 38089 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 38090 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 38091 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 38092 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 38093 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 38094 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 38095 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 38096 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 38097 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 38098 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, |
| 38099 | GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, |
| 38100 | GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 38101 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 38102 | GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s32, |
| 38103 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 38104 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/3, // MIs[3] |
| 38105 | GIM_CheckOpcode, /*MI*/3, AArch64::G_DUPLANE32, |
| 38106 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32, |
| 38107 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64, |
| 38108 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 38109 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 38110 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
| 38111 | GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 38112 | // MIs[4] Operand 1 |
| 38113 | // No operand predicates |
| 38114 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 0, |
| 38115 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 38116 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 38117 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 38118 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 38119 | // (intrinsic_wo_chain:{ *:[i32] } 463:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (vector_extract:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 453:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), 0:{ *:[i64] })) => (EXTRACT_SUBREG:{ *:[i32] } (SQRDMLSHv4i32_indexed:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32Op:{ *:[i32] }:$Rd, ssub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), ssub:{ *:[i32] }) |
| 38120 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 38121 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 38122 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32, |
| 38123 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 38124 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 38125 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 38126 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 38127 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 38128 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, |
| 38129 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 38130 | GIR_AddImm, /*InsnID*/2, /*Imm*/14, |
| 38131 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::FPR128RegClassID, |
| 38132 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::FPR128RegClassID, |
| 38133 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, AArch64::FPR32RegClassID, |
| 38134 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SQRDMLSHv4i32_indexed, |
| 38135 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 38136 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 38137 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rn |
| 38138 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 38139 | GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/4, // idx |
| 38140 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 38141 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 38142 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 38143 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, AArch64::ssub, |
| 38144 | GIR_EraseFromParent, /*InsnID*/0, |
| 38145 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, |
| 38146 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, |
| 38147 | // GIR_Coverage, 4702, |
| 38148 | GIR_Done, |
| 38149 | // Label 2128: @96225 |
| 38150 | GIM_Try, /*On fail goto*//*Label 2129*/ 96317, // Rule ID 4255 // |
| 38151 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_pmull64, |
| 38152 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 38153 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 38154 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 38155 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 38156 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38157 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 38158 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 38159 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 38160 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 38161 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, |
| 38162 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 38163 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 38164 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 38165 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 38166 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 38167 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, |
| 38168 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 38169 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 38170 | // (intrinsic_wo_chain:{ *:[v16i8] } 421:{ *:[iPTR] }, (extractelt:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, 1:{ *:[i64] }), (extractelt:{ *:[i64] } V128:{ *:[v2i64] }:$Rm, 1:{ *:[i64] })) => (PMULLv2i64:{ *:[v16i8] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 38171 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PMULLv2i64, |
| 38172 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 38173 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 38174 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 38175 | GIR_EraseFromParent, /*InsnID*/0, |
| 38176 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 38177 | // GIR_Coverage, 4255, |
| 38178 | GIR_Done, |
| 38179 | // Label 2129: @96317 |
| 38180 | GIM_Try, /*On fail goto*//*Label 2130*/ 96433, // Rule ID 1730 // |
| 38181 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 38182 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 38183 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 38184 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 38185 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 38186 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 38187 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 38188 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 38189 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 38190 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 38191 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, |
| 38192 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38193 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 38194 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 38195 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 38196 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, |
| 38197 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 38198 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 38199 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 38200 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 38201 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 38202 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 38203 | // MIs[3] Operand 1 |
| 38204 | // No operand predicates |
| 38205 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 38206 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 38207 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 38208 | // (intrinsic_wo_chain:{ *:[v4i32] } 446:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 450:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))) => (SQDMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 38209 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALv4i16_indexed, |
| 38210 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 38211 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 38212 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 38213 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 38214 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 38215 | GIR_EraseFromParent, /*InsnID*/0, |
| 38216 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 38217 | // GIR_Coverage, 1730, |
| 38218 | GIR_Done, |
| 38219 | // Label 2130: @96433 |
| 38220 | GIM_Try, /*On fail goto*//*Label 2131*/ 96549, // Rule ID 1735 // |
| 38221 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 38222 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 38223 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 38224 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 38225 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 38226 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 38227 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 38228 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 38229 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 38230 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 38231 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, |
| 38232 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38233 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 38234 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 38235 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 38236 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, |
| 38237 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 38238 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 38239 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 38240 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 38241 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 38242 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 38243 | // MIs[3] Operand 1 |
| 38244 | // No operand predicates |
| 38245 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 38246 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 38247 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 38248 | // (intrinsic_wo_chain:{ *:[v4i32] } 463:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 450:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))) => (SQDMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 38249 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLv4i16_indexed, |
| 38250 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 38251 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 38252 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 38253 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 38254 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 38255 | GIR_EraseFromParent, /*InsnID*/0, |
| 38256 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 38257 | // GIR_Coverage, 1735, |
| 38258 | GIR_Done, |
| 38259 | // Label 2131: @96549 |
| 38260 | GIM_Try, /*On fail goto*//*Label 2132*/ 96665, // Rule ID 1740 // |
| 38261 | GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, |
| 38262 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 38263 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 38264 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38265 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 38266 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 38267 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 38268 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 38269 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 38270 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 38271 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 38272 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38273 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 38274 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 38275 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 38276 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, |
| 38277 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 38278 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 38279 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 38280 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 38281 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 38282 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 38283 | // MIs[3] Operand 1 |
| 38284 | // No operand predicates |
| 38285 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 38286 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 38287 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 38288 | // (intrinsic_wo_chain:{ *:[v4i16] } 446:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 453:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))) => (SQRDMLAHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 38289 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv4i16_indexed, |
| 38290 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 38291 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 38292 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 38293 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 38294 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 38295 | GIR_EraseFromParent, /*InsnID*/0, |
| 38296 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 38297 | // GIR_Coverage, 1740, |
| 38298 | GIR_Done, |
| 38299 | // Label 2132: @96665 |
| 38300 | GIM_Try, /*On fail goto*//*Label 2133*/ 96781, // Rule ID 1741 // |
| 38301 | GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, |
| 38302 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 38303 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 38304 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 38305 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 38306 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 38307 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 38308 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 38309 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 38310 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 38311 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 38312 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 38313 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, |
| 38314 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 38315 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 38316 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, |
| 38317 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 38318 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 38319 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 38320 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 38321 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 38322 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 38323 | // MIs[3] Operand 1 |
| 38324 | // No operand predicates |
| 38325 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 38326 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 38327 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 38328 | // (intrinsic_wo_chain:{ *:[v8i16] } 446:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 453:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))) => (SQRDMLAHv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 38329 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv8i16_indexed, |
| 38330 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 38331 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 38332 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 38333 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 38334 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 38335 | GIR_EraseFromParent, /*InsnID*/0, |
| 38336 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 38337 | // GIR_Coverage, 1741, |
| 38338 | GIR_Done, |
| 38339 | // Label 2133: @96781 |
| 38340 | GIM_Try, /*On fail goto*//*Label 2134*/ 96897, // Rule ID 1745 // |
| 38341 | GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, |
| 38342 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 38343 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 38344 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38345 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 38346 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 38347 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 38348 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 38349 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 38350 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 38351 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 38352 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38353 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 38354 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 38355 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 38356 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, |
| 38357 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 38358 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 38359 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 38360 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 38361 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 38362 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 38363 | // MIs[3] Operand 1 |
| 38364 | // No operand predicates |
| 38365 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 38366 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 38367 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 38368 | // (intrinsic_wo_chain:{ *:[v4i16] } 463:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 453:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))) => (SQRDMLSHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 38369 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv4i16_indexed, |
| 38370 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 38371 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 38372 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 38373 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 38374 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 38375 | GIR_EraseFromParent, /*InsnID*/0, |
| 38376 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 38377 | // GIR_Coverage, 1745, |
| 38378 | GIR_Done, |
| 38379 | // Label 2134: @96897 |
| 38380 | GIM_Try, /*On fail goto*//*Label 2135*/ 97013, // Rule ID 1746 // |
| 38381 | GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, |
| 38382 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 38383 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 38384 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 38385 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 38386 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 38387 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 38388 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 38389 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 38390 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 38391 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 38392 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 38393 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, |
| 38394 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 38395 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 38396 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, |
| 38397 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 38398 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 38399 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 38400 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 38401 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 38402 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 38403 | // MIs[3] Operand 1 |
| 38404 | // No operand predicates |
| 38405 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 38406 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 38407 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 38408 | // (intrinsic_wo_chain:{ *:[v8i16] } 463:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 453:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))) => (SQRDMLSHv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 38409 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv8i16_indexed, |
| 38410 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 38411 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 38412 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 38413 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 38414 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 38415 | GIR_EraseFromParent, /*InsnID*/0, |
| 38416 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 38417 | // GIR_Coverage, 1746, |
| 38418 | GIR_Done, |
| 38419 | // Label 2135: @97013 |
| 38420 | GIM_Try, /*On fail goto*//*Label 2136*/ 97129, // Rule ID 1732 // |
| 38421 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 38422 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 38423 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 38424 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 38425 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 38426 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 38427 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 38428 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 38429 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 38430 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 38431 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, |
| 38432 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 38433 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 38434 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 38435 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 38436 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 38437 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 38438 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 38439 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 38440 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 38441 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 38442 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 38443 | // MIs[3] Operand 1 |
| 38444 | // No operand predicates |
| 38445 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 38446 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 38447 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 38448 | // (intrinsic_wo_chain:{ *:[v2i64] } 446:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 450:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (SQDMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 38449 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALv2i32_indexed, |
| 38450 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 38451 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 38452 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 38453 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 38454 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 38455 | GIR_EraseFromParent, /*InsnID*/0, |
| 38456 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 38457 | // GIR_Coverage, 1732, |
| 38458 | GIR_Done, |
| 38459 | // Label 2136: @97129 |
| 38460 | GIM_Try, /*On fail goto*//*Label 2137*/ 97245, // Rule ID 1737 // |
| 38461 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 38462 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 38463 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 38464 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 38465 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 38466 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 38467 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 38468 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 38469 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 38470 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 38471 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, |
| 38472 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 38473 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 38474 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 38475 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 38476 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 38477 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 38478 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 38479 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 38480 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 38481 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 38482 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 38483 | // MIs[3] Operand 1 |
| 38484 | // No operand predicates |
| 38485 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 38486 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 38487 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 38488 | // (intrinsic_wo_chain:{ *:[v2i64] } 463:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 450:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (SQDMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 38489 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLv2i32_indexed, |
| 38490 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 38491 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 38492 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 38493 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 38494 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 38495 | GIR_EraseFromParent, /*InsnID*/0, |
| 38496 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 38497 | // GIR_Coverage, 1737, |
| 38498 | GIR_Done, |
| 38499 | // Label 2137: @97245 |
| 38500 | GIM_Try, /*On fail goto*//*Label 2138*/ 97361, // Rule ID 1742 // |
| 38501 | GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, |
| 38502 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 38503 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 38504 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 38505 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 38506 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 38507 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 38508 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 38509 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 38510 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 38511 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 38512 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 38513 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 38514 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 38515 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 38516 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 38517 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 38518 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 38519 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 38520 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 38521 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 38522 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 38523 | // MIs[3] Operand 1 |
| 38524 | // No operand predicates |
| 38525 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 38526 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 38527 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 38528 | // (intrinsic_wo_chain:{ *:[v2i32] } 446:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 453:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (SQRDMLAHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 38529 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv2i32_indexed, |
| 38530 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 38531 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 38532 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 38533 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 38534 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 38535 | GIR_EraseFromParent, /*InsnID*/0, |
| 38536 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 38537 | // GIR_Coverage, 1742, |
| 38538 | GIR_Done, |
| 38539 | // Label 2138: @97361 |
| 38540 | GIM_Try, /*On fail goto*//*Label 2139*/ 97477, // Rule ID 1743 // |
| 38541 | GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, |
| 38542 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 38543 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 38544 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 38545 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 38546 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 38547 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 38548 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 38549 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 38550 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 38551 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 38552 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 38553 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, |
| 38554 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 38555 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 38556 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 38557 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 38558 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 38559 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 38560 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 38561 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 38562 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 38563 | // MIs[3] Operand 1 |
| 38564 | // No operand predicates |
| 38565 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 38566 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 38567 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 38568 | // (intrinsic_wo_chain:{ *:[v4i32] } 446:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 453:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (SQRDMLAHv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 38569 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv4i32_indexed, |
| 38570 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 38571 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 38572 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 38573 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 38574 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 38575 | GIR_EraseFromParent, /*InsnID*/0, |
| 38576 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 38577 | // GIR_Coverage, 1743, |
| 38578 | GIR_Done, |
| 38579 | // Label 2139: @97477 |
| 38580 | GIM_Try, /*On fail goto*//*Label 2140*/ 97593, // Rule ID 1747 // |
| 38581 | GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, |
| 38582 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 38583 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 38584 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 38585 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 38586 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 38587 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 38588 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 38589 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 38590 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 38591 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 38592 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 38593 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 38594 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 38595 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 38596 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 38597 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 38598 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 38599 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 38600 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 38601 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 38602 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 38603 | // MIs[3] Operand 1 |
| 38604 | // No operand predicates |
| 38605 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 38606 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 38607 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 38608 | // (intrinsic_wo_chain:{ *:[v2i32] } 463:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 453:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (SQRDMLSHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 38609 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv2i32_indexed, |
| 38610 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 38611 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 38612 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 38613 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 38614 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 38615 | GIR_EraseFromParent, /*InsnID*/0, |
| 38616 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 38617 | // GIR_Coverage, 1747, |
| 38618 | GIR_Done, |
| 38619 | // Label 2140: @97593 |
| 38620 | GIM_Try, /*On fail goto*//*Label 2141*/ 97709, // Rule ID 1748 // |
| 38621 | GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, |
| 38622 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 38623 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 38624 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 38625 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 38626 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 38627 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 38628 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 38629 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 38630 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 38631 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 38632 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 38633 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, |
| 38634 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 38635 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 38636 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 38637 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 38638 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 38639 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 38640 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 38641 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 38642 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 38643 | // MIs[3] Operand 1 |
| 38644 | // No operand predicates |
| 38645 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 38646 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 38647 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 38648 | // (intrinsic_wo_chain:{ *:[v4i32] } 463:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 453:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (SQRDMLSHv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 38649 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv4i32_indexed, |
| 38650 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 38651 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 38652 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 38653 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 38654 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 38655 | GIR_EraseFromParent, /*InsnID*/0, |
| 38656 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 38657 | // GIR_Coverage, 1748, |
| 38658 | GIR_Done, |
| 38659 | // Label 2141: @97709 |
| 38660 | GIM_Try, /*On fail goto*//*Label 2142*/ 97825, // Rule ID 1734 // |
| 38661 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 38662 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 38663 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 38664 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 38665 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 38666 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 38667 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 38668 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 38669 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 38670 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 38671 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmulls_scalar, |
| 38672 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 38673 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 38674 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 38675 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 38676 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 38677 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 38678 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 38679 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 38680 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 38681 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 38682 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 38683 | // MIs[3] Operand 1 |
| 38684 | // No operand predicates |
| 38685 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 38686 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 38687 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 38688 | // (intrinsic_wo_chain:{ *:[i64] } 446:{ *:[iPTR] }, FPR64Op:{ *:[i64] }:$Rd, (intrinsic_wo_chain:{ *:[i64] } 451:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (SQDMLALv1i64_indexed:{ *:[i64] } FPR64Op:{ *:[i64] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 38689 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALv1i64_indexed, |
| 38690 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 38691 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 38692 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 38693 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 38694 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 38695 | GIR_EraseFromParent, /*InsnID*/0, |
| 38696 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 38697 | // GIR_Coverage, 1734, |
| 38698 | GIR_Done, |
| 38699 | // Label 2142: @97825 |
| 38700 | GIM_Try, /*On fail goto*//*Label 2143*/ 97941, // Rule ID 1739 // |
| 38701 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 38702 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 38703 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 38704 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 38705 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 38706 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 38707 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 38708 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 38709 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 38710 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 38711 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmulls_scalar, |
| 38712 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 38713 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 38714 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 38715 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 38716 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 38717 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 38718 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 38719 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 38720 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 38721 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 38722 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 38723 | // MIs[3] Operand 1 |
| 38724 | // No operand predicates |
| 38725 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 38726 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 38727 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 38728 | // (intrinsic_wo_chain:{ *:[i64] } 463:{ *:[iPTR] }, FPR64Op:{ *:[i64] }:$Rd, (intrinsic_wo_chain:{ *:[i64] } 451:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (SQDMLSLv1i64_indexed:{ *:[i64] } FPR64Op:{ *:[i64] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 38729 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLv1i64_indexed, |
| 38730 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 38731 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 38732 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 38733 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 38734 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 38735 | GIR_EraseFromParent, /*InsnID*/0, |
| 38736 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 38737 | // GIR_Coverage, 1739, |
| 38738 | GIR_Done, |
| 38739 | // Label 2143: @97941 |
| 38740 | GIM_Try, /*On fail goto*//*Label 2144*/ 98057, // Rule ID 1744 // |
| 38741 | GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, |
| 38742 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 38743 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 38744 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 38745 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 38746 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 38747 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 38748 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 38749 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 38750 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 38751 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 38752 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 38753 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 38754 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 38755 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 38756 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 38757 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 38758 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 38759 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 38760 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 38761 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 38762 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 38763 | // MIs[3] Operand 1 |
| 38764 | // No operand predicates |
| 38765 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 38766 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 38767 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 38768 | // (intrinsic_wo_chain:{ *:[i32] } 446:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (intrinsic_wo_chain:{ *:[i32] } 453:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (SQRDMLAHi32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 38769 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHi32_indexed, |
| 38770 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 38771 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 38772 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 38773 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 38774 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 38775 | GIR_EraseFromParent, /*InsnID*/0, |
| 38776 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 38777 | // GIR_Coverage, 1744, |
| 38778 | GIR_Done, |
| 38779 | // Label 2144: @98057 |
| 38780 | GIM_Try, /*On fail goto*//*Label 2145*/ 98173, // Rule ID 1749 // |
| 38781 | GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, |
| 38782 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 38783 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 38784 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 38785 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 38786 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 38787 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 38788 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 38789 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 38790 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 38791 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 38792 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 38793 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 38794 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 38795 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 38796 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 38797 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 38798 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 38799 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 38800 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 38801 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 38802 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 38803 | // MIs[3] Operand 1 |
| 38804 | // No operand predicates |
| 38805 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 38806 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 38807 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 38808 | // (intrinsic_wo_chain:{ *:[i32] } 463:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (intrinsic_wo_chain:{ *:[i32] } 453:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (SQRDMLSHi32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 38809 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHi32_indexed, |
| 38810 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 38811 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 38812 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 38813 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 38814 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 38815 | GIR_EraseFromParent, /*InsnID*/0, |
| 38816 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 38817 | // GIR_Coverage, 1749, |
| 38818 | GIR_Done, |
| 38819 | // Label 2145: @98173 |
| 38820 | GIM_Try, /*On fail goto*//*Label 2146*/ 98274, // Rule ID 4719 // |
| 38821 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, |
| 38822 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, |
| 38823 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 38824 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 38825 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 38826 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38827 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 38828 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 38829 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 38830 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 38831 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535, |
| 38832 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 38833 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 38834 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, |
| 38835 | // MIs[2] Operand 1 |
| 38836 | // No operand predicates |
| 38837 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 38838 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 38839 | // (intrinsic_wo_chain:{ *:[f16] } 531:{ *:[iPTR] }, (and:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) => (UCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[bf16] } FPR32:{ *:[i32] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) |
| 38840 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 38841 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 38842 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 38843 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/7, // Rn |
| 38844 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR16RegClassID, |
| 38845 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR32RegClassID, |
| 38846 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFh, |
| 38847 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 38848 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 38849 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 38850 | GIR_EraseFromParent, /*InsnID*/0, |
| 38851 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 38852 | // GIR_Coverage, 4719, |
| 38853 | GIR_Done, |
| 38854 | // Label 2146: @98274 |
| 38855 | GIM_Try, /*On fail goto*//*Label 2147*/ 98358, // Rule ID 1305 // |
| 38856 | GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, |
| 38857 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 38858 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 38859 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38860 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 38861 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 38862 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 38863 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 38864 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 38865 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 38866 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 38867 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38868 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 38869 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 38870 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 38871 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 38872 | // (intrinsic_wo_chain:{ *:[v4i16] } 446:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 453:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SQRDMLAHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 38873 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv4i16, |
| 38874 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 38875 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 38876 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 38877 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 38878 | GIR_EraseFromParent, /*InsnID*/0, |
| 38879 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 38880 | // GIR_Coverage, 1305, |
| 38881 | GIR_Done, |
| 38882 | // Label 2147: @98358 |
| 38883 | GIM_Try, /*On fail goto*//*Label 2148*/ 98442, // Rule ID 1306 // |
| 38884 | GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, |
| 38885 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 38886 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 38887 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 38888 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 38889 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 38890 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 38891 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 38892 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 38893 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 38894 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 38895 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 38896 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, |
| 38897 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 38898 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 38899 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 38900 | // (intrinsic_wo_chain:{ *:[v8i16] } 446:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 453:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (SQRDMLAHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 38901 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv8i16, |
| 38902 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 38903 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 38904 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 38905 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 38906 | GIR_EraseFromParent, /*InsnID*/0, |
| 38907 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 38908 | // GIR_Coverage, 1306, |
| 38909 | GIR_Done, |
| 38910 | // Label 2148: @98442 |
| 38911 | GIM_Try, /*On fail goto*//*Label 2149*/ 98526, // Rule ID 1307 // |
| 38912 | GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, |
| 38913 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 38914 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 38915 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 38916 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 38917 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 38918 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 38919 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 38920 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 38921 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 38922 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 38923 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 38924 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 38925 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 38926 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 38927 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 38928 | // (intrinsic_wo_chain:{ *:[v2i32] } 446:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 453:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SQRDMLAHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 38929 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv2i32, |
| 38930 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 38931 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 38932 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 38933 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 38934 | GIR_EraseFromParent, /*InsnID*/0, |
| 38935 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 38936 | // GIR_Coverage, 1307, |
| 38937 | GIR_Done, |
| 38938 | // Label 2149: @98526 |
| 38939 | GIM_Try, /*On fail goto*//*Label 2150*/ 98610, // Rule ID 1308 // |
| 38940 | GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, |
| 38941 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 38942 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 38943 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 38944 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 38945 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 38946 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 38947 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 38948 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 38949 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 38950 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 38951 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 38952 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, |
| 38953 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 38954 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 38955 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 38956 | // (intrinsic_wo_chain:{ *:[v4i32] } 446:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 453:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (SQRDMLAHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 38957 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv4i32, |
| 38958 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 38959 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 38960 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 38961 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 38962 | GIR_EraseFromParent, /*InsnID*/0, |
| 38963 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 38964 | // GIR_Coverage, 1308, |
| 38965 | GIR_Done, |
| 38966 | // Label 2150: @98610 |
| 38967 | GIM_Try, /*On fail goto*//*Label 2151*/ 98694, // Rule ID 1309 // |
| 38968 | GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, |
| 38969 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 38970 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 38971 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38972 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 38973 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 38974 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 38975 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 38976 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 38977 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 38978 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 38979 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38980 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 38981 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 38982 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 38983 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 38984 | // (intrinsic_wo_chain:{ *:[v4i16] } 463:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 453:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SQRDMLSHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 38985 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv4i16, |
| 38986 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 38987 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 38988 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 38989 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 38990 | GIR_EraseFromParent, /*InsnID*/0, |
| 38991 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 38992 | // GIR_Coverage, 1309, |
| 38993 | GIR_Done, |
| 38994 | // Label 2151: @98694 |
| 38995 | GIM_Try, /*On fail goto*//*Label 2152*/ 98778, // Rule ID 1310 // |
| 38996 | GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, |
| 38997 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 38998 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 38999 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 39000 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 39001 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 39002 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 39003 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39004 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 39005 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 39006 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 39007 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 39008 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, |
| 39009 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 39010 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 39011 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39012 | // (intrinsic_wo_chain:{ *:[v8i16] } 463:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 453:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (SQRDMLSHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 39013 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv8i16, |
| 39014 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 39015 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 39016 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 39017 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 39018 | GIR_EraseFromParent, /*InsnID*/0, |
| 39019 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39020 | // GIR_Coverage, 1310, |
| 39021 | GIR_Done, |
| 39022 | // Label 2152: @98778 |
| 39023 | GIM_Try, /*On fail goto*//*Label 2153*/ 98862, // Rule ID 1311 // |
| 39024 | GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, |
| 39025 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 39026 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 39027 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 39028 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 39029 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 39030 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 39031 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39032 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 39033 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 39034 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 39035 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 39036 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 39037 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 39038 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 39039 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39040 | // (intrinsic_wo_chain:{ *:[v2i32] } 463:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 453:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SQRDMLSHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 39041 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv2i32, |
| 39042 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 39043 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 39044 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 39045 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 39046 | GIR_EraseFromParent, /*InsnID*/0, |
| 39047 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39048 | // GIR_Coverage, 1311, |
| 39049 | GIR_Done, |
| 39050 | // Label 2153: @98862 |
| 39051 | GIM_Try, /*On fail goto*//*Label 2154*/ 98946, // Rule ID 1312 // |
| 39052 | GIM_CheckFeatures, GIFBS_HasNEON_HasRDM, |
| 39053 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 39054 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 39055 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 39056 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 39057 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 39058 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 39059 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39060 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 39061 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 39062 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 39063 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 39064 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, |
| 39065 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 39066 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 39067 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39068 | // (intrinsic_wo_chain:{ *:[v4i32] } 463:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 453:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (SQRDMLSHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 39069 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv4i32, |
| 39070 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 39071 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 39072 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 39073 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 39074 | GIR_EraseFromParent, /*InsnID*/0, |
| 39075 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39076 | // GIR_Coverage, 1312, |
| 39077 | GIR_Done, |
| 39078 | // Label 2154: @98946 |
| 39079 | GIM_Try, /*On fail goto*//*Label 2155*/ 99030, // Rule ID 1459 // |
| 39080 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 39081 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 39082 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 39083 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 39084 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 39085 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 39086 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 39087 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39088 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 39089 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 39090 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, |
| 39091 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 39092 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 39093 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 39094 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 39095 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39096 | // (intrinsic_wo_chain:{ *:[v4i32] } 446:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 450:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SQDMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 39097 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALv4i16_v4i32, |
| 39098 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 39099 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 39100 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 39101 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 39102 | GIR_EraseFromParent, /*InsnID*/0, |
| 39103 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39104 | // GIR_Coverage, 1459, |
| 39105 | GIR_Done, |
| 39106 | // Label 2155: @99030 |
| 39107 | GIM_Try, /*On fail goto*//*Label 2156*/ 99114, // Rule ID 1461 // |
| 39108 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 39109 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 39110 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 39111 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 39112 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 39113 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 39114 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 39115 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39116 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 39117 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 39118 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, |
| 39119 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 39120 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 39121 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 39122 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 39123 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39124 | // (intrinsic_wo_chain:{ *:[v2i64] } 446:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 450:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SQDMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 39125 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALv2i32_v2i64, |
| 39126 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 39127 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 39128 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 39129 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 39130 | GIR_EraseFromParent, /*InsnID*/0, |
| 39131 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39132 | // GIR_Coverage, 1461, |
| 39133 | GIR_Done, |
| 39134 | // Label 2156: @99114 |
| 39135 | GIM_Try, /*On fail goto*//*Label 2157*/ 99198, // Rule ID 1463 // |
| 39136 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 39137 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 39138 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 39139 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 39140 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 39141 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 39142 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 39143 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39144 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 39145 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 39146 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, |
| 39147 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 39148 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 39149 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 39150 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 39151 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39152 | // (intrinsic_wo_chain:{ *:[v4i32] } 463:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 450:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SQDMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 39153 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLv4i16_v4i32, |
| 39154 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 39155 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 39156 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 39157 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 39158 | GIR_EraseFromParent, /*InsnID*/0, |
| 39159 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39160 | // GIR_Coverage, 1463, |
| 39161 | GIR_Done, |
| 39162 | // Label 2157: @99198 |
| 39163 | GIM_Try, /*On fail goto*//*Label 2158*/ 99282, // Rule ID 1465 // |
| 39164 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 39165 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 39166 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 39167 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 39168 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 39169 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 39170 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 39171 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39172 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 39173 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 39174 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, |
| 39175 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 39176 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 39177 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 39178 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 39179 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39180 | // (intrinsic_wo_chain:{ *:[v2i64] } 463:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 450:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SQDMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 39181 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLv2i32_v2i64, |
| 39182 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 39183 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 39184 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 39185 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 39186 | GIR_EraseFromParent, /*InsnID*/0, |
| 39187 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39188 | // GIR_Coverage, 1465, |
| 39189 | GIR_Done, |
| 39190 | // Label 2158: @99282 |
| 39191 | GIM_Try, /*On fail goto*//*Label 2159*/ 99366, // Rule ID 4130 // |
| 39192 | GIM_CheckFeatures, GIFBS_HasRDM, |
| 39193 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 39194 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 39195 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 39196 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 39197 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 39198 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 39199 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39200 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 39201 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 39202 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 39203 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 39204 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 39205 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 39206 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 39207 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39208 | // (intrinsic_wo_chain:{ *:[i32] } 446:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, (intrinsic_wo_chain:{ *:[i32] } 453:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)) => (SQRDMLAHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) |
| 39209 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLAHv1i32, |
| 39210 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 39211 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 39212 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 39213 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 39214 | GIR_EraseFromParent, /*InsnID*/0, |
| 39215 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39216 | // GIR_Coverage, 4130, |
| 39217 | GIR_Done, |
| 39218 | // Label 2159: @99366 |
| 39219 | GIM_Try, /*On fail goto*//*Label 2160*/ 99450, // Rule ID 4131 // |
| 39220 | GIM_CheckFeatures, GIFBS_HasRDM, |
| 39221 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 39222 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 39223 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 39224 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 39225 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 39226 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 39227 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39228 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 39229 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 39230 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 39231 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 39232 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 39233 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 39234 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 39235 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39236 | // (intrinsic_wo_chain:{ *:[i32] } 463:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, (intrinsic_wo_chain:{ *:[i32] } 453:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)) => (SQRDMLSHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) |
| 39237 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMLSHv1i32, |
| 39238 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 39239 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 39240 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 39241 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 39242 | GIR_EraseFromParent, /*InsnID*/0, |
| 39243 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39244 | // GIR_Coverage, 4131, |
| 39245 | GIR_Done, |
| 39246 | // Label 2160: @99450 |
| 39247 | GIM_Try, /*On fail goto*//*Label 2161*/ 99532, // Rule ID 4132 // |
| 39248 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 39249 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 39250 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 39251 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 39252 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 39253 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 39254 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39255 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 39256 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 39257 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmulls_scalar, |
| 39258 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 39259 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 39260 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 39261 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 39262 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39263 | // (intrinsic_wo_chain:{ *:[i64] } 446:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, (intrinsic_wo_chain:{ *:[i64] } 451:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)) => (SQDMLALi32:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) |
| 39264 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLALi32, |
| 39265 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 39266 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 39267 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 39268 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 39269 | GIR_EraseFromParent, /*InsnID*/0, |
| 39270 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39271 | // GIR_Coverage, 4132, |
| 39272 | GIR_Done, |
| 39273 | // Label 2161: @99532 |
| 39274 | GIM_Try, /*On fail goto*//*Label 2162*/ 99614, // Rule ID 4133 // |
| 39275 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 39276 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 39277 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 39278 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 39279 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 39280 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 39281 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39282 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 39283 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 39284 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sqdmulls_scalar, |
| 39285 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 39286 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 39287 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 39288 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 39289 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39290 | // (intrinsic_wo_chain:{ *:[i64] } 463:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, (intrinsic_wo_chain:{ *:[i64] } 451:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)) => (SQDMLSLi32:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) |
| 39291 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMLSLi32, |
| 39292 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 39293 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 39294 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 39295 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 39296 | GIR_EraseFromParent, /*InsnID*/0, |
| 39297 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39298 | // GIR_Coverage, 4133, |
| 39299 | GIR_Done, |
| 39300 | // Label 2162: @99614 |
| 39301 | GIM_Try, /*On fail goto*//*Label 2163*/ 99698, // Rule ID 7754 // |
| 39302 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 39303 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, |
| 39304 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 39305 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 39306 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 39307 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 39308 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39309 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 39310 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39311 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39312 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 39313 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 39314 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 39315 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 39316 | // MIs[2] Operand 1 |
| 39317 | // No operand predicates |
| 39318 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 39319 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39320 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 39321 | // (intrinsic_wo_chain:{ *:[v4f16] } 400:{ *:[iPTR] }, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rn) => (FMULXv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 39322 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv4i16_indexed, |
| 39323 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 39324 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 39325 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39326 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 39327 | GIR_EraseFromParent, /*InsnID*/0, |
| 39328 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39329 | // GIR_Coverage, 7754, |
| 39330 | GIR_Done, |
| 39331 | // Label 2163: @99698 |
| 39332 | GIM_Try, /*On fail goto*//*Label 2164*/ 99782, // Rule ID 7755 // |
| 39333 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 39334 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, |
| 39335 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 39336 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 39337 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 39338 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 39339 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39340 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 39341 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39342 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39343 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 39344 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 39345 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 39346 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 39347 | // MIs[2] Operand 1 |
| 39348 | // No operand predicates |
| 39349 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 39350 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39351 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 39352 | // (intrinsic_wo_chain:{ *:[v8f16] } 400:{ *:[iPTR] }, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rn) => (FMULXv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 39353 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv8i16_indexed, |
| 39354 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 39355 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 39356 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39357 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 39358 | GIR_EraseFromParent, /*InsnID*/0, |
| 39359 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39360 | // GIR_Coverage, 7755, |
| 39361 | GIR_Done, |
| 39362 | // Label 2164: @99782 |
| 39363 | GIM_Try, /*On fail goto*//*Label 2165*/ 99866, // Rule ID 7756 // |
| 39364 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 39365 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, |
| 39366 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 39367 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 39368 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 39369 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 39370 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39371 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 39372 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 39373 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39374 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 39375 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 39376 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 39377 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 39378 | // MIs[2] Operand 1 |
| 39379 | // No operand predicates |
| 39380 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 39381 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39382 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 39383 | // (intrinsic_wo_chain:{ *:[v2f32] } 400:{ *:[iPTR] }, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rn) => (FMULXv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 39384 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv2i32_indexed, |
| 39385 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 39386 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 39387 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39388 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 39389 | GIR_EraseFromParent, /*InsnID*/0, |
| 39390 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39391 | // GIR_Coverage, 7756, |
| 39392 | GIR_Done, |
| 39393 | // Label 2165: @99866 |
| 39394 | GIM_Try, /*On fail goto*//*Label 2166*/ 99950, // Rule ID 7757 // |
| 39395 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 39396 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, |
| 39397 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 39398 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 39399 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 39400 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 39401 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39402 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 39403 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 39404 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39405 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 39406 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 39407 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 39408 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 39409 | // MIs[2] Operand 1 |
| 39410 | // No operand predicates |
| 39411 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 39412 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39413 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 39414 | // (intrinsic_wo_chain:{ *:[v4f32] } 400:{ *:[iPTR] }, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rn) => (FMULXv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 39415 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv4i32_indexed, |
| 39416 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 39417 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 39418 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39419 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 39420 | GIR_EraseFromParent, /*InsnID*/0, |
| 39421 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39422 | // GIR_Coverage, 7757, |
| 39423 | GIR_Done, |
| 39424 | // Label 2166: @99950 |
| 39425 | GIM_Try, /*On fail goto*//*Label 2167*/ 100034, // Rule ID 7758 // |
| 39426 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 39427 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, |
| 39428 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 39429 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 39430 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 39431 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 39432 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39433 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE64, |
| 39434 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 39435 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39436 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 39437 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 39438 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 39439 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 39440 | // MIs[2] Operand 1 |
| 39441 | // No operand predicates |
| 39442 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 39443 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39444 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 39445 | // (intrinsic_wo_chain:{ *:[v2f64] } 400:{ *:[iPTR] }, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rn) => (FMULXv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 39446 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv2i64_indexed, |
| 39447 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 39448 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 39449 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39450 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 39451 | GIR_EraseFromParent, /*InsnID*/0, |
| 39452 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39453 | // GIR_Coverage, 7758, |
| 39454 | GIR_Done, |
| 39455 | // Label 2167: @100034 |
| 39456 | GIM_Try, /*On fail goto*//*Label 2168*/ 100118, // Rule ID 7759 // |
| 39457 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 39458 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, |
| 39459 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, |
| 39460 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 39461 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, |
| 39462 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 39463 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39464 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 39465 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39466 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39467 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 39468 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 39469 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 39470 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 39471 | // MIs[2] Operand 1 |
| 39472 | // No operand predicates |
| 39473 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, |
| 39474 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39475 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 39476 | // (intrinsic_wo_chain:{ *:[f16] } 400:{ *:[iPTR] }, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16Op:{ *:[f16] }:$Rn) => (FMULXv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 39477 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv1i16_indexed, |
| 39478 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 39479 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 39480 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39481 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 39482 | GIR_EraseFromParent, /*InsnID*/0, |
| 39483 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39484 | // GIR_Coverage, 7759, |
| 39485 | GIR_Done, |
| 39486 | // Label 2168: @100118 |
| 39487 | GIM_Try, /*On fail goto*//*Label 2169*/ 100202, // Rule ID 7760 // |
| 39488 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 39489 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, |
| 39490 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 39491 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 39492 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 39493 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 39494 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39495 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 39496 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 39497 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39498 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 39499 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 39500 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 39501 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 39502 | // MIs[2] Operand 1 |
| 39503 | // No operand predicates |
| 39504 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 39505 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39506 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 39507 | // (intrinsic_wo_chain:{ *:[f32] } 400:{ *:[iPTR] }, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32Op:{ *:[f32] }:$Rn) => (FMULXv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 39508 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv1i32_indexed, |
| 39509 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 39510 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 39511 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39512 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 39513 | GIR_EraseFromParent, /*InsnID*/0, |
| 39514 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39515 | // GIR_Coverage, 7760, |
| 39516 | GIR_Done, |
| 39517 | // Label 2169: @100202 |
| 39518 | GIM_Try, /*On fail goto*//*Label 2170*/ 100286, // Rule ID 7761 // |
| 39519 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 39520 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, |
| 39521 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 39522 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 39523 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 39524 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 39525 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39526 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 39527 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 39528 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39529 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 39530 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 39531 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 39532 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 39533 | // MIs[2] Operand 1 |
| 39534 | // No operand predicates |
| 39535 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 39536 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39537 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 39538 | // (intrinsic_wo_chain:{ *:[f64] } 400:{ *:[iPTR] }, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64Op:{ *:[f64] }:$Rn) => (FMULXv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 39539 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv1i64_indexed, |
| 39540 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 39541 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 39542 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39543 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 39544 | GIR_EraseFromParent, /*InsnID*/0, |
| 39545 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39546 | // GIR_Coverage, 7761, |
| 39547 | GIR_Done, |
| 39548 | // Label 2170: @100286 |
| 39549 | GIM_Try, /*On fail goto*//*Label 2171*/ 100370, // Rule ID 1688 // |
| 39550 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 39551 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, |
| 39552 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 39553 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 39554 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 39555 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 39556 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 39557 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39558 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 39559 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39560 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39561 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 39562 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 39563 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 39564 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 39565 | // MIs[2] Operand 1 |
| 39566 | // No operand predicates |
| 39567 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39568 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 39569 | // (intrinsic_wo_chain:{ *:[v4f16] } 400:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMULXv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 39570 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv4i16_indexed, |
| 39571 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 39572 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 39573 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39574 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 39575 | GIR_EraseFromParent, /*InsnID*/0, |
| 39576 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39577 | // GIR_Coverage, 1688, |
| 39578 | GIR_Done, |
| 39579 | // Label 2171: @100370 |
| 39580 | GIM_Try, /*On fail goto*//*Label 2172*/ 100454, // Rule ID 1689 // |
| 39581 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 39582 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, |
| 39583 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 39584 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 39585 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 39586 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 39587 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 39588 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39589 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 39590 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39591 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39592 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 39593 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 39594 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 39595 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 39596 | // MIs[2] Operand 1 |
| 39597 | // No operand predicates |
| 39598 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39599 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 39600 | // (intrinsic_wo_chain:{ *:[v8f16] } 400:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMULXv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 39601 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv8i16_indexed, |
| 39602 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 39603 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 39604 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39605 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 39606 | GIR_EraseFromParent, /*InsnID*/0, |
| 39607 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39608 | // GIR_Coverage, 1689, |
| 39609 | GIR_Done, |
| 39610 | // Label 2172: @100454 |
| 39611 | GIM_Try, /*On fail goto*//*Label 2173*/ 100538, // Rule ID 1704 // |
| 39612 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 39613 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, |
| 39614 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 39615 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 39616 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 39617 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 39618 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 39619 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39620 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 39621 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39622 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39623 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 39624 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 39625 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 39626 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 39627 | // MIs[2] Operand 1 |
| 39628 | // No operand predicates |
| 39629 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39630 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 39631 | // (intrinsic_wo_chain:{ *:[v4i16] } 447:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (SQDMULHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 39632 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv4i16_indexed, |
| 39633 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 39634 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 39635 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39636 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 39637 | GIR_EraseFromParent, /*InsnID*/0, |
| 39638 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39639 | // GIR_Coverage, 1704, |
| 39640 | GIR_Done, |
| 39641 | // Label 2173: @100538 |
| 39642 | GIM_Try, /*On fail goto*//*Label 2174*/ 100622, // Rule ID 1705 // |
| 39643 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 39644 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, |
| 39645 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 39646 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 39647 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 39648 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 39649 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 39650 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39651 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 39652 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39653 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39654 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 39655 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 39656 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 39657 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 39658 | // MIs[2] Operand 1 |
| 39659 | // No operand predicates |
| 39660 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39661 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 39662 | // (intrinsic_wo_chain:{ *:[v8i16] } 447:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (SQDMULHv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 39663 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv8i16_indexed, |
| 39664 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 39665 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 39666 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39667 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 39668 | GIR_EraseFromParent, /*InsnID*/0, |
| 39669 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39670 | // GIR_Coverage, 1705, |
| 39671 | GIR_Done, |
| 39672 | // Label 2174: @100622 |
| 39673 | GIM_Try, /*On fail goto*//*Label 2175*/ 100706, // Rule ID 1709 // |
| 39674 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 39675 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 39676 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 39677 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 39678 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 39679 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 39680 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 39681 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39682 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 39683 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39684 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39685 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 39686 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 39687 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 39688 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 39689 | // MIs[2] Operand 1 |
| 39690 | // No operand predicates |
| 39691 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39692 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 39693 | // (intrinsic_wo_chain:{ *:[v4i16] } 453:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (SQRDMULHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 39694 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv4i16_indexed, |
| 39695 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 39696 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 39697 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39698 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 39699 | GIR_EraseFromParent, /*InsnID*/0, |
| 39700 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39701 | // GIR_Coverage, 1709, |
| 39702 | GIR_Done, |
| 39703 | // Label 2175: @100706 |
| 39704 | GIM_Try, /*On fail goto*//*Label 2176*/ 100790, // Rule ID 1710 // |
| 39705 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 39706 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 39707 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 39708 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 39709 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 39710 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 39711 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 39712 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39713 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 39714 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39715 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39716 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 39717 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 39718 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 39719 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 39720 | // MIs[2] Operand 1 |
| 39721 | // No operand predicates |
| 39722 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39723 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 39724 | // (intrinsic_wo_chain:{ *:[v8i16] } 453:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (SQRDMULHv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 39725 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv8i16_indexed, |
| 39726 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 39727 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 39728 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39729 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 39730 | GIR_EraseFromParent, /*InsnID*/0, |
| 39731 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39732 | // GIR_Coverage, 1710, |
| 39733 | GIR_Done, |
| 39734 | // Label 2176: @100790 |
| 39735 | GIM_Try, /*On fail goto*//*Label 2177*/ 100874, // Rule ID 1726 // |
| 39736 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 39737 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smull, |
| 39738 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 39739 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 39740 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 39741 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 39742 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 39743 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39744 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 39745 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39746 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39747 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 39748 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 39749 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 39750 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 39751 | // MIs[2] Operand 1 |
| 39752 | // No operand predicates |
| 39753 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39754 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 39755 | // (intrinsic_wo_chain:{ *:[v4i32] } 444:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (SMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 39756 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMULLv4i16_indexed, |
| 39757 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 39758 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 39759 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39760 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 39761 | GIR_EraseFromParent, /*InsnID*/0, |
| 39762 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39763 | // GIR_Coverage, 1726, |
| 39764 | GIR_Done, |
| 39765 | // Label 2177: @100874 |
| 39766 | GIM_Try, /*On fail goto*//*Label 2178*/ 100958, // Rule ID 1750 // |
| 39767 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 39768 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, |
| 39769 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 39770 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 39771 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 39772 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 39773 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 39774 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39775 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 39776 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39777 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39778 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 39779 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 39780 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 39781 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 39782 | // MIs[2] Operand 1 |
| 39783 | // No operand predicates |
| 39784 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39785 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 39786 | // (intrinsic_wo_chain:{ *:[v4i32] } 450:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (SQDMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 39787 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULLv4i16_indexed, |
| 39788 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 39789 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 39790 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39791 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 39792 | GIR_EraseFromParent, /*InsnID*/0, |
| 39793 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39794 | // GIR_Coverage, 1750, |
| 39795 | GIR_Done, |
| 39796 | // Label 2178: @100958 |
| 39797 | GIM_Try, /*On fail goto*//*Label 2179*/ 101042, // Rule ID 1762 // |
| 39798 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 39799 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umull, |
| 39800 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 39801 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 39802 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 39803 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 39804 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 39805 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39806 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 39807 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39808 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39809 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 39810 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 39811 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 39812 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 39813 | // MIs[2] Operand 1 |
| 39814 | // No operand predicates |
| 39815 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39816 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 39817 | // (intrinsic_wo_chain:{ *:[v4i32] } 503:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (UMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 39818 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMULLv4i16_indexed, |
| 39819 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 39820 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 39821 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39822 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 39823 | GIR_EraseFromParent, /*InsnID*/0, |
| 39824 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39825 | // GIR_Coverage, 1762, |
| 39826 | GIR_Done, |
| 39827 | // Label 2179: @101042 |
| 39828 | GIM_Try, /*On fail goto*//*Label 2180*/ 101126, // Rule ID 1690 // |
| 39829 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 39830 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, |
| 39831 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 39832 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 39833 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 39834 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 39835 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 39836 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39837 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 39838 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 39839 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39840 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 39841 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 39842 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 39843 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 39844 | // MIs[2] Operand 1 |
| 39845 | // No operand predicates |
| 39846 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39847 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 39848 | // (intrinsic_wo_chain:{ *:[v2f32] } 400:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (FMULXv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 39849 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv2i32_indexed, |
| 39850 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 39851 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 39852 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39853 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 39854 | GIR_EraseFromParent, /*InsnID*/0, |
| 39855 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39856 | // GIR_Coverage, 1690, |
| 39857 | GIR_Done, |
| 39858 | // Label 2180: @101126 |
| 39859 | GIM_Try, /*On fail goto*//*Label 2181*/ 101210, // Rule ID 1691 // |
| 39860 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 39861 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, |
| 39862 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 39863 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 39864 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 39865 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 39866 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 39867 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39868 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 39869 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 39870 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39871 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 39872 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 39873 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 39874 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 39875 | // MIs[2] Operand 1 |
| 39876 | // No operand predicates |
| 39877 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39878 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 39879 | // (intrinsic_wo_chain:{ *:[v4f32] } 400:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (FMULXv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 39880 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv4i32_indexed, |
| 39881 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 39882 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 39883 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39884 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 39885 | GIR_EraseFromParent, /*InsnID*/0, |
| 39886 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39887 | // GIR_Coverage, 1691, |
| 39888 | GIR_Done, |
| 39889 | // Label 2181: @101210 |
| 39890 | GIM_Try, /*On fail goto*//*Label 2182*/ 101294, // Rule ID 1706 // |
| 39891 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 39892 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, |
| 39893 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 39894 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 39895 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 39896 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 39897 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 39898 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39899 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 39900 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 39901 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39902 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 39903 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 39904 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 39905 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 39906 | // MIs[2] Operand 1 |
| 39907 | // No operand predicates |
| 39908 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39909 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 39910 | // (intrinsic_wo_chain:{ *:[v2i32] } 447:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (SQDMULHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 39911 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv2i32_indexed, |
| 39912 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 39913 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 39914 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39915 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 39916 | GIR_EraseFromParent, /*InsnID*/0, |
| 39917 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39918 | // GIR_Coverage, 1706, |
| 39919 | GIR_Done, |
| 39920 | // Label 2182: @101294 |
| 39921 | GIM_Try, /*On fail goto*//*Label 2183*/ 101378, // Rule ID 1707 // |
| 39922 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 39923 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, |
| 39924 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 39925 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 39926 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 39927 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 39928 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 39929 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39930 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 39931 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 39932 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39933 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 39934 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 39935 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 39936 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 39937 | // MIs[2] Operand 1 |
| 39938 | // No operand predicates |
| 39939 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39940 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 39941 | // (intrinsic_wo_chain:{ *:[v4i32] } 447:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (SQDMULHv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 39942 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv4i32_indexed, |
| 39943 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 39944 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 39945 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39946 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 39947 | GIR_EraseFromParent, /*InsnID*/0, |
| 39948 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39949 | // GIR_Coverage, 1707, |
| 39950 | GIR_Done, |
| 39951 | // Label 2183: @101378 |
| 39952 | GIM_Try, /*On fail goto*//*Label 2184*/ 101462, // Rule ID 1711 // |
| 39953 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 39954 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 39955 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 39956 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 39957 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 39958 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 39959 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 39960 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39961 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 39962 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 39963 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39964 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 39965 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 39966 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 39967 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 39968 | // MIs[2] Operand 1 |
| 39969 | // No operand predicates |
| 39970 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 39971 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 39972 | // (intrinsic_wo_chain:{ *:[v2i32] } 453:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (SQRDMULHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 39973 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv2i32_indexed, |
| 39974 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 39975 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 39976 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 39977 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 39978 | GIR_EraseFromParent, /*InsnID*/0, |
| 39979 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 39980 | // GIR_Coverage, 1711, |
| 39981 | GIR_Done, |
| 39982 | // Label 2184: @101462 |
| 39983 | GIM_Try, /*On fail goto*//*Label 2185*/ 101546, // Rule ID 1712 // |
| 39984 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 39985 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 39986 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 39987 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 39988 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 39989 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 39990 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 39991 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39992 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 39993 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 39994 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 39995 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 39996 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 39997 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 39998 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 39999 | // MIs[2] Operand 1 |
| 40000 | // No operand predicates |
| 40001 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40002 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 40003 | // (intrinsic_wo_chain:{ *:[v4i32] } 453:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (SQRDMULHv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 40004 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv4i32_indexed, |
| 40005 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40006 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40007 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 40008 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 40009 | GIR_EraseFromParent, /*InsnID*/0, |
| 40010 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40011 | // GIR_Coverage, 1712, |
| 40012 | GIR_Done, |
| 40013 | // Label 2185: @101546 |
| 40014 | GIM_Try, /*On fail goto*//*Label 2186*/ 101630, // Rule ID 1728 // |
| 40015 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40016 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smull, |
| 40017 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 40018 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 40019 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 40020 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 40021 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 40022 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40023 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 40024 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40025 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40026 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 40027 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 40028 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 40029 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 40030 | // MIs[2] Operand 1 |
| 40031 | // No operand predicates |
| 40032 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40033 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 40034 | // (intrinsic_wo_chain:{ *:[v2i64] } 444:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (SMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 40035 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMULLv2i32_indexed, |
| 40036 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40037 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40038 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 40039 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 40040 | GIR_EraseFromParent, /*InsnID*/0, |
| 40041 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40042 | // GIR_Coverage, 1728, |
| 40043 | GIR_Done, |
| 40044 | // Label 2186: @101630 |
| 40045 | GIM_Try, /*On fail goto*//*Label 2187*/ 101714, // Rule ID 1752 // |
| 40046 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40047 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, |
| 40048 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 40049 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 40050 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 40051 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 40052 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 40053 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40054 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 40055 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40056 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40057 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 40058 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 40059 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 40060 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 40061 | // MIs[2] Operand 1 |
| 40062 | // No operand predicates |
| 40063 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40064 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 40065 | // (intrinsic_wo_chain:{ *:[v2i64] } 450:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (SQDMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 40066 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULLv2i32_indexed, |
| 40067 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40068 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40069 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 40070 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 40071 | GIR_EraseFromParent, /*InsnID*/0, |
| 40072 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40073 | // GIR_Coverage, 1752, |
| 40074 | GIR_Done, |
| 40075 | // Label 2187: @101714 |
| 40076 | GIM_Try, /*On fail goto*//*Label 2188*/ 101798, // Rule ID 1764 // |
| 40077 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40078 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umull, |
| 40079 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 40080 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 40081 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 40082 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 40083 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 40084 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40085 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 40086 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40087 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40088 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 40089 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 40090 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 40091 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 40092 | // MIs[2] Operand 1 |
| 40093 | // No operand predicates |
| 40094 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40095 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 40096 | // (intrinsic_wo_chain:{ *:[v2i64] } 503:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (UMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 40097 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMULLv2i32_indexed, |
| 40098 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40099 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40100 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 40101 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 40102 | GIR_EraseFromParent, /*InsnID*/0, |
| 40103 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40104 | // GIR_Coverage, 1764, |
| 40105 | GIR_Done, |
| 40106 | // Label 2188: @101798 |
| 40107 | GIM_Try, /*On fail goto*//*Label 2189*/ 101882, // Rule ID 1692 // |
| 40108 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40109 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, |
| 40110 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 40111 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 40112 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 40113 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 40114 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 40115 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40116 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE64, |
| 40117 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 40118 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40119 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 40120 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 40121 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 40122 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 40123 | // MIs[2] Operand 1 |
| 40124 | // No operand predicates |
| 40125 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40126 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 40127 | // (intrinsic_wo_chain:{ *:[v2f64] } 400:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)) => (FMULXv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 40128 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv2i64_indexed, |
| 40129 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40130 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40131 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 40132 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 40133 | GIR_EraseFromParent, /*InsnID*/0, |
| 40134 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40135 | // GIR_Coverage, 1692, |
| 40136 | GIR_Done, |
| 40137 | // Label 2189: @101882 |
| 40138 | GIM_Try, /*On fail goto*//*Label 2190*/ 101966, // Rule ID 1693 // |
| 40139 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 40140 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, |
| 40141 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, |
| 40142 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 40143 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, |
| 40144 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 40145 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 40146 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40147 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 40148 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 40149 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40150 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 40151 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 40152 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 40153 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 40154 | // MIs[2] Operand 1 |
| 40155 | // No operand predicates |
| 40156 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40157 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 40158 | // (intrinsic_wo_chain:{ *:[f16] } 400:{ *:[iPTR] }, FPR16Op:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMULXv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 40159 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv1i16_indexed, |
| 40160 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40161 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40162 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 40163 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 40164 | GIR_EraseFromParent, /*InsnID*/0, |
| 40165 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40166 | // GIR_Coverage, 1693, |
| 40167 | GIR_Done, |
| 40168 | // Label 2190: @101966 |
| 40169 | GIM_Try, /*On fail goto*//*Label 2191*/ 102050, // Rule ID 1694 // |
| 40170 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40171 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, |
| 40172 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 40173 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 40174 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40175 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 40176 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 40177 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40178 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 40179 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40180 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40181 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 40182 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 40183 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 40184 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 40185 | // MIs[2] Operand 1 |
| 40186 | // No operand predicates |
| 40187 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40188 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 40189 | // (intrinsic_wo_chain:{ *:[f32] } 400:{ *:[iPTR] }, FPR32Op:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (FMULXv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 40190 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv1i32_indexed, |
| 40191 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40192 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40193 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 40194 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 40195 | GIR_EraseFromParent, /*InsnID*/0, |
| 40196 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40197 | // GIR_Coverage, 1694, |
| 40198 | GIR_Done, |
| 40199 | // Label 2191: @102050 |
| 40200 | GIM_Try, /*On fail goto*//*Label 2192*/ 102134, // Rule ID 1695 // |
| 40201 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40202 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, |
| 40203 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 40204 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 40205 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 40206 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 40207 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 40208 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40209 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 40210 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 40211 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40212 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 40213 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 40214 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 40215 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 40216 | // MIs[2] Operand 1 |
| 40217 | // No operand predicates |
| 40218 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40219 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 40220 | // (intrinsic_wo_chain:{ *:[f64] } 400:{ *:[iPTR] }, FPR64Op:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)) => (FMULXv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 40221 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv1i64_indexed, |
| 40222 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40223 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40224 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 40225 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 40226 | GIR_EraseFromParent, /*InsnID*/0, |
| 40227 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40228 | // GIR_Coverage, 1695, |
| 40229 | GIR_Done, |
| 40230 | // Label 2192: @102134 |
| 40231 | GIM_Try, /*On fail goto*//*Label 2193*/ 102218, // Rule ID 1708 // |
| 40232 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40233 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, |
| 40234 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 40235 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 40236 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40237 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 40238 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 40239 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40240 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 40241 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40242 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40243 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 40244 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 40245 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 40246 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 40247 | // MIs[2] Operand 1 |
| 40248 | // No operand predicates |
| 40249 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40250 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 40251 | // (intrinsic_wo_chain:{ *:[i32] } 447:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (SQDMULHv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 40252 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv1i32_indexed, |
| 40253 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40254 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40255 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 40256 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 40257 | GIR_EraseFromParent, /*InsnID*/0, |
| 40258 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40259 | // GIR_Coverage, 1708, |
| 40260 | GIR_Done, |
| 40261 | // Label 2193: @102218 |
| 40262 | GIM_Try, /*On fail goto*//*Label 2194*/ 102302, // Rule ID 1713 // |
| 40263 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40264 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 40265 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 40266 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 40267 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40268 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 40269 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 40270 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40271 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 40272 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40273 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40274 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 40275 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 40276 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 40277 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 40278 | // MIs[2] Operand 1 |
| 40279 | // No operand predicates |
| 40280 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40281 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 40282 | // (intrinsic_wo_chain:{ *:[i32] } 453:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (SQRDMULHv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 40283 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv1i32_indexed, |
| 40284 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40285 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40286 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 40287 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 40288 | GIR_EraseFromParent, /*InsnID*/0, |
| 40289 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40290 | // GIR_Coverage, 1713, |
| 40291 | GIR_Done, |
| 40292 | // Label 2194: @102302 |
| 40293 | GIM_Try, /*On fail goto*//*Label 2195*/ 102384, // Rule ID 4703 // |
| 40294 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulls_scalar, |
| 40295 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 40296 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 40297 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40298 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 40299 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 40300 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40301 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 40302 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40303 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40304 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 40305 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 40306 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 40307 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 40308 | // MIs[2] Operand 1 |
| 40309 | // No operand predicates |
| 40310 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40311 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 40312 | // (intrinsic_wo_chain:{ *:[i64] } 451:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Vm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (SQDMULLv1i64_indexed:{ *:[i64] } FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Vm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 40313 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULLv1i64_indexed, |
| 40314 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40315 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40316 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 40317 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 40318 | GIR_EraseFromParent, /*InsnID*/0, |
| 40319 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40320 | // GIR_Coverage, 4703, |
| 40321 | GIR_Done, |
| 40322 | // Label 2195: @102384 |
| 40323 | GIM_Try, /*On fail goto*//*Label 2196*/ 102443, // Rule ID 1767 // |
| 40324 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40325 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn, |
| 40326 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 40327 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 40328 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40329 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 40330 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 40331 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40332 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40333 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, |
| 40334 | // MIs[1] Operand 1 |
| 40335 | // No operand predicates |
| 40336 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40337 | // (intrinsic_wo_chain:{ *:[i32] } 457:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (SQRSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40338 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNs, |
| 40339 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40340 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40341 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40342 | GIR_EraseFromParent, /*InsnID*/0, |
| 40343 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40344 | // GIR_Coverage, 1767, |
| 40345 | GIR_Done, |
| 40346 | // Label 2196: @102443 |
| 40347 | GIM_Try, /*On fail goto*//*Label 2197*/ 102502, // Rule ID 1768 // |
| 40348 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40349 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun, |
| 40350 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 40351 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 40352 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40353 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 40354 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 40355 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40356 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40357 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, |
| 40358 | // MIs[1] Operand 1 |
| 40359 | // No operand predicates |
| 40360 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40361 | // (intrinsic_wo_chain:{ *:[i32] } 458:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (SQRSHRUNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40362 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNs, |
| 40363 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40364 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40365 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40366 | GIR_EraseFromParent, /*InsnID*/0, |
| 40367 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40368 | // GIR_Coverage, 1768, |
| 40369 | GIR_Done, |
| 40370 | // Label 2197: @102502 |
| 40371 | GIM_Try, /*On fail goto*//*Label 2198*/ 102561, // Rule ID 1773 // |
| 40372 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40373 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrn, |
| 40374 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 40375 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 40376 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40377 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 40378 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 40379 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40380 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40381 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, |
| 40382 | // MIs[1] Operand 1 |
| 40383 | // No operand predicates |
| 40384 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40385 | // (intrinsic_wo_chain:{ *:[i32] } 461:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (SQSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40386 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNs, |
| 40387 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40388 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40389 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40390 | GIR_EraseFromParent, /*InsnID*/0, |
| 40391 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40392 | // GIR_Coverage, 1773, |
| 40393 | GIR_Done, |
| 40394 | // Label 2198: @102561 |
| 40395 | GIM_Try, /*On fail goto*//*Label 2199*/ 102620, // Rule ID 1774 // |
| 40396 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40397 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrun, |
| 40398 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 40399 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 40400 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40401 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 40402 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 40403 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40404 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40405 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, |
| 40406 | // MIs[1] Operand 1 |
| 40407 | // No operand predicates |
| 40408 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40409 | // (intrinsic_wo_chain:{ *:[i32] } 462:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (SQSHRUNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40410 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNs, |
| 40411 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40412 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40413 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40414 | GIR_EraseFromParent, /*InsnID*/0, |
| 40415 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40416 | // GIR_Coverage, 1774, |
| 40417 | GIR_Done, |
| 40418 | // Label 2199: @102620 |
| 40419 | GIM_Try, /*On fail goto*//*Label 2200*/ 102679, // Rule ID 1779 // |
| 40420 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40421 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn, |
| 40422 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 40423 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 40424 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40425 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 40426 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 40427 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40428 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40429 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, |
| 40430 | // MIs[1] Operand 1 |
| 40431 | // No operand predicates |
| 40432 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40433 | // (intrinsic_wo_chain:{ *:[i32] } 506:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (UQRSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40434 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNs, |
| 40435 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40436 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40437 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40438 | GIR_EraseFromParent, /*InsnID*/0, |
| 40439 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40440 | // GIR_Coverage, 1779, |
| 40441 | GIR_Done, |
| 40442 | // Label 2200: @102679 |
| 40443 | GIM_Try, /*On fail goto*//*Label 2201*/ 102738, // Rule ID 1782 // |
| 40444 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40445 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshrn, |
| 40446 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 40447 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 40448 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40449 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 40450 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 40451 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40452 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40453 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, |
| 40454 | // MIs[1] Operand 1 |
| 40455 | // No operand predicates |
| 40456 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40457 | // (intrinsic_wo_chain:{ *:[i32] } 508:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (UQSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40458 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNs, |
| 40459 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40460 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40461 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40462 | GIR_EraseFromParent, /*InsnID*/0, |
| 40463 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40464 | // GIR_Coverage, 1782, |
| 40465 | GIR_Done, |
| 40466 | // Label 2201: @102738 |
| 40467 | GIM_Try, /*On fail goto*//*Label 2202*/ 102797, // Rule ID 1802 // |
| 40468 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40469 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rshrn, |
| 40470 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 40471 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 40472 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40473 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 40474 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 40475 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40476 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40477 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, |
| 40478 | // MIs[1] Operand 1 |
| 40479 | // No operand predicates |
| 40480 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40481 | // (intrinsic_wo_chain:{ *:[v8i8] } 424:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) => (RSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40482 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv8i8_shift, |
| 40483 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40484 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40485 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40486 | GIR_EraseFromParent, /*InsnID*/0, |
| 40487 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40488 | // GIR_Coverage, 1802, |
| 40489 | GIR_Done, |
| 40490 | // Label 2202: @102797 |
| 40491 | GIM_Try, /*On fail goto*//*Label 2203*/ 102856, // Rule ID 1803 // |
| 40492 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40493 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rshrn, |
| 40494 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 40495 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 40496 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40497 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 40498 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 40499 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40500 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40501 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, |
| 40502 | // MIs[1] Operand 1 |
| 40503 | // No operand predicates |
| 40504 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40505 | // (intrinsic_wo_chain:{ *:[v4i16] } 424:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) => (RSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40506 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv4i16_shift, |
| 40507 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40508 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40509 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40510 | GIR_EraseFromParent, /*InsnID*/0, |
| 40511 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40512 | // GIR_Coverage, 1803, |
| 40513 | GIR_Done, |
| 40514 | // Label 2203: @102856 |
| 40515 | GIM_Try, /*On fail goto*//*Label 2204*/ 102915, // Rule ID 1804 // |
| 40516 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40517 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rshrn, |
| 40518 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 40519 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 40520 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40521 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 40522 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 40523 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40524 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40525 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, |
| 40526 | // MIs[1] Operand 1 |
| 40527 | // No operand predicates |
| 40528 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40529 | // (intrinsic_wo_chain:{ *:[v2i32] } 424:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) => (RSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40530 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSHRNv2i32_shift, |
| 40531 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40532 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40533 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40534 | GIR_EraseFromParent, /*InsnID*/0, |
| 40535 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40536 | // GIR_Coverage, 1804, |
| 40537 | GIR_Done, |
| 40538 | // Label 2204: @102915 |
| 40539 | GIM_Try, /*On fail goto*//*Label 2205*/ 102974, // Rule ID 1822 // |
| 40540 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40541 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn, |
| 40542 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 40543 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 40544 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40545 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 40546 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 40547 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40548 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40549 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, |
| 40550 | // MIs[1] Operand 1 |
| 40551 | // No operand predicates |
| 40552 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40553 | // (intrinsic_wo_chain:{ *:[v8i8] } 457:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) => (SQRSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40554 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv8i8_shift, |
| 40555 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40556 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40557 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40558 | GIR_EraseFromParent, /*InsnID*/0, |
| 40559 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40560 | // GIR_Coverage, 1822, |
| 40561 | GIR_Done, |
| 40562 | // Label 2205: @102974 |
| 40563 | GIM_Try, /*On fail goto*//*Label 2206*/ 103033, // Rule ID 1823 // |
| 40564 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40565 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn, |
| 40566 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 40567 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 40568 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40569 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 40570 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 40571 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40572 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40573 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, |
| 40574 | // MIs[1] Operand 1 |
| 40575 | // No operand predicates |
| 40576 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40577 | // (intrinsic_wo_chain:{ *:[v4i16] } 457:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) => (SQRSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40578 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv4i16_shift, |
| 40579 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40580 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40581 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40582 | GIR_EraseFromParent, /*InsnID*/0, |
| 40583 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40584 | // GIR_Coverage, 1823, |
| 40585 | GIR_Done, |
| 40586 | // Label 2206: @103033 |
| 40587 | GIM_Try, /*On fail goto*//*Label 2207*/ 103092, // Rule ID 1824 // |
| 40588 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40589 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrn, |
| 40590 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 40591 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 40592 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40593 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 40594 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 40595 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40596 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40597 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, |
| 40598 | // MIs[1] Operand 1 |
| 40599 | // No operand predicates |
| 40600 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40601 | // (intrinsic_wo_chain:{ *:[v2i32] } 457:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) => (SQRSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40602 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRNv2i32_shift, |
| 40603 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40604 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40605 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40606 | GIR_EraseFromParent, /*InsnID*/0, |
| 40607 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40608 | // GIR_Coverage, 1824, |
| 40609 | GIR_Done, |
| 40610 | // Label 2207: @103092 |
| 40611 | GIM_Try, /*On fail goto*//*Label 2208*/ 103151, // Rule ID 1825 // |
| 40612 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40613 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun, |
| 40614 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 40615 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 40616 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40617 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 40618 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 40619 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40620 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40621 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, |
| 40622 | // MIs[1] Operand 1 |
| 40623 | // No operand predicates |
| 40624 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40625 | // (intrinsic_wo_chain:{ *:[v8i8] } 458:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) => (SQRSHRUNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40626 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv8i8_shift, |
| 40627 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40628 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40629 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40630 | GIR_EraseFromParent, /*InsnID*/0, |
| 40631 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40632 | // GIR_Coverage, 1825, |
| 40633 | GIR_Done, |
| 40634 | // Label 2208: @103151 |
| 40635 | GIM_Try, /*On fail goto*//*Label 2209*/ 103210, // Rule ID 1826 // |
| 40636 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40637 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun, |
| 40638 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 40639 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 40640 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40641 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 40642 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 40643 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40644 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40645 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, |
| 40646 | // MIs[1] Operand 1 |
| 40647 | // No operand predicates |
| 40648 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40649 | // (intrinsic_wo_chain:{ *:[v4i16] } 458:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) => (SQRSHRUNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40650 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv4i16_shift, |
| 40651 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40652 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40653 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40654 | GIR_EraseFromParent, /*InsnID*/0, |
| 40655 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40656 | // GIR_Coverage, 1826, |
| 40657 | GIR_Done, |
| 40658 | // Label 2209: @103210 |
| 40659 | GIM_Try, /*On fail goto*//*Label 2210*/ 103269, // Rule ID 1827 // |
| 40660 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40661 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshrun, |
| 40662 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 40663 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 40664 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40665 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 40666 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 40667 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40668 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40669 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, |
| 40670 | // MIs[1] Operand 1 |
| 40671 | // No operand predicates |
| 40672 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40673 | // (intrinsic_wo_chain:{ *:[v2i32] } 458:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) => (SQRSHRUNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40674 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHRUNv2i32_shift, |
| 40675 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40676 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40677 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40678 | GIR_EraseFromParent, /*InsnID*/0, |
| 40679 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40680 | // GIR_Coverage, 1827, |
| 40681 | GIR_Done, |
| 40682 | // Label 2210: @103269 |
| 40683 | GIM_Try, /*On fail goto*//*Label 2211*/ 103328, // Rule ID 1842 // |
| 40684 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40685 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrn, |
| 40686 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 40687 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 40688 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40689 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 40690 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 40691 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40692 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40693 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, |
| 40694 | // MIs[1] Operand 1 |
| 40695 | // No operand predicates |
| 40696 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40697 | // (intrinsic_wo_chain:{ *:[v8i8] } 461:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) => (SQSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40698 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv8i8_shift, |
| 40699 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40700 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40701 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40702 | GIR_EraseFromParent, /*InsnID*/0, |
| 40703 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40704 | // GIR_Coverage, 1842, |
| 40705 | GIR_Done, |
| 40706 | // Label 2211: @103328 |
| 40707 | GIM_Try, /*On fail goto*//*Label 2212*/ 103387, // Rule ID 1843 // |
| 40708 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40709 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrn, |
| 40710 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 40711 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 40712 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40713 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 40714 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 40715 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40716 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40717 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, |
| 40718 | // MIs[1] Operand 1 |
| 40719 | // No operand predicates |
| 40720 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40721 | // (intrinsic_wo_chain:{ *:[v4i16] } 461:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) => (SQSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40722 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv4i16_shift, |
| 40723 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40724 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40725 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40726 | GIR_EraseFromParent, /*InsnID*/0, |
| 40727 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40728 | // GIR_Coverage, 1843, |
| 40729 | GIR_Done, |
| 40730 | // Label 2212: @103387 |
| 40731 | GIM_Try, /*On fail goto*//*Label 2213*/ 103446, // Rule ID 1844 // |
| 40732 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40733 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrn, |
| 40734 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 40735 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 40736 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40737 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 40738 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 40739 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40740 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40741 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, |
| 40742 | // MIs[1] Operand 1 |
| 40743 | // No operand predicates |
| 40744 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40745 | // (intrinsic_wo_chain:{ *:[v2i32] } 461:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) => (SQSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40746 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRNv2i32_shift, |
| 40747 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40748 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40749 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40750 | GIR_EraseFromParent, /*InsnID*/0, |
| 40751 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40752 | // GIR_Coverage, 1844, |
| 40753 | GIR_Done, |
| 40754 | // Label 2213: @103446 |
| 40755 | GIM_Try, /*On fail goto*//*Label 2214*/ 103505, // Rule ID 1845 // |
| 40756 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40757 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrun, |
| 40758 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 40759 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 40760 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40761 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 40762 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 40763 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40764 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40765 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, |
| 40766 | // MIs[1] Operand 1 |
| 40767 | // No operand predicates |
| 40768 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40769 | // (intrinsic_wo_chain:{ *:[v8i8] } 462:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) => (SQSHRUNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40770 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv8i8_shift, |
| 40771 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40772 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40773 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40774 | GIR_EraseFromParent, /*InsnID*/0, |
| 40775 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40776 | // GIR_Coverage, 1845, |
| 40777 | GIR_Done, |
| 40778 | // Label 2214: @103505 |
| 40779 | GIM_Try, /*On fail goto*//*Label 2215*/ 103564, // Rule ID 1846 // |
| 40780 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40781 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrun, |
| 40782 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 40783 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 40784 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40785 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 40786 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 40787 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40788 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40789 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, |
| 40790 | // MIs[1] Operand 1 |
| 40791 | // No operand predicates |
| 40792 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40793 | // (intrinsic_wo_chain:{ *:[v4i16] } 462:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) => (SQSHRUNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40794 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv4i16_shift, |
| 40795 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40796 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40797 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40798 | GIR_EraseFromParent, /*InsnID*/0, |
| 40799 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40800 | // GIR_Coverage, 1846, |
| 40801 | GIR_Done, |
| 40802 | // Label 2215: @103564 |
| 40803 | GIM_Try, /*On fail goto*//*Label 2216*/ 103623, // Rule ID 1847 // |
| 40804 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40805 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshrun, |
| 40806 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 40807 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 40808 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40809 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 40810 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 40811 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40812 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40813 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, |
| 40814 | // MIs[1] Operand 1 |
| 40815 | // No operand predicates |
| 40816 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40817 | // (intrinsic_wo_chain:{ *:[v2i32] } 462:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) => (SQSHRUNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40818 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHRUNv2i32_shift, |
| 40819 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40820 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40821 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40822 | GIR_EraseFromParent, /*InsnID*/0, |
| 40823 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40824 | // GIR_Coverage, 1847, |
| 40825 | GIR_Done, |
| 40826 | // Label 2216: @103623 |
| 40827 | GIM_Try, /*On fail goto*//*Label 2217*/ 103682, // Rule ID 1894 // |
| 40828 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40829 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn, |
| 40830 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 40831 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 40832 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40833 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 40834 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 40835 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40836 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40837 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, |
| 40838 | // MIs[1] Operand 1 |
| 40839 | // No operand predicates |
| 40840 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40841 | // (intrinsic_wo_chain:{ *:[v8i8] } 506:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) => (UQRSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40842 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv8i8_shift, |
| 40843 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40844 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40845 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40846 | GIR_EraseFromParent, /*InsnID*/0, |
| 40847 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40848 | // GIR_Coverage, 1894, |
| 40849 | GIR_Done, |
| 40850 | // Label 2217: @103682 |
| 40851 | GIM_Try, /*On fail goto*//*Label 2218*/ 103741, // Rule ID 1895 // |
| 40852 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40853 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn, |
| 40854 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 40855 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 40856 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40857 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 40858 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 40859 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40860 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40861 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, |
| 40862 | // MIs[1] Operand 1 |
| 40863 | // No operand predicates |
| 40864 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40865 | // (intrinsic_wo_chain:{ *:[v4i16] } 506:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) => (UQRSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40866 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv4i16_shift, |
| 40867 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40868 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40869 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40870 | GIR_EraseFromParent, /*InsnID*/0, |
| 40871 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40872 | // GIR_Coverage, 1895, |
| 40873 | GIR_Done, |
| 40874 | // Label 2218: @103741 |
| 40875 | GIM_Try, /*On fail goto*//*Label 2219*/ 103800, // Rule ID 1896 // |
| 40876 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40877 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshrn, |
| 40878 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 40879 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 40880 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40881 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 40882 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 40883 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40884 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40885 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, |
| 40886 | // MIs[1] Operand 1 |
| 40887 | // No operand predicates |
| 40888 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40889 | // (intrinsic_wo_chain:{ *:[v2i32] } 506:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) => (UQRSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40890 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHRNv2i32_shift, |
| 40891 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40892 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40893 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40894 | GIR_EraseFromParent, /*InsnID*/0, |
| 40895 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40896 | // GIR_Coverage, 1896, |
| 40897 | GIR_Done, |
| 40898 | // Label 2219: @103800 |
| 40899 | GIM_Try, /*On fail goto*//*Label 2220*/ 103859, // Rule ID 1904 // |
| 40900 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40901 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshrn, |
| 40902 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 40903 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 40904 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40905 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 40906 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 40907 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40908 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40909 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, |
| 40910 | // MIs[1] Operand 1 |
| 40911 | // No operand predicates |
| 40912 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40913 | // (intrinsic_wo_chain:{ *:[v8i8] } 508:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) => (UQSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40914 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv8i8_shift, |
| 40915 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40916 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40917 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40918 | GIR_EraseFromParent, /*InsnID*/0, |
| 40919 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40920 | // GIR_Coverage, 1904, |
| 40921 | GIR_Done, |
| 40922 | // Label 2220: @103859 |
| 40923 | GIM_Try, /*On fail goto*//*Label 2221*/ 103918, // Rule ID 1905 // |
| 40924 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40925 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshrn, |
| 40926 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 40927 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 40928 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40929 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 40930 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 40931 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40932 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40933 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, |
| 40934 | // MIs[1] Operand 1 |
| 40935 | // No operand predicates |
| 40936 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40937 | // (intrinsic_wo_chain:{ *:[v4i16] } 508:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) => (UQSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40938 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv4i16_shift, |
| 40939 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40940 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40941 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40942 | GIR_EraseFromParent, /*InsnID*/0, |
| 40943 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40944 | // GIR_Coverage, 1905, |
| 40945 | GIR_Done, |
| 40946 | // Label 2221: @103918 |
| 40947 | GIM_Try, /*On fail goto*//*Label 2222*/ 103977, // Rule ID 1906 // |
| 40948 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 40949 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshrn, |
| 40950 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 40951 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 40952 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40953 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 40954 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 40955 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40956 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40957 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, |
| 40958 | // MIs[1] Operand 1 |
| 40959 | // No operand predicates |
| 40960 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40961 | // (intrinsic_wo_chain:{ *:[v2i32] } 508:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) => (UQSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 40962 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHRNv2i32_shift, |
| 40963 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40964 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40965 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40966 | GIR_EraseFromParent, /*InsnID*/0, |
| 40967 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40968 | // GIR_Coverage, 1906, |
| 40969 | GIR_Done, |
| 40970 | // Label 2222: @103977 |
| 40971 | GIM_Try, /*On fail goto*//*Label 2223*/ 104034, // Rule ID 4704 // |
| 40972 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, |
| 40973 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 40974 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 40975 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40976 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 40977 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 40978 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 40979 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 40980 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, |
| 40981 | // MIs[1] Operand 1 |
| 40982 | // No operand predicates |
| 40983 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 40984 | // (intrinsic_wo_chain:{ *:[i32] } 527:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (FCVTZSs:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) |
| 40985 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSs, |
| 40986 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 40987 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 40988 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 40989 | GIR_EraseFromParent, /*InsnID*/0, |
| 40990 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 40991 | // GIR_Coverage, 4704, |
| 40992 | GIR_Done, |
| 40993 | // Label 2223: @104034 |
| 40994 | GIM_Try, /*On fail goto*//*Label 2224*/ 104091, // Rule ID 4705 // |
| 40995 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, |
| 40996 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 40997 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 40998 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 40999 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 41000 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 41001 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41002 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41003 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, |
| 41004 | // MIs[1] Operand 1 |
| 41005 | // No operand predicates |
| 41006 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41007 | // (intrinsic_wo_chain:{ *:[i32] } 528:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (FCVTZUs:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) |
| 41008 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUs, |
| 41009 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41010 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41011 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41012 | GIR_EraseFromParent, /*InsnID*/0, |
| 41013 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41014 | // GIR_Coverage, 4705, |
| 41015 | GIR_Done, |
| 41016 | // Label 2224: @104091 |
| 41017 | GIM_Try, /*On fail goto*//*Label 2225*/ 104148, // Rule ID 4706 // |
| 41018 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, |
| 41019 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 41020 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 41021 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41022 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 41023 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 41024 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41025 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41026 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 41027 | // MIs[1] Operand 1 |
| 41028 | // No operand predicates |
| 41029 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41030 | // (intrinsic_wo_chain:{ *:[i64] } 527:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (FCVTZSd:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) |
| 41031 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSd, |
| 41032 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41033 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41034 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41035 | GIR_EraseFromParent, /*InsnID*/0, |
| 41036 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41037 | // GIR_Coverage, 4706, |
| 41038 | GIR_Done, |
| 41039 | // Label 2225: @104148 |
| 41040 | GIM_Try, /*On fail goto*//*Label 2226*/ 104205, // Rule ID 4707 // |
| 41041 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, |
| 41042 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 41043 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 41044 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41045 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 41046 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 41047 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41048 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41049 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 41050 | // MIs[1] Operand 1 |
| 41051 | // No operand predicates |
| 41052 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41053 | // (intrinsic_wo_chain:{ *:[i64] } 528:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (FCVTZUd:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) |
| 41054 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUd, |
| 41055 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41056 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41057 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41058 | GIR_EraseFromParent, /*InsnID*/0, |
| 41059 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41060 | // GIR_Coverage, 4707, |
| 41061 | GIR_Done, |
| 41062 | // Label 2226: @104205 |
| 41063 | GIM_Try, /*On fail goto*//*Label 2227*/ 104262, // Rule ID 4708 // |
| 41064 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, |
| 41065 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 41066 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 41067 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41068 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 41069 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 41070 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41071 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41072 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 41073 | // MIs[1] Operand 1 |
| 41074 | // No operand predicates |
| 41075 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41076 | // (intrinsic_wo_chain:{ *:[v1i64] } 527:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (FCVTZSd:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) |
| 41077 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSd, |
| 41078 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41079 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41080 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41081 | GIR_EraseFromParent, /*InsnID*/0, |
| 41082 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41083 | // GIR_Coverage, 4708, |
| 41084 | GIR_Done, |
| 41085 | // Label 2227: @104262 |
| 41086 | GIM_Try, /*On fail goto*//*Label 2228*/ 104319, // Rule ID 4709 // |
| 41087 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, |
| 41088 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 41089 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 41090 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41091 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 41092 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 41093 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41094 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41095 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 41096 | // MIs[1] Operand 1 |
| 41097 | // No operand predicates |
| 41098 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41099 | // (intrinsic_wo_chain:{ *:[v1i64] } 528:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (FCVTZUd:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) |
| 41100 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUd, |
| 41101 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41102 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41103 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41104 | GIR_EraseFromParent, /*InsnID*/0, |
| 41105 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41106 | // GIR_Coverage, 4709, |
| 41107 | GIR_Done, |
| 41108 | // Label 2228: @104319 |
| 41109 | GIM_Try, /*On fail goto*//*Label 2229*/ 104376, // Rule ID 4710 // |
| 41110 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, |
| 41111 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 41112 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 41113 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41114 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 41115 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 41116 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41117 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41118 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, |
| 41119 | // MIs[1] Operand 1 |
| 41120 | // No operand predicates |
| 41121 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41122 | // (intrinsic_wo_chain:{ *:[f32] } 531:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (UCVTFs:{ *:[f32] } FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) |
| 41123 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFs, |
| 41124 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41125 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41126 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41127 | GIR_EraseFromParent, /*InsnID*/0, |
| 41128 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41129 | // GIR_Coverage, 4710, |
| 41130 | GIR_Done, |
| 41131 | // Label 2229: @104376 |
| 41132 | GIM_Try, /*On fail goto*//*Label 2230*/ 104433, // Rule ID 4711 // |
| 41133 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, |
| 41134 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 41135 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 41136 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41137 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 41138 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 41139 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41140 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41141 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 41142 | // MIs[1] Operand 1 |
| 41143 | // No operand predicates |
| 41144 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41145 | // (intrinsic_wo_chain:{ *:[f64] } 531:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (UCVTFd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) |
| 41146 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFd, |
| 41147 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41148 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41149 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41150 | GIR_EraseFromParent, /*InsnID*/0, |
| 41151 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41152 | // GIR_Coverage, 4711, |
| 41153 | GIR_Done, |
| 41154 | // Label 2230: @104433 |
| 41155 | GIM_Try, /*On fail goto*//*Label 2231*/ 104490, // Rule ID 4712 // |
| 41156 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, |
| 41157 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 41158 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 41159 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41160 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 41161 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 41162 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41163 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41164 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 41165 | // MIs[1] Operand 1 |
| 41166 | // No operand predicates |
| 41167 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41168 | // (intrinsic_wo_chain:{ *:[v1f64] } 530:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (SCVTFd:{ *:[v1f64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) |
| 41169 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFd, |
| 41170 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41171 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41172 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41173 | GIR_EraseFromParent, /*InsnID*/0, |
| 41174 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41175 | // GIR_Coverage, 4712, |
| 41176 | GIR_Done, |
| 41177 | // Label 2231: @104490 |
| 41178 | GIM_Try, /*On fail goto*//*Label 2232*/ 104547, // Rule ID 4713 // |
| 41179 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, |
| 41180 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 41181 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 41182 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41183 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 41184 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 41185 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41186 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41187 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 41188 | // MIs[1] Operand 1 |
| 41189 | // No operand predicates |
| 41190 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41191 | // (intrinsic_wo_chain:{ *:[f64] } 530:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (SCVTFd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) |
| 41192 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFd, |
| 41193 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41194 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41195 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41196 | GIR_EraseFromParent, /*InsnID*/0, |
| 41197 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41198 | // GIR_Coverage, 4713, |
| 41199 | GIR_Done, |
| 41200 | // Label 2232: @104547 |
| 41201 | GIM_Try, /*On fail goto*//*Label 2233*/ 104604, // Rule ID 4714 // |
| 41202 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, |
| 41203 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 41204 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 41205 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41206 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 41207 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 41208 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41209 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41210 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 41211 | // MIs[1] Operand 1 |
| 41212 | // No operand predicates |
| 41213 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41214 | // (intrinsic_wo_chain:{ *:[v1f64] } 531:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (UCVTFd:{ *:[v1f64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) |
| 41215 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFd, |
| 41216 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41217 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41218 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41219 | GIR_EraseFromParent, /*InsnID*/0, |
| 41220 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41221 | // GIR_Coverage, 4714, |
| 41222 | GIR_Done, |
| 41223 | // Label 2233: @104604 |
| 41224 | GIM_Try, /*On fail goto*//*Label 2234*/ 104661, // Rule ID 4715 // |
| 41225 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, |
| 41226 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 41227 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 41228 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41229 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 41230 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 41231 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41232 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41233 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, |
| 41234 | // MIs[1] Operand 1 |
| 41235 | // No operand predicates |
| 41236 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41237 | // (intrinsic_wo_chain:{ *:[f32] } 530:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (SCVTFs:{ *:[f32] } FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) |
| 41238 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFs, |
| 41239 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41240 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41241 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41242 | GIR_EraseFromParent, /*InsnID*/0, |
| 41243 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41244 | // GIR_Coverage, 4715, |
| 41245 | GIR_Done, |
| 41246 | // Label 2234: @104661 |
| 41247 | GIM_Try, /*On fail goto*//*Label 2235*/ 104741, // Rule ID 4717 // |
| 41248 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, |
| 41249 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, |
| 41250 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 41251 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41252 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 41253 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 41254 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41255 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41256 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, |
| 41257 | // MIs[1] Operand 1 |
| 41258 | // No operand predicates |
| 41259 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41260 | // (intrinsic_wo_chain:{ *:[f16] } 530:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) => (SCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[bf16] } FPR32:{ *:[i32] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) |
| 41261 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 41262 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 41263 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 41264 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/7, // Rn |
| 41265 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR16RegClassID, |
| 41266 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR32RegClassID, |
| 41267 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFh, |
| 41268 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41269 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 41270 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41271 | GIR_EraseFromParent, /*InsnID*/0, |
| 41272 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41273 | // GIR_Coverage, 4717, |
| 41274 | GIR_Done, |
| 41275 | // Label 2235: @104741 |
| 41276 | GIM_Try, /*On fail goto*//*Label 2236*/ 104821, // Rule ID 4718 // |
| 41277 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, |
| 41278 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, |
| 41279 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 41280 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41281 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 41282 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 41283 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41284 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41285 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, |
| 41286 | // MIs[1] Operand 1 |
| 41287 | // No operand predicates |
| 41288 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41289 | // (intrinsic_wo_chain:{ *:[f16] } 530:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) => (SCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[bf16] } FPR64:{ *:[i64] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) |
| 41290 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 41291 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 41292 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 41293 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/7, // Rn |
| 41294 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR16RegClassID, |
| 41295 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR64RegClassID, |
| 41296 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFh, |
| 41297 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41298 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 41299 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41300 | GIR_EraseFromParent, /*InsnID*/0, |
| 41301 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41302 | // GIR_Coverage, 4718, |
| 41303 | GIR_Done, |
| 41304 | // Label 2236: @104821 |
| 41305 | GIM_Try, /*On fail goto*//*Label 2237*/ 104901, // Rule ID 4720 // |
| 41306 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, |
| 41307 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, |
| 41308 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 41309 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41310 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 41311 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 41312 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41313 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41314 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, |
| 41315 | // MIs[1] Operand 1 |
| 41316 | // No operand predicates |
| 41317 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41318 | // (intrinsic_wo_chain:{ *:[f16] } 531:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) => (UCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[bf16] } FPR32:{ *:[i32] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) |
| 41319 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 41320 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 41321 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 41322 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/7, // Rn |
| 41323 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR16RegClassID, |
| 41324 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR32RegClassID, |
| 41325 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFh, |
| 41326 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41327 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 41328 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41329 | GIR_EraseFromParent, /*InsnID*/0, |
| 41330 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41331 | // GIR_Coverage, 4720, |
| 41332 | GIR_Done, |
| 41333 | // Label 2237: @104901 |
| 41334 | GIM_Try, /*On fail goto*//*Label 2238*/ 104981, // Rule ID 4721 // |
| 41335 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, |
| 41336 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, |
| 41337 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 41338 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41339 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 41340 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 41341 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41342 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41343 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, |
| 41344 | // MIs[1] Operand 1 |
| 41345 | // No operand predicates |
| 41346 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41347 | // (intrinsic_wo_chain:{ *:[f16] } 531:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) => (UCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[bf16] } FPR64:{ *:[i64] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) |
| 41348 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 41349 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 41350 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 41351 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/7, // Rn |
| 41352 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR16RegClassID, |
| 41353 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR64RegClassID, |
| 41354 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFh, |
| 41355 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41356 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 41357 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41358 | GIR_EraseFromParent, /*InsnID*/0, |
| 41359 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41360 | // GIR_Coverage, 4721, |
| 41361 | GIR_Done, |
| 41362 | // Label 2238: @104981 |
| 41363 | GIM_Try, /*On fail goto*//*Label 2239*/ 105083, // Rule ID 4722 // |
| 41364 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, |
| 41365 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 41366 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 41367 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41368 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 41369 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 41370 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41371 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41372 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, |
| 41373 | // MIs[1] Operand 1 |
| 41374 | // No operand predicates |
| 41375 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41376 | // (intrinsic_wo_chain:{ *:[i32] } 527:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (FCVTZSh:{ *:[bf16] } FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), hsub:{ *:[i32] }) |
| 41377 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41378 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 41379 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::FCVTZSh, |
| 41380 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 41381 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41382 | GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm |
| 41383 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 41384 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 41385 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 41386 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41387 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 41388 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 41389 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 41390 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 41391 | GIR_AddImm, /*InsnID*/0, /*Imm*/7, |
| 41392 | GIR_EraseFromParent, /*InsnID*/0, |
| 41393 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, |
| 41394 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR32RegClassID, |
| 41395 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::FPR16RegClassID, |
| 41396 | // GIR_Coverage, 4722, |
| 41397 | GIR_Done, |
| 41398 | // Label 2239: @105083 |
| 41399 | GIM_Try, /*On fail goto*//*Label 2240*/ 105185, // Rule ID 4723 // |
| 41400 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, |
| 41401 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 41402 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 41403 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41404 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 41405 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 41406 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41407 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41408 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 41409 | // MIs[1] Operand 1 |
| 41410 | // No operand predicates |
| 41411 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41412 | // (intrinsic_wo_chain:{ *:[i64] } 527:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (FCVTZSh:{ *:[bf16] } FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), hsub:{ *:[i32] }) |
| 41413 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 41414 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 41415 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::FCVTZSh, |
| 41416 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 41417 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41418 | GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm |
| 41419 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 41420 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 41421 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 41422 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41423 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 41424 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 41425 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 41426 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 41427 | GIR_AddImm, /*InsnID*/0, /*Imm*/7, |
| 41428 | GIR_EraseFromParent, /*InsnID*/0, |
| 41429 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 41430 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR64RegClassID, |
| 41431 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::FPR16RegClassID, |
| 41432 | // GIR_Coverage, 4723, |
| 41433 | GIR_Done, |
| 41434 | // Label 2240: @105185 |
| 41435 | GIM_Try, /*On fail goto*//*Label 2241*/ 105287, // Rule ID 4724 // |
| 41436 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, |
| 41437 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 41438 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 41439 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41440 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 41441 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 41442 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41443 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41444 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, |
| 41445 | // MIs[1] Operand 1 |
| 41446 | // No operand predicates |
| 41447 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41448 | // (intrinsic_wo_chain:{ *:[i32] } 528:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (FCVTZUh:{ *:[bf16] } FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), hsub:{ *:[i32] }) |
| 41449 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41450 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 41451 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::FCVTZUh, |
| 41452 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 41453 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41454 | GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm |
| 41455 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 41456 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 41457 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 41458 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41459 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 41460 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 41461 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 41462 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 41463 | GIR_AddImm, /*InsnID*/0, /*Imm*/7, |
| 41464 | GIR_EraseFromParent, /*InsnID*/0, |
| 41465 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, |
| 41466 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR32RegClassID, |
| 41467 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::FPR16RegClassID, |
| 41468 | // GIR_Coverage, 4724, |
| 41469 | GIR_Done, |
| 41470 | // Label 2241: @105287 |
| 41471 | GIM_Try, /*On fail goto*//*Label 2242*/ 105389, // Rule ID 4725 // |
| 41472 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, |
| 41473 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 41474 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 41475 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41476 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 41477 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 41478 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41479 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41480 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 41481 | // MIs[1] Operand 1 |
| 41482 | // No operand predicates |
| 41483 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41484 | // (intrinsic_wo_chain:{ *:[i64] } 528:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (FCVTZUh:{ *:[bf16] } FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), hsub:{ *:[i32] }) |
| 41485 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 41486 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 41487 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::FCVTZUh, |
| 41488 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 41489 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41490 | GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm |
| 41491 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 41492 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 41493 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 41494 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41495 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 41496 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 41497 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 41498 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 41499 | GIR_AddImm, /*InsnID*/0, /*Imm*/7, |
| 41500 | GIR_EraseFromParent, /*InsnID*/0, |
| 41501 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 41502 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR64RegClassID, |
| 41503 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::FPR16RegClassID, |
| 41504 | // GIR_Coverage, 4725, |
| 41505 | GIR_Done, |
| 41506 | // Label 2242: @105389 |
| 41507 | GIM_Try, /*On fail goto*//*Label 2243*/ 105445, // Rule ID 1787 // |
| 41508 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 41509 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, |
| 41510 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 41511 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 41512 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41513 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 41514 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 41515 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41516 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41517 | // MIs[1] Operand 1 |
| 41518 | // No operand predicates |
| 41519 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41520 | // (intrinsic_wo_chain:{ *:[v4i16] } 527:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZSv4i16_shift:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 41521 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv4i16_shift, |
| 41522 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41523 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41524 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41525 | GIR_EraseFromParent, /*InsnID*/0, |
| 41526 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41527 | // GIR_Coverage, 1787, |
| 41528 | GIR_Done, |
| 41529 | // Label 2243: @105445 |
| 41530 | GIM_Try, /*On fail goto*//*Label 2244*/ 105501, // Rule ID 1788 // |
| 41531 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 41532 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, |
| 41533 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 41534 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 41535 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41536 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 41537 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 41538 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41539 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41540 | // MIs[1] Operand 1 |
| 41541 | // No operand predicates |
| 41542 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41543 | // (intrinsic_wo_chain:{ *:[v8i16] } 527:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZSv8i16_shift:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 41544 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv8i16_shift, |
| 41545 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41546 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41547 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41548 | GIR_EraseFromParent, /*InsnID*/0, |
| 41549 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41550 | // GIR_Coverage, 1788, |
| 41551 | GIR_Done, |
| 41552 | // Label 2244: @105501 |
| 41553 | GIM_Try, /*On fail goto*//*Label 2245*/ 105557, // Rule ID 1789 // |
| 41554 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 41555 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, |
| 41556 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 41557 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 41558 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41559 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 41560 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 41561 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41562 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41563 | // MIs[1] Operand 1 |
| 41564 | // No operand predicates |
| 41565 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41566 | // (intrinsic_wo_chain:{ *:[v2i32] } 527:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZSv2i32_shift:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 41567 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv2i32_shift, |
| 41568 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41569 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41570 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41571 | GIR_EraseFromParent, /*InsnID*/0, |
| 41572 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41573 | // GIR_Coverage, 1789, |
| 41574 | GIR_Done, |
| 41575 | // Label 2245: @105557 |
| 41576 | GIM_Try, /*On fail goto*//*Label 2246*/ 105613, // Rule ID 1790 // |
| 41577 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 41578 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, |
| 41579 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 41580 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 41581 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41582 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 41583 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 41584 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41585 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41586 | // MIs[1] Operand 1 |
| 41587 | // No operand predicates |
| 41588 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41589 | // (intrinsic_wo_chain:{ *:[v4i32] } 527:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZSv4i32_shift:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 41590 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv4i32_shift, |
| 41591 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41592 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41593 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41594 | GIR_EraseFromParent, /*InsnID*/0, |
| 41595 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41596 | // GIR_Coverage, 1790, |
| 41597 | GIR_Done, |
| 41598 | // Label 2246: @105613 |
| 41599 | GIM_Try, /*On fail goto*//*Label 2247*/ 105669, // Rule ID 1791 // |
| 41600 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 41601 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxs, |
| 41602 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 41603 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 41604 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41605 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 41606 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 41607 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41608 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41609 | // MIs[1] Operand 1 |
| 41610 | // No operand predicates |
| 41611 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41612 | // (intrinsic_wo_chain:{ *:[v2i64] } 527:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZSv2i64_shift:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 41613 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSv2i64_shift, |
| 41614 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41615 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41616 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41617 | GIR_EraseFromParent, /*InsnID*/0, |
| 41618 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41619 | // GIR_Coverage, 1791, |
| 41620 | GIR_Done, |
| 41621 | // Label 2247: @105669 |
| 41622 | GIM_Try, /*On fail goto*//*Label 2248*/ 105725, // Rule ID 1792 // |
| 41623 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 41624 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, |
| 41625 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 41626 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 41627 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41628 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 41629 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 41630 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41631 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41632 | // MIs[1] Operand 1 |
| 41633 | // No operand predicates |
| 41634 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41635 | // (intrinsic_wo_chain:{ *:[v4i16] } 528:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZUv4i16_shift:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 41636 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv4i16_shift, |
| 41637 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41638 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41639 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41640 | GIR_EraseFromParent, /*InsnID*/0, |
| 41641 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41642 | // GIR_Coverage, 1792, |
| 41643 | GIR_Done, |
| 41644 | // Label 2248: @105725 |
| 41645 | GIM_Try, /*On fail goto*//*Label 2249*/ 105781, // Rule ID 1793 // |
| 41646 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 41647 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, |
| 41648 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 41649 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 41650 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41651 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 41652 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 41653 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41654 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41655 | // MIs[1] Operand 1 |
| 41656 | // No operand predicates |
| 41657 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41658 | // (intrinsic_wo_chain:{ *:[v8i16] } 528:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZUv8i16_shift:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 41659 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv8i16_shift, |
| 41660 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41661 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41662 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41663 | GIR_EraseFromParent, /*InsnID*/0, |
| 41664 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41665 | // GIR_Coverage, 1793, |
| 41666 | GIR_Done, |
| 41667 | // Label 2249: @105781 |
| 41668 | GIM_Try, /*On fail goto*//*Label 2250*/ 105837, // Rule ID 1794 // |
| 41669 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 41670 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, |
| 41671 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 41672 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 41673 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41674 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 41675 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 41676 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41677 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41678 | // MIs[1] Operand 1 |
| 41679 | // No operand predicates |
| 41680 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41681 | // (intrinsic_wo_chain:{ *:[v2i32] } 528:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZUv2i32_shift:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 41682 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv2i32_shift, |
| 41683 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41684 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41685 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41686 | GIR_EraseFromParent, /*InsnID*/0, |
| 41687 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41688 | // GIR_Coverage, 1794, |
| 41689 | GIR_Done, |
| 41690 | // Label 2250: @105837 |
| 41691 | GIM_Try, /*On fail goto*//*Label 2251*/ 105893, // Rule ID 1795 // |
| 41692 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 41693 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, |
| 41694 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 41695 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 41696 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41697 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 41698 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 41699 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41700 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41701 | // MIs[1] Operand 1 |
| 41702 | // No operand predicates |
| 41703 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41704 | // (intrinsic_wo_chain:{ *:[v4i32] } 528:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZUv4i32_shift:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 41705 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv4i32_shift, |
| 41706 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41707 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41708 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41709 | GIR_EraseFromParent, /*InsnID*/0, |
| 41710 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41711 | // GIR_Coverage, 1795, |
| 41712 | GIR_Done, |
| 41713 | // Label 2251: @105893 |
| 41714 | GIM_Try, /*On fail goto*//*Label 2252*/ 105949, // Rule ID 1796 // |
| 41715 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 41716 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfp2fxu, |
| 41717 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 41718 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 41719 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41720 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 41721 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 41722 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41723 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41724 | // MIs[1] Operand 1 |
| 41725 | // No operand predicates |
| 41726 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41727 | // (intrinsic_wo_chain:{ *:[v2i64] } 528:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZUv2i64_shift:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 41728 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUv2i64_shift, |
| 41729 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41730 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41731 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41732 | GIR_EraseFromParent, /*InsnID*/0, |
| 41733 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41734 | // GIR_Coverage, 1796, |
| 41735 | GIR_Done, |
| 41736 | // Label 2252: @105949 |
| 41737 | GIM_Try, /*On fail goto*//*Label 2253*/ 106005, // Rule ID 1797 // |
| 41738 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 41739 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, |
| 41740 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 41741 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 41742 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41743 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 41744 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 41745 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41746 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41747 | // MIs[1] Operand 1 |
| 41748 | // No operand predicates |
| 41749 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41750 | // (intrinsic_wo_chain:{ *:[v4f16] } 530:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) => (SCVTFv4i16_shift:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 41751 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv4i16_shift, |
| 41752 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41753 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41754 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41755 | GIR_EraseFromParent, /*InsnID*/0, |
| 41756 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41757 | // GIR_Coverage, 1797, |
| 41758 | GIR_Done, |
| 41759 | // Label 2253: @106005 |
| 41760 | GIM_Try, /*On fail goto*//*Label 2254*/ 106061, // Rule ID 1798 // |
| 41761 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 41762 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, |
| 41763 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 41764 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 41765 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41766 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 41767 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 41768 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41769 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41770 | // MIs[1] Operand 1 |
| 41771 | // No operand predicates |
| 41772 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41773 | // (intrinsic_wo_chain:{ *:[v8f16] } 530:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) => (SCVTFv8i16_shift:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 41774 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv8i16_shift, |
| 41775 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41776 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41777 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41778 | GIR_EraseFromParent, /*InsnID*/0, |
| 41779 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41780 | // GIR_Coverage, 1798, |
| 41781 | GIR_Done, |
| 41782 | // Label 2254: @106061 |
| 41783 | GIM_Try, /*On fail goto*//*Label 2255*/ 106117, // Rule ID 1799 // |
| 41784 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 41785 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, |
| 41786 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 41787 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 41788 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41789 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 41790 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 41791 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41792 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41793 | // MIs[1] Operand 1 |
| 41794 | // No operand predicates |
| 41795 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41796 | // (intrinsic_wo_chain:{ *:[v2f32] } 530:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) => (SCVTFv2i32_shift:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 41797 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv2i32_shift, |
| 41798 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41799 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41800 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41801 | GIR_EraseFromParent, /*InsnID*/0, |
| 41802 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41803 | // GIR_Coverage, 1799, |
| 41804 | GIR_Done, |
| 41805 | // Label 2255: @106117 |
| 41806 | GIM_Try, /*On fail goto*//*Label 2256*/ 106173, // Rule ID 1800 // |
| 41807 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 41808 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, |
| 41809 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 41810 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 41811 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41812 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 41813 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 41814 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41815 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41816 | // MIs[1] Operand 1 |
| 41817 | // No operand predicates |
| 41818 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41819 | // (intrinsic_wo_chain:{ *:[v4f32] } 530:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) => (SCVTFv4i32_shift:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 41820 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv4i32_shift, |
| 41821 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41822 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41823 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41824 | GIR_EraseFromParent, /*InsnID*/0, |
| 41825 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41826 | // GIR_Coverage, 1800, |
| 41827 | GIR_Done, |
| 41828 | // Label 2256: @106173 |
| 41829 | GIM_Try, /*On fail goto*//*Label 2257*/ 106229, // Rule ID 1801 // |
| 41830 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 41831 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxs2fp, |
| 41832 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 41833 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 41834 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41835 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 41836 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 41837 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41838 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41839 | // MIs[1] Operand 1 |
| 41840 | // No operand predicates |
| 41841 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41842 | // (intrinsic_wo_chain:{ *:[v2f64] } 530:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) => (SCVTFv2i64_shift:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 41843 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv2i64_shift, |
| 41844 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41845 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41846 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41847 | GIR_EraseFromParent, /*InsnID*/0, |
| 41848 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41849 | // GIR_Coverage, 1801, |
| 41850 | GIR_Done, |
| 41851 | // Label 2257: @106229 |
| 41852 | GIM_Try, /*On fail goto*//*Label 2258*/ 106285, // Rule ID 1889 // |
| 41853 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 41854 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, |
| 41855 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 41856 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 41857 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41858 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 41859 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 41860 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41861 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41862 | // MIs[1] Operand 1 |
| 41863 | // No operand predicates |
| 41864 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41865 | // (intrinsic_wo_chain:{ *:[v4f16] } 531:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) => (UCVTFv4i16_shift:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 41866 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv4i16_shift, |
| 41867 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41868 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41869 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41870 | GIR_EraseFromParent, /*InsnID*/0, |
| 41871 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41872 | // GIR_Coverage, 1889, |
| 41873 | GIR_Done, |
| 41874 | // Label 2258: @106285 |
| 41875 | GIM_Try, /*On fail goto*//*Label 2259*/ 106341, // Rule ID 1890 // |
| 41876 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 41877 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, |
| 41878 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 41879 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 41880 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41881 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 41882 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 41883 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41884 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41885 | // MIs[1] Operand 1 |
| 41886 | // No operand predicates |
| 41887 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41888 | // (intrinsic_wo_chain:{ *:[v8f16] } 531:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) => (UCVTFv8i16_shift:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 41889 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv8i16_shift, |
| 41890 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41891 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41892 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41893 | GIR_EraseFromParent, /*InsnID*/0, |
| 41894 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41895 | // GIR_Coverage, 1890, |
| 41896 | GIR_Done, |
| 41897 | // Label 2259: @106341 |
| 41898 | GIM_Try, /*On fail goto*//*Label 2260*/ 106397, // Rule ID 1891 // |
| 41899 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 41900 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, |
| 41901 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 41902 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 41903 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41904 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 41905 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 41906 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41907 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41908 | // MIs[1] Operand 1 |
| 41909 | // No operand predicates |
| 41910 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41911 | // (intrinsic_wo_chain:{ *:[v2f32] } 531:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) => (UCVTFv2i32_shift:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 41912 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv2i32_shift, |
| 41913 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41914 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41915 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41916 | GIR_EraseFromParent, /*InsnID*/0, |
| 41917 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41918 | // GIR_Coverage, 1891, |
| 41919 | GIR_Done, |
| 41920 | // Label 2260: @106397 |
| 41921 | GIM_Try, /*On fail goto*//*Label 2261*/ 106453, // Rule ID 1892 // |
| 41922 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 41923 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, |
| 41924 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 41925 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 41926 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41927 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 41928 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 41929 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41930 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41931 | // MIs[1] Operand 1 |
| 41932 | // No operand predicates |
| 41933 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41934 | // (intrinsic_wo_chain:{ *:[v4f32] } 531:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) => (UCVTFv4i32_shift:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 41935 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv4i32_shift, |
| 41936 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41937 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41938 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41939 | GIR_EraseFromParent, /*InsnID*/0, |
| 41940 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41941 | // GIR_Coverage, 1892, |
| 41942 | GIR_Done, |
| 41943 | // Label 2261: @106453 |
| 41944 | GIM_Try, /*On fail goto*//*Label 2262*/ 106509, // Rule ID 1893 // |
| 41945 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 41946 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcvtfxu2fp, |
| 41947 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 41948 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 41949 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41950 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 41951 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 41952 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 41953 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 41954 | // MIs[1] Operand 1 |
| 41955 | // No operand predicates |
| 41956 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 41957 | // (intrinsic_wo_chain:{ *:[v2f64] } 531:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) => (UCVTFv2i64_shift:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 41958 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv2i64_shift, |
| 41959 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41960 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41961 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 41962 | GIR_EraseFromParent, /*InsnID*/0, |
| 41963 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41964 | // GIR_Coverage, 1893, |
| 41965 | GIR_Done, |
| 41966 | // Label 2262: @106509 |
| 41967 | GIM_Try, /*On fail goto*//*Label 2263*/ 106561, // Rule ID 37 // |
| 41968 | GIM_CheckFeatures, GIFBS_HasBF16, |
| 41969 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_bfcvtn2, |
| 41970 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 41971 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 41972 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 41973 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 41974 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 41975 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 41976 | // (intrinsic_wo_chain:{ *:[v8bf16] } 362:{ *:[iPTR] }, V128:{ *:[v8bf16] }:$Rd, V128:{ *:[v4f32] }:$Rn) => (BFCVTN2:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rd, V128:{ *:[v4f32] }:$Rn) |
| 41977 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BFCVTN2, |
| 41978 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 41979 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 41980 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 41981 | GIR_EraseFromParent, /*InsnID*/0, |
| 41982 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 41983 | // GIR_Coverage, 37, |
| 41984 | GIR_Done, |
| 41985 | // Label 2263: @106561 |
| 41986 | GIM_Try, /*On fail goto*//*Label 2264*/ 106613, // Rule ID 120 // |
| 41987 | GIM_CheckFeatures, GIFBS_HasCRC, |
| 41988 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32b, |
| 41989 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 41990 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 41991 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 41992 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 41993 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 41994 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, |
| 41995 | // (intrinsic_wo_chain:{ *:[i32] } 320:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32Brr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 41996 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32Brr, |
| 41997 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 41998 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 41999 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42000 | GIR_EraseFromParent, /*InsnID*/0, |
| 42001 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42002 | // GIR_Coverage, 120, |
| 42003 | GIR_Done, |
| 42004 | // Label 2264: @106613 |
| 42005 | GIM_Try, /*On fail goto*//*Label 2265*/ 106665, // Rule ID 121 // |
| 42006 | GIM_CheckFeatures, GIFBS_HasCRC, |
| 42007 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32h, |
| 42008 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 42009 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 42010 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 42011 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 42012 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 42013 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, |
| 42014 | // (intrinsic_wo_chain:{ *:[i32] } 325:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32Hrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 42015 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32Hrr, |
| 42016 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42017 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42018 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42019 | GIR_EraseFromParent, /*InsnID*/0, |
| 42020 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42021 | // GIR_Coverage, 121, |
| 42022 | GIR_Done, |
| 42023 | // Label 2265: @106665 |
| 42024 | GIM_Try, /*On fail goto*//*Label 2266*/ 106717, // Rule ID 122 // |
| 42025 | GIM_CheckFeatures, GIFBS_HasCRC, |
| 42026 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32w, |
| 42027 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 42028 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 42029 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 42030 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 42031 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 42032 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, |
| 42033 | // (intrinsic_wo_chain:{ *:[i32] } 326:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32Wrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 42034 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32Wrr, |
| 42035 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42036 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42037 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42038 | GIR_EraseFromParent, /*InsnID*/0, |
| 42039 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42040 | // GIR_Coverage, 122, |
| 42041 | GIR_Done, |
| 42042 | // Label 2266: @106717 |
| 42043 | GIM_Try, /*On fail goto*//*Label 2267*/ 106769, // Rule ID 123 // |
| 42044 | GIM_CheckFeatures, GIFBS_HasCRC, |
| 42045 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32x, |
| 42046 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 42047 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 42048 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 42049 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 42050 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 42051 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, |
| 42052 | // (intrinsic_wo_chain:{ *:[i32] } 327:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (CRC32Xrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm) |
| 42053 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32Xrr, |
| 42054 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42055 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42056 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42057 | GIR_EraseFromParent, /*InsnID*/0, |
| 42058 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42059 | // GIR_Coverage, 123, |
| 42060 | GIR_Done, |
| 42061 | // Label 2267: @106769 |
| 42062 | GIM_Try, /*On fail goto*//*Label 2268*/ 106821, // Rule ID 124 // |
| 42063 | GIM_CheckFeatures, GIFBS_HasCRC, |
| 42064 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32cb, |
| 42065 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 42066 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 42067 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 42068 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 42069 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 42070 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, |
| 42071 | // (intrinsic_wo_chain:{ *:[i32] } 321:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32CBrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 42072 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32CBrr, |
| 42073 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42074 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42075 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42076 | GIR_EraseFromParent, /*InsnID*/0, |
| 42077 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42078 | // GIR_Coverage, 124, |
| 42079 | GIR_Done, |
| 42080 | // Label 2268: @106821 |
| 42081 | GIM_Try, /*On fail goto*//*Label 2269*/ 106873, // Rule ID 125 // |
| 42082 | GIM_CheckFeatures, GIFBS_HasCRC, |
| 42083 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32ch, |
| 42084 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 42085 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 42086 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 42087 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 42088 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 42089 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, |
| 42090 | // (intrinsic_wo_chain:{ *:[i32] } 322:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32CHrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 42091 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32CHrr, |
| 42092 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42093 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42094 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42095 | GIR_EraseFromParent, /*InsnID*/0, |
| 42096 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42097 | // GIR_Coverage, 125, |
| 42098 | GIR_Done, |
| 42099 | // Label 2269: @106873 |
| 42100 | GIM_Try, /*On fail goto*//*Label 2270*/ 106925, // Rule ID 126 // |
| 42101 | GIM_CheckFeatures, GIFBS_HasCRC, |
| 42102 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32cw, |
| 42103 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 42104 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 42105 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 42106 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 42107 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 42108 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, |
| 42109 | // (intrinsic_wo_chain:{ *:[i32] } 323:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32CWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 42110 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32CWrr, |
| 42111 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42112 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42113 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42114 | GIR_EraseFromParent, /*InsnID*/0, |
| 42115 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42116 | // GIR_Coverage, 126, |
| 42117 | GIR_Done, |
| 42118 | // Label 2270: @106925 |
| 42119 | GIM_Try, /*On fail goto*//*Label 2271*/ 106977, // Rule ID 127 // |
| 42120 | GIM_CheckFeatures, GIFBS_HasCRC, |
| 42121 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crc32cx, |
| 42122 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 42123 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 42124 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 42125 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 42126 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 42127 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, |
| 42128 | // (intrinsic_wo_chain:{ *:[i32] } 324:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (CRC32CXrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm) |
| 42129 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CRC32CXrr, |
| 42130 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42131 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42132 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42133 | GIR_EraseFromParent, /*InsnID*/0, |
| 42134 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42135 | // GIR_Coverage, 127, |
| 42136 | GIR_Done, |
| 42137 | // Label 2271: @106977 |
| 42138 | GIM_Try, /*On fail goto*//*Label 2272*/ 107029, // Rule ID 849 // |
| 42139 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42140 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, |
| 42141 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 42142 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 42143 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 42144 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 42145 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 42146 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 42147 | // (intrinsic_wo_chain:{ *:[v8i8] } 480:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn) => (SUQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn) |
| 42148 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv8i8, |
| 42149 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 42150 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 42151 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 42152 | GIR_EraseFromParent, /*InsnID*/0, |
| 42153 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42154 | // GIR_Coverage, 849, |
| 42155 | GIR_Done, |
| 42156 | // Label 2272: @107029 |
| 42157 | GIM_Try, /*On fail goto*//*Label 2273*/ 107081, // Rule ID 850 // |
| 42158 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42159 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, |
| 42160 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 42161 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 42162 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 42163 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 42164 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 42165 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 42166 | // (intrinsic_wo_chain:{ *:[v16i8] } 480:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) => (SUQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) |
| 42167 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv16i8, |
| 42168 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 42169 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 42170 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 42171 | GIR_EraseFromParent, /*InsnID*/0, |
| 42172 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42173 | // GIR_Coverage, 850, |
| 42174 | GIR_Done, |
| 42175 | // Label 2273: @107081 |
| 42176 | GIM_Try, /*On fail goto*//*Label 2274*/ 107133, // Rule ID 851 // |
| 42177 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42178 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, |
| 42179 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 42180 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 42181 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 42182 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 42183 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 42184 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 42185 | // (intrinsic_wo_chain:{ *:[v4i16] } 480:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn) => (SUQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn) |
| 42186 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv4i16, |
| 42187 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 42188 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 42189 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 42190 | GIR_EraseFromParent, /*InsnID*/0, |
| 42191 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42192 | // GIR_Coverage, 851, |
| 42193 | GIR_Done, |
| 42194 | // Label 2274: @107133 |
| 42195 | GIM_Try, /*On fail goto*//*Label 2275*/ 107185, // Rule ID 852 // |
| 42196 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42197 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, |
| 42198 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 42199 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 42200 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 42201 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 42202 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 42203 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 42204 | // (intrinsic_wo_chain:{ *:[v8i16] } 480:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn) => (SUQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn) |
| 42205 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv8i16, |
| 42206 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 42207 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 42208 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 42209 | GIR_EraseFromParent, /*InsnID*/0, |
| 42210 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42211 | // GIR_Coverage, 852, |
| 42212 | GIR_Done, |
| 42213 | // Label 2275: @107185 |
| 42214 | GIM_Try, /*On fail goto*//*Label 2276*/ 107237, // Rule ID 853 // |
| 42215 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42216 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, |
| 42217 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 42218 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 42219 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 42220 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 42221 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 42222 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 42223 | // (intrinsic_wo_chain:{ *:[v2i32] } 480:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn) => (SUQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn) |
| 42224 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv2i32, |
| 42225 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 42226 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 42227 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 42228 | GIR_EraseFromParent, /*InsnID*/0, |
| 42229 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42230 | // GIR_Coverage, 853, |
| 42231 | GIR_Done, |
| 42232 | // Label 2276: @107237 |
| 42233 | GIM_Try, /*On fail goto*//*Label 2277*/ 107289, // Rule ID 854 // |
| 42234 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42235 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, |
| 42236 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 42237 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 42238 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 42239 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 42240 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 42241 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 42242 | // (intrinsic_wo_chain:{ *:[v4i32] } 480:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) => (SUQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) |
| 42243 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv4i32, |
| 42244 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 42245 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 42246 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 42247 | GIR_EraseFromParent, /*InsnID*/0, |
| 42248 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42249 | // GIR_Coverage, 854, |
| 42250 | GIR_Done, |
| 42251 | // Label 2277: @107289 |
| 42252 | GIM_Try, /*On fail goto*//*Label 2278*/ 107341, // Rule ID 855 // |
| 42253 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42254 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, |
| 42255 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 42256 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 42257 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 42258 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 42259 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 42260 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 42261 | // (intrinsic_wo_chain:{ *:[v2i64] } 480:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn) => (SUQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn) |
| 42262 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv2i64, |
| 42263 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 42264 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 42265 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 42266 | GIR_EraseFromParent, /*InsnID*/0, |
| 42267 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42268 | // GIR_Coverage, 855, |
| 42269 | GIR_Done, |
| 42270 | // Label 2278: @107341 |
| 42271 | GIM_Try, /*On fail goto*//*Label 2279*/ 107393, // Rule ID 880 // |
| 42272 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42273 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, |
| 42274 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 42275 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 42276 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 42277 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 42278 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 42279 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 42280 | // (intrinsic_wo_chain:{ *:[v8i8] } 519:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn) => (USQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn) |
| 42281 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv8i8, |
| 42282 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 42283 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 42284 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 42285 | GIR_EraseFromParent, /*InsnID*/0, |
| 42286 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42287 | // GIR_Coverage, 880, |
| 42288 | GIR_Done, |
| 42289 | // Label 2279: @107393 |
| 42290 | GIM_Try, /*On fail goto*//*Label 2280*/ 107445, // Rule ID 881 // |
| 42291 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42292 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, |
| 42293 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 42294 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 42295 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 42296 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 42297 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 42298 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 42299 | // (intrinsic_wo_chain:{ *:[v16i8] } 519:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) => (USQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) |
| 42300 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv16i8, |
| 42301 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 42302 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 42303 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 42304 | GIR_EraseFromParent, /*InsnID*/0, |
| 42305 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42306 | // GIR_Coverage, 881, |
| 42307 | GIR_Done, |
| 42308 | // Label 2280: @107445 |
| 42309 | GIM_Try, /*On fail goto*//*Label 2281*/ 107497, // Rule ID 882 // |
| 42310 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42311 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, |
| 42312 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 42313 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 42314 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 42315 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 42316 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 42317 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 42318 | // (intrinsic_wo_chain:{ *:[v4i16] } 519:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn) => (USQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn) |
| 42319 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv4i16, |
| 42320 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 42321 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 42322 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 42323 | GIR_EraseFromParent, /*InsnID*/0, |
| 42324 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42325 | // GIR_Coverage, 882, |
| 42326 | GIR_Done, |
| 42327 | // Label 2281: @107497 |
| 42328 | GIM_Try, /*On fail goto*//*Label 2282*/ 107549, // Rule ID 883 // |
| 42329 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42330 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, |
| 42331 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 42332 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 42333 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 42334 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 42335 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 42336 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 42337 | // (intrinsic_wo_chain:{ *:[v8i16] } 519:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn) => (USQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn) |
| 42338 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv8i16, |
| 42339 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 42340 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 42341 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 42342 | GIR_EraseFromParent, /*InsnID*/0, |
| 42343 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42344 | // GIR_Coverage, 883, |
| 42345 | GIR_Done, |
| 42346 | // Label 2282: @107549 |
| 42347 | GIM_Try, /*On fail goto*//*Label 2283*/ 107601, // Rule ID 884 // |
| 42348 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42349 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, |
| 42350 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 42351 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 42352 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 42353 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 42354 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 42355 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 42356 | // (intrinsic_wo_chain:{ *:[v2i32] } 519:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn) => (USQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn) |
| 42357 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv2i32, |
| 42358 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 42359 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 42360 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 42361 | GIR_EraseFromParent, /*InsnID*/0, |
| 42362 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42363 | // GIR_Coverage, 884, |
| 42364 | GIR_Done, |
| 42365 | // Label 2283: @107601 |
| 42366 | GIM_Try, /*On fail goto*//*Label 2284*/ 107653, // Rule ID 885 // |
| 42367 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42368 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, |
| 42369 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 42370 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 42371 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 42372 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 42373 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 42374 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 42375 | // (intrinsic_wo_chain:{ *:[v4i32] } 519:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) => (USQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) |
| 42376 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv4i32, |
| 42377 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 42378 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 42379 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 42380 | GIR_EraseFromParent, /*InsnID*/0, |
| 42381 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42382 | // GIR_Coverage, 885, |
| 42383 | GIR_Done, |
| 42384 | // Label 2284: @107653 |
| 42385 | GIM_Try, /*On fail goto*//*Label 2285*/ 107705, // Rule ID 886 // |
| 42386 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42387 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, |
| 42388 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 42389 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 42390 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 42391 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 42392 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 42393 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 42394 | // (intrinsic_wo_chain:{ *:[v2i64] } 519:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn) => (USQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn) |
| 42395 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv2i64, |
| 42396 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 42397 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 42398 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 42399 | GIR_EraseFromParent, /*InsnID*/0, |
| 42400 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42401 | // GIR_Coverage, 886, |
| 42402 | GIR_Done, |
| 42403 | // Label 2285: @107705 |
| 42404 | GIM_Try, /*On fail goto*//*Label 2286*/ 107757, // Rule ID 897 // |
| 42405 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42406 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, |
| 42407 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 42408 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 42409 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 42410 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 42411 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 42412 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 42413 | // (intrinsic_wo_chain:{ *:[v8i8] } 359:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (ADDPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 42414 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv8i8, |
| 42415 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42416 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42417 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42418 | GIR_EraseFromParent, /*InsnID*/0, |
| 42419 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42420 | // GIR_Coverage, 897, |
| 42421 | GIR_Done, |
| 42422 | // Label 2286: @107757 |
| 42423 | GIM_Try, /*On fail goto*//*Label 2287*/ 107809, // Rule ID 898 // |
| 42424 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42425 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, |
| 42426 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 42427 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 42428 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 42429 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 42430 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 42431 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 42432 | // (intrinsic_wo_chain:{ *:[v16i8] } 359:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (ADDPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 42433 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv16i8, |
| 42434 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42435 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42436 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42437 | GIR_EraseFromParent, /*InsnID*/0, |
| 42438 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42439 | // GIR_Coverage, 898, |
| 42440 | GIR_Done, |
| 42441 | // Label 2287: @107809 |
| 42442 | GIM_Try, /*On fail goto*//*Label 2288*/ 107861, // Rule ID 899 // |
| 42443 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42444 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, |
| 42445 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 42446 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 42447 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 42448 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 42449 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 42450 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 42451 | // (intrinsic_wo_chain:{ *:[v4i16] } 359:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (ADDPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 42452 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv4i16, |
| 42453 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42454 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42455 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42456 | GIR_EraseFromParent, /*InsnID*/0, |
| 42457 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42458 | // GIR_Coverage, 899, |
| 42459 | GIR_Done, |
| 42460 | // Label 2288: @107861 |
| 42461 | GIM_Try, /*On fail goto*//*Label 2289*/ 107913, // Rule ID 900 // |
| 42462 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42463 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, |
| 42464 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 42465 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 42466 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 42467 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 42468 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 42469 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 42470 | // (intrinsic_wo_chain:{ *:[v8i16] } 359:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (ADDPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 42471 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv8i16, |
| 42472 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42473 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42474 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42475 | GIR_EraseFromParent, /*InsnID*/0, |
| 42476 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42477 | // GIR_Coverage, 900, |
| 42478 | GIR_Done, |
| 42479 | // Label 2289: @107913 |
| 42480 | GIM_Try, /*On fail goto*//*Label 2290*/ 107965, // Rule ID 901 // |
| 42481 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42482 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, |
| 42483 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 42484 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 42485 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 42486 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 42487 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 42488 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 42489 | // (intrinsic_wo_chain:{ *:[v2i32] } 359:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (ADDPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 42490 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv2i32, |
| 42491 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42492 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42493 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42494 | GIR_EraseFromParent, /*InsnID*/0, |
| 42495 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42496 | // GIR_Coverage, 901, |
| 42497 | GIR_Done, |
| 42498 | // Label 2290: @107965 |
| 42499 | GIM_Try, /*On fail goto*//*Label 2291*/ 108017, // Rule ID 902 // |
| 42500 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42501 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, |
| 42502 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 42503 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 42504 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 42505 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 42506 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 42507 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 42508 | // (intrinsic_wo_chain:{ *:[v4i32] } 359:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (ADDPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 42509 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv4i32, |
| 42510 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42511 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42512 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42513 | GIR_EraseFromParent, /*InsnID*/0, |
| 42514 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42515 | // GIR_Coverage, 902, |
| 42516 | GIR_Done, |
| 42517 | // Label 2291: @108017 |
| 42518 | GIM_Try, /*On fail goto*//*Label 2292*/ 108069, // Rule ID 903 // |
| 42519 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42520 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addp, |
| 42521 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 42522 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 42523 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 42524 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 42525 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 42526 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 42527 | // (intrinsic_wo_chain:{ *:[v2i64] } 359:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (ADDPv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 42528 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDPv2i64, |
| 42529 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42530 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42531 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42532 | GIR_EraseFromParent, /*InsnID*/0, |
| 42533 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42534 | // GIR_Coverage, 903, |
| 42535 | GIR_Done, |
| 42536 | // Label 2292: @108069 |
| 42537 | GIM_Try, /*On fail goto*//*Label 2293*/ 108121, // Rule ID 946 // |
| 42538 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 42539 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fabd, |
| 42540 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 42541 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 42542 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 42543 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 42544 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 42545 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 42546 | // (intrinsic_wo_chain:{ *:[v4f16] } 368:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FABDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 42547 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv4f16, |
| 42548 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42549 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42550 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42551 | GIR_EraseFromParent, /*InsnID*/0, |
| 42552 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42553 | // GIR_Coverage, 946, |
| 42554 | GIR_Done, |
| 42555 | // Label 2293: @108121 |
| 42556 | GIM_Try, /*On fail goto*//*Label 2294*/ 108173, // Rule ID 947 // |
| 42557 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 42558 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fabd, |
| 42559 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 42560 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 42561 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 42562 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 42563 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 42564 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 42565 | // (intrinsic_wo_chain:{ *:[v8f16] } 368:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FABDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 42566 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv8f16, |
| 42567 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42568 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42569 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42570 | GIR_EraseFromParent, /*InsnID*/0, |
| 42571 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42572 | // GIR_Coverage, 947, |
| 42573 | GIR_Done, |
| 42574 | // Label 2294: @108173 |
| 42575 | GIM_Try, /*On fail goto*//*Label 2295*/ 108225, // Rule ID 948 // |
| 42576 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42577 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fabd, |
| 42578 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 42579 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 42580 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 42581 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 42582 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 42583 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 42584 | // (intrinsic_wo_chain:{ *:[v2f32] } 368:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FABDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) |
| 42585 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv2f32, |
| 42586 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42587 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42588 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42589 | GIR_EraseFromParent, /*InsnID*/0, |
| 42590 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42591 | // GIR_Coverage, 948, |
| 42592 | GIR_Done, |
| 42593 | // Label 2295: @108225 |
| 42594 | GIM_Try, /*On fail goto*//*Label 2296*/ 108277, // Rule ID 949 // |
| 42595 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42596 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fabd, |
| 42597 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 42598 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 42599 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 42600 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 42601 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 42602 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 42603 | // (intrinsic_wo_chain:{ *:[v4f32] } 368:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FABDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) |
| 42604 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv4f32, |
| 42605 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42606 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42607 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42608 | GIR_EraseFromParent, /*InsnID*/0, |
| 42609 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42610 | // GIR_Coverage, 949, |
| 42611 | GIR_Done, |
| 42612 | // Label 2296: @108277 |
| 42613 | GIM_Try, /*On fail goto*//*Label 2297*/ 108329, // Rule ID 950 // |
| 42614 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42615 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fabd, |
| 42616 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 42617 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 42618 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 42619 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 42620 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 42621 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 42622 | // (intrinsic_wo_chain:{ *:[v2f64] } 368:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FABDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) |
| 42623 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv2f64, |
| 42624 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42625 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42626 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42627 | GIR_EraseFromParent, /*InsnID*/0, |
| 42628 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42629 | // GIR_Coverage, 950, |
| 42630 | GIR_Done, |
| 42631 | // Label 2297: @108329 |
| 42632 | GIM_Try, /*On fail goto*//*Label 2298*/ 108381, // Rule ID 951 // |
| 42633 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 42634 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, |
| 42635 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 42636 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 42637 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 42638 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 42639 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 42640 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 42641 | // (intrinsic_wo_chain:{ *:[v4i16] } 369:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FACGEv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 42642 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGEv4f16, |
| 42643 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42644 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42645 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42646 | GIR_EraseFromParent, /*InsnID*/0, |
| 42647 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42648 | // GIR_Coverage, 951, |
| 42649 | GIR_Done, |
| 42650 | // Label 2298: @108381 |
| 42651 | GIM_Try, /*On fail goto*//*Label 2299*/ 108433, // Rule ID 952 // |
| 42652 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 42653 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, |
| 42654 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 42655 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 42656 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 42657 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 42658 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 42659 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 42660 | // (intrinsic_wo_chain:{ *:[v8i16] } 369:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FACGEv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 42661 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGEv8f16, |
| 42662 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42663 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42664 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42665 | GIR_EraseFromParent, /*InsnID*/0, |
| 42666 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42667 | // GIR_Coverage, 952, |
| 42668 | GIR_Done, |
| 42669 | // Label 2299: @108433 |
| 42670 | GIM_Try, /*On fail goto*//*Label 2300*/ 108485, // Rule ID 953 // |
| 42671 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42672 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, |
| 42673 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 42674 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 42675 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 42676 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 42677 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 42678 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 42679 | // (intrinsic_wo_chain:{ *:[v2i32] } 369:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FACGEv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) |
| 42680 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGEv2f32, |
| 42681 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42682 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42683 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42684 | GIR_EraseFromParent, /*InsnID*/0, |
| 42685 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42686 | // GIR_Coverage, 953, |
| 42687 | GIR_Done, |
| 42688 | // Label 2300: @108485 |
| 42689 | GIM_Try, /*On fail goto*//*Label 2301*/ 108537, // Rule ID 954 // |
| 42690 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42691 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, |
| 42692 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 42693 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 42694 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 42695 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 42696 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 42697 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 42698 | // (intrinsic_wo_chain:{ *:[v4i32] } 369:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FACGEv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) |
| 42699 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGEv4f32, |
| 42700 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42701 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42702 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42703 | GIR_EraseFromParent, /*InsnID*/0, |
| 42704 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42705 | // GIR_Coverage, 954, |
| 42706 | GIR_Done, |
| 42707 | // Label 2301: @108537 |
| 42708 | GIM_Try, /*On fail goto*//*Label 2302*/ 108589, // Rule ID 955 // |
| 42709 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42710 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, |
| 42711 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 42712 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 42713 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 42714 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 42715 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 42716 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 42717 | // (intrinsic_wo_chain:{ *:[v2i64] } 369:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FACGEv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) |
| 42718 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGEv2f64, |
| 42719 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42720 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42721 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42722 | GIR_EraseFromParent, /*InsnID*/0, |
| 42723 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42724 | // GIR_Coverage, 955, |
| 42725 | GIR_Done, |
| 42726 | // Label 2302: @108589 |
| 42727 | GIM_Try, /*On fail goto*//*Label 2303*/ 108641, // Rule ID 956 // |
| 42728 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 42729 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, |
| 42730 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 42731 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 42732 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 42733 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 42734 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 42735 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 42736 | // (intrinsic_wo_chain:{ *:[v4i16] } 370:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FACGTv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 42737 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGTv4f16, |
| 42738 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42739 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42740 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42741 | GIR_EraseFromParent, /*InsnID*/0, |
| 42742 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42743 | // GIR_Coverage, 956, |
| 42744 | GIR_Done, |
| 42745 | // Label 2303: @108641 |
| 42746 | GIM_Try, /*On fail goto*//*Label 2304*/ 108693, // Rule ID 957 // |
| 42747 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 42748 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, |
| 42749 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 42750 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 42751 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 42752 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 42753 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 42754 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 42755 | // (intrinsic_wo_chain:{ *:[v8i16] } 370:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FACGTv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 42756 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGTv8f16, |
| 42757 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42758 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42759 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42760 | GIR_EraseFromParent, /*InsnID*/0, |
| 42761 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42762 | // GIR_Coverage, 957, |
| 42763 | GIR_Done, |
| 42764 | // Label 2304: @108693 |
| 42765 | GIM_Try, /*On fail goto*//*Label 2305*/ 108745, // Rule ID 958 // |
| 42766 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42767 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, |
| 42768 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 42769 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 42770 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 42771 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 42772 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 42773 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 42774 | // (intrinsic_wo_chain:{ *:[v2i32] } 370:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FACGTv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) |
| 42775 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGTv2f32, |
| 42776 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42777 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42778 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42779 | GIR_EraseFromParent, /*InsnID*/0, |
| 42780 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42781 | // GIR_Coverage, 958, |
| 42782 | GIR_Done, |
| 42783 | // Label 2305: @108745 |
| 42784 | GIM_Try, /*On fail goto*//*Label 2306*/ 108797, // Rule ID 959 // |
| 42785 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42786 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, |
| 42787 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 42788 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 42789 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 42790 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 42791 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 42792 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 42793 | // (intrinsic_wo_chain:{ *:[v4i32] } 370:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FACGTv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) |
| 42794 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGTv4f32, |
| 42795 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42796 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42797 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42798 | GIR_EraseFromParent, /*InsnID*/0, |
| 42799 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42800 | // GIR_Coverage, 959, |
| 42801 | GIR_Done, |
| 42802 | // Label 2306: @108797 |
| 42803 | GIM_Try, /*On fail goto*//*Label 2307*/ 108849, // Rule ID 960 // |
| 42804 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42805 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, |
| 42806 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 42807 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 42808 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 42809 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 42810 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 42811 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 42812 | // (intrinsic_wo_chain:{ *:[v2i64] } 370:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FACGTv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) |
| 42813 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGTv2f64, |
| 42814 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42815 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42816 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42817 | GIR_EraseFromParent, /*InsnID*/0, |
| 42818 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42819 | // GIR_Coverage, 960, |
| 42820 | GIR_Done, |
| 42821 | // Label 2307: @108849 |
| 42822 | GIM_Try, /*On fail goto*//*Label 2308*/ 108901, // Rule ID 961 // |
| 42823 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 42824 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_faddp, |
| 42825 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 42826 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 42827 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 42828 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 42829 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 42830 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 42831 | // (intrinsic_wo_chain:{ *:[v4f16] } 371:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FADDPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 42832 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv4f16, |
| 42833 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42834 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42835 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42836 | GIR_EraseFromParent, /*InsnID*/0, |
| 42837 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42838 | // GIR_Coverage, 961, |
| 42839 | GIR_Done, |
| 42840 | // Label 2308: @108901 |
| 42841 | GIM_Try, /*On fail goto*//*Label 2309*/ 108953, // Rule ID 962 // |
| 42842 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 42843 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_faddp, |
| 42844 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 42845 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 42846 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 42847 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 42848 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 42849 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 42850 | // (intrinsic_wo_chain:{ *:[v8f16] } 371:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FADDPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 42851 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv8f16, |
| 42852 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42853 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42854 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42855 | GIR_EraseFromParent, /*InsnID*/0, |
| 42856 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42857 | // GIR_Coverage, 962, |
| 42858 | GIR_Done, |
| 42859 | // Label 2309: @108953 |
| 42860 | GIM_Try, /*On fail goto*//*Label 2310*/ 109005, // Rule ID 963 // |
| 42861 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42862 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_faddp, |
| 42863 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 42864 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 42865 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 42866 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 42867 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 42868 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 42869 | // (intrinsic_wo_chain:{ *:[v2f32] } 371:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FADDPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) |
| 42870 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2f32, |
| 42871 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42872 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42873 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42874 | GIR_EraseFromParent, /*InsnID*/0, |
| 42875 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42876 | // GIR_Coverage, 963, |
| 42877 | GIR_Done, |
| 42878 | // Label 2310: @109005 |
| 42879 | GIM_Try, /*On fail goto*//*Label 2311*/ 109057, // Rule ID 964 // |
| 42880 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42881 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_faddp, |
| 42882 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 42883 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 42884 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 42885 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 42886 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 42887 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 42888 | // (intrinsic_wo_chain:{ *:[v4f32] } 371:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FADDPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) |
| 42889 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv4f32, |
| 42890 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42891 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42892 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42893 | GIR_EraseFromParent, /*InsnID*/0, |
| 42894 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42895 | // GIR_Coverage, 964, |
| 42896 | GIR_Done, |
| 42897 | // Label 2311: @109057 |
| 42898 | GIM_Try, /*On fail goto*//*Label 2312*/ 109109, // Rule ID 965 // |
| 42899 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42900 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_faddp, |
| 42901 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 42902 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 42903 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 42904 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 42905 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 42906 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 42907 | // (intrinsic_wo_chain:{ *:[v2f64] } 371:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FADDPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) |
| 42908 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2f64, |
| 42909 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42910 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42911 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42912 | GIR_EraseFromParent, /*InsnID*/0, |
| 42913 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42914 | // GIR_Coverage, 965, |
| 42915 | GIR_Done, |
| 42916 | // Label 2312: @109109 |
| 42917 | GIM_Try, /*On fail goto*//*Label 2313*/ 109161, // Rule ID 991 // |
| 42918 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 42919 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmp, |
| 42920 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 42921 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 42922 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 42923 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 42924 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 42925 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 42926 | // (intrinsic_wo_chain:{ *:[v4f16] } 386:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMAXNMPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 42927 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv4f16, |
| 42928 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42929 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42930 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42931 | GIR_EraseFromParent, /*InsnID*/0, |
| 42932 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42933 | // GIR_Coverage, 991, |
| 42934 | GIR_Done, |
| 42935 | // Label 2313: @109161 |
| 42936 | GIM_Try, /*On fail goto*//*Label 2314*/ 109213, // Rule ID 992 // |
| 42937 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 42938 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmp, |
| 42939 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 42940 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 42941 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 42942 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 42943 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 42944 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 42945 | // (intrinsic_wo_chain:{ *:[v8f16] } 386:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMAXNMPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 42946 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv8f16, |
| 42947 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42948 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42949 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42950 | GIR_EraseFromParent, /*InsnID*/0, |
| 42951 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42952 | // GIR_Coverage, 992, |
| 42953 | GIR_Done, |
| 42954 | // Label 2314: @109213 |
| 42955 | GIM_Try, /*On fail goto*//*Label 2315*/ 109265, // Rule ID 993 // |
| 42956 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42957 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmp, |
| 42958 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 42959 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 42960 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 42961 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 42962 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 42963 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 42964 | // (intrinsic_wo_chain:{ *:[v2f32] } 386:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMAXNMPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) |
| 42965 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv2f32, |
| 42966 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42967 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42968 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42969 | GIR_EraseFromParent, /*InsnID*/0, |
| 42970 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42971 | // GIR_Coverage, 993, |
| 42972 | GIR_Done, |
| 42973 | // Label 2315: @109265 |
| 42974 | GIM_Try, /*On fail goto*//*Label 2316*/ 109317, // Rule ID 994 // |
| 42975 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42976 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmp, |
| 42977 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 42978 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 42979 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 42980 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 42981 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 42982 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 42983 | // (intrinsic_wo_chain:{ *:[v4f32] } 386:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMAXNMPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) |
| 42984 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv4f32, |
| 42985 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 42986 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 42987 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 42988 | GIR_EraseFromParent, /*InsnID*/0, |
| 42989 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 42990 | // GIR_Coverage, 994, |
| 42991 | GIR_Done, |
| 42992 | // Label 2316: @109317 |
| 42993 | GIM_Try, /*On fail goto*//*Label 2317*/ 109369, // Rule ID 995 // |
| 42994 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 42995 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxnmp, |
| 42996 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 42997 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 42998 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 42999 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43000 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43001 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43002 | // (intrinsic_wo_chain:{ *:[v2f64] } 386:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMAXNMPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) |
| 43003 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXNMPv2f64, |
| 43004 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43005 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43006 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43007 | GIR_EraseFromParent, /*InsnID*/0, |
| 43008 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43009 | // GIR_Coverage, 995, |
| 43010 | GIR_Done, |
| 43011 | // Label 2317: @109369 |
| 43012 | GIM_Try, /*On fail goto*//*Label 2318*/ 109421, // Rule ID 1001 // |
| 43013 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 43014 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxp, |
| 43015 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 43016 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43017 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 43018 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 43019 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 43020 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 43021 | // (intrinsic_wo_chain:{ *:[v4f16] } 388:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMAXPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 43022 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv4f16, |
| 43023 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43024 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43025 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43026 | GIR_EraseFromParent, /*InsnID*/0, |
| 43027 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43028 | // GIR_Coverage, 1001, |
| 43029 | GIR_Done, |
| 43030 | // Label 2318: @109421 |
| 43031 | GIM_Try, /*On fail goto*//*Label 2319*/ 109473, // Rule ID 1002 // |
| 43032 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 43033 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxp, |
| 43034 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 43035 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43036 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 43037 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43038 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43039 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43040 | // (intrinsic_wo_chain:{ *:[v8f16] } 388:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMAXPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 43041 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv8f16, |
| 43042 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43043 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43044 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43045 | GIR_EraseFromParent, /*InsnID*/0, |
| 43046 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43047 | // GIR_Coverage, 1002, |
| 43048 | GIR_Done, |
| 43049 | // Label 2319: @109473 |
| 43050 | GIM_Try, /*On fail goto*//*Label 2320*/ 109525, // Rule ID 1003 // |
| 43051 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43052 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxp, |
| 43053 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 43054 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 43055 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 43056 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 43057 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 43058 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 43059 | // (intrinsic_wo_chain:{ *:[v2f32] } 388:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMAXPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) |
| 43060 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv2f32, |
| 43061 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43062 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43063 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43064 | GIR_EraseFromParent, /*InsnID*/0, |
| 43065 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43066 | // GIR_Coverage, 1003, |
| 43067 | GIR_Done, |
| 43068 | // Label 2320: @109525 |
| 43069 | GIM_Try, /*On fail goto*//*Label 2321*/ 109577, // Rule ID 1004 // |
| 43070 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43071 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxp, |
| 43072 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 43073 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 43074 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 43075 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43076 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43077 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43078 | // (intrinsic_wo_chain:{ *:[v4f32] } 388:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMAXPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) |
| 43079 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv4f32, |
| 43080 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43081 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43082 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43083 | GIR_EraseFromParent, /*InsnID*/0, |
| 43084 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43085 | // GIR_Coverage, 1004, |
| 43086 | GIR_Done, |
| 43087 | // Label 2321: @109577 |
| 43088 | GIM_Try, /*On fail goto*//*Label 2322*/ 109629, // Rule ID 1005 // |
| 43089 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43090 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmaxp, |
| 43091 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 43092 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 43093 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 43094 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43095 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43096 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43097 | // (intrinsic_wo_chain:{ *:[v2f64] } 388:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMAXPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) |
| 43098 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMAXPv2f64, |
| 43099 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43100 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43101 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43102 | GIR_EraseFromParent, /*InsnID*/0, |
| 43103 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43104 | // GIR_Coverage, 1005, |
| 43105 | GIR_Done, |
| 43106 | // Label 2322: @109629 |
| 43107 | GIM_Try, /*On fail goto*//*Label 2323*/ 109681, // Rule ID 1011 // |
| 43108 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 43109 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmp, |
| 43110 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 43111 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43112 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 43113 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 43114 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 43115 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 43116 | // (intrinsic_wo_chain:{ *:[v4f16] } 392:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMINNMPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 43117 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv4f16, |
| 43118 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43119 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43120 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43121 | GIR_EraseFromParent, /*InsnID*/0, |
| 43122 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43123 | // GIR_Coverage, 1011, |
| 43124 | GIR_Done, |
| 43125 | // Label 2323: @109681 |
| 43126 | GIM_Try, /*On fail goto*//*Label 2324*/ 109733, // Rule ID 1012 // |
| 43127 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 43128 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmp, |
| 43129 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 43130 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43131 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 43132 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43133 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43134 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43135 | // (intrinsic_wo_chain:{ *:[v8f16] } 392:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMINNMPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 43136 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv8f16, |
| 43137 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43138 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43139 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43140 | GIR_EraseFromParent, /*InsnID*/0, |
| 43141 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43142 | // GIR_Coverage, 1012, |
| 43143 | GIR_Done, |
| 43144 | // Label 2324: @109733 |
| 43145 | GIM_Try, /*On fail goto*//*Label 2325*/ 109785, // Rule ID 1013 // |
| 43146 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43147 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmp, |
| 43148 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 43149 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 43150 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 43151 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 43152 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 43153 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 43154 | // (intrinsic_wo_chain:{ *:[v2f32] } 392:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMINNMPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) |
| 43155 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv2f32, |
| 43156 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43157 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43158 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43159 | GIR_EraseFromParent, /*InsnID*/0, |
| 43160 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43161 | // GIR_Coverage, 1013, |
| 43162 | GIR_Done, |
| 43163 | // Label 2325: @109785 |
| 43164 | GIM_Try, /*On fail goto*//*Label 2326*/ 109837, // Rule ID 1014 // |
| 43165 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43166 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmp, |
| 43167 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 43168 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 43169 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 43170 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43171 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43172 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43173 | // (intrinsic_wo_chain:{ *:[v4f32] } 392:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMINNMPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) |
| 43174 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv4f32, |
| 43175 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43176 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43177 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43178 | GIR_EraseFromParent, /*InsnID*/0, |
| 43179 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43180 | // GIR_Coverage, 1014, |
| 43181 | GIR_Done, |
| 43182 | // Label 2326: @109837 |
| 43183 | GIM_Try, /*On fail goto*//*Label 2327*/ 109889, // Rule ID 1015 // |
| 43184 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43185 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminnmp, |
| 43186 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 43187 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 43188 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 43189 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43190 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43191 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43192 | // (intrinsic_wo_chain:{ *:[v2f64] } 392:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMINNMPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) |
| 43193 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINNMPv2f64, |
| 43194 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43195 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43196 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43197 | GIR_EraseFromParent, /*InsnID*/0, |
| 43198 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43199 | // GIR_Coverage, 1015, |
| 43200 | GIR_Done, |
| 43201 | // Label 2327: @109889 |
| 43202 | GIM_Try, /*On fail goto*//*Label 2328*/ 109941, // Rule ID 1021 // |
| 43203 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 43204 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminp, |
| 43205 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 43206 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43207 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 43208 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 43209 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 43210 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 43211 | // (intrinsic_wo_chain:{ *:[v4f16] } 394:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMINPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 43212 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv4f16, |
| 43213 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43214 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43215 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43216 | GIR_EraseFromParent, /*InsnID*/0, |
| 43217 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43218 | // GIR_Coverage, 1021, |
| 43219 | GIR_Done, |
| 43220 | // Label 2328: @109941 |
| 43221 | GIM_Try, /*On fail goto*//*Label 2329*/ 109993, // Rule ID 1022 // |
| 43222 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 43223 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminp, |
| 43224 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 43225 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43226 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 43227 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43228 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43229 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43230 | // (intrinsic_wo_chain:{ *:[v8f16] } 394:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMINPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 43231 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv8f16, |
| 43232 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43233 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43234 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43235 | GIR_EraseFromParent, /*InsnID*/0, |
| 43236 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43237 | // GIR_Coverage, 1022, |
| 43238 | GIR_Done, |
| 43239 | // Label 2329: @109993 |
| 43240 | GIM_Try, /*On fail goto*//*Label 2330*/ 110045, // Rule ID 1023 // |
| 43241 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43242 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminp, |
| 43243 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 43244 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 43245 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 43246 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 43247 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 43248 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 43249 | // (intrinsic_wo_chain:{ *:[v2f32] } 394:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMINPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) |
| 43250 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv2f32, |
| 43251 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43252 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43253 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43254 | GIR_EraseFromParent, /*InsnID*/0, |
| 43255 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43256 | // GIR_Coverage, 1023, |
| 43257 | GIR_Done, |
| 43258 | // Label 2330: @110045 |
| 43259 | GIM_Try, /*On fail goto*//*Label 2331*/ 110097, // Rule ID 1024 // |
| 43260 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43261 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminp, |
| 43262 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 43263 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 43264 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 43265 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43266 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43267 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43268 | // (intrinsic_wo_chain:{ *:[v4f32] } 394:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMINPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) |
| 43269 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv4f32, |
| 43270 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43271 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43272 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43273 | GIR_EraseFromParent, /*InsnID*/0, |
| 43274 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43275 | // GIR_Coverage, 1024, |
| 43276 | GIR_Done, |
| 43277 | // Label 2331: @110097 |
| 43278 | GIM_Try, /*On fail goto*//*Label 2332*/ 110149, // Rule ID 1025 // |
| 43279 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43280 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fminp, |
| 43281 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 43282 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 43283 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 43284 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43285 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43286 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43287 | // (intrinsic_wo_chain:{ *:[v2f64] } 394:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMINPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) |
| 43288 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMINPv2f64, |
| 43289 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43290 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43291 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43292 | GIR_EraseFromParent, /*InsnID*/0, |
| 43293 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43294 | // GIR_Coverage, 1025, |
| 43295 | GIR_Done, |
| 43296 | // Label 2332: @110149 |
| 43297 | GIM_Try, /*On fail goto*//*Label 2333*/ 110201, // Rule ID 1041 // |
| 43298 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 43299 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, |
| 43300 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 43301 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43302 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 43303 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 43304 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 43305 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 43306 | // (intrinsic_wo_chain:{ *:[v4f16] } 400:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMULXv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 43307 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv4f16, |
| 43308 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43309 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43310 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43311 | GIR_EraseFromParent, /*InsnID*/0, |
| 43312 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43313 | // GIR_Coverage, 1041, |
| 43314 | GIR_Done, |
| 43315 | // Label 2333: @110201 |
| 43316 | GIM_Try, /*On fail goto*//*Label 2334*/ 110253, // Rule ID 1042 // |
| 43317 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 43318 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, |
| 43319 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 43320 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43321 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 43322 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43323 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43324 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43325 | // (intrinsic_wo_chain:{ *:[v8f16] } 400:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMULXv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 43326 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv8f16, |
| 43327 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43328 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43329 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43330 | GIR_EraseFromParent, /*InsnID*/0, |
| 43331 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43332 | // GIR_Coverage, 1042, |
| 43333 | GIR_Done, |
| 43334 | // Label 2334: @110253 |
| 43335 | GIM_Try, /*On fail goto*//*Label 2335*/ 110305, // Rule ID 1043 // |
| 43336 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43337 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, |
| 43338 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 43339 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 43340 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 43341 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 43342 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 43343 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 43344 | // (intrinsic_wo_chain:{ *:[v2f32] } 400:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMULXv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) |
| 43345 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv2f32, |
| 43346 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43347 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43348 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43349 | GIR_EraseFromParent, /*InsnID*/0, |
| 43350 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43351 | // GIR_Coverage, 1043, |
| 43352 | GIR_Done, |
| 43353 | // Label 2335: @110305 |
| 43354 | GIM_Try, /*On fail goto*//*Label 2336*/ 110357, // Rule ID 1044 // |
| 43355 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43356 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, |
| 43357 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 43358 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 43359 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 43360 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43361 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43362 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43363 | // (intrinsic_wo_chain:{ *:[v4f32] } 400:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMULXv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) |
| 43364 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv4f32, |
| 43365 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43366 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43367 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43368 | GIR_EraseFromParent, /*InsnID*/0, |
| 43369 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43370 | // GIR_Coverage, 1044, |
| 43371 | GIR_Done, |
| 43372 | // Label 2336: @110357 |
| 43373 | GIM_Try, /*On fail goto*//*Label 2337*/ 110409, // Rule ID 1045 // |
| 43374 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43375 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, |
| 43376 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 43377 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 43378 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 43379 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43380 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43381 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43382 | // (intrinsic_wo_chain:{ *:[v2f64] } 400:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMULXv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) |
| 43383 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULXv2f64, |
| 43384 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43385 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43386 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43387 | GIR_EraseFromParent, /*InsnID*/0, |
| 43388 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43389 | // GIR_Coverage, 1045, |
| 43390 | GIR_Done, |
| 43391 | // Label 2337: @110409 |
| 43392 | GIM_Try, /*On fail goto*//*Label 2338*/ 110461, // Rule ID 1051 // |
| 43393 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 43394 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, |
| 43395 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 43396 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43397 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 43398 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 43399 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 43400 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 43401 | // (intrinsic_wo_chain:{ *:[v4f16] } 402:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FRECPSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 43402 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPSv4f16, |
| 43403 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43404 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43405 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43406 | GIR_EraseFromParent, /*InsnID*/0, |
| 43407 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43408 | // GIR_Coverage, 1051, |
| 43409 | GIR_Done, |
| 43410 | // Label 2338: @110461 |
| 43411 | GIM_Try, /*On fail goto*//*Label 2339*/ 110513, // Rule ID 1052 // |
| 43412 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 43413 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, |
| 43414 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 43415 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43416 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 43417 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43418 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43419 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43420 | // (intrinsic_wo_chain:{ *:[v8f16] } 402:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FRECPSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 43421 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPSv8f16, |
| 43422 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43423 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43424 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43425 | GIR_EraseFromParent, /*InsnID*/0, |
| 43426 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43427 | // GIR_Coverage, 1052, |
| 43428 | GIR_Done, |
| 43429 | // Label 2339: @110513 |
| 43430 | GIM_Try, /*On fail goto*//*Label 2340*/ 110565, // Rule ID 1053 // |
| 43431 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43432 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, |
| 43433 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 43434 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 43435 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 43436 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 43437 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 43438 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 43439 | // (intrinsic_wo_chain:{ *:[v2f32] } 402:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FRECPSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) |
| 43440 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPSv2f32, |
| 43441 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43442 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43443 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43444 | GIR_EraseFromParent, /*InsnID*/0, |
| 43445 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43446 | // GIR_Coverage, 1053, |
| 43447 | GIR_Done, |
| 43448 | // Label 2340: @110565 |
| 43449 | GIM_Try, /*On fail goto*//*Label 2341*/ 110617, // Rule ID 1054 // |
| 43450 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43451 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, |
| 43452 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 43453 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 43454 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 43455 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43456 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43457 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43458 | // (intrinsic_wo_chain:{ *:[v4f32] } 402:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FRECPSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) |
| 43459 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPSv4f32, |
| 43460 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43461 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43462 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43463 | GIR_EraseFromParent, /*InsnID*/0, |
| 43464 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43465 | // GIR_Coverage, 1054, |
| 43466 | GIR_Done, |
| 43467 | // Label 2341: @110617 |
| 43468 | GIM_Try, /*On fail goto*//*Label 2342*/ 110669, // Rule ID 1055 // |
| 43469 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43470 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, |
| 43471 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 43472 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 43473 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 43474 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43475 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43476 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43477 | // (intrinsic_wo_chain:{ *:[v2f64] } 402:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FRECPSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) |
| 43478 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPSv2f64, |
| 43479 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43480 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43481 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43482 | GIR_EraseFromParent, /*InsnID*/0, |
| 43483 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43484 | // GIR_Coverage, 1055, |
| 43485 | GIR_Done, |
| 43486 | // Label 2342: @110669 |
| 43487 | GIM_Try, /*On fail goto*//*Label 2343*/ 110721, // Rule ID 1056 // |
| 43488 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 43489 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, |
| 43490 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 43491 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43492 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 43493 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 43494 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 43495 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 43496 | // (intrinsic_wo_chain:{ *:[v4f16] } 406:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FRSQRTSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 43497 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTSv4f16, |
| 43498 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43499 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43500 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43501 | GIR_EraseFromParent, /*InsnID*/0, |
| 43502 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43503 | // GIR_Coverage, 1056, |
| 43504 | GIR_Done, |
| 43505 | // Label 2343: @110721 |
| 43506 | GIM_Try, /*On fail goto*//*Label 2344*/ 110773, // Rule ID 1057 // |
| 43507 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 43508 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, |
| 43509 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 43510 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43511 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 43512 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43513 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43514 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43515 | // (intrinsic_wo_chain:{ *:[v8f16] } 406:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FRSQRTSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 43516 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTSv8f16, |
| 43517 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43518 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43519 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43520 | GIR_EraseFromParent, /*InsnID*/0, |
| 43521 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43522 | // GIR_Coverage, 1057, |
| 43523 | GIR_Done, |
| 43524 | // Label 2344: @110773 |
| 43525 | GIM_Try, /*On fail goto*//*Label 2345*/ 110825, // Rule ID 1058 // |
| 43526 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43527 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, |
| 43528 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 43529 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 43530 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 43531 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 43532 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 43533 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 43534 | // (intrinsic_wo_chain:{ *:[v2f32] } 406:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FRSQRTSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) |
| 43535 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTSv2f32, |
| 43536 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43537 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43538 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43539 | GIR_EraseFromParent, /*InsnID*/0, |
| 43540 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43541 | // GIR_Coverage, 1058, |
| 43542 | GIR_Done, |
| 43543 | // Label 2345: @110825 |
| 43544 | GIM_Try, /*On fail goto*//*Label 2346*/ 110877, // Rule ID 1059 // |
| 43545 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43546 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, |
| 43547 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 43548 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 43549 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 43550 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43551 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43552 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43553 | // (intrinsic_wo_chain:{ *:[v4f32] } 406:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FRSQRTSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) |
| 43554 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTSv4f32, |
| 43555 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43556 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43557 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43558 | GIR_EraseFromParent, /*InsnID*/0, |
| 43559 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43560 | // GIR_Coverage, 1059, |
| 43561 | GIR_Done, |
| 43562 | // Label 2346: @110877 |
| 43563 | GIM_Try, /*On fail goto*//*Label 2347*/ 110929, // Rule ID 1060 // |
| 43564 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43565 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, |
| 43566 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 43567 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 43568 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 43569 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43570 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43571 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43572 | // (intrinsic_wo_chain:{ *:[v2f64] } 406:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FRSQRTSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) |
| 43573 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTSv2f64, |
| 43574 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43575 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43576 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43577 | GIR_EraseFromParent, /*InsnID*/0, |
| 43578 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43579 | // GIR_Coverage, 1060, |
| 43580 | GIR_Done, |
| 43581 | // Label 2347: @110929 |
| 43582 | GIM_Try, /*On fail goto*//*Label 2348*/ 110981, // Rule ID 1072 // |
| 43583 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43584 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_pmul, |
| 43585 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 43586 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 43587 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 43588 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 43589 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 43590 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 43591 | // (intrinsic_wo_chain:{ *:[v8i8] } 419:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (PMULv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 43592 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PMULv8i8, |
| 43593 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43594 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43595 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43596 | GIR_EraseFromParent, /*InsnID*/0, |
| 43597 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43598 | // GIR_Coverage, 1072, |
| 43599 | GIR_Done, |
| 43600 | // Label 2348: @110981 |
| 43601 | GIM_Try, /*On fail goto*//*Label 2349*/ 111033, // Rule ID 1073 // |
| 43602 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43603 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_pmul, |
| 43604 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 43605 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 43606 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 43607 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43608 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43609 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43610 | // (intrinsic_wo_chain:{ *:[v16i8] } 419:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (PMULv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 43611 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PMULv16i8, |
| 43612 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43613 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43614 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43615 | GIR_EraseFromParent, /*InsnID*/0, |
| 43616 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43617 | // GIR_Coverage, 1073, |
| 43618 | GIR_Done, |
| 43619 | // Label 2349: @111033 |
| 43620 | GIM_Try, /*On fail goto*//*Label 2350*/ 111085, // Rule ID 1087 // |
| 43621 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43622 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 43623 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 43624 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 43625 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 43626 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 43627 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 43628 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 43629 | // (intrinsic_wo_chain:{ *:[v8i8] } 426:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SABDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 43630 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv8i8, |
| 43631 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43632 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43633 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43634 | GIR_EraseFromParent, /*InsnID*/0, |
| 43635 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43636 | // GIR_Coverage, 1087, |
| 43637 | GIR_Done, |
| 43638 | // Label 2350: @111085 |
| 43639 | GIM_Try, /*On fail goto*//*Label 2351*/ 111137, // Rule ID 1089 // |
| 43640 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43641 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 43642 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 43643 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 43644 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 43645 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43646 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43647 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43648 | // (intrinsic_wo_chain:{ *:[v16i8] } 426:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SABDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 43649 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv16i8, |
| 43650 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43651 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43652 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43653 | GIR_EraseFromParent, /*InsnID*/0, |
| 43654 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43655 | // GIR_Coverage, 1089, |
| 43656 | GIR_Done, |
| 43657 | // Label 2351: @111137 |
| 43658 | GIM_Try, /*On fail goto*//*Label 2352*/ 111189, // Rule ID 1091 // |
| 43659 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43660 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 43661 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 43662 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43663 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 43664 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 43665 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 43666 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 43667 | // (intrinsic_wo_chain:{ *:[v4i16] } 426:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SABDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 43668 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv4i16, |
| 43669 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43670 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43671 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43672 | GIR_EraseFromParent, /*InsnID*/0, |
| 43673 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43674 | // GIR_Coverage, 1091, |
| 43675 | GIR_Done, |
| 43676 | // Label 2352: @111189 |
| 43677 | GIM_Try, /*On fail goto*//*Label 2353*/ 111241, // Rule ID 1093 // |
| 43678 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43679 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 43680 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 43681 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43682 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 43683 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43684 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43685 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43686 | // (intrinsic_wo_chain:{ *:[v8i16] } 426:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SABDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 43687 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv8i16, |
| 43688 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43689 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43690 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43691 | GIR_EraseFromParent, /*InsnID*/0, |
| 43692 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43693 | // GIR_Coverage, 1093, |
| 43694 | GIR_Done, |
| 43695 | // Label 2353: @111241 |
| 43696 | GIM_Try, /*On fail goto*//*Label 2354*/ 111293, // Rule ID 1095 // |
| 43697 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43698 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 43699 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 43700 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 43701 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 43702 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 43703 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 43704 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 43705 | // (intrinsic_wo_chain:{ *:[v2i32] } 426:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SABDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 43706 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv2i32, |
| 43707 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43708 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43709 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43710 | GIR_EraseFromParent, /*InsnID*/0, |
| 43711 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43712 | // GIR_Coverage, 1095, |
| 43713 | GIR_Done, |
| 43714 | // Label 2354: @111293 |
| 43715 | GIM_Try, /*On fail goto*//*Label 2355*/ 111345, // Rule ID 1097 // |
| 43716 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43717 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 43718 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 43719 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 43720 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 43721 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43722 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43723 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43724 | // (intrinsic_wo_chain:{ *:[v4i32] } 426:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SABDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 43725 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDv4i32, |
| 43726 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43727 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43728 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43729 | GIR_EraseFromParent, /*InsnID*/0, |
| 43730 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43731 | // GIR_Coverage, 1097, |
| 43732 | GIR_Done, |
| 43733 | // Label 2355: @111345 |
| 43734 | GIM_Try, /*On fail goto*//*Label 2356*/ 111397, // Rule ID 1104 // |
| 43735 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43736 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shsub, |
| 43737 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 43738 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 43739 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 43740 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 43741 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 43742 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 43743 | // (intrinsic_wo_chain:{ *:[v8i8] } 436:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SHSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 43744 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv8i8, |
| 43745 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43746 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43747 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43748 | GIR_EraseFromParent, /*InsnID*/0, |
| 43749 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43750 | // GIR_Coverage, 1104, |
| 43751 | GIR_Done, |
| 43752 | // Label 2356: @111397 |
| 43753 | GIM_Try, /*On fail goto*//*Label 2357*/ 111449, // Rule ID 1105 // |
| 43754 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43755 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shsub, |
| 43756 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 43757 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 43758 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 43759 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43760 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43761 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43762 | // (intrinsic_wo_chain:{ *:[v16i8] } 436:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SHSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 43763 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv16i8, |
| 43764 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43765 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43766 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43767 | GIR_EraseFromParent, /*InsnID*/0, |
| 43768 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43769 | // GIR_Coverage, 1105, |
| 43770 | GIR_Done, |
| 43771 | // Label 2357: @111449 |
| 43772 | GIM_Try, /*On fail goto*//*Label 2358*/ 111501, // Rule ID 1106 // |
| 43773 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43774 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shsub, |
| 43775 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 43776 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43777 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 43778 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 43779 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 43780 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 43781 | // (intrinsic_wo_chain:{ *:[v4i16] } 436:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SHSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 43782 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv4i16, |
| 43783 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43784 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43785 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43786 | GIR_EraseFromParent, /*InsnID*/0, |
| 43787 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43788 | // GIR_Coverage, 1106, |
| 43789 | GIR_Done, |
| 43790 | // Label 2358: @111501 |
| 43791 | GIM_Try, /*On fail goto*//*Label 2359*/ 111553, // Rule ID 1107 // |
| 43792 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43793 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shsub, |
| 43794 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 43795 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43796 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 43797 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43798 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43799 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43800 | // (intrinsic_wo_chain:{ *:[v8i16] } 436:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SHSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 43801 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv8i16, |
| 43802 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43803 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43804 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43805 | GIR_EraseFromParent, /*InsnID*/0, |
| 43806 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43807 | // GIR_Coverage, 1107, |
| 43808 | GIR_Done, |
| 43809 | // Label 2359: @111553 |
| 43810 | GIM_Try, /*On fail goto*//*Label 2360*/ 111605, // Rule ID 1108 // |
| 43811 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43812 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shsub, |
| 43813 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 43814 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 43815 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 43816 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 43817 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 43818 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 43819 | // (intrinsic_wo_chain:{ *:[v2i32] } 436:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SHSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 43820 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv2i32, |
| 43821 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43822 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43823 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43824 | GIR_EraseFromParent, /*InsnID*/0, |
| 43825 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43826 | // GIR_Coverage, 1108, |
| 43827 | GIR_Done, |
| 43828 | // Label 2360: @111605 |
| 43829 | GIM_Try, /*On fail goto*//*Label 2361*/ 111657, // Rule ID 1109 // |
| 43830 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43831 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_shsub, |
| 43832 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 43833 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 43834 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 43835 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43836 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43837 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43838 | // (intrinsic_wo_chain:{ *:[v4i32] } 436:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 43839 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHSUBv4i32, |
| 43840 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43841 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43842 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43843 | GIR_EraseFromParent, /*InsnID*/0, |
| 43844 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43845 | // GIR_Coverage, 1109, |
| 43846 | GIR_Done, |
| 43847 | // Label 2361: @111657 |
| 43848 | GIM_Try, /*On fail goto*//*Label 2362*/ 111709, // Rule ID 1110 // |
| 43849 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43850 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smaxp, |
| 43851 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 43852 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 43853 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 43854 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 43855 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 43856 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 43857 | // (intrinsic_wo_chain:{ *:[v8i8] } 438:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SMAXPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 43858 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv8i8, |
| 43859 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43860 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43861 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43862 | GIR_EraseFromParent, /*InsnID*/0, |
| 43863 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43864 | // GIR_Coverage, 1110, |
| 43865 | GIR_Done, |
| 43866 | // Label 2362: @111709 |
| 43867 | GIM_Try, /*On fail goto*//*Label 2363*/ 111761, // Rule ID 1111 // |
| 43868 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43869 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smaxp, |
| 43870 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 43871 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 43872 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 43873 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43874 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43875 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43876 | // (intrinsic_wo_chain:{ *:[v16i8] } 438:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SMAXPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 43877 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv16i8, |
| 43878 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43879 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43880 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43881 | GIR_EraseFromParent, /*InsnID*/0, |
| 43882 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43883 | // GIR_Coverage, 1111, |
| 43884 | GIR_Done, |
| 43885 | // Label 2363: @111761 |
| 43886 | GIM_Try, /*On fail goto*//*Label 2364*/ 111813, // Rule ID 1112 // |
| 43887 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43888 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smaxp, |
| 43889 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 43890 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43891 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 43892 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 43893 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 43894 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 43895 | // (intrinsic_wo_chain:{ *:[v4i16] } 438:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SMAXPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 43896 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv4i16, |
| 43897 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43898 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43899 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43900 | GIR_EraseFromParent, /*InsnID*/0, |
| 43901 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43902 | // GIR_Coverage, 1112, |
| 43903 | GIR_Done, |
| 43904 | // Label 2364: @111813 |
| 43905 | GIM_Try, /*On fail goto*//*Label 2365*/ 111865, // Rule ID 1113 // |
| 43906 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43907 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smaxp, |
| 43908 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 43909 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43910 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 43911 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43912 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43913 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43914 | // (intrinsic_wo_chain:{ *:[v8i16] } 438:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SMAXPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 43915 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv8i16, |
| 43916 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43917 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43918 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43919 | GIR_EraseFromParent, /*InsnID*/0, |
| 43920 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43921 | // GIR_Coverage, 1113, |
| 43922 | GIR_Done, |
| 43923 | // Label 2365: @111865 |
| 43924 | GIM_Try, /*On fail goto*//*Label 2366*/ 111917, // Rule ID 1114 // |
| 43925 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43926 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smaxp, |
| 43927 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 43928 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 43929 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 43930 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 43931 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 43932 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 43933 | // (intrinsic_wo_chain:{ *:[v2i32] } 438:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SMAXPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 43934 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv2i32, |
| 43935 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43936 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43937 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43938 | GIR_EraseFromParent, /*InsnID*/0, |
| 43939 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43940 | // GIR_Coverage, 1114, |
| 43941 | GIR_Done, |
| 43942 | // Label 2366: @111917 |
| 43943 | GIM_Try, /*On fail goto*//*Label 2367*/ 111969, // Rule ID 1115 // |
| 43944 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43945 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smaxp, |
| 43946 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 43947 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 43948 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 43949 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43950 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43951 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43952 | // (intrinsic_wo_chain:{ *:[v4i32] } 438:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SMAXPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 43953 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMAXPv4i32, |
| 43954 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43955 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43956 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43957 | GIR_EraseFromParent, /*InsnID*/0, |
| 43958 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43959 | // GIR_Coverage, 1115, |
| 43960 | GIR_Done, |
| 43961 | // Label 2367: @111969 |
| 43962 | GIM_Try, /*On fail goto*//*Label 2368*/ 112021, // Rule ID 1122 // |
| 43963 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43964 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sminp, |
| 43965 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 43966 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 43967 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 43968 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 43969 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 43970 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 43971 | // (intrinsic_wo_chain:{ *:[v8i8] } 441:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SMINPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 43972 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv8i8, |
| 43973 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43974 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43975 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43976 | GIR_EraseFromParent, /*InsnID*/0, |
| 43977 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43978 | // GIR_Coverage, 1122, |
| 43979 | GIR_Done, |
| 43980 | // Label 2368: @112021 |
| 43981 | GIM_Try, /*On fail goto*//*Label 2369*/ 112073, // Rule ID 1123 // |
| 43982 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 43983 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sminp, |
| 43984 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 43985 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 43986 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 43987 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 43988 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 43989 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 43990 | // (intrinsic_wo_chain:{ *:[v16i8] } 441:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SMINPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 43991 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv16i8, |
| 43992 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 43993 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 43994 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 43995 | GIR_EraseFromParent, /*InsnID*/0, |
| 43996 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 43997 | // GIR_Coverage, 1123, |
| 43998 | GIR_Done, |
| 43999 | // Label 2369: @112073 |
| 44000 | GIM_Try, /*On fail goto*//*Label 2370*/ 112125, // Rule ID 1124 // |
| 44001 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44002 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sminp, |
| 44003 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 44004 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 44005 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 44006 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 44007 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 44008 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 44009 | // (intrinsic_wo_chain:{ *:[v4i16] } 441:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SMINPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 44010 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv4i16, |
| 44011 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44012 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44013 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44014 | GIR_EraseFromParent, /*InsnID*/0, |
| 44015 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44016 | // GIR_Coverage, 1124, |
| 44017 | GIR_Done, |
| 44018 | // Label 2370: @112125 |
| 44019 | GIM_Try, /*On fail goto*//*Label 2371*/ 112177, // Rule ID 1125 // |
| 44020 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44021 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sminp, |
| 44022 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 44023 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 44024 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 44025 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44026 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44027 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44028 | // (intrinsic_wo_chain:{ *:[v8i16] } 441:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SMINPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 44029 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv8i16, |
| 44030 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44031 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44032 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44033 | GIR_EraseFromParent, /*InsnID*/0, |
| 44034 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44035 | // GIR_Coverage, 1125, |
| 44036 | GIR_Done, |
| 44037 | // Label 2371: @112177 |
| 44038 | GIM_Try, /*On fail goto*//*Label 2372*/ 112229, // Rule ID 1126 // |
| 44039 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44040 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sminp, |
| 44041 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 44042 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 44043 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 44044 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 44045 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 44046 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 44047 | // (intrinsic_wo_chain:{ *:[v2i32] } 441:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SMINPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 44048 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv2i32, |
| 44049 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44050 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44051 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44052 | GIR_EraseFromParent, /*InsnID*/0, |
| 44053 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44054 | // GIR_Coverage, 1126, |
| 44055 | GIR_Done, |
| 44056 | // Label 2372: @112229 |
| 44057 | GIM_Try, /*On fail goto*//*Label 2373*/ 112281, // Rule ID 1127 // |
| 44058 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44059 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sminp, |
| 44060 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 44061 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 44062 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 44063 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44064 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44065 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44066 | // (intrinsic_wo_chain:{ *:[v4i32] } 441:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SMINPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 44067 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMINPv4i32, |
| 44068 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44069 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44070 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44071 | GIR_EraseFromParent, /*InsnID*/0, |
| 44072 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44073 | // GIR_Coverage, 1127, |
| 44074 | GIR_Done, |
| 44075 | // Label 2373: @112281 |
| 44076 | GIM_Try, /*On fail goto*//*Label 2374*/ 112333, // Rule ID 1134 // |
| 44077 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44078 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 44079 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 44080 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 44081 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 44082 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 44083 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 44084 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 44085 | // (intrinsic_wo_chain:{ *:[v8i8] } 446:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 44086 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv8i8, |
| 44087 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44088 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44089 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44090 | GIR_EraseFromParent, /*InsnID*/0, |
| 44091 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44092 | // GIR_Coverage, 1134, |
| 44093 | GIR_Done, |
| 44094 | // Label 2374: @112333 |
| 44095 | GIM_Try, /*On fail goto*//*Label 2375*/ 112385, // Rule ID 1135 // |
| 44096 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44097 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 44098 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 44099 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 44100 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 44101 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44102 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44103 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44104 | // (intrinsic_wo_chain:{ *:[v16i8] } 446:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 44105 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv16i8, |
| 44106 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44107 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44108 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44109 | GIR_EraseFromParent, /*InsnID*/0, |
| 44110 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44111 | // GIR_Coverage, 1135, |
| 44112 | GIR_Done, |
| 44113 | // Label 2375: @112385 |
| 44114 | GIM_Try, /*On fail goto*//*Label 2376*/ 112437, // Rule ID 1136 // |
| 44115 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44116 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 44117 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 44118 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 44119 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 44120 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 44121 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 44122 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 44123 | // (intrinsic_wo_chain:{ *:[v4i16] } 446:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 44124 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv4i16, |
| 44125 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44126 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44127 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44128 | GIR_EraseFromParent, /*InsnID*/0, |
| 44129 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44130 | // GIR_Coverage, 1136, |
| 44131 | GIR_Done, |
| 44132 | // Label 2376: @112437 |
| 44133 | GIM_Try, /*On fail goto*//*Label 2377*/ 112489, // Rule ID 1137 // |
| 44134 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44135 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 44136 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 44137 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 44138 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 44139 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44140 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44141 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44142 | // (intrinsic_wo_chain:{ *:[v8i16] } 446:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 44143 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv8i16, |
| 44144 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44145 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44146 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44147 | GIR_EraseFromParent, /*InsnID*/0, |
| 44148 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44149 | // GIR_Coverage, 1137, |
| 44150 | GIR_Done, |
| 44151 | // Label 2377: @112489 |
| 44152 | GIM_Try, /*On fail goto*//*Label 2378*/ 112541, // Rule ID 1138 // |
| 44153 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44154 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 44155 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 44156 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 44157 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 44158 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 44159 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 44160 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 44161 | // (intrinsic_wo_chain:{ *:[v2i32] } 446:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 44162 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv2i32, |
| 44163 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44164 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44165 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44166 | GIR_EraseFromParent, /*InsnID*/0, |
| 44167 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44168 | // GIR_Coverage, 1138, |
| 44169 | GIR_Done, |
| 44170 | // Label 2378: @112541 |
| 44171 | GIM_Try, /*On fail goto*//*Label 2379*/ 112593, // Rule ID 1139 // |
| 44172 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44173 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 44174 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 44175 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 44176 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 44177 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44178 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44179 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44180 | // (intrinsic_wo_chain:{ *:[v4i32] } 446:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 44181 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv4i32, |
| 44182 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44183 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44184 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44185 | GIR_EraseFromParent, /*InsnID*/0, |
| 44186 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44187 | // GIR_Coverage, 1139, |
| 44188 | GIR_Done, |
| 44189 | // Label 2379: @112593 |
| 44190 | GIM_Try, /*On fail goto*//*Label 2380*/ 112645, // Rule ID 1140 // |
| 44191 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44192 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 44193 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 44194 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 44195 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 44196 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44197 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44198 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44199 | // (intrinsic_wo_chain:{ *:[v2i64] } 446:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 44200 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv2i64, |
| 44201 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44202 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44203 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44204 | GIR_EraseFromParent, /*InsnID*/0, |
| 44205 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44206 | // GIR_Coverage, 1140, |
| 44207 | GIR_Done, |
| 44208 | // Label 2380: @112645 |
| 44209 | GIM_Try, /*On fail goto*//*Label 2381*/ 112697, // Rule ID 1141 // |
| 44210 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44211 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, |
| 44212 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 44213 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 44214 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 44215 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 44216 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 44217 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 44218 | // (intrinsic_wo_chain:{ *:[v4i16] } 447:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQDMULHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 44219 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv4i16, |
| 44220 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44221 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44222 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44223 | GIR_EraseFromParent, /*InsnID*/0, |
| 44224 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44225 | // GIR_Coverage, 1141, |
| 44226 | GIR_Done, |
| 44227 | // Label 2381: @112697 |
| 44228 | GIM_Try, /*On fail goto*//*Label 2382*/ 112749, // Rule ID 1142 // |
| 44229 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44230 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, |
| 44231 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 44232 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 44233 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 44234 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44235 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44236 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44237 | // (intrinsic_wo_chain:{ *:[v8i16] } 447:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQDMULHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 44238 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv8i16, |
| 44239 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44240 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44241 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44242 | GIR_EraseFromParent, /*InsnID*/0, |
| 44243 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44244 | // GIR_Coverage, 1142, |
| 44245 | GIR_Done, |
| 44246 | // Label 2382: @112749 |
| 44247 | GIM_Try, /*On fail goto*//*Label 2383*/ 112801, // Rule ID 1143 // |
| 44248 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44249 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, |
| 44250 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 44251 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 44252 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 44253 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 44254 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 44255 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 44256 | // (intrinsic_wo_chain:{ *:[v2i32] } 447:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQDMULHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 44257 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv2i32, |
| 44258 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44259 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44260 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44261 | GIR_EraseFromParent, /*InsnID*/0, |
| 44262 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44263 | // GIR_Coverage, 1143, |
| 44264 | GIR_Done, |
| 44265 | // Label 2383: @112801 |
| 44266 | GIM_Try, /*On fail goto*//*Label 2384*/ 112853, // Rule ID 1144 // |
| 44267 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44268 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, |
| 44269 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 44270 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 44271 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 44272 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44273 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44274 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44275 | // (intrinsic_wo_chain:{ *:[v4i32] } 447:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQDMULHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 44276 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv4i32, |
| 44277 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44278 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44279 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44280 | GIR_EraseFromParent, /*InsnID*/0, |
| 44281 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44282 | // GIR_Coverage, 1144, |
| 44283 | GIR_Done, |
| 44284 | // Label 2384: @112853 |
| 44285 | GIM_Try, /*On fail goto*//*Label 2385*/ 112905, // Rule ID 1145 // |
| 44286 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44287 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 44288 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 44289 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 44290 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 44291 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 44292 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 44293 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 44294 | // (intrinsic_wo_chain:{ *:[v4i16] } 453:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQRDMULHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 44295 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv4i16, |
| 44296 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44297 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44298 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44299 | GIR_EraseFromParent, /*InsnID*/0, |
| 44300 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44301 | // GIR_Coverage, 1145, |
| 44302 | GIR_Done, |
| 44303 | // Label 2385: @112905 |
| 44304 | GIM_Try, /*On fail goto*//*Label 2386*/ 112957, // Rule ID 1146 // |
| 44305 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44306 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 44307 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 44308 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 44309 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 44310 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44311 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44312 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44313 | // (intrinsic_wo_chain:{ *:[v8i16] } 453:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQRDMULHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 44314 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv8i16, |
| 44315 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44316 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44317 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44318 | GIR_EraseFromParent, /*InsnID*/0, |
| 44319 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44320 | // GIR_Coverage, 1146, |
| 44321 | GIR_Done, |
| 44322 | // Label 2386: @112957 |
| 44323 | GIM_Try, /*On fail goto*//*Label 2387*/ 113009, // Rule ID 1147 // |
| 44324 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44325 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 44326 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 44327 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 44328 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 44329 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 44330 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 44331 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 44332 | // (intrinsic_wo_chain:{ *:[v2i32] } 453:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQRDMULHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 44333 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv2i32, |
| 44334 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44335 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44336 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44337 | GIR_EraseFromParent, /*InsnID*/0, |
| 44338 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44339 | // GIR_Coverage, 1147, |
| 44340 | GIR_Done, |
| 44341 | // Label 2387: @113009 |
| 44342 | GIM_Try, /*On fail goto*//*Label 2388*/ 113061, // Rule ID 1148 // |
| 44343 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44344 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 44345 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 44346 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 44347 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 44348 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44349 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44350 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44351 | // (intrinsic_wo_chain:{ *:[v4i32] } 453:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQRDMULHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 44352 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv4i32, |
| 44353 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44354 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44355 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44356 | GIR_EraseFromParent, /*InsnID*/0, |
| 44357 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44358 | // GIR_Coverage, 1148, |
| 44359 | GIR_Done, |
| 44360 | // Label 2388: @113061 |
| 44361 | GIM_Try, /*On fail goto*//*Label 2389*/ 113113, // Rule ID 1149 // |
| 44362 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44363 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, |
| 44364 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 44365 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 44366 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 44367 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 44368 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 44369 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 44370 | // (intrinsic_wo_chain:{ *:[v8i8] } 456:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SQRSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 44371 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv8i8, |
| 44372 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44373 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44374 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44375 | GIR_EraseFromParent, /*InsnID*/0, |
| 44376 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44377 | // GIR_Coverage, 1149, |
| 44378 | GIR_Done, |
| 44379 | // Label 2389: @113113 |
| 44380 | GIM_Try, /*On fail goto*//*Label 2390*/ 113165, // Rule ID 1150 // |
| 44381 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44382 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, |
| 44383 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 44384 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 44385 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 44386 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44387 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44388 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44389 | // (intrinsic_wo_chain:{ *:[v16i8] } 456:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SQRSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 44390 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv16i8, |
| 44391 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44392 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44393 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44394 | GIR_EraseFromParent, /*InsnID*/0, |
| 44395 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44396 | // GIR_Coverage, 1150, |
| 44397 | GIR_Done, |
| 44398 | // Label 2390: @113165 |
| 44399 | GIM_Try, /*On fail goto*//*Label 2391*/ 113217, // Rule ID 1151 // |
| 44400 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44401 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, |
| 44402 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 44403 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 44404 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 44405 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 44406 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 44407 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 44408 | // (intrinsic_wo_chain:{ *:[v4i16] } 456:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQRSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 44409 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv4i16, |
| 44410 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44411 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44412 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44413 | GIR_EraseFromParent, /*InsnID*/0, |
| 44414 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44415 | // GIR_Coverage, 1151, |
| 44416 | GIR_Done, |
| 44417 | // Label 2391: @113217 |
| 44418 | GIM_Try, /*On fail goto*//*Label 2392*/ 113269, // Rule ID 1152 // |
| 44419 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44420 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, |
| 44421 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 44422 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 44423 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 44424 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44425 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44426 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44427 | // (intrinsic_wo_chain:{ *:[v8i16] } 456:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQRSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 44428 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv8i16, |
| 44429 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44430 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44431 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44432 | GIR_EraseFromParent, /*InsnID*/0, |
| 44433 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44434 | // GIR_Coverage, 1152, |
| 44435 | GIR_Done, |
| 44436 | // Label 2392: @113269 |
| 44437 | GIM_Try, /*On fail goto*//*Label 2393*/ 113321, // Rule ID 1153 // |
| 44438 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44439 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, |
| 44440 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 44441 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 44442 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 44443 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 44444 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 44445 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 44446 | // (intrinsic_wo_chain:{ *:[v2i32] } 456:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQRSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 44447 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv2i32, |
| 44448 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44449 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44450 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44451 | GIR_EraseFromParent, /*InsnID*/0, |
| 44452 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44453 | // GIR_Coverage, 1153, |
| 44454 | GIR_Done, |
| 44455 | // Label 2393: @113321 |
| 44456 | GIM_Try, /*On fail goto*//*Label 2394*/ 113373, // Rule ID 1154 // |
| 44457 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44458 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, |
| 44459 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 44460 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 44461 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 44462 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44463 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44464 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44465 | // (intrinsic_wo_chain:{ *:[v4i32] } 456:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQRSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 44466 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv4i32, |
| 44467 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44468 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44469 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44470 | GIR_EraseFromParent, /*InsnID*/0, |
| 44471 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44472 | // GIR_Coverage, 1154, |
| 44473 | GIR_Done, |
| 44474 | // Label 2394: @113373 |
| 44475 | GIM_Try, /*On fail goto*//*Label 2395*/ 113425, // Rule ID 1155 // |
| 44476 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44477 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, |
| 44478 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 44479 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 44480 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 44481 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44482 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44483 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44484 | // (intrinsic_wo_chain:{ *:[v2i64] } 456:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SQRSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 44485 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv2i64, |
| 44486 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44487 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44488 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44489 | GIR_EraseFromParent, /*InsnID*/0, |
| 44490 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44491 | // GIR_Coverage, 1155, |
| 44492 | GIR_Done, |
| 44493 | // Label 2395: @113425 |
| 44494 | GIM_Try, /*On fail goto*//*Label 2396*/ 113477, // Rule ID 1156 // |
| 44495 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44496 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, |
| 44497 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 44498 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 44499 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 44500 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 44501 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 44502 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 44503 | // (intrinsic_wo_chain:{ *:[v8i8] } 459:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SQSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 44504 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv8i8, |
| 44505 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44506 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44507 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44508 | GIR_EraseFromParent, /*InsnID*/0, |
| 44509 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44510 | // GIR_Coverage, 1156, |
| 44511 | GIR_Done, |
| 44512 | // Label 2396: @113477 |
| 44513 | GIM_Try, /*On fail goto*//*Label 2397*/ 113529, // Rule ID 1157 // |
| 44514 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44515 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, |
| 44516 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 44517 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 44518 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 44519 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44520 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44521 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44522 | // (intrinsic_wo_chain:{ *:[v16i8] } 459:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SQSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 44523 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv16i8, |
| 44524 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44525 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44526 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44527 | GIR_EraseFromParent, /*InsnID*/0, |
| 44528 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44529 | // GIR_Coverage, 1157, |
| 44530 | GIR_Done, |
| 44531 | // Label 2397: @113529 |
| 44532 | GIM_Try, /*On fail goto*//*Label 2398*/ 113581, // Rule ID 1158 // |
| 44533 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44534 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, |
| 44535 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 44536 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 44537 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 44538 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 44539 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 44540 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 44541 | // (intrinsic_wo_chain:{ *:[v4i16] } 459:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 44542 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv4i16, |
| 44543 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44544 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44545 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44546 | GIR_EraseFromParent, /*InsnID*/0, |
| 44547 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44548 | // GIR_Coverage, 1158, |
| 44549 | GIR_Done, |
| 44550 | // Label 2398: @113581 |
| 44551 | GIM_Try, /*On fail goto*//*Label 2399*/ 113633, // Rule ID 1159 // |
| 44552 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44553 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, |
| 44554 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 44555 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 44556 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 44557 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44558 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44559 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44560 | // (intrinsic_wo_chain:{ *:[v8i16] } 459:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 44561 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv8i16, |
| 44562 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44563 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44564 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44565 | GIR_EraseFromParent, /*InsnID*/0, |
| 44566 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44567 | // GIR_Coverage, 1159, |
| 44568 | GIR_Done, |
| 44569 | // Label 2399: @113633 |
| 44570 | GIM_Try, /*On fail goto*//*Label 2400*/ 113685, // Rule ID 1160 // |
| 44571 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44572 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, |
| 44573 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 44574 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 44575 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 44576 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 44577 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 44578 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 44579 | // (intrinsic_wo_chain:{ *:[v2i32] } 459:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 44580 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv2i32, |
| 44581 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44582 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44583 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44584 | GIR_EraseFromParent, /*InsnID*/0, |
| 44585 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44586 | // GIR_Coverage, 1160, |
| 44587 | GIR_Done, |
| 44588 | // Label 2400: @113685 |
| 44589 | GIM_Try, /*On fail goto*//*Label 2401*/ 113737, // Rule ID 1161 // |
| 44590 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44591 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, |
| 44592 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 44593 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 44594 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 44595 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44596 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44597 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44598 | // (intrinsic_wo_chain:{ *:[v4i32] } 459:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 44599 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv4i32, |
| 44600 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44601 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44602 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44603 | GIR_EraseFromParent, /*InsnID*/0, |
| 44604 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44605 | // GIR_Coverage, 1161, |
| 44606 | GIR_Done, |
| 44607 | // Label 2401: @113737 |
| 44608 | GIM_Try, /*On fail goto*//*Label 2402*/ 113789, // Rule ID 1162 // |
| 44609 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44610 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, |
| 44611 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 44612 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 44613 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 44614 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44615 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44616 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44617 | // (intrinsic_wo_chain:{ *:[v2i64] } 459:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SQSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 44618 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv2i64, |
| 44619 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44620 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44621 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44622 | GIR_EraseFromParent, /*InsnID*/0, |
| 44623 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44624 | // GIR_Coverage, 1162, |
| 44625 | GIR_Done, |
| 44626 | // Label 2402: @113789 |
| 44627 | GIM_Try, /*On fail goto*//*Label 2403*/ 113841, // Rule ID 1163 // |
| 44628 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44629 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 44630 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 44631 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 44632 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 44633 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 44634 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 44635 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 44636 | // (intrinsic_wo_chain:{ *:[v8i8] } 463:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SQSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 44637 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv8i8, |
| 44638 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44639 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44640 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44641 | GIR_EraseFromParent, /*InsnID*/0, |
| 44642 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44643 | // GIR_Coverage, 1163, |
| 44644 | GIR_Done, |
| 44645 | // Label 2403: @113841 |
| 44646 | GIM_Try, /*On fail goto*//*Label 2404*/ 113893, // Rule ID 1164 // |
| 44647 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44648 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 44649 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 44650 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 44651 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 44652 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44653 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44654 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44655 | // (intrinsic_wo_chain:{ *:[v16i8] } 463:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SQSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 44656 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv16i8, |
| 44657 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44658 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44659 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44660 | GIR_EraseFromParent, /*InsnID*/0, |
| 44661 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44662 | // GIR_Coverage, 1164, |
| 44663 | GIR_Done, |
| 44664 | // Label 2404: @113893 |
| 44665 | GIM_Try, /*On fail goto*//*Label 2405*/ 113945, // Rule ID 1165 // |
| 44666 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44667 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 44668 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 44669 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 44670 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 44671 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 44672 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 44673 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 44674 | // (intrinsic_wo_chain:{ *:[v4i16] } 463:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 44675 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv4i16, |
| 44676 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44677 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44678 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44679 | GIR_EraseFromParent, /*InsnID*/0, |
| 44680 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44681 | // GIR_Coverage, 1165, |
| 44682 | GIR_Done, |
| 44683 | // Label 2405: @113945 |
| 44684 | GIM_Try, /*On fail goto*//*Label 2406*/ 113997, // Rule ID 1166 // |
| 44685 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44686 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 44687 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 44688 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 44689 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 44690 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44691 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44692 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44693 | // (intrinsic_wo_chain:{ *:[v8i16] } 463:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 44694 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv8i16, |
| 44695 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44696 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44697 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44698 | GIR_EraseFromParent, /*InsnID*/0, |
| 44699 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44700 | // GIR_Coverage, 1166, |
| 44701 | GIR_Done, |
| 44702 | // Label 2406: @113997 |
| 44703 | GIM_Try, /*On fail goto*//*Label 2407*/ 114049, // Rule ID 1167 // |
| 44704 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44705 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 44706 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 44707 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 44708 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 44709 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 44710 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 44711 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 44712 | // (intrinsic_wo_chain:{ *:[v2i32] } 463:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 44713 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv2i32, |
| 44714 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44715 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44716 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44717 | GIR_EraseFromParent, /*InsnID*/0, |
| 44718 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44719 | // GIR_Coverage, 1167, |
| 44720 | GIR_Done, |
| 44721 | // Label 2407: @114049 |
| 44722 | GIM_Try, /*On fail goto*//*Label 2408*/ 114101, // Rule ID 1168 // |
| 44723 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44724 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 44725 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 44726 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 44727 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 44728 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44729 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44730 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44731 | // (intrinsic_wo_chain:{ *:[v4i32] } 463:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 44732 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv4i32, |
| 44733 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44734 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44735 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44736 | GIR_EraseFromParent, /*InsnID*/0, |
| 44737 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44738 | // GIR_Coverage, 1168, |
| 44739 | GIR_Done, |
| 44740 | // Label 2408: @114101 |
| 44741 | GIM_Try, /*On fail goto*//*Label 2409*/ 114153, // Rule ID 1169 // |
| 44742 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44743 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 44744 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 44745 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 44746 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 44747 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44748 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44749 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44750 | // (intrinsic_wo_chain:{ *:[v2i64] } 463:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SQSUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 44751 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv2i64, |
| 44752 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44753 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44754 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44755 | GIR_EraseFromParent, /*InsnID*/0, |
| 44756 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44757 | // GIR_Coverage, 1169, |
| 44758 | GIR_Done, |
| 44759 | // Label 2409: @114153 |
| 44760 | GIM_Try, /*On fail goto*//*Label 2410*/ 114205, // Rule ID 1176 // |
| 44761 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44762 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, |
| 44763 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 44764 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 44765 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 44766 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 44767 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 44768 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 44769 | // (intrinsic_wo_chain:{ *:[v8i8] } 467:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SRSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 44770 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv8i8, |
| 44771 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44772 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44773 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44774 | GIR_EraseFromParent, /*InsnID*/0, |
| 44775 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44776 | // GIR_Coverage, 1176, |
| 44777 | GIR_Done, |
| 44778 | // Label 2410: @114205 |
| 44779 | GIM_Try, /*On fail goto*//*Label 2411*/ 114257, // Rule ID 1177 // |
| 44780 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44781 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, |
| 44782 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 44783 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 44784 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 44785 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44786 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44787 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44788 | // (intrinsic_wo_chain:{ *:[v16i8] } 467:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SRSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 44789 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv16i8, |
| 44790 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44791 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44792 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44793 | GIR_EraseFromParent, /*InsnID*/0, |
| 44794 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44795 | // GIR_Coverage, 1177, |
| 44796 | GIR_Done, |
| 44797 | // Label 2411: @114257 |
| 44798 | GIM_Try, /*On fail goto*//*Label 2412*/ 114309, // Rule ID 1178 // |
| 44799 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44800 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, |
| 44801 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 44802 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 44803 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 44804 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 44805 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 44806 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 44807 | // (intrinsic_wo_chain:{ *:[v4i16] } 467:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SRSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 44808 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv4i16, |
| 44809 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44810 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44811 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44812 | GIR_EraseFromParent, /*InsnID*/0, |
| 44813 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44814 | // GIR_Coverage, 1178, |
| 44815 | GIR_Done, |
| 44816 | // Label 2412: @114309 |
| 44817 | GIM_Try, /*On fail goto*//*Label 2413*/ 114361, // Rule ID 1179 // |
| 44818 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44819 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, |
| 44820 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 44821 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 44822 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 44823 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44824 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44825 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44826 | // (intrinsic_wo_chain:{ *:[v8i16] } 467:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SRSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 44827 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv8i16, |
| 44828 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44829 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44830 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44831 | GIR_EraseFromParent, /*InsnID*/0, |
| 44832 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44833 | // GIR_Coverage, 1179, |
| 44834 | GIR_Done, |
| 44835 | // Label 2413: @114361 |
| 44836 | GIM_Try, /*On fail goto*//*Label 2414*/ 114413, // Rule ID 1180 // |
| 44837 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44838 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, |
| 44839 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 44840 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 44841 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 44842 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 44843 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 44844 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 44845 | // (intrinsic_wo_chain:{ *:[v2i32] } 467:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SRSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 44846 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv2i32, |
| 44847 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44848 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44849 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44850 | GIR_EraseFromParent, /*InsnID*/0, |
| 44851 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44852 | // GIR_Coverage, 1180, |
| 44853 | GIR_Done, |
| 44854 | // Label 2414: @114413 |
| 44855 | GIM_Try, /*On fail goto*//*Label 2415*/ 114465, // Rule ID 1181 // |
| 44856 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44857 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, |
| 44858 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 44859 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 44860 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 44861 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44862 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44863 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44864 | // (intrinsic_wo_chain:{ *:[v4i32] } 467:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SRSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 44865 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv4i32, |
| 44866 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44867 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44868 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44869 | GIR_EraseFromParent, /*InsnID*/0, |
| 44870 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44871 | // GIR_Coverage, 1181, |
| 44872 | GIR_Done, |
| 44873 | // Label 2415: @114465 |
| 44874 | GIM_Try, /*On fail goto*//*Label 2416*/ 114517, // Rule ID 1182 // |
| 44875 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44876 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, |
| 44877 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 44878 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 44879 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 44880 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44881 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44882 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44883 | // (intrinsic_wo_chain:{ *:[v2i64] } 467:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SRSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 44884 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv2i64, |
| 44885 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44886 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44887 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44888 | GIR_EraseFromParent, /*InsnID*/0, |
| 44889 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44890 | // GIR_Coverage, 1182, |
| 44891 | GIR_Done, |
| 44892 | // Label 2416: @114517 |
| 44893 | GIM_Try, /*On fail goto*//*Label 2417*/ 114569, // Rule ID 1183 // |
| 44894 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44895 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, |
| 44896 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 44897 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 44898 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 44899 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 44900 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 44901 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 44902 | // (intrinsic_wo_chain:{ *:[v8i8] } 468:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 44903 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv8i8, |
| 44904 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44905 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44906 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44907 | GIR_EraseFromParent, /*InsnID*/0, |
| 44908 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44909 | // GIR_Coverage, 1183, |
| 44910 | GIR_Done, |
| 44911 | // Label 2417: @114569 |
| 44912 | GIM_Try, /*On fail goto*//*Label 2418*/ 114621, // Rule ID 1184 // |
| 44913 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44914 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, |
| 44915 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 44916 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 44917 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 44918 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44919 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44920 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44921 | // (intrinsic_wo_chain:{ *:[v16i8] } 468:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 44922 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv16i8, |
| 44923 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44924 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44925 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44926 | GIR_EraseFromParent, /*InsnID*/0, |
| 44927 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44928 | // GIR_Coverage, 1184, |
| 44929 | GIR_Done, |
| 44930 | // Label 2418: @114621 |
| 44931 | GIM_Try, /*On fail goto*//*Label 2419*/ 114673, // Rule ID 1185 // |
| 44932 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44933 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, |
| 44934 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 44935 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 44936 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 44937 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 44938 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 44939 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 44940 | // (intrinsic_wo_chain:{ *:[v4i16] } 468:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 44941 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv4i16, |
| 44942 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44943 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44944 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44945 | GIR_EraseFromParent, /*InsnID*/0, |
| 44946 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44947 | // GIR_Coverage, 1185, |
| 44948 | GIR_Done, |
| 44949 | // Label 2419: @114673 |
| 44950 | GIM_Try, /*On fail goto*//*Label 2420*/ 114725, // Rule ID 1186 // |
| 44951 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44952 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, |
| 44953 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 44954 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 44955 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 44956 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44957 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44958 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44959 | // (intrinsic_wo_chain:{ *:[v8i16] } 468:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 44960 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv8i16, |
| 44961 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44962 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44963 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44964 | GIR_EraseFromParent, /*InsnID*/0, |
| 44965 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44966 | // GIR_Coverage, 1186, |
| 44967 | GIR_Done, |
| 44968 | // Label 2420: @114725 |
| 44969 | GIM_Try, /*On fail goto*//*Label 2421*/ 114777, // Rule ID 1187 // |
| 44970 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44971 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, |
| 44972 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 44973 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 44974 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 44975 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 44976 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 44977 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 44978 | // (intrinsic_wo_chain:{ *:[v2i32] } 468:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 44979 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv2i32, |
| 44980 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 44981 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 44982 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 44983 | GIR_EraseFromParent, /*InsnID*/0, |
| 44984 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 44985 | // GIR_Coverage, 1187, |
| 44986 | GIR_Done, |
| 44987 | // Label 2421: @114777 |
| 44988 | GIM_Try, /*On fail goto*//*Label 2422*/ 114829, // Rule ID 1188 // |
| 44989 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 44990 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, |
| 44991 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 44992 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 44993 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 44994 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 44995 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 44996 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 44997 | // (intrinsic_wo_chain:{ *:[v4i32] } 468:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 44998 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv4i32, |
| 44999 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45000 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45001 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45002 | GIR_EraseFromParent, /*InsnID*/0, |
| 45003 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45004 | // GIR_Coverage, 1188, |
| 45005 | GIR_Done, |
| 45006 | // Label 2422: @114829 |
| 45007 | GIM_Try, /*On fail goto*//*Label 2423*/ 114881, // Rule ID 1189 // |
| 45008 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45009 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, |
| 45010 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 45011 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 45012 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 45013 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45014 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45015 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45016 | // (intrinsic_wo_chain:{ *:[v2i64] } 468:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 45017 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv2i64, |
| 45018 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45019 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45020 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45021 | GIR_EraseFromParent, /*InsnID*/0, |
| 45022 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45023 | // GIR_Coverage, 1189, |
| 45024 | GIR_Done, |
| 45025 | // Label 2423: @114881 |
| 45026 | GIM_Try, /*On fail goto*//*Label 2424*/ 114933, // Rule ID 1210 // |
| 45027 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45028 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 45029 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 45030 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 45031 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 45032 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 45033 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 45034 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 45035 | // (intrinsic_wo_chain:{ *:[v8i8] } 489:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UABDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 45036 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv8i8, |
| 45037 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45038 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45039 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45040 | GIR_EraseFromParent, /*InsnID*/0, |
| 45041 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45042 | // GIR_Coverage, 1210, |
| 45043 | GIR_Done, |
| 45044 | // Label 2424: @114933 |
| 45045 | GIM_Try, /*On fail goto*//*Label 2425*/ 114985, // Rule ID 1212 // |
| 45046 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45047 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 45048 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 45049 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 45050 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 45051 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45052 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45053 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45054 | // (intrinsic_wo_chain:{ *:[v16i8] } 489:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UABDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 45055 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv16i8, |
| 45056 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45057 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45058 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45059 | GIR_EraseFromParent, /*InsnID*/0, |
| 45060 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45061 | // GIR_Coverage, 1212, |
| 45062 | GIR_Done, |
| 45063 | // Label 2425: @114985 |
| 45064 | GIM_Try, /*On fail goto*//*Label 2426*/ 115037, // Rule ID 1214 // |
| 45065 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45066 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 45067 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 45068 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 45069 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 45070 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 45071 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 45072 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 45073 | // (intrinsic_wo_chain:{ *:[v4i16] } 489:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UABDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 45074 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv4i16, |
| 45075 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45076 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45077 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45078 | GIR_EraseFromParent, /*InsnID*/0, |
| 45079 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45080 | // GIR_Coverage, 1214, |
| 45081 | GIR_Done, |
| 45082 | // Label 2426: @115037 |
| 45083 | GIM_Try, /*On fail goto*//*Label 2427*/ 115089, // Rule ID 1216 // |
| 45084 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45085 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 45086 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 45087 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 45088 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 45089 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45090 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45091 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45092 | // (intrinsic_wo_chain:{ *:[v8i16] } 489:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UABDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 45093 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv8i16, |
| 45094 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45095 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45096 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45097 | GIR_EraseFromParent, /*InsnID*/0, |
| 45098 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45099 | // GIR_Coverage, 1216, |
| 45100 | GIR_Done, |
| 45101 | // Label 2427: @115089 |
| 45102 | GIM_Try, /*On fail goto*//*Label 2428*/ 115141, // Rule ID 1218 // |
| 45103 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45104 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 45105 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 45106 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 45107 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 45108 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 45109 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 45110 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 45111 | // (intrinsic_wo_chain:{ *:[v2i32] } 489:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UABDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 45112 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv2i32, |
| 45113 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45114 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45115 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45116 | GIR_EraseFromParent, /*InsnID*/0, |
| 45117 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45118 | // GIR_Coverage, 1218, |
| 45119 | GIR_Done, |
| 45120 | // Label 2428: @115141 |
| 45121 | GIM_Try, /*On fail goto*//*Label 2429*/ 115193, // Rule ID 1220 // |
| 45122 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45123 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 45124 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 45125 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 45126 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 45127 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45128 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45129 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45130 | // (intrinsic_wo_chain:{ *:[v4i32] } 489:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UABDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 45131 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDv4i32, |
| 45132 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45133 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45134 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45135 | GIR_EraseFromParent, /*InsnID*/0, |
| 45136 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45137 | // GIR_Coverage, 1220, |
| 45138 | GIR_Done, |
| 45139 | // Label 2429: @115193 |
| 45140 | GIM_Try, /*On fail goto*//*Label 2430*/ 115245, // Rule ID 1227 // |
| 45141 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45142 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhsub, |
| 45143 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 45144 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 45145 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 45146 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 45147 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 45148 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 45149 | // (intrinsic_wo_chain:{ *:[v8i8] } 495:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UHSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 45150 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv8i8, |
| 45151 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45152 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45153 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45154 | GIR_EraseFromParent, /*InsnID*/0, |
| 45155 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45156 | // GIR_Coverage, 1227, |
| 45157 | GIR_Done, |
| 45158 | // Label 2430: @115245 |
| 45159 | GIM_Try, /*On fail goto*//*Label 2431*/ 115297, // Rule ID 1228 // |
| 45160 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45161 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhsub, |
| 45162 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 45163 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 45164 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 45165 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45166 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45167 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45168 | // (intrinsic_wo_chain:{ *:[v16i8] } 495:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UHSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 45169 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv16i8, |
| 45170 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45171 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45172 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45173 | GIR_EraseFromParent, /*InsnID*/0, |
| 45174 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45175 | // GIR_Coverage, 1228, |
| 45176 | GIR_Done, |
| 45177 | // Label 2431: @115297 |
| 45178 | GIM_Try, /*On fail goto*//*Label 2432*/ 115349, // Rule ID 1229 // |
| 45179 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45180 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhsub, |
| 45181 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 45182 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 45183 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 45184 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 45185 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 45186 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 45187 | // (intrinsic_wo_chain:{ *:[v4i16] } 495:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UHSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 45188 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv4i16, |
| 45189 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45190 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45191 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45192 | GIR_EraseFromParent, /*InsnID*/0, |
| 45193 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45194 | // GIR_Coverage, 1229, |
| 45195 | GIR_Done, |
| 45196 | // Label 2432: @115349 |
| 45197 | GIM_Try, /*On fail goto*//*Label 2433*/ 115401, // Rule ID 1230 // |
| 45198 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45199 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhsub, |
| 45200 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 45201 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 45202 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 45203 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45204 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45205 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45206 | // (intrinsic_wo_chain:{ *:[v8i16] } 495:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UHSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 45207 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv8i16, |
| 45208 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45209 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45210 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45211 | GIR_EraseFromParent, /*InsnID*/0, |
| 45212 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45213 | // GIR_Coverage, 1230, |
| 45214 | GIR_Done, |
| 45215 | // Label 2433: @115401 |
| 45216 | GIM_Try, /*On fail goto*//*Label 2434*/ 115453, // Rule ID 1231 // |
| 45217 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45218 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhsub, |
| 45219 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 45220 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 45221 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 45222 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 45223 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 45224 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 45225 | // (intrinsic_wo_chain:{ *:[v2i32] } 495:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UHSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 45226 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv2i32, |
| 45227 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45228 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45229 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45230 | GIR_EraseFromParent, /*InsnID*/0, |
| 45231 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45232 | // GIR_Coverage, 1231, |
| 45233 | GIR_Done, |
| 45234 | // Label 2434: @115453 |
| 45235 | GIM_Try, /*On fail goto*//*Label 2435*/ 115505, // Rule ID 1232 // |
| 45236 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45237 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uhsub, |
| 45238 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 45239 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 45240 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 45241 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45242 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45243 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45244 | // (intrinsic_wo_chain:{ *:[v4i32] } 495:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UHSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 45245 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UHSUBv4i32, |
| 45246 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45247 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45248 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45249 | GIR_EraseFromParent, /*InsnID*/0, |
| 45250 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45251 | // GIR_Coverage, 1232, |
| 45252 | GIR_Done, |
| 45253 | // Label 2435: @115505 |
| 45254 | GIM_Try, /*On fail goto*//*Label 2436*/ 115557, // Rule ID 1233 // |
| 45255 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45256 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umaxp, |
| 45257 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 45258 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 45259 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 45260 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 45261 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 45262 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 45263 | // (intrinsic_wo_chain:{ *:[v8i8] } 497:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UMAXPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 45264 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv8i8, |
| 45265 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45266 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45267 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45268 | GIR_EraseFromParent, /*InsnID*/0, |
| 45269 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45270 | // GIR_Coverage, 1233, |
| 45271 | GIR_Done, |
| 45272 | // Label 2436: @115557 |
| 45273 | GIM_Try, /*On fail goto*//*Label 2437*/ 115609, // Rule ID 1234 // |
| 45274 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45275 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umaxp, |
| 45276 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 45277 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 45278 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 45279 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45280 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45281 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45282 | // (intrinsic_wo_chain:{ *:[v16i8] } 497:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UMAXPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 45283 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv16i8, |
| 45284 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45285 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45286 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45287 | GIR_EraseFromParent, /*InsnID*/0, |
| 45288 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45289 | // GIR_Coverage, 1234, |
| 45290 | GIR_Done, |
| 45291 | // Label 2437: @115609 |
| 45292 | GIM_Try, /*On fail goto*//*Label 2438*/ 115661, // Rule ID 1235 // |
| 45293 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45294 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umaxp, |
| 45295 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 45296 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 45297 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 45298 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 45299 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 45300 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 45301 | // (intrinsic_wo_chain:{ *:[v4i16] } 497:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UMAXPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 45302 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv4i16, |
| 45303 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45304 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45305 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45306 | GIR_EraseFromParent, /*InsnID*/0, |
| 45307 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45308 | // GIR_Coverage, 1235, |
| 45309 | GIR_Done, |
| 45310 | // Label 2438: @115661 |
| 45311 | GIM_Try, /*On fail goto*//*Label 2439*/ 115713, // Rule ID 1236 // |
| 45312 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45313 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umaxp, |
| 45314 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 45315 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 45316 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 45317 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45318 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45319 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45320 | // (intrinsic_wo_chain:{ *:[v8i16] } 497:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UMAXPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 45321 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv8i16, |
| 45322 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45323 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45324 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45325 | GIR_EraseFromParent, /*InsnID*/0, |
| 45326 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45327 | // GIR_Coverage, 1236, |
| 45328 | GIR_Done, |
| 45329 | // Label 2439: @115713 |
| 45330 | GIM_Try, /*On fail goto*//*Label 2440*/ 115765, // Rule ID 1237 // |
| 45331 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45332 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umaxp, |
| 45333 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 45334 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 45335 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 45336 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 45337 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 45338 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 45339 | // (intrinsic_wo_chain:{ *:[v2i32] } 497:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UMAXPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 45340 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv2i32, |
| 45341 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45342 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45343 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45344 | GIR_EraseFromParent, /*InsnID*/0, |
| 45345 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45346 | // GIR_Coverage, 1237, |
| 45347 | GIR_Done, |
| 45348 | // Label 2440: @115765 |
| 45349 | GIM_Try, /*On fail goto*//*Label 2441*/ 115817, // Rule ID 1238 // |
| 45350 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45351 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umaxp, |
| 45352 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 45353 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 45354 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 45355 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45356 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45357 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45358 | // (intrinsic_wo_chain:{ *:[v4i32] } 497:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UMAXPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 45359 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMAXPv4i32, |
| 45360 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45361 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45362 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45363 | GIR_EraseFromParent, /*InsnID*/0, |
| 45364 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45365 | // GIR_Coverage, 1238, |
| 45366 | GIR_Done, |
| 45367 | // Label 2441: @115817 |
| 45368 | GIM_Try, /*On fail goto*//*Label 2442*/ 115869, // Rule ID 1245 // |
| 45369 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45370 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uminp, |
| 45371 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 45372 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 45373 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 45374 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 45375 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 45376 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 45377 | // (intrinsic_wo_chain:{ *:[v8i8] } 500:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UMINPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 45378 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv8i8, |
| 45379 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45380 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45381 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45382 | GIR_EraseFromParent, /*InsnID*/0, |
| 45383 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45384 | // GIR_Coverage, 1245, |
| 45385 | GIR_Done, |
| 45386 | // Label 2442: @115869 |
| 45387 | GIM_Try, /*On fail goto*//*Label 2443*/ 115921, // Rule ID 1246 // |
| 45388 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45389 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uminp, |
| 45390 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 45391 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 45392 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 45393 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45394 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45395 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45396 | // (intrinsic_wo_chain:{ *:[v16i8] } 500:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UMINPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 45397 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv16i8, |
| 45398 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45399 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45400 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45401 | GIR_EraseFromParent, /*InsnID*/0, |
| 45402 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45403 | // GIR_Coverage, 1246, |
| 45404 | GIR_Done, |
| 45405 | // Label 2443: @115921 |
| 45406 | GIM_Try, /*On fail goto*//*Label 2444*/ 115973, // Rule ID 1247 // |
| 45407 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45408 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uminp, |
| 45409 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 45410 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 45411 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 45412 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 45413 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 45414 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 45415 | // (intrinsic_wo_chain:{ *:[v4i16] } 500:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UMINPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 45416 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv4i16, |
| 45417 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45418 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45419 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45420 | GIR_EraseFromParent, /*InsnID*/0, |
| 45421 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45422 | // GIR_Coverage, 1247, |
| 45423 | GIR_Done, |
| 45424 | // Label 2444: @115973 |
| 45425 | GIM_Try, /*On fail goto*//*Label 2445*/ 116025, // Rule ID 1248 // |
| 45426 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45427 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uminp, |
| 45428 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 45429 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 45430 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 45431 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45432 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45433 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45434 | // (intrinsic_wo_chain:{ *:[v8i16] } 500:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UMINPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 45435 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv8i16, |
| 45436 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45437 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45438 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45439 | GIR_EraseFromParent, /*InsnID*/0, |
| 45440 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45441 | // GIR_Coverage, 1248, |
| 45442 | GIR_Done, |
| 45443 | // Label 2445: @116025 |
| 45444 | GIM_Try, /*On fail goto*//*Label 2446*/ 116077, // Rule ID 1249 // |
| 45445 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45446 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uminp, |
| 45447 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 45448 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 45449 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 45450 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 45451 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 45452 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 45453 | // (intrinsic_wo_chain:{ *:[v2i32] } 500:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UMINPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 45454 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv2i32, |
| 45455 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45456 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45457 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45458 | GIR_EraseFromParent, /*InsnID*/0, |
| 45459 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45460 | // GIR_Coverage, 1249, |
| 45461 | GIR_Done, |
| 45462 | // Label 2446: @116077 |
| 45463 | GIM_Try, /*On fail goto*//*Label 2447*/ 116129, // Rule ID 1250 // |
| 45464 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45465 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uminp, |
| 45466 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 45467 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 45468 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 45469 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45470 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45471 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45472 | // (intrinsic_wo_chain:{ *:[v4i32] } 500:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UMINPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 45473 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMINPv4i32, |
| 45474 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45475 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45476 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45477 | GIR_EraseFromParent, /*InsnID*/0, |
| 45478 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45479 | // GIR_Coverage, 1250, |
| 45480 | GIR_Done, |
| 45481 | // Label 2447: @116129 |
| 45482 | GIM_Try, /*On fail goto*//*Label 2448*/ 116181, // Rule ID 1257 // |
| 45483 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45484 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, |
| 45485 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 45486 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 45487 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 45488 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 45489 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 45490 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 45491 | // (intrinsic_wo_chain:{ *:[v8i8] } 504:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 45492 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv8i8, |
| 45493 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45494 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45495 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45496 | GIR_EraseFromParent, /*InsnID*/0, |
| 45497 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45498 | // GIR_Coverage, 1257, |
| 45499 | GIR_Done, |
| 45500 | // Label 2448: @116181 |
| 45501 | GIM_Try, /*On fail goto*//*Label 2449*/ 116233, // Rule ID 1258 // |
| 45502 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45503 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, |
| 45504 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 45505 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 45506 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 45507 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45508 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45509 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45510 | // (intrinsic_wo_chain:{ *:[v16i8] } 504:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 45511 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv16i8, |
| 45512 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45513 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45514 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45515 | GIR_EraseFromParent, /*InsnID*/0, |
| 45516 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45517 | // GIR_Coverage, 1258, |
| 45518 | GIR_Done, |
| 45519 | // Label 2449: @116233 |
| 45520 | GIM_Try, /*On fail goto*//*Label 2450*/ 116285, // Rule ID 1259 // |
| 45521 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45522 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, |
| 45523 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 45524 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 45525 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 45526 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 45527 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 45528 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 45529 | // (intrinsic_wo_chain:{ *:[v4i16] } 504:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 45530 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv4i16, |
| 45531 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45532 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45533 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45534 | GIR_EraseFromParent, /*InsnID*/0, |
| 45535 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45536 | // GIR_Coverage, 1259, |
| 45537 | GIR_Done, |
| 45538 | // Label 2450: @116285 |
| 45539 | GIM_Try, /*On fail goto*//*Label 2451*/ 116337, // Rule ID 1260 // |
| 45540 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45541 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, |
| 45542 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 45543 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 45544 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 45545 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45546 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45547 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45548 | // (intrinsic_wo_chain:{ *:[v8i16] } 504:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 45549 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv8i16, |
| 45550 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45551 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45552 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45553 | GIR_EraseFromParent, /*InsnID*/0, |
| 45554 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45555 | // GIR_Coverage, 1260, |
| 45556 | GIR_Done, |
| 45557 | // Label 2451: @116337 |
| 45558 | GIM_Try, /*On fail goto*//*Label 2452*/ 116389, // Rule ID 1261 // |
| 45559 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45560 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, |
| 45561 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 45562 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 45563 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 45564 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 45565 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 45566 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 45567 | // (intrinsic_wo_chain:{ *:[v2i32] } 504:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 45568 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv2i32, |
| 45569 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45570 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45571 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45572 | GIR_EraseFromParent, /*InsnID*/0, |
| 45573 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45574 | // GIR_Coverage, 1261, |
| 45575 | GIR_Done, |
| 45576 | // Label 2452: @116389 |
| 45577 | GIM_Try, /*On fail goto*//*Label 2453*/ 116441, // Rule ID 1262 // |
| 45578 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45579 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, |
| 45580 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 45581 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 45582 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 45583 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45584 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45585 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45586 | // (intrinsic_wo_chain:{ *:[v4i32] } 504:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 45587 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv4i32, |
| 45588 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45589 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45590 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45591 | GIR_EraseFromParent, /*InsnID*/0, |
| 45592 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45593 | // GIR_Coverage, 1262, |
| 45594 | GIR_Done, |
| 45595 | // Label 2453: @116441 |
| 45596 | GIM_Try, /*On fail goto*//*Label 2454*/ 116493, // Rule ID 1263 // |
| 45597 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45598 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, |
| 45599 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 45600 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 45601 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 45602 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45603 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45604 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45605 | // (intrinsic_wo_chain:{ *:[v2i64] } 504:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (UQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 45606 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv2i64, |
| 45607 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45608 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45609 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45610 | GIR_EraseFromParent, /*InsnID*/0, |
| 45611 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45612 | // GIR_Coverage, 1263, |
| 45613 | GIR_Done, |
| 45614 | // Label 2454: @116493 |
| 45615 | GIM_Try, /*On fail goto*//*Label 2455*/ 116545, // Rule ID 1264 // |
| 45616 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45617 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, |
| 45618 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 45619 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 45620 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 45621 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 45622 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 45623 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 45624 | // (intrinsic_wo_chain:{ *:[v8i8] } 505:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UQRSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 45625 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv8i8, |
| 45626 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45627 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45628 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45629 | GIR_EraseFromParent, /*InsnID*/0, |
| 45630 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45631 | // GIR_Coverage, 1264, |
| 45632 | GIR_Done, |
| 45633 | // Label 2455: @116545 |
| 45634 | GIM_Try, /*On fail goto*//*Label 2456*/ 116597, // Rule ID 1265 // |
| 45635 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45636 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, |
| 45637 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 45638 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 45639 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 45640 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45641 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45642 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45643 | // (intrinsic_wo_chain:{ *:[v16i8] } 505:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UQRSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 45644 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv16i8, |
| 45645 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45646 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45647 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45648 | GIR_EraseFromParent, /*InsnID*/0, |
| 45649 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45650 | // GIR_Coverage, 1265, |
| 45651 | GIR_Done, |
| 45652 | // Label 2456: @116597 |
| 45653 | GIM_Try, /*On fail goto*//*Label 2457*/ 116649, // Rule ID 1266 // |
| 45654 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45655 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, |
| 45656 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 45657 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 45658 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 45659 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 45660 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 45661 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 45662 | // (intrinsic_wo_chain:{ *:[v4i16] } 505:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UQRSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 45663 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv4i16, |
| 45664 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45665 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45666 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45667 | GIR_EraseFromParent, /*InsnID*/0, |
| 45668 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45669 | // GIR_Coverage, 1266, |
| 45670 | GIR_Done, |
| 45671 | // Label 2457: @116649 |
| 45672 | GIM_Try, /*On fail goto*//*Label 2458*/ 116701, // Rule ID 1267 // |
| 45673 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45674 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, |
| 45675 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 45676 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 45677 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 45678 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45679 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45680 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45681 | // (intrinsic_wo_chain:{ *:[v8i16] } 505:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UQRSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 45682 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv8i16, |
| 45683 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45684 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45685 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45686 | GIR_EraseFromParent, /*InsnID*/0, |
| 45687 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45688 | // GIR_Coverage, 1267, |
| 45689 | GIR_Done, |
| 45690 | // Label 2458: @116701 |
| 45691 | GIM_Try, /*On fail goto*//*Label 2459*/ 116753, // Rule ID 1268 // |
| 45692 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45693 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, |
| 45694 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 45695 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 45696 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 45697 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 45698 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 45699 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 45700 | // (intrinsic_wo_chain:{ *:[v2i32] } 505:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UQRSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 45701 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv2i32, |
| 45702 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45703 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45704 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45705 | GIR_EraseFromParent, /*InsnID*/0, |
| 45706 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45707 | // GIR_Coverage, 1268, |
| 45708 | GIR_Done, |
| 45709 | // Label 2459: @116753 |
| 45710 | GIM_Try, /*On fail goto*//*Label 2460*/ 116805, // Rule ID 1269 // |
| 45711 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45712 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, |
| 45713 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 45714 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 45715 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 45716 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45717 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45718 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45719 | // (intrinsic_wo_chain:{ *:[v4i32] } 505:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UQRSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 45720 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv4i32, |
| 45721 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45722 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45723 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45724 | GIR_EraseFromParent, /*InsnID*/0, |
| 45725 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45726 | // GIR_Coverage, 1269, |
| 45727 | GIR_Done, |
| 45728 | // Label 2460: @116805 |
| 45729 | GIM_Try, /*On fail goto*//*Label 2461*/ 116857, // Rule ID 1270 // |
| 45730 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45731 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, |
| 45732 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 45733 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 45734 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 45735 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45736 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45737 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45738 | // (intrinsic_wo_chain:{ *:[v2i64] } 505:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (UQRSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 45739 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv2i64, |
| 45740 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45741 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45742 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45743 | GIR_EraseFromParent, /*InsnID*/0, |
| 45744 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45745 | // GIR_Coverage, 1270, |
| 45746 | GIR_Done, |
| 45747 | // Label 2461: @116857 |
| 45748 | GIM_Try, /*On fail goto*//*Label 2462*/ 116909, // Rule ID 1271 // |
| 45749 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45750 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, |
| 45751 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 45752 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 45753 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 45754 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 45755 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 45756 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 45757 | // (intrinsic_wo_chain:{ *:[v8i8] } 507:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UQSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 45758 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv8i8, |
| 45759 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45760 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45761 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45762 | GIR_EraseFromParent, /*InsnID*/0, |
| 45763 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45764 | // GIR_Coverage, 1271, |
| 45765 | GIR_Done, |
| 45766 | // Label 2462: @116909 |
| 45767 | GIM_Try, /*On fail goto*//*Label 2463*/ 116961, // Rule ID 1272 // |
| 45768 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45769 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, |
| 45770 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 45771 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 45772 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 45773 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45774 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45775 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45776 | // (intrinsic_wo_chain:{ *:[v16i8] } 507:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UQSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 45777 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv16i8, |
| 45778 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45779 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45780 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45781 | GIR_EraseFromParent, /*InsnID*/0, |
| 45782 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45783 | // GIR_Coverage, 1272, |
| 45784 | GIR_Done, |
| 45785 | // Label 2463: @116961 |
| 45786 | GIM_Try, /*On fail goto*//*Label 2464*/ 117013, // Rule ID 1273 // |
| 45787 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45788 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, |
| 45789 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 45790 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 45791 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 45792 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 45793 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 45794 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 45795 | // (intrinsic_wo_chain:{ *:[v4i16] } 507:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UQSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 45796 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv4i16, |
| 45797 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45798 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45799 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45800 | GIR_EraseFromParent, /*InsnID*/0, |
| 45801 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45802 | // GIR_Coverage, 1273, |
| 45803 | GIR_Done, |
| 45804 | // Label 2464: @117013 |
| 45805 | GIM_Try, /*On fail goto*//*Label 2465*/ 117065, // Rule ID 1274 // |
| 45806 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45807 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, |
| 45808 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 45809 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 45810 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 45811 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45812 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45813 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45814 | // (intrinsic_wo_chain:{ *:[v8i16] } 507:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UQSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 45815 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv8i16, |
| 45816 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45817 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45818 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45819 | GIR_EraseFromParent, /*InsnID*/0, |
| 45820 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45821 | // GIR_Coverage, 1274, |
| 45822 | GIR_Done, |
| 45823 | // Label 2465: @117065 |
| 45824 | GIM_Try, /*On fail goto*//*Label 2466*/ 117117, // Rule ID 1275 // |
| 45825 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45826 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, |
| 45827 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 45828 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 45829 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 45830 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 45831 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 45832 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 45833 | // (intrinsic_wo_chain:{ *:[v2i32] } 507:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UQSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 45834 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv2i32, |
| 45835 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45836 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45837 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45838 | GIR_EraseFromParent, /*InsnID*/0, |
| 45839 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45840 | // GIR_Coverage, 1275, |
| 45841 | GIR_Done, |
| 45842 | // Label 2466: @117117 |
| 45843 | GIM_Try, /*On fail goto*//*Label 2467*/ 117169, // Rule ID 1276 // |
| 45844 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45845 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, |
| 45846 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 45847 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 45848 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 45849 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45850 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45851 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45852 | // (intrinsic_wo_chain:{ *:[v4i32] } 507:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UQSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 45853 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv4i32, |
| 45854 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45855 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45856 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45857 | GIR_EraseFromParent, /*InsnID*/0, |
| 45858 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45859 | // GIR_Coverage, 1276, |
| 45860 | GIR_Done, |
| 45861 | // Label 2467: @117169 |
| 45862 | GIM_Try, /*On fail goto*//*Label 2468*/ 117221, // Rule ID 1277 // |
| 45863 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45864 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, |
| 45865 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 45866 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 45867 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 45868 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45869 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45870 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45871 | // (intrinsic_wo_chain:{ *:[v2i64] } 507:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (UQSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 45872 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv2i64, |
| 45873 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45874 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45875 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45876 | GIR_EraseFromParent, /*InsnID*/0, |
| 45877 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45878 | // GIR_Coverage, 1277, |
| 45879 | GIR_Done, |
| 45880 | // Label 2468: @117221 |
| 45881 | GIM_Try, /*On fail goto*//*Label 2469*/ 117273, // Rule ID 1278 // |
| 45882 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45883 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, |
| 45884 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 45885 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 45886 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 45887 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 45888 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 45889 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 45890 | // (intrinsic_wo_chain:{ *:[v8i8] } 509:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UQSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 45891 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv8i8, |
| 45892 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45893 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45894 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45895 | GIR_EraseFromParent, /*InsnID*/0, |
| 45896 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45897 | // GIR_Coverage, 1278, |
| 45898 | GIR_Done, |
| 45899 | // Label 2469: @117273 |
| 45900 | GIM_Try, /*On fail goto*//*Label 2470*/ 117325, // Rule ID 1279 // |
| 45901 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45902 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, |
| 45903 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 45904 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 45905 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 45906 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45907 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45908 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45909 | // (intrinsic_wo_chain:{ *:[v16i8] } 509:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UQSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 45910 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv16i8, |
| 45911 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45912 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45913 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45914 | GIR_EraseFromParent, /*InsnID*/0, |
| 45915 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45916 | // GIR_Coverage, 1279, |
| 45917 | GIR_Done, |
| 45918 | // Label 2470: @117325 |
| 45919 | GIM_Try, /*On fail goto*//*Label 2471*/ 117377, // Rule ID 1280 // |
| 45920 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45921 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, |
| 45922 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 45923 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 45924 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 45925 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 45926 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 45927 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 45928 | // (intrinsic_wo_chain:{ *:[v4i16] } 509:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UQSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 45929 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv4i16, |
| 45930 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45931 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45932 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45933 | GIR_EraseFromParent, /*InsnID*/0, |
| 45934 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45935 | // GIR_Coverage, 1280, |
| 45936 | GIR_Done, |
| 45937 | // Label 2471: @117377 |
| 45938 | GIM_Try, /*On fail goto*//*Label 2472*/ 117429, // Rule ID 1281 // |
| 45939 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45940 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, |
| 45941 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 45942 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 45943 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 45944 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45945 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45946 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45947 | // (intrinsic_wo_chain:{ *:[v8i16] } 509:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UQSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 45948 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv8i16, |
| 45949 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45950 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45951 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45952 | GIR_EraseFromParent, /*InsnID*/0, |
| 45953 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45954 | // GIR_Coverage, 1281, |
| 45955 | GIR_Done, |
| 45956 | // Label 2472: @117429 |
| 45957 | GIM_Try, /*On fail goto*//*Label 2473*/ 117481, // Rule ID 1282 // |
| 45958 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45959 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, |
| 45960 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 45961 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 45962 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 45963 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 45964 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 45965 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 45966 | // (intrinsic_wo_chain:{ *:[v2i32] } 509:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UQSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 45967 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv2i32, |
| 45968 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45969 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45970 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45971 | GIR_EraseFromParent, /*InsnID*/0, |
| 45972 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45973 | // GIR_Coverage, 1282, |
| 45974 | GIR_Done, |
| 45975 | // Label 2473: @117481 |
| 45976 | GIM_Try, /*On fail goto*//*Label 2474*/ 117533, // Rule ID 1283 // |
| 45977 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45978 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, |
| 45979 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 45980 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 45981 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 45982 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 45983 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 45984 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 45985 | // (intrinsic_wo_chain:{ *:[v4i32] } 509:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UQSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 45986 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv4i32, |
| 45987 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 45988 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 45989 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 45990 | GIR_EraseFromParent, /*InsnID*/0, |
| 45991 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 45992 | // GIR_Coverage, 1283, |
| 45993 | GIR_Done, |
| 45994 | // Label 2474: @117533 |
| 45995 | GIM_Try, /*On fail goto*//*Label 2475*/ 117585, // Rule ID 1284 // |
| 45996 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 45997 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, |
| 45998 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 45999 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 46000 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 46001 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 46002 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 46003 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 46004 | // (intrinsic_wo_chain:{ *:[v2i64] } 509:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (UQSUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 46005 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv2i64, |
| 46006 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46007 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46008 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46009 | GIR_EraseFromParent, /*InsnID*/0, |
| 46010 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46011 | // GIR_Coverage, 1284, |
| 46012 | GIR_Done, |
| 46013 | // Label 2475: @117585 |
| 46014 | GIM_Try, /*On fail goto*//*Label 2476*/ 117637, // Rule ID 1291 // |
| 46015 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46016 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, |
| 46017 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 46018 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 46019 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 46020 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46021 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 46022 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 46023 | // (intrinsic_wo_chain:{ *:[v8i8] } 513:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (URSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 46024 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv8i8, |
| 46025 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46026 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46027 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46028 | GIR_EraseFromParent, /*InsnID*/0, |
| 46029 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46030 | // GIR_Coverage, 1291, |
| 46031 | GIR_Done, |
| 46032 | // Label 2476: @117637 |
| 46033 | GIM_Try, /*On fail goto*//*Label 2477*/ 117689, // Rule ID 1292 // |
| 46034 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46035 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, |
| 46036 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 46037 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 46038 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 46039 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 46040 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 46041 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 46042 | // (intrinsic_wo_chain:{ *:[v16i8] } 513:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (URSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 46043 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv16i8, |
| 46044 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46045 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46046 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46047 | GIR_EraseFromParent, /*InsnID*/0, |
| 46048 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46049 | // GIR_Coverage, 1292, |
| 46050 | GIR_Done, |
| 46051 | // Label 2477: @117689 |
| 46052 | GIM_Try, /*On fail goto*//*Label 2478*/ 117741, // Rule ID 1293 // |
| 46053 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46054 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, |
| 46055 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 46056 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 46057 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 46058 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46059 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 46060 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 46061 | // (intrinsic_wo_chain:{ *:[v4i16] } 513:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (URSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 46062 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv4i16, |
| 46063 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46064 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46065 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46066 | GIR_EraseFromParent, /*InsnID*/0, |
| 46067 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46068 | // GIR_Coverage, 1293, |
| 46069 | GIR_Done, |
| 46070 | // Label 2478: @117741 |
| 46071 | GIM_Try, /*On fail goto*//*Label 2479*/ 117793, // Rule ID 1294 // |
| 46072 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46073 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, |
| 46074 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 46075 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 46076 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 46077 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 46078 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 46079 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 46080 | // (intrinsic_wo_chain:{ *:[v8i16] } 513:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (URSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 46081 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv8i16, |
| 46082 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46083 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46084 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46085 | GIR_EraseFromParent, /*InsnID*/0, |
| 46086 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46087 | // GIR_Coverage, 1294, |
| 46088 | GIR_Done, |
| 46089 | // Label 2479: @117793 |
| 46090 | GIM_Try, /*On fail goto*//*Label 2480*/ 117845, // Rule ID 1295 // |
| 46091 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46092 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, |
| 46093 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 46094 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 46095 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 46096 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46097 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 46098 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 46099 | // (intrinsic_wo_chain:{ *:[v2i32] } 513:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (URSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 46100 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv2i32, |
| 46101 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46102 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46103 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46104 | GIR_EraseFromParent, /*InsnID*/0, |
| 46105 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46106 | // GIR_Coverage, 1295, |
| 46107 | GIR_Done, |
| 46108 | // Label 2480: @117845 |
| 46109 | GIM_Try, /*On fail goto*//*Label 2481*/ 117897, // Rule ID 1296 // |
| 46110 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46111 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, |
| 46112 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 46113 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 46114 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 46115 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 46116 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 46117 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 46118 | // (intrinsic_wo_chain:{ *:[v4i32] } 513:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (URSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 46119 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv4i32, |
| 46120 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46121 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46122 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46123 | GIR_EraseFromParent, /*InsnID*/0, |
| 46124 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46125 | // GIR_Coverage, 1296, |
| 46126 | GIR_Done, |
| 46127 | // Label 2481: @117897 |
| 46128 | GIM_Try, /*On fail goto*//*Label 2482*/ 117949, // Rule ID 1297 // |
| 46129 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46130 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, |
| 46131 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 46132 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 46133 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 46134 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 46135 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 46136 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 46137 | // (intrinsic_wo_chain:{ *:[v2i64] } 513:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (URSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 46138 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv2i64, |
| 46139 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46140 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46141 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46142 | GIR_EraseFromParent, /*InsnID*/0, |
| 46143 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46144 | // GIR_Coverage, 1297, |
| 46145 | GIR_Done, |
| 46146 | // Label 2482: @117949 |
| 46147 | GIM_Try, /*On fail goto*//*Label 2483*/ 118001, // Rule ID 1298 // |
| 46148 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46149 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, |
| 46150 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 46151 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 46152 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 46153 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46154 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 46155 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 46156 | // (intrinsic_wo_chain:{ *:[v8i8] } 516:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (USHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 46157 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv8i8, |
| 46158 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46159 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46160 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46161 | GIR_EraseFromParent, /*InsnID*/0, |
| 46162 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46163 | // GIR_Coverage, 1298, |
| 46164 | GIR_Done, |
| 46165 | // Label 2483: @118001 |
| 46166 | GIM_Try, /*On fail goto*//*Label 2484*/ 118053, // Rule ID 1299 // |
| 46167 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46168 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, |
| 46169 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 46170 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 46171 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 46172 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 46173 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 46174 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 46175 | // (intrinsic_wo_chain:{ *:[v16i8] } 516:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (USHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 46176 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv16i8, |
| 46177 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46178 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46179 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46180 | GIR_EraseFromParent, /*InsnID*/0, |
| 46181 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46182 | // GIR_Coverage, 1299, |
| 46183 | GIR_Done, |
| 46184 | // Label 2484: @118053 |
| 46185 | GIM_Try, /*On fail goto*//*Label 2485*/ 118105, // Rule ID 1300 // |
| 46186 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46187 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, |
| 46188 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 46189 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 46190 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 46191 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46192 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 46193 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 46194 | // (intrinsic_wo_chain:{ *:[v4i16] } 516:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (USHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 46195 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv4i16, |
| 46196 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46197 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46198 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46199 | GIR_EraseFromParent, /*InsnID*/0, |
| 46200 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46201 | // GIR_Coverage, 1300, |
| 46202 | GIR_Done, |
| 46203 | // Label 2485: @118105 |
| 46204 | GIM_Try, /*On fail goto*//*Label 2486*/ 118157, // Rule ID 1301 // |
| 46205 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46206 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, |
| 46207 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 46208 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 46209 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 46210 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 46211 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 46212 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 46213 | // (intrinsic_wo_chain:{ *:[v8i16] } 516:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (USHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 46214 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv8i16, |
| 46215 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46216 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46217 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46218 | GIR_EraseFromParent, /*InsnID*/0, |
| 46219 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46220 | // GIR_Coverage, 1301, |
| 46221 | GIR_Done, |
| 46222 | // Label 2486: @118157 |
| 46223 | GIM_Try, /*On fail goto*//*Label 2487*/ 118209, // Rule ID 1302 // |
| 46224 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46225 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, |
| 46226 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 46227 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 46228 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 46229 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46230 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 46231 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 46232 | // (intrinsic_wo_chain:{ *:[v2i32] } 516:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (USHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 46233 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv2i32, |
| 46234 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46235 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46236 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46237 | GIR_EraseFromParent, /*InsnID*/0, |
| 46238 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46239 | // GIR_Coverage, 1302, |
| 46240 | GIR_Done, |
| 46241 | // Label 2487: @118209 |
| 46242 | GIM_Try, /*On fail goto*//*Label 2488*/ 118261, // Rule ID 1303 // |
| 46243 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46244 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, |
| 46245 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 46246 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 46247 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 46248 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 46249 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 46250 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 46251 | // (intrinsic_wo_chain:{ *:[v4i32] } 516:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (USHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 46252 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv4i32, |
| 46253 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46254 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46255 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46256 | GIR_EraseFromParent, /*InsnID*/0, |
| 46257 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46258 | // GIR_Coverage, 1303, |
| 46259 | GIR_Done, |
| 46260 | // Label 2488: @118261 |
| 46261 | GIM_Try, /*On fail goto*//*Label 2489*/ 118313, // Rule ID 1304 // |
| 46262 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46263 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, |
| 46264 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 46265 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 46266 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 46267 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 46268 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 46269 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 46270 | // (intrinsic_wo_chain:{ *:[v2i64] } 516:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (USHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 46271 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv2i64, |
| 46272 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46273 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46274 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46275 | GIR_EraseFromParent, /*InsnID*/0, |
| 46276 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46277 | // GIR_Coverage, 1304, |
| 46278 | GIR_Done, |
| 46279 | // Label 2489: @118313 |
| 46280 | GIM_Try, /*On fail goto*//*Label 2490*/ 118365, // Rule ID 1334 // |
| 46281 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46282 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sisd_fabd, |
| 46283 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 46284 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 46285 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 46286 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46287 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 46288 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 46289 | // (intrinsic_wo_chain:{ *:[f64] } 538:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FABD64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) |
| 46290 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD64, |
| 46291 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46292 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46293 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46294 | GIR_EraseFromParent, /*InsnID*/0, |
| 46295 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46296 | // GIR_Coverage, 1334, |
| 46297 | GIR_Done, |
| 46298 | // Label 2490: @118365 |
| 46299 | GIM_Try, /*On fail goto*//*Label 2491*/ 118417, // Rule ID 1335 // |
| 46300 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46301 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sisd_fabd, |
| 46302 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 46303 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 46304 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 46305 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 46306 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 46307 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 46308 | // (intrinsic_wo_chain:{ *:[f32] } 538:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FABD32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) |
| 46309 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD32, |
| 46310 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46311 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46312 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46313 | GIR_EraseFromParent, /*InsnID*/0, |
| 46314 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46315 | // GIR_Coverage, 1335, |
| 46316 | GIR_Done, |
| 46317 | // Label 2491: @118417 |
| 46318 | GIM_Try, /*On fail goto*//*Label 2492*/ 118469, // Rule ID 1336 // |
| 46319 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 46320 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sisd_fabd, |
| 46321 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, |
| 46322 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 46323 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, |
| 46324 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 46325 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 46326 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, |
| 46327 | // (intrinsic_wo_chain:{ *:[f16] } 538:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FABD16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) |
| 46328 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD16, |
| 46329 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46330 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46331 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46332 | GIR_EraseFromParent, /*InsnID*/0, |
| 46333 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46334 | // GIR_Coverage, 1336, |
| 46335 | GIR_Done, |
| 46336 | // Label 2492: @118469 |
| 46337 | GIM_Try, /*On fail goto*//*Label 2493*/ 118521, // Rule ID 1337 // |
| 46338 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46339 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, |
| 46340 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 46341 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 46342 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 46343 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46344 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 46345 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 46346 | // (intrinsic_wo_chain:{ *:[i64] } 369:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FACGE64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) |
| 46347 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGE64, |
| 46348 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46349 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46350 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46351 | GIR_EraseFromParent, /*InsnID*/0, |
| 46352 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46353 | // GIR_Coverage, 1337, |
| 46354 | GIR_Done, |
| 46355 | // Label 2493: @118521 |
| 46356 | GIM_Try, /*On fail goto*//*Label 2494*/ 118573, // Rule ID 1338 // |
| 46357 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46358 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, |
| 46359 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 46360 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 46361 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 46362 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 46363 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 46364 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 46365 | // (intrinsic_wo_chain:{ *:[i32] } 369:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FACGE32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) |
| 46366 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGE32, |
| 46367 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46368 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46369 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46370 | GIR_EraseFromParent, /*InsnID*/0, |
| 46371 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46372 | // GIR_Coverage, 1338, |
| 46373 | GIR_Done, |
| 46374 | // Label 2494: @118573 |
| 46375 | GIM_Try, /*On fail goto*//*Label 2495*/ 118625, // Rule ID 1339 // |
| 46376 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46377 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, |
| 46378 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 46379 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 46380 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 46381 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46382 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 46383 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 46384 | // (intrinsic_wo_chain:{ *:[i64] } 370:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FACGT64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) |
| 46385 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGT64, |
| 46386 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46387 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46388 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46389 | GIR_EraseFromParent, /*InsnID*/0, |
| 46390 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46391 | // GIR_Coverage, 1339, |
| 46392 | GIR_Done, |
| 46393 | // Label 2495: @118625 |
| 46394 | GIM_Try, /*On fail goto*//*Label 2496*/ 118677, // Rule ID 1340 // |
| 46395 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46396 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, |
| 46397 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 46398 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 46399 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 46400 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 46401 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 46402 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 46403 | // (intrinsic_wo_chain:{ *:[i32] } 370:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FACGT32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) |
| 46404 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGT32, |
| 46405 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46406 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46407 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46408 | GIR_EraseFromParent, /*InsnID*/0, |
| 46409 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46410 | // GIR_Coverage, 1340, |
| 46411 | GIR_Done, |
| 46412 | // Label 2496: @118677 |
| 46413 | GIM_Try, /*On fail goto*//*Label 2497*/ 118729, // Rule ID 1347 // |
| 46414 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46415 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, |
| 46416 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 46417 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 46418 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 46419 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46420 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 46421 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 46422 | // (intrinsic_wo_chain:{ *:[f64] } 400:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FMULX64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) |
| 46423 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULX64, |
| 46424 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46425 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46426 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46427 | GIR_EraseFromParent, /*InsnID*/0, |
| 46428 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46429 | // GIR_Coverage, 1347, |
| 46430 | GIR_Done, |
| 46431 | // Label 2497: @118729 |
| 46432 | GIM_Try, /*On fail goto*//*Label 2498*/ 118781, // Rule ID 1348 // |
| 46433 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46434 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, |
| 46435 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 46436 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 46437 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 46438 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 46439 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 46440 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 46441 | // (intrinsic_wo_chain:{ *:[f32] } 400:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FMULX32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) |
| 46442 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULX32, |
| 46443 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46444 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46445 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46446 | GIR_EraseFromParent, /*InsnID*/0, |
| 46447 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46448 | // GIR_Coverage, 1348, |
| 46449 | GIR_Done, |
| 46450 | // Label 2498: @118781 |
| 46451 | GIM_Try, /*On fail goto*//*Label 2499*/ 118833, // Rule ID 1349 // |
| 46452 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 46453 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, |
| 46454 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, |
| 46455 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 46456 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, |
| 46457 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 46458 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 46459 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, |
| 46460 | // (intrinsic_wo_chain:{ *:[f16] } 400:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FMULX16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) |
| 46461 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULX16, |
| 46462 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46463 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46464 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46465 | GIR_EraseFromParent, /*InsnID*/0, |
| 46466 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46467 | // GIR_Coverage, 1349, |
| 46468 | GIR_Done, |
| 46469 | // Label 2499: @118833 |
| 46470 | GIM_Try, /*On fail goto*//*Label 2500*/ 118885, // Rule ID 1350 // |
| 46471 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46472 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, |
| 46473 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 46474 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 46475 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 46476 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46477 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 46478 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 46479 | // (intrinsic_wo_chain:{ *:[f64] } 402:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FRECPS64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) |
| 46480 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPS64, |
| 46481 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46482 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46483 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46484 | GIR_EraseFromParent, /*InsnID*/0, |
| 46485 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46486 | // GIR_Coverage, 1350, |
| 46487 | GIR_Done, |
| 46488 | // Label 2500: @118885 |
| 46489 | GIM_Try, /*On fail goto*//*Label 2501*/ 118937, // Rule ID 1351 // |
| 46490 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46491 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, |
| 46492 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 46493 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 46494 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 46495 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 46496 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 46497 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 46498 | // (intrinsic_wo_chain:{ *:[f32] } 402:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FRECPS32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) |
| 46499 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPS32, |
| 46500 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46501 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46502 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46503 | GIR_EraseFromParent, /*InsnID*/0, |
| 46504 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46505 | // GIR_Coverage, 1351, |
| 46506 | GIR_Done, |
| 46507 | // Label 2501: @118937 |
| 46508 | GIM_Try, /*On fail goto*//*Label 2502*/ 118989, // Rule ID 1352 // |
| 46509 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 46510 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, |
| 46511 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, |
| 46512 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 46513 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, |
| 46514 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 46515 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 46516 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, |
| 46517 | // (intrinsic_wo_chain:{ *:[f16] } 402:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FRECPS16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) |
| 46518 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPS16, |
| 46519 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46520 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46521 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46522 | GIR_EraseFromParent, /*InsnID*/0, |
| 46523 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46524 | // GIR_Coverage, 1352, |
| 46525 | GIR_Done, |
| 46526 | // Label 2502: @118989 |
| 46527 | GIM_Try, /*On fail goto*//*Label 2503*/ 119041, // Rule ID 1353 // |
| 46528 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46529 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, |
| 46530 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 46531 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 46532 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 46533 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46534 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 46535 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 46536 | // (intrinsic_wo_chain:{ *:[f64] } 406:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FRSQRTS64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) |
| 46537 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTS64, |
| 46538 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46539 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46540 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46541 | GIR_EraseFromParent, /*InsnID*/0, |
| 46542 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46543 | // GIR_Coverage, 1353, |
| 46544 | GIR_Done, |
| 46545 | // Label 2503: @119041 |
| 46546 | GIM_Try, /*On fail goto*//*Label 2504*/ 119093, // Rule ID 1354 // |
| 46547 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46548 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, |
| 46549 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 46550 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 46551 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 46552 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 46553 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 46554 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 46555 | // (intrinsic_wo_chain:{ *:[f32] } 406:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FRSQRTS32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) |
| 46556 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTS32, |
| 46557 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46558 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46559 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46560 | GIR_EraseFromParent, /*InsnID*/0, |
| 46561 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46562 | // GIR_Coverage, 1354, |
| 46563 | GIR_Done, |
| 46564 | // Label 2504: @119093 |
| 46565 | GIM_Try, /*On fail goto*//*Label 2505*/ 119145, // Rule ID 1355 // |
| 46566 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 46567 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, |
| 46568 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, |
| 46569 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 46570 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, |
| 46571 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 46572 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 46573 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, |
| 46574 | // (intrinsic_wo_chain:{ *:[f16] } 406:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FRSQRTS16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) |
| 46575 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTS16, |
| 46576 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46577 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46578 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46579 | GIR_EraseFromParent, /*InsnID*/0, |
| 46580 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46581 | // GIR_Coverage, 1355, |
| 46582 | GIR_Done, |
| 46583 | // Label 2505: @119145 |
| 46584 | GIM_Try, /*On fail goto*//*Label 2506*/ 119197, // Rule ID 1356 // |
| 46585 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46586 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 46587 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 46588 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 46589 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 46590 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46591 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 46592 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 46593 | // (intrinsic_wo_chain:{ *:[v1i64] } 446:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) |
| 46594 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv1i64, |
| 46595 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46596 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46597 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46598 | GIR_EraseFromParent, /*InsnID*/0, |
| 46599 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46600 | // GIR_Coverage, 1356, |
| 46601 | GIR_Done, |
| 46602 | // Label 2506: @119197 |
| 46603 | GIM_Try, /*On fail goto*//*Label 2507*/ 119249, // Rule ID 1357 // |
| 46604 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46605 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulh, |
| 46606 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 46607 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 46608 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 46609 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 46610 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 46611 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 46612 | // (intrinsic_wo_chain:{ *:[i32] } 447:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQDMULHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) |
| 46613 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULHv1i32, |
| 46614 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46615 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46616 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46617 | GIR_EraseFromParent, /*InsnID*/0, |
| 46618 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46619 | // GIR_Coverage, 1357, |
| 46620 | GIR_Done, |
| 46621 | // Label 2507: @119249 |
| 46622 | GIM_Try, /*On fail goto*//*Label 2508*/ 119301, // Rule ID 1358 // |
| 46623 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46624 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrdmulh, |
| 46625 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 46626 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 46627 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 46628 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 46629 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 46630 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 46631 | // (intrinsic_wo_chain:{ *:[i32] } 453:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQRDMULHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) |
| 46632 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRDMULHv1i32, |
| 46633 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46634 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46635 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46636 | GIR_EraseFromParent, /*InsnID*/0, |
| 46637 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46638 | // GIR_Coverage, 1358, |
| 46639 | GIR_Done, |
| 46640 | // Label 2508: @119301 |
| 46641 | GIM_Try, /*On fail goto*//*Label 2509*/ 119353, // Rule ID 1359 // |
| 46642 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46643 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, |
| 46644 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 46645 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 46646 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 46647 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46648 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 46649 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 46650 | // (intrinsic_wo_chain:{ *:[v1i64] } 456:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SQRSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) |
| 46651 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv1i64, |
| 46652 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46653 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46654 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46655 | GIR_EraseFromParent, /*InsnID*/0, |
| 46656 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46657 | // GIR_Coverage, 1359, |
| 46658 | GIR_Done, |
| 46659 | // Label 2509: @119353 |
| 46660 | GIM_Try, /*On fail goto*//*Label 2510*/ 119405, // Rule ID 1360 // |
| 46661 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46662 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, |
| 46663 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 46664 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 46665 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 46666 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46667 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 46668 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 46669 | // (intrinsic_wo_chain:{ *:[v1i64] } 459:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SQSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) |
| 46670 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv1i64, |
| 46671 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46672 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46673 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46674 | GIR_EraseFromParent, /*InsnID*/0, |
| 46675 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46676 | // GIR_Coverage, 1360, |
| 46677 | GIR_Done, |
| 46678 | // Label 2510: @119405 |
| 46679 | GIM_Try, /*On fail goto*//*Label 2511*/ 119457, // Rule ID 1361 // |
| 46680 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46681 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 46682 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 46683 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 46684 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 46685 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46686 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 46687 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 46688 | // (intrinsic_wo_chain:{ *:[v1i64] } 463:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SQSUBv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) |
| 46689 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv1i64, |
| 46690 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46691 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46692 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46693 | GIR_EraseFromParent, /*InsnID*/0, |
| 46694 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46695 | // GIR_Coverage, 1361, |
| 46696 | GIR_Done, |
| 46697 | // Label 2511: @119457 |
| 46698 | GIM_Try, /*On fail goto*//*Label 2512*/ 119509, // Rule ID 1362 // |
| 46699 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46700 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, |
| 46701 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 46702 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 46703 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 46704 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46705 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 46706 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 46707 | // (intrinsic_wo_chain:{ *:[v1i64] } 467:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SRSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) |
| 46708 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv1i64, |
| 46709 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46710 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46711 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46712 | GIR_EraseFromParent, /*InsnID*/0, |
| 46713 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46714 | // GIR_Coverage, 1362, |
| 46715 | GIR_Done, |
| 46716 | // Label 2512: @119509 |
| 46717 | GIM_Try, /*On fail goto*//*Label 2513*/ 119561, // Rule ID 1363 // |
| 46718 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46719 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, |
| 46720 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 46721 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 46722 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 46723 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46724 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 46725 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 46726 | // (intrinsic_wo_chain:{ *:[v1i64] } 468:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) |
| 46727 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv1i64, |
| 46728 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46729 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46730 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46731 | GIR_EraseFromParent, /*InsnID*/0, |
| 46732 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46733 | // GIR_Coverage, 1363, |
| 46734 | GIR_Done, |
| 46735 | // Label 2513: @119561 |
| 46736 | GIM_Try, /*On fail goto*//*Label 2514*/ 119613, // Rule ID 1365 // |
| 46737 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46738 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, |
| 46739 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 46740 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 46741 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 46742 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46743 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 46744 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 46745 | // (intrinsic_wo_chain:{ *:[v1i64] } 504:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (UQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) |
| 46746 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv1i64, |
| 46747 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46748 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46749 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46750 | GIR_EraseFromParent, /*InsnID*/0, |
| 46751 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46752 | // GIR_Coverage, 1365, |
| 46753 | GIR_Done, |
| 46754 | // Label 2514: @119613 |
| 46755 | GIM_Try, /*On fail goto*//*Label 2515*/ 119665, // Rule ID 1366 // |
| 46756 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46757 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, |
| 46758 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 46759 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 46760 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 46761 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46762 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 46763 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 46764 | // (intrinsic_wo_chain:{ *:[v1i64] } 505:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (UQRSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) |
| 46765 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv1i64, |
| 46766 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46767 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46768 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46769 | GIR_EraseFromParent, /*InsnID*/0, |
| 46770 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46771 | // GIR_Coverage, 1366, |
| 46772 | GIR_Done, |
| 46773 | // Label 2515: @119665 |
| 46774 | GIM_Try, /*On fail goto*//*Label 2516*/ 119717, // Rule ID 1367 // |
| 46775 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46776 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, |
| 46777 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 46778 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 46779 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 46780 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46781 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 46782 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 46783 | // (intrinsic_wo_chain:{ *:[v1i64] } 507:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (UQSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) |
| 46784 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv1i64, |
| 46785 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46786 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46787 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46788 | GIR_EraseFromParent, /*InsnID*/0, |
| 46789 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46790 | // GIR_Coverage, 1367, |
| 46791 | GIR_Done, |
| 46792 | // Label 2516: @119717 |
| 46793 | GIM_Try, /*On fail goto*//*Label 2517*/ 119769, // Rule ID 1368 // |
| 46794 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46795 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, |
| 46796 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 46797 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 46798 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 46799 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46800 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 46801 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 46802 | // (intrinsic_wo_chain:{ *:[v1i64] } 509:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (UQSUBv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) |
| 46803 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv1i64, |
| 46804 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46805 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46806 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46807 | GIR_EraseFromParent, /*InsnID*/0, |
| 46808 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46809 | // GIR_Coverage, 1368, |
| 46810 | GIR_Done, |
| 46811 | // Label 2517: @119769 |
| 46812 | GIM_Try, /*On fail goto*//*Label 2518*/ 119821, // Rule ID 1369 // |
| 46813 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46814 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, |
| 46815 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 46816 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 46817 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 46818 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46819 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 46820 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 46821 | // (intrinsic_wo_chain:{ *:[v1i64] } 513:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (URSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) |
| 46822 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv1i64, |
| 46823 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46824 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46825 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46826 | GIR_EraseFromParent, /*InsnID*/0, |
| 46827 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46828 | // GIR_Coverage, 1369, |
| 46829 | GIR_Done, |
| 46830 | // Label 2518: @119821 |
| 46831 | GIM_Try, /*On fail goto*//*Label 2519*/ 119873, // Rule ID 1370 // |
| 46832 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46833 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, |
| 46834 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 46835 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 46836 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 46837 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46838 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 46839 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 46840 | // (intrinsic_wo_chain:{ *:[v1i64] } 516:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (USHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) |
| 46841 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv1i64, |
| 46842 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46843 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46844 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46845 | GIR_EraseFromParent, /*InsnID*/0, |
| 46846 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46847 | // GIR_Coverage, 1370, |
| 46848 | GIR_Done, |
| 46849 | // Label 2519: @119873 |
| 46850 | GIM_Try, /*On fail goto*//*Label 2520*/ 119925, // Rule ID 1371 // |
| 46851 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46852 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmulls_scalar, |
| 46853 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 46854 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 46855 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 46856 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46857 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 46858 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 46859 | // (intrinsic_wo_chain:{ *:[i64] } 451:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQDMULLi32:{ *:[i64] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) |
| 46860 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULLi32, |
| 46861 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46862 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46863 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46864 | GIR_EraseFromParent, /*InsnID*/0, |
| 46865 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46866 | // GIR_Coverage, 1371, |
| 46867 | GIR_Done, |
| 46868 | // Label 2520: @119925 |
| 46869 | GIM_Try, /*On fail goto*//*Label 2521*/ 119977, // Rule ID 1384 // |
| 46870 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46871 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, |
| 46872 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 46873 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 46874 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 46875 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46876 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 46877 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 46878 | // (intrinsic_wo_chain:{ *:[i64] } 480:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn) => (SUQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn) |
| 46879 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv1i64, |
| 46880 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 46881 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 46882 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 46883 | GIR_EraseFromParent, /*InsnID*/0, |
| 46884 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46885 | // GIR_Coverage, 1384, |
| 46886 | GIR_Done, |
| 46887 | // Label 2521: @119977 |
| 46888 | GIM_Try, /*On fail goto*//*Label 2522*/ 120029, // Rule ID 1385 // |
| 46889 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46890 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, |
| 46891 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 46892 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 46893 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 46894 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 46895 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 46896 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 46897 | // (intrinsic_wo_chain:{ *:[i32] } 480:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn) => (SUQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn) |
| 46898 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv1i32, |
| 46899 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 46900 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 46901 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 46902 | GIR_EraseFromParent, /*InsnID*/0, |
| 46903 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46904 | // GIR_Coverage, 1385, |
| 46905 | GIR_Done, |
| 46906 | // Label 2522: @120029 |
| 46907 | GIM_Try, /*On fail goto*//*Label 2523*/ 120081, // Rule ID 1390 // |
| 46908 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46909 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, |
| 46910 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 46911 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 46912 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 46913 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46914 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 46915 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 46916 | // (intrinsic_wo_chain:{ *:[i64] } 519:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn) => (USQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn) |
| 46917 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv1i64, |
| 46918 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 46919 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 46920 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 46921 | GIR_EraseFromParent, /*InsnID*/0, |
| 46922 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46923 | // GIR_Coverage, 1390, |
| 46924 | GIR_Done, |
| 46925 | // Label 2523: @120081 |
| 46926 | GIM_Try, /*On fail goto*//*Label 2524*/ 120133, // Rule ID 1391 // |
| 46927 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46928 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, |
| 46929 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 46930 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 46931 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 46932 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 46933 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 46934 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 46935 | // (intrinsic_wo_chain:{ *:[i32] } 519:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn) => (USQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn) |
| 46936 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv1i32, |
| 46937 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 46938 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 46939 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 46940 | GIR_EraseFromParent, /*InsnID*/0, |
| 46941 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46942 | // GIR_Coverage, 1391, |
| 46943 | GIR_Done, |
| 46944 | // Label 2524: @120133 |
| 46945 | GIM_Try, /*On fail goto*//*Label 2525*/ 120185, // Rule ID 1392 // |
| 46946 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46947 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addhn, |
| 46948 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 46949 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 46950 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 46951 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46952 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 46953 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 46954 | // (intrinsic_wo_chain:{ *:[v8i8] } 358:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (ADDHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 46955 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv8i16_v8i8, |
| 46956 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46957 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46958 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46959 | GIR_EraseFromParent, /*InsnID*/0, |
| 46960 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46961 | // GIR_Coverage, 1392, |
| 46962 | GIR_Done, |
| 46963 | // Label 2525: @120185 |
| 46964 | GIM_Try, /*On fail goto*//*Label 2526*/ 120237, // Rule ID 1393 // |
| 46965 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46966 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addhn, |
| 46967 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 46968 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 46969 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 46970 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46971 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 46972 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 46973 | // (intrinsic_wo_chain:{ *:[v4i16] } 358:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (ADDHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 46974 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv4i32_v4i16, |
| 46975 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46976 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46977 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46978 | GIR_EraseFromParent, /*InsnID*/0, |
| 46979 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46980 | // GIR_Coverage, 1393, |
| 46981 | GIR_Done, |
| 46982 | // Label 2526: @120237 |
| 46983 | GIM_Try, /*On fail goto*//*Label 2527*/ 120289, // Rule ID 1394 // |
| 46984 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 46985 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_addhn, |
| 46986 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 46987 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 46988 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 46989 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 46990 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 46991 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 46992 | // (intrinsic_wo_chain:{ *:[v2i32] } 358:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (ADDHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 46993 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv2i64_v2i32, |
| 46994 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 46995 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 46996 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 46997 | GIR_EraseFromParent, /*InsnID*/0, |
| 46998 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 46999 | // GIR_Coverage, 1394, |
| 47000 | GIR_Done, |
| 47001 | // Label 2527: @120289 |
| 47002 | GIM_Try, /*On fail goto*//*Label 2528*/ 120341, // Rule ID 1395 // |
| 47003 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47004 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_subhn, |
| 47005 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 47006 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 47007 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 47008 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 47009 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 47010 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 47011 | // (intrinsic_wo_chain:{ *:[v8i8] } 479:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SUBHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 47012 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv8i16_v8i8, |
| 47013 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47014 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47015 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47016 | GIR_EraseFromParent, /*InsnID*/0, |
| 47017 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47018 | // GIR_Coverage, 1395, |
| 47019 | GIR_Done, |
| 47020 | // Label 2528: @120341 |
| 47021 | GIM_Try, /*On fail goto*//*Label 2529*/ 120393, // Rule ID 1396 // |
| 47022 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47023 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_subhn, |
| 47024 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 47025 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 47026 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 47027 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 47028 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 47029 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 47030 | // (intrinsic_wo_chain:{ *:[v4i16] } 479:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SUBHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 47031 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv4i32_v4i16, |
| 47032 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47033 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47034 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47035 | GIR_EraseFromParent, /*InsnID*/0, |
| 47036 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47037 | // GIR_Coverage, 1396, |
| 47038 | GIR_Done, |
| 47039 | // Label 2529: @120393 |
| 47040 | GIM_Try, /*On fail goto*//*Label 2530*/ 120445, // Rule ID 1397 // |
| 47041 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47042 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_subhn, |
| 47043 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 47044 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 47045 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 47046 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 47047 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 47048 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 47049 | // (intrinsic_wo_chain:{ *:[v2i32] } 479:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SUBHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 47050 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv2i64_v2i32, |
| 47051 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47052 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47053 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47054 | GIR_EraseFromParent, /*InsnID*/0, |
| 47055 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47056 | // GIR_Coverage, 1397, |
| 47057 | GIR_Done, |
| 47058 | // Label 2530: @120445 |
| 47059 | GIM_Try, /*On fail goto*//*Label 2531*/ 120497, // Rule ID 1398 // |
| 47060 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47061 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_raddhn, |
| 47062 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 47063 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 47064 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 47065 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 47066 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 47067 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 47068 | // (intrinsic_wo_chain:{ *:[v8i8] } 422:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (RADDHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 47069 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv8i16_v8i8, |
| 47070 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47071 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47072 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47073 | GIR_EraseFromParent, /*InsnID*/0, |
| 47074 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47075 | // GIR_Coverage, 1398, |
| 47076 | GIR_Done, |
| 47077 | // Label 2531: @120497 |
| 47078 | GIM_Try, /*On fail goto*//*Label 2532*/ 120549, // Rule ID 1399 // |
| 47079 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47080 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_raddhn, |
| 47081 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 47082 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 47083 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 47084 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 47085 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 47086 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 47087 | // (intrinsic_wo_chain:{ *:[v4i16] } 422:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (RADDHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 47088 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv4i32_v4i16, |
| 47089 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47090 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47091 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47092 | GIR_EraseFromParent, /*InsnID*/0, |
| 47093 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47094 | // GIR_Coverage, 1399, |
| 47095 | GIR_Done, |
| 47096 | // Label 2532: @120549 |
| 47097 | GIM_Try, /*On fail goto*//*Label 2533*/ 120601, // Rule ID 1400 // |
| 47098 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47099 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_raddhn, |
| 47100 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 47101 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 47102 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 47103 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 47104 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 47105 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 47106 | // (intrinsic_wo_chain:{ *:[v2i32] } 422:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (RADDHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 47107 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RADDHNv2i64_v2i32, |
| 47108 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47109 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47110 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47111 | GIR_EraseFromParent, /*InsnID*/0, |
| 47112 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47113 | // GIR_Coverage, 1400, |
| 47114 | GIR_Done, |
| 47115 | // Label 2533: @120601 |
| 47116 | GIM_Try, /*On fail goto*//*Label 2534*/ 120653, // Rule ID 1401 // |
| 47117 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47118 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rsubhn, |
| 47119 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 47120 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 47121 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 47122 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 47123 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 47124 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 47125 | // (intrinsic_wo_chain:{ *:[v8i8] } 425:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (RSUBHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 47126 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv8i16_v8i8, |
| 47127 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47128 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47129 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47130 | GIR_EraseFromParent, /*InsnID*/0, |
| 47131 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47132 | // GIR_Coverage, 1401, |
| 47133 | GIR_Done, |
| 47134 | // Label 2534: @120653 |
| 47135 | GIM_Try, /*On fail goto*//*Label 2535*/ 120705, // Rule ID 1402 // |
| 47136 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47137 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rsubhn, |
| 47138 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 47139 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 47140 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 47141 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 47142 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 47143 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 47144 | // (intrinsic_wo_chain:{ *:[v4i16] } 425:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (RSUBHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 47145 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv4i32_v4i16, |
| 47146 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47147 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47148 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47149 | GIR_EraseFromParent, /*InsnID*/0, |
| 47150 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47151 | // GIR_Coverage, 1402, |
| 47152 | GIR_Done, |
| 47153 | // Label 2535: @120705 |
| 47154 | GIM_Try, /*On fail goto*//*Label 2536*/ 120757, // Rule ID 1403 // |
| 47155 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47156 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_rsubhn, |
| 47157 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 47158 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 47159 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 47160 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 47161 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 47162 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 47163 | // (intrinsic_wo_chain:{ *:[v2i32] } 425:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (RSUBHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 47164 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::RSUBHNv2i64_v2i32, |
| 47165 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47166 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47167 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47168 | GIR_EraseFromParent, /*InsnID*/0, |
| 47169 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47170 | // GIR_Coverage, 1403, |
| 47171 | GIR_Done, |
| 47172 | // Label 2536: @120757 |
| 47173 | GIM_Try, /*On fail goto*//*Label 2537*/ 120809, // Rule ID 1404 // |
| 47174 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47175 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_pmull, |
| 47176 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 47177 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 47178 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 47179 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 47180 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 47181 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 47182 | // (intrinsic_wo_chain:{ *:[v8i16] } 420:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (PMULLv8i8:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 47183 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PMULLv8i8, |
| 47184 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47185 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47186 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47187 | GIR_EraseFromParent, /*InsnID*/0, |
| 47188 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47189 | // GIR_Coverage, 1404, |
| 47190 | GIR_Done, |
| 47191 | // Label 2537: @120809 |
| 47192 | GIM_Try, /*On fail goto*//*Label 2538*/ 120861, // Rule ID 1453 // |
| 47193 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47194 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smull, |
| 47195 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 47196 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 47197 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 47198 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 47199 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 47200 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 47201 | // (intrinsic_wo_chain:{ *:[v8i16] } 444:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SMULLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 47202 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMULLv8i8_v8i16, |
| 47203 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47204 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47205 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47206 | GIR_EraseFromParent, /*InsnID*/0, |
| 47207 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47208 | // GIR_Coverage, 1453, |
| 47209 | GIR_Done, |
| 47210 | // Label 2538: @120861 |
| 47211 | GIM_Try, /*On fail goto*//*Label 2539*/ 120913, // Rule ID 1455 // |
| 47212 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47213 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smull, |
| 47214 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 47215 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 47216 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 47217 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 47218 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 47219 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 47220 | // (intrinsic_wo_chain:{ *:[v4i32] } 444:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SMULLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 47221 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMULLv4i16_v4i32, |
| 47222 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47223 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47224 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47225 | GIR_EraseFromParent, /*InsnID*/0, |
| 47226 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47227 | // GIR_Coverage, 1455, |
| 47228 | GIR_Done, |
| 47229 | // Label 2539: @120913 |
| 47230 | GIM_Try, /*On fail goto*//*Label 2540*/ 120965, // Rule ID 1457 // |
| 47231 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47232 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smull, |
| 47233 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 47234 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 47235 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 47236 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 47237 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 47238 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 47239 | // (intrinsic_wo_chain:{ *:[v2i64] } 444:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SMULLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 47240 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMULLv2i32_v2i64, |
| 47241 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47242 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47243 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47244 | GIR_EraseFromParent, /*InsnID*/0, |
| 47245 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47246 | // GIR_Coverage, 1457, |
| 47247 | GIR_Done, |
| 47248 | // Label 2540: @120965 |
| 47249 | GIM_Try, /*On fail goto*//*Label 2541*/ 121017, // Rule ID 1467 // |
| 47250 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47251 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, |
| 47252 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 47253 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 47254 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 47255 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 47256 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 47257 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 47258 | // (intrinsic_wo_chain:{ *:[v4i32] } 450:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQDMULLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 47259 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULLv4i16_v4i32, |
| 47260 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47261 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47262 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47263 | GIR_EraseFromParent, /*InsnID*/0, |
| 47264 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47265 | // GIR_Coverage, 1467, |
| 47266 | GIR_Done, |
| 47267 | // Label 2541: @121017 |
| 47268 | GIM_Try, /*On fail goto*//*Label 2542*/ 121069, // Rule ID 1469 // |
| 47269 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47270 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqdmull, |
| 47271 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 47272 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 47273 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 47274 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 47275 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 47276 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 47277 | // (intrinsic_wo_chain:{ *:[v2i64] } 450:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQDMULLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 47278 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQDMULLv2i32_v2i64, |
| 47279 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47280 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47281 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47282 | GIR_EraseFromParent, /*InsnID*/0, |
| 47283 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47284 | // GIR_Coverage, 1469, |
| 47285 | GIR_Done, |
| 47286 | // Label 2542: @121069 |
| 47287 | GIM_Try, /*On fail goto*//*Label 2543*/ 121121, // Rule ID 1543 // |
| 47288 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47289 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umull, |
| 47290 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 47291 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 47292 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 47293 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 47294 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 47295 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 47296 | // (intrinsic_wo_chain:{ *:[v8i16] } 503:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UMULLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 47297 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMULLv8i8_v8i16, |
| 47298 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47299 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47300 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47301 | GIR_EraseFromParent, /*InsnID*/0, |
| 47302 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47303 | // GIR_Coverage, 1543, |
| 47304 | GIR_Done, |
| 47305 | // Label 2543: @121121 |
| 47306 | GIM_Try, /*On fail goto*//*Label 2544*/ 121173, // Rule ID 1545 // |
| 47307 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47308 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umull, |
| 47309 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 47310 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 47311 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 47312 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 47313 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 47314 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 47315 | // (intrinsic_wo_chain:{ *:[v4i32] } 503:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UMULLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 47316 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMULLv4i16_v4i32, |
| 47317 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47318 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47319 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47320 | GIR_EraseFromParent, /*InsnID*/0, |
| 47321 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47322 | // GIR_Coverage, 1545, |
| 47323 | GIR_Done, |
| 47324 | // Label 2544: @121173 |
| 47325 | GIM_Try, /*On fail goto*//*Label 2545*/ 121225, // Rule ID 1547 // |
| 47326 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47327 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_umull, |
| 47328 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 47329 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 47330 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 47331 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 47332 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 47333 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 47334 | // (intrinsic_wo_chain:{ *:[v2i64] } 503:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UMULLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 47335 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMULLv2i32_v2i64, |
| 47336 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47337 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47338 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47339 | GIR_EraseFromParent, /*InsnID*/0, |
| 47340 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47341 | // GIR_Coverage, 1547, |
| 47342 | GIR_Done, |
| 47343 | // Label 2545: @121225 |
| 47344 | GIM_Try, /*On fail goto*//*Label 2546*/ 121277, // Rule ID 1941 // |
| 47345 | GIM_CheckFeatures, GIFBS_HasAES, |
| 47346 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aese, |
| 47347 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 47348 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 47349 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 47350 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 47351 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 47352 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 47353 | // (intrinsic_wo_chain:{ *:[v16i8] } 329:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) => (AESErr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) |
| 47354 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESErr, |
| 47355 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 47356 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 47357 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 47358 | GIR_EraseFromParent, /*InsnID*/0, |
| 47359 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47360 | // GIR_Coverage, 1941, |
| 47361 | GIR_Done, |
| 47362 | // Label 2546: @121277 |
| 47363 | GIM_Try, /*On fail goto*//*Label 2547*/ 121329, // Rule ID 1942 // |
| 47364 | GIM_CheckFeatures, GIFBS_HasAES, |
| 47365 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_aesd, |
| 47366 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 47367 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 47368 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 47369 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 47370 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 47371 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 47372 | // (intrinsic_wo_chain:{ *:[v16i8] } 328:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) => (AESDrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) |
| 47373 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::AESDrr, |
| 47374 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 47375 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 47376 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 47377 | GIR_EraseFromParent, /*InsnID*/0, |
| 47378 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47379 | // GIR_Coverage, 1942, |
| 47380 | GIR_Done, |
| 47381 | // Label 2547: @121329 |
| 47382 | GIM_Try, /*On fail goto*//*Label 2548*/ 121381, // Rule ID 1953 // |
| 47383 | GIM_CheckFeatures, GIFBS_HasSHA2, |
| 47384 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha1su1, |
| 47385 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 47386 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 47387 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 47388 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 47389 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 47390 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 47391 | // (intrinsic_wo_chain:{ *:[v4i32] } 337:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) => (SHA1SU1rr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) |
| 47392 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1SU1rr, |
| 47393 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 47394 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 47395 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 47396 | GIR_EraseFromParent, /*InsnID*/0, |
| 47397 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47398 | // GIR_Coverage, 1953, |
| 47399 | GIR_Done, |
| 47400 | // Label 2548: @121381 |
| 47401 | GIM_Try, /*On fail goto*//*Label 2549*/ 121433, // Rule ID 1954 // |
| 47402 | GIM_CheckFeatures, GIFBS_HasSHA2, |
| 47403 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha256su0, |
| 47404 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 47405 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 47406 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 47407 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 47408 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 47409 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 47410 | // (intrinsic_wo_chain:{ *:[v4i32] } 340:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) => (SHA256SU0rr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) |
| 47411 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA256SU0rr, |
| 47412 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 47413 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 47414 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 47415 | GIR_EraseFromParent, /*InsnID*/0, |
| 47416 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47417 | // GIR_Coverage, 1954, |
| 47418 | GIR_Done, |
| 47419 | // Label 2549: @121433 |
| 47420 | GIM_Try, /*On fail goto*//*Label 2550*/ 121485, // Rule ID 2703 // |
| 47421 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47422 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 47423 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 47424 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 47425 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 47426 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 47427 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 47428 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 47429 | // (intrinsic_wo_chain:{ *:[i64] } 446:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) |
| 47430 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv1i64, |
| 47431 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47432 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47433 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47434 | GIR_EraseFromParent, /*InsnID*/0, |
| 47435 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47436 | // GIR_Coverage, 2703, |
| 47437 | GIR_Done, |
| 47438 | // Label 2550: @121485 |
| 47439 | GIM_Try, /*On fail goto*//*Label 2551*/ 121537, // Rule ID 2704 // |
| 47440 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47441 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqadd, |
| 47442 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 47443 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 47444 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 47445 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 47446 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 47447 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 47448 | // (intrinsic_wo_chain:{ *:[i32] } 446:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) |
| 47449 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQADDv1i32, |
| 47450 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47451 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47452 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47453 | GIR_EraseFromParent, /*InsnID*/0, |
| 47454 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47455 | // GIR_Coverage, 2704, |
| 47456 | GIR_Done, |
| 47457 | // Label 2551: @121537 |
| 47458 | GIM_Try, /*On fail goto*//*Label 2552*/ 121589, // Rule ID 2705 // |
| 47459 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47460 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sisd_fabd, |
| 47461 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 47462 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 47463 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 47464 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 47465 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 47466 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 47467 | // (intrinsic_wo_chain:{ *:[v1f64] } 538:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FABD64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) |
| 47468 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD64, |
| 47469 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47470 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47471 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47472 | GIR_EraseFromParent, /*InsnID*/0, |
| 47473 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47474 | // GIR_Coverage, 2705, |
| 47475 | GIR_Done, |
| 47476 | // Label 2552: @121589 |
| 47477 | GIM_Try, /*On fail goto*//*Label 2553*/ 121641, // Rule ID 2706 // |
| 47478 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47479 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, |
| 47480 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 47481 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 47482 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 47483 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 47484 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 47485 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 47486 | // (intrinsic_wo_chain:{ *:[v1i64] } 369:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FACGE64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) |
| 47487 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGE64, |
| 47488 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47489 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47490 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47491 | GIR_EraseFromParent, /*InsnID*/0, |
| 47492 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47493 | // GIR_Coverage, 2706, |
| 47494 | GIR_Done, |
| 47495 | // Label 2553: @121641 |
| 47496 | GIM_Try, /*On fail goto*//*Label 2554*/ 121693, // Rule ID 2711 // |
| 47497 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47498 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_suqadd, |
| 47499 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 47500 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 47501 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 47502 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 47503 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 47504 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 47505 | // (intrinsic_wo_chain:{ *:[v1i64] } 480:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn) => (SUQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn) |
| 47506 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUQADDv1i64, |
| 47507 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 47508 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 47509 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 47510 | GIR_EraseFromParent, /*InsnID*/0, |
| 47511 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47512 | // GIR_Coverage, 2711, |
| 47513 | GIR_Done, |
| 47514 | // Label 2554: @121693 |
| 47515 | GIM_Try, /*On fail goto*//*Label 2555*/ 121748, // Rule ID 3408 // |
| 47516 | GIM_CheckFeatures, GIFBS_HasComplxNum_HasFullFP16_HasNEON, |
| 47517 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot90, |
| 47518 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 47519 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 47520 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 47521 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 47522 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 47523 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 47524 | // (intrinsic_wo_chain:{ *:[v4f16] } 521:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FCADDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm, 0:{ *:[i32] }) |
| 47525 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv4f16, |
| 47526 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47527 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47528 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47529 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 47530 | GIR_EraseFromParent, /*InsnID*/0, |
| 47531 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47532 | // GIR_Coverage, 3408, |
| 47533 | GIR_Done, |
| 47534 | // Label 2555: @121748 |
| 47535 | GIM_Try, /*On fail goto*//*Label 2556*/ 121803, // Rule ID 3409 // |
| 47536 | GIM_CheckFeatures, GIFBS_HasComplxNum_HasFullFP16_HasNEON, |
| 47537 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot270, |
| 47538 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, |
| 47539 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 47540 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 47541 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 47542 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 47543 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 47544 | // (intrinsic_wo_chain:{ *:[v4f16] } 520:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FCADDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm, 1:{ *:[i32] }) |
| 47545 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv4f16, |
| 47546 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47547 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47548 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47549 | GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 47550 | GIR_EraseFromParent, /*InsnID*/0, |
| 47551 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47552 | // GIR_Coverage, 3409, |
| 47553 | GIR_Done, |
| 47554 | // Label 2556: @121803 |
| 47555 | GIM_Try, /*On fail goto*//*Label 2557*/ 121858, // Rule ID 3410 // |
| 47556 | GIM_CheckFeatures, GIFBS_HasComplxNum_HasFullFP16_HasNEON, |
| 47557 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot90, |
| 47558 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 47559 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 47560 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 47561 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 47562 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 47563 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 47564 | // (intrinsic_wo_chain:{ *:[v8f16] } 521:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FCADDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, 0:{ *:[i32] }) |
| 47565 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv8f16, |
| 47566 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47567 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47568 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47569 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 47570 | GIR_EraseFromParent, /*InsnID*/0, |
| 47571 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47572 | // GIR_Coverage, 3410, |
| 47573 | GIR_Done, |
| 47574 | // Label 2557: @121858 |
| 47575 | GIM_Try, /*On fail goto*//*Label 2558*/ 121913, // Rule ID 3411 // |
| 47576 | GIM_CheckFeatures, GIFBS_HasComplxNum_HasFullFP16_HasNEON, |
| 47577 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot270, |
| 47578 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 47579 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 47580 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 47581 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 47582 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 47583 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 47584 | // (intrinsic_wo_chain:{ *:[v8f16] } 520:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FCADDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, 1:{ *:[i32] }) |
| 47585 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv8f16, |
| 47586 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47587 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47588 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47589 | GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 47590 | GIR_EraseFromParent, /*InsnID*/0, |
| 47591 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47592 | // GIR_Coverage, 3411, |
| 47593 | GIR_Done, |
| 47594 | // Label 2558: @121913 |
| 47595 | GIM_Try, /*On fail goto*//*Label 2559*/ 121968, // Rule ID 3412 // |
| 47596 | GIM_CheckFeatures, GIFBS_HasComplxNum_HasNEON, |
| 47597 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot90, |
| 47598 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 47599 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 47600 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 47601 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 47602 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 47603 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 47604 | // (intrinsic_wo_chain:{ *:[v2f32] } 521:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FCADDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm, 0:{ *:[i32] }) |
| 47605 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv2f32, |
| 47606 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47607 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47608 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47609 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 47610 | GIR_EraseFromParent, /*InsnID*/0, |
| 47611 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47612 | // GIR_Coverage, 3412, |
| 47613 | GIR_Done, |
| 47614 | // Label 2559: @121968 |
| 47615 | GIM_Try, /*On fail goto*//*Label 2560*/ 122023, // Rule ID 3413 // |
| 47616 | GIM_CheckFeatures, GIFBS_HasComplxNum_HasNEON, |
| 47617 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot270, |
| 47618 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 47619 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 47620 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 47621 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 47622 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 47623 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 47624 | // (intrinsic_wo_chain:{ *:[v2f32] } 520:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FCADDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm, 1:{ *:[i32] }) |
| 47625 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv2f32, |
| 47626 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47627 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47628 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47629 | GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 47630 | GIR_EraseFromParent, /*InsnID*/0, |
| 47631 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47632 | // GIR_Coverage, 3413, |
| 47633 | GIR_Done, |
| 47634 | // Label 2560: @122023 |
| 47635 | GIM_Try, /*On fail goto*//*Label 2561*/ 122078, // Rule ID 3414 // |
| 47636 | GIM_CheckFeatures, GIFBS_HasComplxNum_HasNEON, |
| 47637 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot90, |
| 47638 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 47639 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 47640 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 47641 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 47642 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 47643 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 47644 | // (intrinsic_wo_chain:{ *:[v4f32] } 521:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FCADDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, 0:{ *:[i32] }) |
| 47645 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv4f32, |
| 47646 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47647 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47648 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47649 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 47650 | GIR_EraseFromParent, /*InsnID*/0, |
| 47651 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47652 | // GIR_Coverage, 3414, |
| 47653 | GIR_Done, |
| 47654 | // Label 2561: @122078 |
| 47655 | GIM_Try, /*On fail goto*//*Label 2562*/ 122133, // Rule ID 3415 // |
| 47656 | GIM_CheckFeatures, GIFBS_HasComplxNum_HasNEON, |
| 47657 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot270, |
| 47658 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 47659 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 47660 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 47661 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 47662 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 47663 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 47664 | // (intrinsic_wo_chain:{ *:[v4f32] } 520:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FCADDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, 1:{ *:[i32] }) |
| 47665 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv4f32, |
| 47666 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47667 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47668 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47669 | GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 47670 | GIR_EraseFromParent, /*InsnID*/0, |
| 47671 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47672 | // GIR_Coverage, 3415, |
| 47673 | GIR_Done, |
| 47674 | // Label 2562: @122133 |
| 47675 | GIM_Try, /*On fail goto*//*Label 2563*/ 122188, // Rule ID 3416 // |
| 47676 | GIM_CheckFeatures, GIFBS_HasComplxNum_HasNEON, |
| 47677 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot90, |
| 47678 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 47679 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 47680 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 47681 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 47682 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 47683 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 47684 | // (intrinsic_wo_chain:{ *:[v2f64] } 521:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FCADDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, 0:{ *:[i32] }) |
| 47685 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv2f64, |
| 47686 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47687 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47688 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47689 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 47690 | GIR_EraseFromParent, /*InsnID*/0, |
| 47691 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47692 | // GIR_Coverage, 3416, |
| 47693 | GIR_Done, |
| 47694 | // Label 2563: @122188 |
| 47695 | GIM_Try, /*On fail goto*//*Label 2564*/ 122243, // Rule ID 3417 // |
| 47696 | GIM_CheckFeatures, GIFBS_HasComplxNum_HasNEON, |
| 47697 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcadd_rot270, |
| 47698 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 47699 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 47700 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 47701 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 47702 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 47703 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 47704 | // (intrinsic_wo_chain:{ *:[v2f64] } 520:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FCADDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, 1:{ *:[i32] }) |
| 47705 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCADDv2f64, |
| 47706 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47707 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47708 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47709 | GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 47710 | GIR_EraseFromParent, /*InsnID*/0, |
| 47711 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47712 | // GIR_Coverage, 3417, |
| 47713 | GIR_Done, |
| 47714 | // Label 2564: @122243 |
| 47715 | GIM_Try, /*On fail goto*//*Label 2565*/ 122293, // Rule ID 3475 // |
| 47716 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_udiv, |
| 47717 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 47718 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 47719 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 47720 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 47721 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 47722 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, |
| 47723 | // (intrinsic_wo_chain:{ *:[i32] } 1160:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (UDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 47724 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UDIVWr, |
| 47725 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47726 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47727 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47728 | GIR_EraseFromParent, /*InsnID*/0, |
| 47729 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47730 | // GIR_Coverage, 3475, |
| 47731 | GIR_Done, |
| 47732 | // Label 2565: @122293 |
| 47733 | GIM_Try, /*On fail goto*//*Label 2566*/ 122343, // Rule ID 3476 // |
| 47734 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_udiv, |
| 47735 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 47736 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 47737 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 47738 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 47739 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 47740 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, |
| 47741 | // (intrinsic_wo_chain:{ *:[i64] } 1160:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (UDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) |
| 47742 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UDIVXr, |
| 47743 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47744 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47745 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47746 | GIR_EraseFromParent, /*InsnID*/0, |
| 47747 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47748 | // GIR_Coverage, 3476, |
| 47749 | GIR_Done, |
| 47750 | // Label 2566: @122343 |
| 47751 | GIM_Try, /*On fail goto*//*Label 2567*/ 122393, // Rule ID 3477 // |
| 47752 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sdiv, |
| 47753 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 47754 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 47755 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 47756 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 47757 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32RegClassID, |
| 47758 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR32RegClassID, |
| 47759 | // (intrinsic_wo_chain:{ *:[i32] } 535:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (SDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 47760 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SDIVWr, |
| 47761 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47762 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47763 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47764 | GIR_EraseFromParent, /*InsnID*/0, |
| 47765 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47766 | // GIR_Coverage, 3477, |
| 47767 | GIR_Done, |
| 47768 | // Label 2567: @122393 |
| 47769 | GIM_Try, /*On fail goto*//*Label 2568*/ 122443, // Rule ID 3478 // |
| 47770 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_sdiv, |
| 47771 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 47772 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 47773 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 47774 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 47775 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 47776 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, |
| 47777 | // (intrinsic_wo_chain:{ *:[i64] } 535:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (SDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) |
| 47778 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SDIVXr, |
| 47779 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47780 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47781 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47782 | GIR_EraseFromParent, /*InsnID*/0, |
| 47783 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47784 | // GIR_Coverage, 3478, |
| 47785 | GIR_Done, |
| 47786 | // Label 2568: @122443 |
| 47787 | GIM_Try, /*On fail goto*//*Label 2569*/ 122493, // Rule ID 4105 // |
| 47788 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fabd, |
| 47789 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 47790 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 47791 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 47792 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 47793 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 47794 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 47795 | // (intrinsic_wo_chain:{ *:[v1f64] } 368:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FABD64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) |
| 47796 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD64, |
| 47797 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47798 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47799 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47800 | GIR_EraseFromParent, /*InsnID*/0, |
| 47801 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47802 | // GIR_Coverage, 4105, |
| 47803 | GIR_Done, |
| 47804 | // Label 2569: @122493 |
| 47805 | GIM_Try, /*On fail goto*//*Label 2570*/ 122545, // Rule ID 4109 // |
| 47806 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47807 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, |
| 47808 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 47809 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 47810 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 47811 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 47812 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 47813 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 47814 | // (intrinsic_wo_chain:{ *:[v1i64] } 370:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FACGT64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) |
| 47815 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FACGT64, |
| 47816 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47817 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47818 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47819 | GIR_EraseFromParent, /*InsnID*/0, |
| 47820 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47821 | // GIR_Coverage, 4109, |
| 47822 | GIR_Done, |
| 47823 | // Label 2570: @122545 |
| 47824 | GIM_Try, /*On fail goto*//*Label 2571*/ 122597, // Rule ID 4113 // |
| 47825 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47826 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmulx, |
| 47827 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 47828 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 47829 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 47830 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 47831 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 47832 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 47833 | // (intrinsic_wo_chain:{ *:[v1f64] } 400:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FMULX64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) |
| 47834 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULX64, |
| 47835 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47836 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47837 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47838 | GIR_EraseFromParent, /*InsnID*/0, |
| 47839 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47840 | // GIR_Coverage, 4113, |
| 47841 | GIR_Done, |
| 47842 | // Label 2571: @122597 |
| 47843 | GIM_Try, /*On fail goto*//*Label 2572*/ 122649, // Rule ID 4114 // |
| 47844 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47845 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frecps, |
| 47846 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 47847 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 47848 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 47849 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 47850 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 47851 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 47852 | // (intrinsic_wo_chain:{ *:[v1f64] } 402:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FRECPS64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) |
| 47853 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRECPS64, |
| 47854 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47855 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47856 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47857 | GIR_EraseFromParent, /*InsnID*/0, |
| 47858 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47859 | // GIR_Coverage, 4114, |
| 47860 | GIR_Done, |
| 47861 | // Label 2572: @122649 |
| 47862 | GIM_Try, /*On fail goto*//*Label 2573*/ 122701, // Rule ID 4115 // |
| 47863 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47864 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_frsqrts, |
| 47865 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 47866 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 47867 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 47868 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 47869 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 47870 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 47871 | // (intrinsic_wo_chain:{ *:[v1f64] } 406:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FRSQRTS64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) |
| 47872 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FRSQRTS64, |
| 47873 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47874 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47875 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47876 | GIR_EraseFromParent, /*InsnID*/0, |
| 47877 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47878 | // GIR_Coverage, 4115, |
| 47879 | GIR_Done, |
| 47880 | // Label 2573: @122701 |
| 47881 | GIM_Try, /*On fail goto*//*Label 2574*/ 122753, // Rule ID 4116 // |
| 47882 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47883 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, |
| 47884 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 47885 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 47886 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 47887 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 47888 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 47889 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 47890 | // (intrinsic_wo_chain:{ *:[i64] } 456:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SQRSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) |
| 47891 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv1i64, |
| 47892 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47893 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47894 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47895 | GIR_EraseFromParent, /*InsnID*/0, |
| 47896 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47897 | // GIR_Coverage, 4116, |
| 47898 | GIR_Done, |
| 47899 | // Label 2574: @122753 |
| 47900 | GIM_Try, /*On fail goto*//*Label 2575*/ 122805, // Rule ID 4117 // |
| 47901 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47902 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqrshl, |
| 47903 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 47904 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 47905 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 47906 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 47907 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 47908 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 47909 | // (intrinsic_wo_chain:{ *:[i32] } 456:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQRSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) |
| 47910 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQRSHLv1i32, |
| 47911 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47912 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47913 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47914 | GIR_EraseFromParent, /*InsnID*/0, |
| 47915 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47916 | // GIR_Coverage, 4117, |
| 47917 | GIR_Done, |
| 47918 | // Label 2575: @122805 |
| 47919 | GIM_Try, /*On fail goto*//*Label 2576*/ 122857, // Rule ID 4118 // |
| 47920 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47921 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, |
| 47922 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 47923 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 47924 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 47925 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 47926 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 47927 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 47928 | // (intrinsic_wo_chain:{ *:[i64] } 459:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SQSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) |
| 47929 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv1i64, |
| 47930 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47931 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47932 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47933 | GIR_EraseFromParent, /*InsnID*/0, |
| 47934 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47935 | // GIR_Coverage, 4118, |
| 47936 | GIR_Done, |
| 47937 | // Label 2576: @122857 |
| 47938 | GIM_Try, /*On fail goto*//*Label 2577*/ 122909, // Rule ID 4119 // |
| 47939 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47940 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqshl, |
| 47941 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 47942 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 47943 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 47944 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 47945 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 47946 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 47947 | // (intrinsic_wo_chain:{ *:[i32] } 459:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) |
| 47948 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSHLv1i32, |
| 47949 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47950 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47951 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47952 | GIR_EraseFromParent, /*InsnID*/0, |
| 47953 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47954 | // GIR_Coverage, 4119, |
| 47955 | GIR_Done, |
| 47956 | // Label 2577: @122909 |
| 47957 | GIM_Try, /*On fail goto*//*Label 2578*/ 122961, // Rule ID 4120 // |
| 47958 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47959 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 47960 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 47961 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 47962 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 47963 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 47964 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 47965 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 47966 | // (intrinsic_wo_chain:{ *:[i64] } 463:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SQSUBv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) |
| 47967 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv1i64, |
| 47968 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47969 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47970 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47971 | GIR_EraseFromParent, /*InsnID*/0, |
| 47972 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47973 | // GIR_Coverage, 4120, |
| 47974 | GIR_Done, |
| 47975 | // Label 2578: @122961 |
| 47976 | GIM_Try, /*On fail goto*//*Label 2579*/ 123013, // Rule ID 4121 // |
| 47977 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47978 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sqsub, |
| 47979 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 47980 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 47981 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 47982 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 47983 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 47984 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 47985 | // (intrinsic_wo_chain:{ *:[i32] } 463:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQSUBv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) |
| 47986 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SQSUBv1i32, |
| 47987 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 47988 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 47989 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 47990 | GIR_EraseFromParent, /*InsnID*/0, |
| 47991 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 47992 | // GIR_Coverage, 4121, |
| 47993 | GIR_Done, |
| 47994 | // Label 2579: @123013 |
| 47995 | GIM_Try, /*On fail goto*//*Label 2580*/ 123065, // Rule ID 4122 // |
| 47996 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 47997 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, |
| 47998 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 47999 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 48000 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 48001 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 48002 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 48003 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 48004 | // (intrinsic_wo_chain:{ *:[i64] } 504:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (UQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) |
| 48005 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv1i64, |
| 48006 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 48007 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 48008 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 48009 | GIR_EraseFromParent, /*InsnID*/0, |
| 48010 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48011 | // GIR_Coverage, 4122, |
| 48012 | GIR_Done, |
| 48013 | // Label 2580: @123065 |
| 48014 | GIM_Try, /*On fail goto*//*Label 2581*/ 123117, // Rule ID 4123 // |
| 48015 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 48016 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqadd, |
| 48017 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 48018 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 48019 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 48020 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 48021 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 48022 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 48023 | // (intrinsic_wo_chain:{ *:[i32] } 504:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (UQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) |
| 48024 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQADDv1i32, |
| 48025 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 48026 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 48027 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 48028 | GIR_EraseFromParent, /*InsnID*/0, |
| 48029 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48030 | // GIR_Coverage, 4123, |
| 48031 | GIR_Done, |
| 48032 | // Label 2581: @123117 |
| 48033 | GIM_Try, /*On fail goto*//*Label 2582*/ 123169, // Rule ID 4124 // |
| 48034 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 48035 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, |
| 48036 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 48037 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 48038 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 48039 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 48040 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 48041 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 48042 | // (intrinsic_wo_chain:{ *:[i64] } 505:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (UQRSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) |
| 48043 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv1i64, |
| 48044 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 48045 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 48046 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 48047 | GIR_EraseFromParent, /*InsnID*/0, |
| 48048 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48049 | // GIR_Coverage, 4124, |
| 48050 | GIR_Done, |
| 48051 | // Label 2582: @123169 |
| 48052 | GIM_Try, /*On fail goto*//*Label 2583*/ 123221, // Rule ID 4125 // |
| 48053 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 48054 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqrshl, |
| 48055 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 48056 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 48057 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 48058 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 48059 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 48060 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 48061 | // (intrinsic_wo_chain:{ *:[i32] } 505:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (UQRSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) |
| 48062 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQRSHLv1i32, |
| 48063 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 48064 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 48065 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 48066 | GIR_EraseFromParent, /*InsnID*/0, |
| 48067 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48068 | // GIR_Coverage, 4125, |
| 48069 | GIR_Done, |
| 48070 | // Label 2583: @123221 |
| 48071 | GIM_Try, /*On fail goto*//*Label 2584*/ 123273, // Rule ID 4126 // |
| 48072 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 48073 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, |
| 48074 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 48075 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 48076 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 48077 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 48078 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 48079 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 48080 | // (intrinsic_wo_chain:{ *:[i64] } 507:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (UQSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) |
| 48081 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv1i64, |
| 48082 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 48083 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 48084 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 48085 | GIR_EraseFromParent, /*InsnID*/0, |
| 48086 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48087 | // GIR_Coverage, 4126, |
| 48088 | GIR_Done, |
| 48089 | // Label 2584: @123273 |
| 48090 | GIM_Try, /*On fail goto*//*Label 2585*/ 123325, // Rule ID 4127 // |
| 48091 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 48092 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqshl, |
| 48093 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 48094 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 48095 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 48096 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 48097 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 48098 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 48099 | // (intrinsic_wo_chain:{ *:[i32] } 507:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (UQSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) |
| 48100 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSHLv1i32, |
| 48101 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 48102 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 48103 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 48104 | GIR_EraseFromParent, /*InsnID*/0, |
| 48105 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48106 | // GIR_Coverage, 4127, |
| 48107 | GIR_Done, |
| 48108 | // Label 2585: @123325 |
| 48109 | GIM_Try, /*On fail goto*//*Label 2586*/ 123377, // Rule ID 4128 // |
| 48110 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 48111 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, |
| 48112 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 48113 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 48114 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 48115 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 48116 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 48117 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 48118 | // (intrinsic_wo_chain:{ *:[i64] } 509:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (UQSUBv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) |
| 48119 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv1i64, |
| 48120 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 48121 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 48122 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 48123 | GIR_EraseFromParent, /*InsnID*/0, |
| 48124 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48125 | // GIR_Coverage, 4128, |
| 48126 | GIR_Done, |
| 48127 | // Label 2586: @123377 |
| 48128 | GIM_Try, /*On fail goto*//*Label 2587*/ 123429, // Rule ID 4129 // |
| 48129 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 48130 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_uqsub, |
| 48131 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 48132 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 48133 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 48134 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 48135 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 48136 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 48137 | // (intrinsic_wo_chain:{ *:[i32] } 509:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (UQSUBv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) |
| 48138 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UQSUBv1i32, |
| 48139 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 48140 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 48141 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 48142 | GIR_EraseFromParent, /*InsnID*/0, |
| 48143 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48144 | // GIR_Coverage, 4129, |
| 48145 | GIR_Done, |
| 48146 | // Label 2587: @123429 |
| 48147 | GIM_Try, /*On fail goto*//*Label 2588*/ 123481, // Rule ID 4144 // |
| 48148 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 48149 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usqadd, |
| 48150 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 48151 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 48152 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 48153 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 48154 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 48155 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 48156 | // (intrinsic_wo_chain:{ *:[v1i64] } 519:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn) => (USQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn) |
| 48157 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USQADDv1i64, |
| 48158 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 48159 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 48160 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 48161 | GIR_EraseFromParent, /*InsnID*/0, |
| 48162 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48163 | // GIR_Coverage, 4144, |
| 48164 | GIR_Done, |
| 48165 | // Label 2588: @123481 |
| 48166 | GIM_Try, /*On fail goto*//*Label 2589*/ 123531, // Rule ID 4254 // |
| 48167 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_pmull64, |
| 48168 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 48169 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 48170 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 48171 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 48172 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 48173 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 48174 | // (intrinsic_wo_chain:{ *:[v16i8] } 421:{ *:[iPTR] }, V64:{ *:[i64] }:$Rn, V64:{ *:[i64] }:$Rm) => (PMULLv1i64:{ *:[v16i8] } V64:{ *:[i64] }:$Rn, V64:{ *:[i64] }:$Rm) |
| 48175 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::PMULLv1i64, |
| 48176 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 48177 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 48178 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 48179 | GIR_EraseFromParent, /*InsnID*/0, |
| 48180 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48181 | // GIR_Coverage, 4254, |
| 48182 | GIR_Done, |
| 48183 | // Label 2589: @123531 |
| 48184 | GIM_Try, /*On fail goto*//*Label 2590*/ 123581, // Rule ID 4333 // |
| 48185 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_tbl1, |
| 48186 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 48187 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 48188 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 48189 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 48190 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 48191 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 48192 | // (intrinsic_wo_chain:{ *:[v8i8] } 481:{ *:[iPTR] }, VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri) => (TBLv8i8One:{ *:[v8i8] } VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri) |
| 48193 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TBLv8i8One, |
| 48194 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd |
| 48195 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 48196 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ri |
| 48197 | GIR_EraseFromParent, /*InsnID*/0, |
| 48198 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48199 | // GIR_Coverage, 4333, |
| 48200 | GIR_Done, |
| 48201 | // Label 2590: @123581 |
| 48202 | GIM_Try, /*On fail goto*//*Label 2591*/ 123631, // Rule ID 4334 // |
| 48203 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_tbl1, |
| 48204 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 48205 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 48206 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 48207 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 48208 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 48209 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 48210 | // (intrinsic_wo_chain:{ *:[v16i8] } 481:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn) => (TBLv16i8One:{ *:[v16i8] } V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn) |
| 48211 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TBLv16i8One, |
| 48212 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd |
| 48213 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ri |
| 48214 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 48215 | GIR_EraseFromParent, /*InsnID*/0, |
| 48216 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48217 | // GIR_Coverage, 4334, |
| 48218 | GIR_Done, |
| 48219 | // Label 2591: @123631 |
| 48220 | GIM_Try, /*On fail goto*//*Label 2592*/ 123726, // Rule ID 4726 // |
| 48221 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facge, |
| 48222 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 48223 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 48224 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, |
| 48225 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 48226 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 48227 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, |
| 48228 | // (intrinsic_wo_chain:{ *:[i32] } 369:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (FACGE16:{ *:[bf16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm), hsub:{ *:[i32] }) |
| 48229 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 48230 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 48231 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::FACGE16, |
| 48232 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 48233 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 48234 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 48235 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 48236 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 48237 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 48238 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48239 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 48240 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 48241 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 48242 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 48243 | GIR_AddImm, /*InsnID*/0, /*Imm*/7, |
| 48244 | GIR_EraseFromParent, /*InsnID*/0, |
| 48245 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, |
| 48246 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR32RegClassID, |
| 48247 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::FPR16RegClassID, |
| 48248 | // GIR_Coverage, 4726, |
| 48249 | GIR_Done, |
| 48250 | // Label 2592: @123726 |
| 48251 | GIM_Try, /*On fail goto*//*Label 2593*/ 123821, // Rule ID 4727 // |
| 48252 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_facgt, |
| 48253 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 48254 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 48255 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, |
| 48256 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 48257 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 48258 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, |
| 48259 | // (intrinsic_wo_chain:{ *:[i32] } 370:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (FACGT16:{ *:[bf16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm), hsub:{ *:[i32] }) |
| 48260 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 48261 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 48262 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::FACGT16, |
| 48263 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 48264 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 48265 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 48266 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 48267 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 48268 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 48269 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 48270 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 48271 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 48272 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 48273 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 48274 | GIR_AddImm, /*InsnID*/0, /*Imm*/7, |
| 48275 | GIR_EraseFromParent, /*InsnID*/0, |
| 48276 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, |
| 48277 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR32RegClassID, |
| 48278 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::FPR16RegClassID, |
| 48279 | // GIR_Coverage, 4727, |
| 48280 | GIR_Done, |
| 48281 | // Label 2593: @123821 |
| 48282 | GIM_Try, /*On fail goto*//*Label 2594*/ 123871, // Rule ID 5335 // |
| 48283 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sshl, |
| 48284 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 48285 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 48286 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 48287 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 48288 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 48289 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 48290 | // (intrinsic_wo_chain:{ *:[i64] } 468:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) |
| 48291 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLv1i64, |
| 48292 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 48293 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 48294 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 48295 | GIR_EraseFromParent, /*InsnID*/0, |
| 48296 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48297 | // GIR_Coverage, 5335, |
| 48298 | GIR_Done, |
| 48299 | // Label 2594: @123871 |
| 48300 | GIM_Try, /*On fail goto*//*Label 2595*/ 123921, // Rule ID 5336 // |
| 48301 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ushl, |
| 48302 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 48303 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 48304 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 48305 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 48306 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 48307 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 48308 | // (intrinsic_wo_chain:{ *:[i64] } 516:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (USHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) |
| 48309 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLv1i64, |
| 48310 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 48311 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 48312 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 48313 | GIR_EraseFromParent, /*InsnID*/0, |
| 48314 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48315 | // GIR_Coverage, 5336, |
| 48316 | GIR_Done, |
| 48317 | // Label 2595: @123921 |
| 48318 | GIM_Try, /*On fail goto*//*Label 2596*/ 123971, // Rule ID 5337 // |
| 48319 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_srshl, |
| 48320 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 48321 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 48322 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 48323 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 48324 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 48325 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 48326 | // (intrinsic_wo_chain:{ *:[i64] } 467:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SRSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) |
| 48327 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SRSHLv1i64, |
| 48328 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 48329 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 48330 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 48331 | GIR_EraseFromParent, /*InsnID*/0, |
| 48332 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48333 | // GIR_Coverage, 5337, |
| 48334 | GIR_Done, |
| 48335 | // Label 2596: @123971 |
| 48336 | GIM_Try, /*On fail goto*//*Label 2597*/ 124021, // Rule ID 5338 // |
| 48337 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_urshl, |
| 48338 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 48339 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 48340 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 48341 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 48342 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 48343 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 48344 | // (intrinsic_wo_chain:{ *:[i64] } 513:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (URSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) |
| 48345 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::URSHLv1i64, |
| 48346 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 48347 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 48348 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 48349 | GIR_EraseFromParent, /*InsnID*/0, |
| 48350 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48351 | // GIR_Coverage, 5338, |
| 48352 | GIR_Done, |
| 48353 | // Label 2597: @124021 |
| 48354 | GIM_Try, /*On fail goto*//*Label 2598*/ 124073, // Rule ID 129 // |
| 48355 | GIM_CheckFeatures, GIFBS_HasMTE, |
| 48356 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_gmi, |
| 48357 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 48358 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 48359 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 48360 | // MIs[0] Rn |
| 48361 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, |
| 48362 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, |
| 48363 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, |
| 48364 | // (intrinsic_wo_chain:{ *:[i64] } 346:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (GMI:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) |
| 48365 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::GMI, |
| 48366 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 48367 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 48368 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 48369 | GIR_EraseFromParent, /*InsnID*/0, |
| 48370 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48371 | // GIR_Coverage, 129, |
| 48372 | GIR_Done, |
| 48373 | // Label 2598: @124073 |
| 48374 | GIM_Try, /*On fail goto*//*Label 2599*/ 124125, // Rule ID 130 // |
| 48375 | GIM_CheckFeatures, GIFBS_HasMTE, |
| 48376 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_subp, |
| 48377 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 48378 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 48379 | // MIs[0] Rn |
| 48380 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, |
| 48381 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, |
| 48382 | // MIs[0] Rm |
| 48383 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, |
| 48384 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, |
| 48385 | // (intrinsic_wo_chain:{ *:[i64] } 550:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm) => (SUBP:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm) |
| 48386 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBP, |
| 48387 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 48388 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 48389 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 48390 | GIR_EraseFromParent, /*InsnID*/0, |
| 48391 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48392 | // GIR_Coverage, 130, |
| 48393 | GIR_Done, |
| 48394 | // Label 2599: @124125 |
| 48395 | GIM_Reject, |
| 48396 | // Label 2124: @124126 |
| 48397 | GIM_Try, /*On fail goto*//*Label 2600*/ 128162, |
| 48398 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, |
| 48399 | GIM_Try, /*On fail goto*//*Label 2601*/ 124240, // Rule ID 46 // |
| 48400 | GIM_CheckFeatures, GIFBS_HasMatMulInt8, |
| 48401 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usdot, |
| 48402 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 48403 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 48404 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 48405 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, |
| 48406 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 48407 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 48408 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 48409 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, |
| 48410 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 48411 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 48412 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 48413 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 48414 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 48415 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 48416 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 48417 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 48418 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 48419 | // MIs[3] Operand 1 |
| 48420 | // No operand predicates |
| 48421 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, |
| 48422 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 48423 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 48424 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 48425 | // (intrinsic_wo_chain:{ *:[v2i32] } 515:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, (bitconvert:{ *:[v8i8] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V64:{ *:[v8i8] }:$Rn) => (SUDOTlanev8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 48426 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUDOTlanev8i8, |
| 48427 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 48428 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 48429 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rn |
| 48430 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 48431 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 48432 | GIR_EraseFromParent, /*InsnID*/0, |
| 48433 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48434 | // GIR_Coverage, 46, |
| 48435 | GIR_Done, |
| 48436 | // Label 2601: @124240 |
| 48437 | GIM_Try, /*On fail goto*//*Label 2602*/ 124349, // Rule ID 47 // |
| 48438 | GIM_CheckFeatures, GIFBS_HasMatMulInt8, |
| 48439 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usdot, |
| 48440 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 48441 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 48442 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 48443 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, |
| 48444 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 48445 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 48446 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 48447 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, |
| 48448 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 48449 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 48450 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 48451 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 48452 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 48453 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 48454 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 48455 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 48456 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 48457 | // MIs[3] Operand 1 |
| 48458 | // No operand predicates |
| 48459 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 48460 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 48461 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 48462 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 48463 | // (intrinsic_wo_chain:{ *:[v4i32] } 515:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (bitconvert:{ *:[v16i8] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v16i8] }:$Rn) => (SUDOTlanev16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 48464 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUDOTlanev16i8, |
| 48465 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 48466 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 48467 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rn |
| 48468 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 48469 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 48470 | GIR_EraseFromParent, /*InsnID*/0, |
| 48471 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48472 | // GIR_Coverage, 47, |
| 48473 | GIR_Done, |
| 48474 | // Label 2602: @124349 |
| 48475 | GIM_Try, /*On fail goto*//*Label 2603*/ 124458, // Rule ID 23 // |
| 48476 | GIM_CheckFeatures, GIFBS_HasDotProd, |
| 48477 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sdot, |
| 48478 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 48479 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 48480 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 48481 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, |
| 48482 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 48483 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 48484 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 48485 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 48486 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, |
| 48487 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 48488 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 48489 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 48490 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 48491 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 48492 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 48493 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 48494 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 48495 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 48496 | // MIs[3] Operand 1 |
| 48497 | // No operand predicates |
| 48498 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 48499 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 48500 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 48501 | // (intrinsic_wo_chain:{ *:[v2i32] } 433:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, (bitconvert:{ *:[v8i8] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (SDOTlanev8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 48502 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SDOTlanev8i8, |
| 48503 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 48504 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 48505 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 48506 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 48507 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 48508 | GIR_EraseFromParent, /*InsnID*/0, |
| 48509 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48510 | // GIR_Coverage, 23, |
| 48511 | GIR_Done, |
| 48512 | // Label 2603: @124458 |
| 48513 | GIM_Try, /*On fail goto*//*Label 2604*/ 124567, // Rule ID 24 // |
| 48514 | GIM_CheckFeatures, GIFBS_HasDotProd, |
| 48515 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sdot, |
| 48516 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 48517 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 48518 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 48519 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, |
| 48520 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 48521 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 48522 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 48523 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 48524 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, |
| 48525 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 48526 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 48527 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 48528 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 48529 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 48530 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 48531 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 48532 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 48533 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 48534 | // MIs[3] Operand 1 |
| 48535 | // No operand predicates |
| 48536 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 48537 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 48538 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 48539 | // (intrinsic_wo_chain:{ *:[v4i32] } 433:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, (bitconvert:{ *:[v16i8] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (SDOTlanev16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 48540 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SDOTlanev16i8, |
| 48541 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 48542 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 48543 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 48544 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 48545 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 48546 | GIR_EraseFromParent, /*InsnID*/0, |
| 48547 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48548 | // GIR_Coverage, 24, |
| 48549 | GIR_Done, |
| 48550 | // Label 2604: @124567 |
| 48551 | GIM_Try, /*On fail goto*//*Label 2605*/ 124676, // Rule ID 25 // |
| 48552 | GIM_CheckFeatures, GIFBS_HasDotProd, |
| 48553 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_udot, |
| 48554 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 48555 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 48556 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 48557 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, |
| 48558 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 48559 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 48560 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 48561 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 48562 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, |
| 48563 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 48564 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 48565 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 48566 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 48567 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 48568 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 48569 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 48570 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 48571 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 48572 | // MIs[3] Operand 1 |
| 48573 | // No operand predicates |
| 48574 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 48575 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 48576 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 48577 | // (intrinsic_wo_chain:{ *:[v2i32] } 493:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, (bitconvert:{ *:[v8i8] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (UDOTlanev8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 48578 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UDOTlanev8i8, |
| 48579 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 48580 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 48581 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 48582 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 48583 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 48584 | GIR_EraseFromParent, /*InsnID*/0, |
| 48585 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48586 | // GIR_Coverage, 25, |
| 48587 | GIR_Done, |
| 48588 | // Label 2605: @124676 |
| 48589 | GIM_Try, /*On fail goto*//*Label 2606*/ 124785, // Rule ID 26 // |
| 48590 | GIM_CheckFeatures, GIFBS_HasDotProd, |
| 48591 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_udot, |
| 48592 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 48593 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 48594 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 48595 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, |
| 48596 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 48597 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 48598 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 48599 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 48600 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, |
| 48601 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 48602 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 48603 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 48604 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 48605 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 48606 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 48607 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 48608 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 48609 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 48610 | // MIs[3] Operand 1 |
| 48611 | // No operand predicates |
| 48612 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 48613 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 48614 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 48615 | // (intrinsic_wo_chain:{ *:[v4i32] } 493:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, (bitconvert:{ *:[v16i8] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (UDOTlanev16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 48616 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UDOTlanev16i8, |
| 48617 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 48618 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 48619 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 48620 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 48621 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 48622 | GIR_EraseFromParent, /*InsnID*/0, |
| 48623 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48624 | // GIR_Coverage, 26, |
| 48625 | GIR_Done, |
| 48626 | // Label 2606: @124785 |
| 48627 | GIM_Try, /*On fail goto*//*Label 2607*/ 124894, // Rule ID 29 // |
| 48628 | GIM_CheckFeatures, GIFBS_HasBF16, |
| 48629 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_bfdot, |
| 48630 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 48631 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 48632 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 48633 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, |
| 48634 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 48635 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 48636 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 48637 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 48638 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, |
| 48639 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 48640 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 48641 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 48642 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 48643 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 48644 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 48645 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 48646 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 48647 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 48648 | // MIs[3] Operand 1 |
| 48649 | // No operand predicates |
| 48650 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 48651 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 48652 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 48653 | // (intrinsic_wo_chain:{ *:[v2f32] } 363:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4bf16] }:$Rn, (bitconvert:{ *:[v4bf16] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (BF16DOTlanev4bf16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4bf16] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 48654 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BF16DOTlanev4bf16, |
| 48655 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 48656 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 48657 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 48658 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 48659 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 48660 | GIR_EraseFromParent, /*InsnID*/0, |
| 48661 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48662 | // GIR_Coverage, 29, |
| 48663 | GIR_Done, |
| 48664 | // Label 2607: @124894 |
| 48665 | GIM_Try, /*On fail goto*//*Label 2608*/ 125003, // Rule ID 30 // |
| 48666 | GIM_CheckFeatures, GIFBS_HasBF16, |
| 48667 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_bfdot, |
| 48668 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 48669 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 48670 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 48671 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
| 48672 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 48673 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 48674 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 48675 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 48676 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, |
| 48677 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 48678 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 48679 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 48680 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 48681 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 48682 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 48683 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 48684 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 48685 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 48686 | // MIs[3] Operand 1 |
| 48687 | // No operand predicates |
| 48688 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 48689 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 48690 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 48691 | // (intrinsic_wo_chain:{ *:[v4f32] } 363:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, (bitconvert:{ *:[v8bf16] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (BF16DOTlanev8bf16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 48692 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BF16DOTlanev8bf16, |
| 48693 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 48694 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 48695 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 48696 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 48697 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 48698 | GIR_EraseFromParent, /*InsnID*/0, |
| 48699 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48700 | // GIR_Coverage, 30, |
| 48701 | GIR_Done, |
| 48702 | // Label 2608: @125003 |
| 48703 | GIM_Try, /*On fail goto*//*Label 2609*/ 125112, // Rule ID 44 // |
| 48704 | GIM_CheckFeatures, GIFBS_HasMatMulInt8, |
| 48705 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usdot, |
| 48706 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 48707 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 48708 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 48709 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, |
| 48710 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 48711 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 48712 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 48713 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 48714 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, |
| 48715 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 48716 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 48717 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 48718 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 48719 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 48720 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 48721 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 48722 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 48723 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 48724 | // MIs[3] Operand 1 |
| 48725 | // No operand predicates |
| 48726 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 48727 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 48728 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 48729 | // (intrinsic_wo_chain:{ *:[v2i32] } 515:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, (bitconvert:{ *:[v8i8] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (USDOTlanev8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 48730 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USDOTlanev8i8, |
| 48731 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 48732 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 48733 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 48734 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 48735 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 48736 | GIR_EraseFromParent, /*InsnID*/0, |
| 48737 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48738 | // GIR_Coverage, 44, |
| 48739 | GIR_Done, |
| 48740 | // Label 2609: @125112 |
| 48741 | GIM_Try, /*On fail goto*//*Label 2610*/ 125221, // Rule ID 45 // |
| 48742 | GIM_CheckFeatures, GIFBS_HasMatMulInt8, |
| 48743 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usdot, |
| 48744 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 48745 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 48746 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 48747 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, |
| 48748 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 48749 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 48750 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 48751 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 48752 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, |
| 48753 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 48754 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 48755 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 48756 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 48757 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 48758 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 48759 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 48760 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 48761 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 48762 | // MIs[3] Operand 1 |
| 48763 | // No operand predicates |
| 48764 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 48765 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 48766 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 48767 | // (intrinsic_wo_chain:{ *:[v4i32] } 515:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, (bitconvert:{ *:[v16i8] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (USDOTlanev16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 48768 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USDOTlanev16i8, |
| 48769 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 48770 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 48771 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 48772 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 48773 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 48774 | GIR_EraseFromParent, /*InsnID*/0, |
| 48775 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48776 | // GIR_Coverage, 45, |
| 48777 | GIR_Done, |
| 48778 | // Label 2610: @125221 |
| 48779 | GIM_Try, /*On fail goto*//*Label 2611*/ 125317, // Rule ID 34 // |
| 48780 | GIM_CheckFeatures, GIFBS_HasBF16, |
| 48781 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_bfmlalb, |
| 48782 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 48783 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 48784 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 48785 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
| 48786 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 48787 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 48788 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 48789 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 48790 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 48791 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 48792 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 48793 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 48794 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 48795 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 48796 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 48797 | // MIs[2] Operand 1 |
| 48798 | // No operand predicates |
| 48799 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 48800 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 48801 | // (intrinsic_wo_chain:{ *:[v4f32] } 364:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, (AArch64duplane16:{ *:[v8bf16] } V128_lo:{ *:[v8bf16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (BFMLALBIdx:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128_lo:{ *:[v8bf16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 48802 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BFMLALBIdx, |
| 48803 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 48804 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 48805 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 48806 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 48807 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 48808 | GIR_EraseFromParent, /*InsnID*/0, |
| 48809 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48810 | // GIR_Coverage, 34, |
| 48811 | GIR_Done, |
| 48812 | // Label 2611: @125317 |
| 48813 | GIM_Try, /*On fail goto*//*Label 2612*/ 125413, // Rule ID 35 // |
| 48814 | GIM_CheckFeatures, GIFBS_HasBF16, |
| 48815 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_bfmlalt, |
| 48816 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 48817 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 48818 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 48819 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
| 48820 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 48821 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 48822 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 48823 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 48824 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 48825 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 48826 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 48827 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 48828 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 48829 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 48830 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 48831 | // MIs[2] Operand 1 |
| 48832 | // No operand predicates |
| 48833 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 48834 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 48835 | // (intrinsic_wo_chain:{ *:[v4f32] } 365:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, (AArch64duplane16:{ *:[v8bf16] } V128_lo:{ *:[v8bf16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (BFMLALTIdx:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128_lo:{ *:[v8bf16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 48836 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BFMLALTIdx, |
| 48837 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 48838 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 48839 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 48840 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 48841 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 48842 | GIR_EraseFromParent, /*InsnID*/0, |
| 48843 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48844 | // GIR_Coverage, 35, |
| 48845 | GIR_Done, |
| 48846 | // Label 2612: @125413 |
| 48847 | GIM_Try, /*On fail goto*//*Label 2613*/ 125509, // Rule ID 56 // |
| 48848 | GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, |
| 48849 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlal, |
| 48850 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 48851 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 48852 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 48853 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, |
| 48854 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 48855 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 48856 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 48857 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 48858 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 48859 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 48860 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 48861 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 48862 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 48863 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 48864 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 48865 | // MIs[2] Operand 1 |
| 48866 | // No operand predicates |
| 48867 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 48868 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 48869 | // (intrinsic_wo_chain:{ *:[v2f32] } 396:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMLALlanev4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 48870 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLALlanev4f16, |
| 48871 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 48872 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 48873 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 48874 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 48875 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 48876 | GIR_EraseFromParent, /*InsnID*/0, |
| 48877 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48878 | // GIR_Coverage, 56, |
| 48879 | GIR_Done, |
| 48880 | // Label 2613: @125509 |
| 48881 | GIM_Try, /*On fail goto*//*Label 2614*/ 125605, // Rule ID 57 // |
| 48882 | GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, |
| 48883 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlal, |
| 48884 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 48885 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 48886 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 48887 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
| 48888 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 48889 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 48890 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 48891 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 48892 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 48893 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 48894 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 48895 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 48896 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 48897 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 48898 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 48899 | // MIs[2] Operand 1 |
| 48900 | // No operand predicates |
| 48901 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 48902 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 48903 | // (intrinsic_wo_chain:{ *:[v4f32] } 396:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMLALlanev8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 48904 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLALlanev8f16, |
| 48905 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 48906 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 48907 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 48908 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 48909 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 48910 | GIR_EraseFromParent, /*InsnID*/0, |
| 48911 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48912 | // GIR_Coverage, 57, |
| 48913 | GIR_Done, |
| 48914 | // Label 2614: @125605 |
| 48915 | GIM_Try, /*On fail goto*//*Label 2615*/ 125701, // Rule ID 58 // |
| 48916 | GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, |
| 48917 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlsl, |
| 48918 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 48919 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 48920 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 48921 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, |
| 48922 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 48923 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 48924 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 48925 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 48926 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 48927 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 48928 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 48929 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 48930 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 48931 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 48932 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 48933 | // MIs[2] Operand 1 |
| 48934 | // No operand predicates |
| 48935 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 48936 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 48937 | // (intrinsic_wo_chain:{ *:[v2f32] } 398:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMLSLlanev4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 48938 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSLlanev4f16, |
| 48939 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 48940 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 48941 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 48942 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 48943 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 48944 | GIR_EraseFromParent, /*InsnID*/0, |
| 48945 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48946 | // GIR_Coverage, 58, |
| 48947 | GIR_Done, |
| 48948 | // Label 2615: @125701 |
| 48949 | GIM_Try, /*On fail goto*//*Label 2616*/ 125797, // Rule ID 59 // |
| 48950 | GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, |
| 48951 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlsl, |
| 48952 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 48953 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 48954 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 48955 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
| 48956 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 48957 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 48958 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 48959 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 48960 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 48961 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 48962 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 48963 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 48964 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 48965 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 48966 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 48967 | // MIs[2] Operand 1 |
| 48968 | // No operand predicates |
| 48969 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 48970 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 48971 | // (intrinsic_wo_chain:{ *:[v4f32] } 398:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMLSLlanev8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 48972 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSLlanev8f16, |
| 48973 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 48974 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 48975 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 48976 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 48977 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 48978 | GIR_EraseFromParent, /*InsnID*/0, |
| 48979 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 48980 | // GIR_Coverage, 59, |
| 48981 | GIR_Done, |
| 48982 | // Label 2616: @125797 |
| 48983 | GIM_Try, /*On fail goto*//*Label 2617*/ 125893, // Rule ID 60 // |
| 48984 | GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, |
| 48985 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlal2, |
| 48986 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 48987 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 48988 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 48989 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, |
| 48990 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 48991 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 48992 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 48993 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 48994 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 48995 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 48996 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 48997 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 48998 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 48999 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 49000 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 49001 | // MIs[2] Operand 1 |
| 49002 | // No operand predicates |
| 49003 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 49004 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 49005 | // (intrinsic_wo_chain:{ *:[v2f32] } 397:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMLAL2lanev4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 49006 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAL2lanev4f16, |
| 49007 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49008 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49009 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49010 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 49011 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 49012 | GIR_EraseFromParent, /*InsnID*/0, |
| 49013 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49014 | // GIR_Coverage, 60, |
| 49015 | GIR_Done, |
| 49016 | // Label 2617: @125893 |
| 49017 | GIM_Try, /*On fail goto*//*Label 2618*/ 125989, // Rule ID 61 // |
| 49018 | GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, |
| 49019 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlal2, |
| 49020 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 49021 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 49022 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 49023 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
| 49024 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49025 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49026 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 49027 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 49028 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 49029 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 49030 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 49031 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 49032 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 49033 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 49034 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 49035 | // MIs[2] Operand 1 |
| 49036 | // No operand predicates |
| 49037 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 49038 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 49039 | // (intrinsic_wo_chain:{ *:[v4f32] } 397:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMLAL2lanev8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 49040 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAL2lanev8f16, |
| 49041 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49042 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49043 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49044 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 49045 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 49046 | GIR_EraseFromParent, /*InsnID*/0, |
| 49047 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49048 | // GIR_Coverage, 61, |
| 49049 | GIR_Done, |
| 49050 | // Label 2618: @125989 |
| 49051 | GIM_Try, /*On fail goto*//*Label 2619*/ 126085, // Rule ID 62 // |
| 49052 | GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, |
| 49053 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlsl2, |
| 49054 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 49055 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 49056 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 49057 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, |
| 49058 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 49059 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 49060 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 49061 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 49062 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 49063 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 49064 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 49065 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 49066 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 49067 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 49068 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 49069 | // MIs[2] Operand 1 |
| 49070 | // No operand predicates |
| 49071 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 49072 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 49073 | // (intrinsic_wo_chain:{ *:[v2f32] } 399:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMLSL2lanev4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 49074 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSL2lanev4f16, |
| 49075 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49076 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49077 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49078 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 49079 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 49080 | GIR_EraseFromParent, /*InsnID*/0, |
| 49081 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49082 | // GIR_Coverage, 62, |
| 49083 | GIR_Done, |
| 49084 | // Label 2619: @126085 |
| 49085 | GIM_Try, /*On fail goto*//*Label 2620*/ 126181, // Rule ID 63 // |
| 49086 | GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, |
| 49087 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlsl2, |
| 49088 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 49089 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 49090 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 49091 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
| 49092 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49093 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49094 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 49095 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 49096 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 49097 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 49098 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 49099 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 49100 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 49101 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 49102 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 49103 | // MIs[2] Operand 1 |
| 49104 | // No operand predicates |
| 49105 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 49106 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 49107 | // (intrinsic_wo_chain:{ *:[v4f32] } 399:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMLSL2lanev8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 49108 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSL2lanev8f16, |
| 49109 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49110 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49111 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49112 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 49113 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 49114 | GIR_EraseFromParent, /*InsnID*/0, |
| 49115 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49116 | // GIR_Coverage, 63, |
| 49117 | GIR_Done, |
| 49118 | // Label 2620: @126181 |
| 49119 | GIM_Try, /*On fail goto*//*Label 2621*/ 126245, // Rule ID 19 // |
| 49120 | GIM_CheckFeatures, GIFBS_HasDotProd, |
| 49121 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sdot, |
| 49122 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 49123 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 49124 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 49125 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, |
| 49126 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 49127 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 49128 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 49129 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, |
| 49130 | // (intrinsic_wo_chain:{ *:[v2i32] } 433:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SDOTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 49131 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SDOTv8i8, |
| 49132 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49133 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49134 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49135 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49136 | GIR_EraseFromParent, /*InsnID*/0, |
| 49137 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49138 | // GIR_Coverage, 19, |
| 49139 | GIR_Done, |
| 49140 | // Label 2621: @126245 |
| 49141 | GIM_Try, /*On fail goto*//*Label 2622*/ 126309, // Rule ID 20 // |
| 49142 | GIM_CheckFeatures, GIFBS_HasDotProd, |
| 49143 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_sdot, |
| 49144 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 49145 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 49146 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 49147 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, |
| 49148 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49149 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49150 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 49151 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 49152 | // (intrinsic_wo_chain:{ *:[v4i32] } 433:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SDOTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 49153 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SDOTv16i8, |
| 49154 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49155 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49156 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49157 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49158 | GIR_EraseFromParent, /*InsnID*/0, |
| 49159 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49160 | // GIR_Coverage, 20, |
| 49161 | GIR_Done, |
| 49162 | // Label 2622: @126309 |
| 49163 | GIM_Try, /*On fail goto*//*Label 2623*/ 126373, // Rule ID 21 // |
| 49164 | GIM_CheckFeatures, GIFBS_HasDotProd, |
| 49165 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_udot, |
| 49166 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 49167 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 49168 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 49169 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, |
| 49170 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 49171 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 49172 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 49173 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, |
| 49174 | // (intrinsic_wo_chain:{ *:[v2i32] } 493:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UDOTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 49175 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UDOTv8i8, |
| 49176 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49177 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49178 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49179 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49180 | GIR_EraseFromParent, /*InsnID*/0, |
| 49181 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49182 | // GIR_Coverage, 21, |
| 49183 | GIR_Done, |
| 49184 | // Label 2623: @126373 |
| 49185 | GIM_Try, /*On fail goto*//*Label 2624*/ 126437, // Rule ID 22 // |
| 49186 | GIM_CheckFeatures, GIFBS_HasDotProd, |
| 49187 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_udot, |
| 49188 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 49189 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 49190 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 49191 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, |
| 49192 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49193 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49194 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 49195 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 49196 | // (intrinsic_wo_chain:{ *:[v4i32] } 493:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UDOTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 49197 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UDOTv16i8, |
| 49198 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49199 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49200 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49201 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49202 | GIR_EraseFromParent, /*InsnID*/0, |
| 49203 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49204 | // GIR_Coverage, 22, |
| 49205 | GIR_Done, |
| 49206 | // Label 2624: @126437 |
| 49207 | GIM_Try, /*On fail goto*//*Label 2625*/ 126501, // Rule ID 27 // |
| 49208 | GIM_CheckFeatures, GIFBS_HasBF16, |
| 49209 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_bfdot, |
| 49210 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 49211 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 49212 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 49213 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, |
| 49214 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 49215 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 49216 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 49217 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, |
| 49218 | // (intrinsic_wo_chain:{ *:[v2f32] } 363:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm) => (BFDOTv4bf16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm) |
| 49219 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BFDOTv4bf16, |
| 49220 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49221 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49222 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49223 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49224 | GIR_EraseFromParent, /*InsnID*/0, |
| 49225 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49226 | // GIR_Coverage, 27, |
| 49227 | GIR_Done, |
| 49228 | // Label 2625: @126501 |
| 49229 | GIM_Try, /*On fail goto*//*Label 2626*/ 126565, // Rule ID 28 // |
| 49230 | GIM_CheckFeatures, GIFBS_HasBF16, |
| 49231 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_bfdot, |
| 49232 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 49233 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 49234 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 49235 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
| 49236 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49237 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49238 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 49239 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 49240 | // (intrinsic_wo_chain:{ *:[v4f32] } 363:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (BFDOTv8bf16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) |
| 49241 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BFDOTv8bf16, |
| 49242 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49243 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49244 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49245 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49246 | GIR_EraseFromParent, /*InsnID*/0, |
| 49247 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49248 | // GIR_Coverage, 28, |
| 49249 | GIR_Done, |
| 49250 | // Label 2626: @126565 |
| 49251 | GIM_Try, /*On fail goto*//*Label 2627*/ 126629, // Rule ID 31 // |
| 49252 | GIM_CheckFeatures, GIFBS_HasBF16, |
| 49253 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_bfmmla, |
| 49254 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 49255 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 49256 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 49257 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
| 49258 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49259 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49260 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 49261 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 49262 | // (intrinsic_wo_chain:{ *:[v4f32] } 366:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (BFMMLA:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) |
| 49263 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BFMMLA, |
| 49264 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49265 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49266 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49267 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49268 | GIR_EraseFromParent, /*InsnID*/0, |
| 49269 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49270 | // GIR_Coverage, 31, |
| 49271 | GIR_Done, |
| 49272 | // Label 2627: @126629 |
| 49273 | GIM_Try, /*On fail goto*//*Label 2628*/ 126693, // Rule ID 32 // |
| 49274 | GIM_CheckFeatures, GIFBS_HasBF16, |
| 49275 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_bfmlalb, |
| 49276 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 49277 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 49278 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 49279 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
| 49280 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49281 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49282 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 49283 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 49284 | // (intrinsic_wo_chain:{ *:[v4f32] } 364:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (BFMLALB:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) |
| 49285 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BFMLALB, |
| 49286 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49287 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49288 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49289 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49290 | GIR_EraseFromParent, /*InsnID*/0, |
| 49291 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49292 | // GIR_Coverage, 32, |
| 49293 | GIR_Done, |
| 49294 | // Label 2628: @126693 |
| 49295 | GIM_Try, /*On fail goto*//*Label 2629*/ 126757, // Rule ID 33 // |
| 49296 | GIM_CheckFeatures, GIFBS_HasBF16, |
| 49297 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_bfmlalt, |
| 49298 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 49299 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 49300 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 49301 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
| 49302 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49303 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49304 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 49305 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 49306 | // (intrinsic_wo_chain:{ *:[v4f32] } 365:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (BFMLALT:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) |
| 49307 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::BFMLALT, |
| 49308 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49309 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49310 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49311 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49312 | GIR_EraseFromParent, /*InsnID*/0, |
| 49313 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49314 | // GIR_Coverage, 33, |
| 49315 | GIR_Done, |
| 49316 | // Label 2629: @126757 |
| 49317 | GIM_Try, /*On fail goto*//*Label 2630*/ 126821, // Rule ID 39 // |
| 49318 | GIM_CheckFeatures, GIFBS_HasMatMulInt8, |
| 49319 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_smmla, |
| 49320 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 49321 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 49322 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 49323 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, |
| 49324 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49325 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49326 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 49327 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 49328 | // (intrinsic_wo_chain:{ *:[v4i32] } 443:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SMMLA:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 49329 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMMLA, |
| 49330 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49331 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49332 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49333 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49334 | GIR_EraseFromParent, /*InsnID*/0, |
| 49335 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49336 | // GIR_Coverage, 39, |
| 49337 | GIR_Done, |
| 49338 | // Label 2630: @126821 |
| 49339 | GIM_Try, /*On fail goto*//*Label 2631*/ 126885, // Rule ID 40 // |
| 49340 | GIM_CheckFeatures, GIFBS_HasMatMulInt8, |
| 49341 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_ummla, |
| 49342 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 49343 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 49344 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 49345 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, |
| 49346 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49347 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49348 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 49349 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 49350 | // (intrinsic_wo_chain:{ *:[v4i32] } 502:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UMMLA:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 49351 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMMLA, |
| 49352 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49353 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49354 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49355 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49356 | GIR_EraseFromParent, /*InsnID*/0, |
| 49357 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49358 | // GIR_Coverage, 40, |
| 49359 | GIR_Done, |
| 49360 | // Label 2631: @126885 |
| 49361 | GIM_Try, /*On fail goto*//*Label 2632*/ 126949, // Rule ID 41 // |
| 49362 | GIM_CheckFeatures, GIFBS_HasMatMulInt8, |
| 49363 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usmmla, |
| 49364 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 49365 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 49366 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 49367 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, |
| 49368 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49369 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49370 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 49371 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 49372 | // (intrinsic_wo_chain:{ *:[v4i32] } 518:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (USMMLA:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 49373 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USMMLA, |
| 49374 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49375 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49376 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49377 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49378 | GIR_EraseFromParent, /*InsnID*/0, |
| 49379 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49380 | // GIR_Coverage, 41, |
| 49381 | GIR_Done, |
| 49382 | // Label 2632: @126949 |
| 49383 | GIM_Try, /*On fail goto*//*Label 2633*/ 127013, // Rule ID 42 // |
| 49384 | GIM_CheckFeatures, GIFBS_HasMatMulInt8, |
| 49385 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usdot, |
| 49386 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 49387 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 49388 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, |
| 49389 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, |
| 49390 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 49391 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 49392 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 49393 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, |
| 49394 | // (intrinsic_wo_chain:{ *:[v2i32] } 515:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (USDOTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 49395 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USDOTv8i8, |
| 49396 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49397 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49398 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49399 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49400 | GIR_EraseFromParent, /*InsnID*/0, |
| 49401 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49402 | // GIR_Coverage, 42, |
| 49403 | GIR_Done, |
| 49404 | // Label 2633: @127013 |
| 49405 | GIM_Try, /*On fail goto*//*Label 2634*/ 127077, // Rule ID 43 // |
| 49406 | GIM_CheckFeatures, GIFBS_HasMatMulInt8, |
| 49407 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_usdot, |
| 49408 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 49409 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 49410 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 49411 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, |
| 49412 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49413 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49414 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 49415 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 49416 | // (intrinsic_wo_chain:{ *:[v4i32] } 515:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (USDOTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 49417 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USDOTv16i8, |
| 49418 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49419 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49420 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49421 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49422 | GIR_EraseFromParent, /*InsnID*/0, |
| 49423 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49424 | // GIR_Coverage, 43, |
| 49425 | GIR_Done, |
| 49426 | // Label 2634: @127077 |
| 49427 | GIM_Try, /*On fail goto*//*Label 2635*/ 127141, // Rule ID 48 // |
| 49428 | GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, |
| 49429 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlal, |
| 49430 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 49431 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 49432 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 49433 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, |
| 49434 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 49435 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 49436 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 49437 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, |
| 49438 | // (intrinsic_wo_chain:{ *:[v2f32] } 396:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMLALv4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 49439 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLALv4f16, |
| 49440 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49441 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49442 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49443 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49444 | GIR_EraseFromParent, /*InsnID*/0, |
| 49445 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49446 | // GIR_Coverage, 48, |
| 49447 | GIR_Done, |
| 49448 | // Label 2635: @127141 |
| 49449 | GIM_Try, /*On fail goto*//*Label 2636*/ 127205, // Rule ID 49 // |
| 49450 | GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, |
| 49451 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlal, |
| 49452 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 49453 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 49454 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 49455 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
| 49456 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49457 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49458 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 49459 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 49460 | // (intrinsic_wo_chain:{ *:[v4f32] } 396:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMLALv8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 49461 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLALv8f16, |
| 49462 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49463 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49464 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49465 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49466 | GIR_EraseFromParent, /*InsnID*/0, |
| 49467 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49468 | // GIR_Coverage, 49, |
| 49469 | GIR_Done, |
| 49470 | // Label 2636: @127205 |
| 49471 | GIM_Try, /*On fail goto*//*Label 2637*/ 127269, // Rule ID 50 // |
| 49472 | GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, |
| 49473 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlsl, |
| 49474 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 49475 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 49476 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 49477 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, |
| 49478 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 49479 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 49480 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 49481 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, |
| 49482 | // (intrinsic_wo_chain:{ *:[v2f32] } 398:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMLSLv4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 49483 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSLv4f16, |
| 49484 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49485 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49486 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49487 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49488 | GIR_EraseFromParent, /*InsnID*/0, |
| 49489 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49490 | // GIR_Coverage, 50, |
| 49491 | GIR_Done, |
| 49492 | // Label 2637: @127269 |
| 49493 | GIM_Try, /*On fail goto*//*Label 2638*/ 127333, // Rule ID 51 // |
| 49494 | GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, |
| 49495 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlsl, |
| 49496 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 49497 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 49498 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 49499 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
| 49500 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49501 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49502 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 49503 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 49504 | // (intrinsic_wo_chain:{ *:[v4f32] } 398:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMLSLv8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 49505 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSLv8f16, |
| 49506 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49507 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49508 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49509 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49510 | GIR_EraseFromParent, /*InsnID*/0, |
| 49511 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49512 | // GIR_Coverage, 51, |
| 49513 | GIR_Done, |
| 49514 | // Label 2638: @127333 |
| 49515 | GIM_Try, /*On fail goto*//*Label 2639*/ 127397, // Rule ID 52 // |
| 49516 | GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, |
| 49517 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlal2, |
| 49518 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 49519 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 49520 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 49521 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, |
| 49522 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 49523 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 49524 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 49525 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, |
| 49526 | // (intrinsic_wo_chain:{ *:[v2f32] } 397:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMLAL2v4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 49527 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAL2v4f16, |
| 49528 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49529 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49530 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49531 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49532 | GIR_EraseFromParent, /*InsnID*/0, |
| 49533 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49534 | // GIR_Coverage, 52, |
| 49535 | GIR_Done, |
| 49536 | // Label 2639: @127397 |
| 49537 | GIM_Try, /*On fail goto*//*Label 2640*/ 127461, // Rule ID 53 // |
| 49538 | GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, |
| 49539 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlal2, |
| 49540 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 49541 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 49542 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 49543 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
| 49544 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49545 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49546 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 49547 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 49548 | // (intrinsic_wo_chain:{ *:[v4f32] } 397:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMLAL2v8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 49549 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAL2v8f16, |
| 49550 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49551 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49552 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49553 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49554 | GIR_EraseFromParent, /*InsnID*/0, |
| 49555 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49556 | // GIR_Coverage, 53, |
| 49557 | GIR_Done, |
| 49558 | // Label 2640: @127461 |
| 49559 | GIM_Try, /*On fail goto*//*Label 2641*/ 127525, // Rule ID 54 // |
| 49560 | GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, |
| 49561 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlsl2, |
| 49562 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, |
| 49563 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 49564 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 49565 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, |
| 49566 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 49567 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 49568 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 49569 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, |
| 49570 | // (intrinsic_wo_chain:{ *:[v2f32] } 399:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMLSL2v4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 49571 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSL2v4f16, |
| 49572 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49573 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49574 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49575 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49576 | GIR_EraseFromParent, /*InsnID*/0, |
| 49577 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49578 | // GIR_Coverage, 54, |
| 49579 | GIR_Done, |
| 49580 | // Label 2641: @127525 |
| 49581 | GIM_Try, /*On fail goto*//*Label 2642*/ 127589, // Rule ID 55 // |
| 49582 | GIM_CheckFeatures, GIFBS_HasFP16FML_HasNEON, |
| 49583 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_fmlsl2, |
| 49584 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 49585 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 49586 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 49587 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
| 49588 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49589 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49590 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 49591 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 49592 | // (intrinsic_wo_chain:{ *:[v4f32] } 399:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMLSL2v8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 49593 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSL2v8f16, |
| 49594 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49595 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49596 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49597 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49598 | GIR_EraseFromParent, /*InsnID*/0, |
| 49599 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49600 | // GIR_Coverage, 55, |
| 49601 | GIR_Done, |
| 49602 | // Label 2642: @127589 |
| 49603 | GIM_Try, /*On fail goto*//*Label 2643*/ 127653, // Rule ID 1945 // |
| 49604 | GIM_CheckFeatures, GIFBS_HasSHA2, |
| 49605 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha1c, |
| 49606 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 49607 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 49608 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 49609 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
| 49610 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49611 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49612 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 49613 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 49614 | // (intrinsic_wo_chain:{ *:[v4i32] } 332:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA1Crrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 49615 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1Crrr, |
| 49616 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49617 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49618 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49619 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49620 | GIR_EraseFromParent, /*InsnID*/0, |
| 49621 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49622 | // GIR_Coverage, 1945, |
| 49623 | GIR_Done, |
| 49624 | // Label 2643: @127653 |
| 49625 | GIM_Try, /*On fail goto*//*Label 2644*/ 127717, // Rule ID 1946 // |
| 49626 | GIM_CheckFeatures, GIFBS_HasSHA2, |
| 49627 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha1p, |
| 49628 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 49629 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 49630 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 49631 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
| 49632 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49633 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49634 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 49635 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 49636 | // (intrinsic_wo_chain:{ *:[v4i32] } 335:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA1Prrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 49637 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1Prrr, |
| 49638 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49639 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49640 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49641 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49642 | GIR_EraseFromParent, /*InsnID*/0, |
| 49643 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49644 | // GIR_Coverage, 1946, |
| 49645 | GIR_Done, |
| 49646 | // Label 2644: @127717 |
| 49647 | GIM_Try, /*On fail goto*//*Label 2645*/ 127781, // Rule ID 1947 // |
| 49648 | GIM_CheckFeatures, GIFBS_HasSHA2, |
| 49649 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha1m, |
| 49650 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 49651 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 49652 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 49653 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
| 49654 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49655 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49656 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 49657 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 49658 | // (intrinsic_wo_chain:{ *:[v4i32] } 334:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA1Mrrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 49659 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1Mrrr, |
| 49660 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49661 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49662 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49663 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49664 | GIR_EraseFromParent, /*InsnID*/0, |
| 49665 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49666 | // GIR_Coverage, 1947, |
| 49667 | GIR_Done, |
| 49668 | // Label 2645: @127781 |
| 49669 | GIM_Try, /*On fail goto*//*Label 2646*/ 127845, // Rule ID 1948 // |
| 49670 | GIM_CheckFeatures, GIFBS_HasSHA2, |
| 49671 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha1su0, |
| 49672 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 49673 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 49674 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 49675 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
| 49676 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49677 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49678 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 49679 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 49680 | // (intrinsic_wo_chain:{ *:[v4i32] } 336:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA1SU0rrr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 49681 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA1SU0rrr, |
| 49682 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49683 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49684 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49685 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49686 | GIR_EraseFromParent, /*InsnID*/0, |
| 49687 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49688 | // GIR_Coverage, 1948, |
| 49689 | GIR_Done, |
| 49690 | // Label 2646: @127845 |
| 49691 | GIM_Try, /*On fail goto*//*Label 2647*/ 127909, // Rule ID 1949 // |
| 49692 | GIM_CheckFeatures, GIFBS_HasSHA2, |
| 49693 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha256h, |
| 49694 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 49695 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 49696 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 49697 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
| 49698 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49699 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49700 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 49701 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 49702 | // (intrinsic_wo_chain:{ *:[v4i32] } 338:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA256Hrrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 49703 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA256Hrrr, |
| 49704 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49705 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49706 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49707 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49708 | GIR_EraseFromParent, /*InsnID*/0, |
| 49709 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49710 | // GIR_Coverage, 1949, |
| 49711 | GIR_Done, |
| 49712 | // Label 2647: @127909 |
| 49713 | GIM_Try, /*On fail goto*//*Label 2648*/ 127973, // Rule ID 1950 // |
| 49714 | GIM_CheckFeatures, GIFBS_HasSHA2, |
| 49715 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha256h2, |
| 49716 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 49717 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 49718 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 49719 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
| 49720 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49721 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49722 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 49723 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 49724 | // (intrinsic_wo_chain:{ *:[v4i32] } 339:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA256H2rrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 49725 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA256H2rrr, |
| 49726 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49727 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49728 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49729 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49730 | GIR_EraseFromParent, /*InsnID*/0, |
| 49731 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49732 | // GIR_Coverage, 1950, |
| 49733 | GIR_Done, |
| 49734 | // Label 2648: @127973 |
| 49735 | GIM_Try, /*On fail goto*//*Label 2649*/ 128037, // Rule ID 1951 // |
| 49736 | GIM_CheckFeatures, GIFBS_HasSHA2, |
| 49737 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_crypto_sha256su1, |
| 49738 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 49739 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 49740 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 49741 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
| 49742 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49743 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49744 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 49745 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 49746 | // (intrinsic_wo_chain:{ *:[v4i32] } 341:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA256SU1rrr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 49747 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHA256SU1rrr, |
| 49748 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49749 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49750 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49751 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rm |
| 49752 | GIR_EraseFromParent, /*InsnID*/0, |
| 49753 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49754 | // GIR_Coverage, 1951, |
| 49755 | GIR_Done, |
| 49756 | // Label 2649: @128037 |
| 49757 | GIM_Try, /*On fail goto*//*Label 2650*/ 128099, // Rule ID 4335 // |
| 49758 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_tbx1, |
| 49759 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, |
| 49760 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 49761 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 49762 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, |
| 49763 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 49764 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 49765 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 49766 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR64RegClassID, |
| 49767 | // (intrinsic_wo_chain:{ *:[v8i8] } 485:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri) => (TBXv8i8One:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri) |
| 49768 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TBXv8i8One, |
| 49769 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49770 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49771 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 49772 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ri |
| 49773 | GIR_EraseFromParent, /*InsnID*/0, |
| 49774 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49775 | // GIR_Coverage, 4335, |
| 49776 | GIR_Done, |
| 49777 | // Label 2650: @128099 |
| 49778 | GIM_Try, /*On fail goto*//*Label 2651*/ 128161, // Rule ID 4336 // |
| 49779 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_tbx1, |
| 49780 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 49781 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 49782 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 49783 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, |
| 49784 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49785 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49786 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 49787 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 49788 | // (intrinsic_wo_chain:{ *:[v16i8] } 485:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn) => (TBXv16i8One:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn) |
| 49789 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TBXv16i8One, |
| 49790 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49791 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rd |
| 49792 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ri |
| 49793 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rn |
| 49794 | GIR_EraseFromParent, /*InsnID*/0, |
| 49795 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49796 | // GIR_Coverage, 4336, |
| 49797 | GIR_Done, |
| 49798 | // Label 2651: @128161 |
| 49799 | GIM_Reject, |
| 49800 | // Label 2600: @128162 |
| 49801 | GIM_Try, /*On fail goto*//*Label 2652*/ 128508, |
| 49802 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/6, |
| 49803 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_neon_vcopy_lane, |
| 49804 | GIM_Try, /*On fail goto*//*Label 2653*/ 128255, // Rule ID 4433 // |
| 49805 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 49806 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 49807 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 49808 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, |
| 49809 | GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64, |
| 49810 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49811 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49812 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 49813 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 49814 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexB, |
| 49815 | // MIs[1] Operand 1 |
| 49816 | // No operand predicates |
| 49817 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 49818 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] |
| 49819 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 49820 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexB, |
| 49821 | // MIs[2] Operand 1 |
| 49822 | // No operand predicates |
| 49823 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 49824 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 49825 | // (intrinsic_wo_chain:{ *:[v16i8] } 526:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, V128:{ *:[v16i8] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx2) => (INSvi8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, V128:{ *:[v16i8] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx2) |
| 49826 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi8lane, |
| 49827 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49828 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd |
| 49829 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx |
| 49830 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vs |
| 49831 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2 |
| 49832 | GIR_EraseFromParent, /*InsnID*/0, |
| 49833 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49834 | // GIR_Coverage, 4433, |
| 49835 | GIR_Done, |
| 49836 | // Label 2653: @128255 |
| 49837 | GIM_Try, /*On fail goto*//*Label 2654*/ 128339, // Rule ID 4434 // |
| 49838 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 49839 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 49840 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 49841 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
| 49842 | GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64, |
| 49843 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49844 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49845 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 49846 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 49847 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 49848 | // MIs[1] Operand 1 |
| 49849 | // No operand predicates |
| 49850 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 49851 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] |
| 49852 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 49853 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 49854 | // MIs[2] Operand 1 |
| 49855 | // No operand predicates |
| 49856 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 49857 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 49858 | // (intrinsic_wo_chain:{ *:[v8i16] } 526:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, V128:{ *:[v8i16] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx2) => (INSvi16lane:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, V128:{ *:[v8i16] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx2) |
| 49859 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi16lane, |
| 49860 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49861 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd |
| 49862 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx |
| 49863 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vs |
| 49864 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2 |
| 49865 | GIR_EraseFromParent, /*InsnID*/0, |
| 49866 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49867 | // GIR_Coverage, 4434, |
| 49868 | GIR_Done, |
| 49869 | // Label 2654: @128339 |
| 49870 | GIM_Try, /*On fail goto*//*Label 2655*/ 128423, // Rule ID 4435 // |
| 49871 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 49872 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 49873 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 49874 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
| 49875 | GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64, |
| 49876 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49877 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49878 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 49879 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 49880 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 49881 | // MIs[1] Operand 1 |
| 49882 | // No operand predicates |
| 49883 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 49884 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] |
| 49885 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 49886 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 49887 | // MIs[2] Operand 1 |
| 49888 | // No operand predicates |
| 49889 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 49890 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 49891 | // (intrinsic_wo_chain:{ *:[v4i32] } 526:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, V128:{ *:[v4i32] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx2) => (INSvi32lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, V128:{ *:[v4i32] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx2) |
| 49892 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi32lane, |
| 49893 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49894 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd |
| 49895 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx |
| 49896 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vs |
| 49897 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2 |
| 49898 | GIR_EraseFromParent, /*InsnID*/0, |
| 49899 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49900 | // GIR_Coverage, 4435, |
| 49901 | GIR_Done, |
| 49902 | // Label 2655: @128423 |
| 49903 | GIM_Try, /*On fail goto*//*Label 2656*/ 128507, // Rule ID 4436 // |
| 49904 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 49905 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 49906 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 49907 | GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, |
| 49908 | GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64, |
| 49909 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 49910 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 49911 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 49912 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 49913 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 49914 | // MIs[1] Operand 1 |
| 49915 | // No operand predicates |
| 49916 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/AArch64::FPR128RegClassID, |
| 49917 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] |
| 49918 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 49919 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 49920 | // MIs[2] Operand 1 |
| 49921 | // No operand predicates |
| 49922 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 49923 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 49924 | // (intrinsic_wo_chain:{ *:[v2i64] } 526:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, V128:{ *:[v2i64] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx2) => (INSvi64lane:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, V128:{ *:[v2i64] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx2) |
| 49925 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::INSvi64lane, |
| 49926 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 49927 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd |
| 49928 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx |
| 49929 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vs |
| 49930 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2 |
| 49931 | GIR_EraseFromParent, /*InsnID*/0, |
| 49932 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49933 | // GIR_Coverage, 4436, |
| 49934 | GIR_Done, |
| 49935 | // Label 2656: @128507 |
| 49936 | GIM_Reject, |
| 49937 | // Label 2652: @128508 |
| 49938 | GIM_Reject, |
| 49939 | // Label 31: @128509 |
| 49940 | GIM_Try, /*On fail goto*//*Label 2657*/ 128576, |
| 49941 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/1, |
| 49942 | GIM_Try, /*On fail goto*//*Label 2658*/ 128534, // Rule ID 69 // |
| 49943 | GIM_CheckFeatures, GIFBS_HasTME, |
| 49944 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_tcommit, |
| 49945 | // (intrinsic_void 1157:{ *:[iPTR] }) => (TCOMMIT) |
| 49946 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TCOMMIT, |
| 49947 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 49948 | GIR_EraseFromParent, /*InsnID*/0, |
| 49949 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49950 | // GIR_Coverage, 69, |
| 49951 | GIR_Done, |
| 49952 | // Label 2658: @128534 |
| 49953 | GIM_Try, /*On fail goto*//*Label 2659*/ 128554, // Rule ID 1958 // |
| 49954 | GIM_CheckFeatures, GIFBS_HasSVE, |
| 49955 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_sve_setffr, |
| 49956 | // (intrinsic_void 864:{ *:[iPTR] }) => (SETFFR) |
| 49957 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SETFFR, |
| 49958 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 49959 | GIR_EraseFromParent, /*InsnID*/0, |
| 49960 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49961 | // GIR_Coverage, 1958, |
| 49962 | GIR_Done, |
| 49963 | // Label 2659: @128554 |
| 49964 | GIM_Try, /*On fail goto*//*Label 2660*/ 128575, // Rule ID 5442 // |
| 49965 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_clrex, |
| 49966 | // (intrinsic_void 317:{ *:[iPTR] }) => (CLREX 15:{ *:[i64] }) |
| 49967 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLREX, |
| 49968 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 49969 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 49970 | GIR_EraseFromParent, /*InsnID*/0, |
| 49971 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49972 | // GIR_Coverage, 5442, |
| 49973 | GIR_Done, |
| 49974 | // Label 2660: @128575 |
| 49975 | GIM_Reject, |
| 49976 | // Label 2657: @128576 |
| 49977 | GIM_Try, /*On fail goto*//*Label 2661*/ 128850, |
| 49978 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, |
| 49979 | GIM_Try, /*On fail goto*//*Label 2662*/ 128619, // Rule ID 15 // |
| 49980 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_hint, |
| 49981 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 49982 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 49983 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 49984 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_127, |
| 49985 | // MIs[1] Operand 1 |
| 49986 | // No operand predicates |
| 49987 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 49988 | // (intrinsic_void 347:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_127>>:$imm) => (HINT (imm:{ *:[i32] }):$imm) |
| 49989 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::HINT, |
| 49990 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 49991 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 49992 | GIR_EraseFromParent, /*InsnID*/0, |
| 49993 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 49994 | // GIR_Coverage, 15, |
| 49995 | GIR_Done, |
| 49996 | // Label 2662: @128619 |
| 49997 | GIM_Try, /*On fail goto*//*Label 2663*/ 128657, // Rule ID 16 // |
| 49998 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_dmb, |
| 49999 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 50000 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 50001 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 50002 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm32_0_15, |
| 50003 | // MIs[1] Operand 1 |
| 50004 | // No operand predicates |
| 50005 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 50006 | // (intrinsic_void 342:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$CRm) => (DMB (imm:{ *:[i32] }):$CRm) |
| 50007 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DMB, |
| 50008 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm |
| 50009 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 50010 | GIR_EraseFromParent, /*InsnID*/0, |
| 50011 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50012 | // GIR_Coverage, 16, |
| 50013 | GIR_Done, |
| 50014 | // Label 2663: @128657 |
| 50015 | GIM_Try, /*On fail goto*//*Label 2664*/ 128695, // Rule ID 17 // |
| 50016 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_dsb, |
| 50017 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 50018 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 50019 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 50020 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm32_0_15, |
| 50021 | // MIs[1] Operand 1 |
| 50022 | // No operand predicates |
| 50023 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 50024 | // (intrinsic_void 343:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$CRm) => (DSB (imm:{ *:[i32] }):$CRm) |
| 50025 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DSB, |
| 50026 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm |
| 50027 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 50028 | GIR_EraseFromParent, /*InsnID*/0, |
| 50029 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50030 | // GIR_Coverage, 17, |
| 50031 | GIR_Done, |
| 50032 | // Label 2664: @128695 |
| 50033 | GIM_Try, /*On fail goto*//*Label 2665*/ 128733, // Rule ID 18 // |
| 50034 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_isb, |
| 50035 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 50036 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 50037 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 50038 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm32_0_15, |
| 50039 | // MIs[1] Operand 1 |
| 50040 | // No operand predicates |
| 50041 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 50042 | // (intrinsic_void 350:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$CRm) => (ISB (imm:{ *:[i32] }):$CRm) |
| 50043 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ISB, |
| 50044 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm |
| 50045 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 50046 | GIR_EraseFromParent, /*InsnID*/0, |
| 50047 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50048 | // GIR_Coverage, 18, |
| 50049 | GIR_Done, |
| 50050 | // Label 2665: @128733 |
| 50051 | GIM_Try, /*On fail goto*//*Label 2666*/ 128760, // Rule ID 70 // |
| 50052 | GIM_CheckFeatures, GIFBS_HasTME, |
| 50053 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::aarch64_tcancel, |
| 50054 | // MIs[0] imm |
| 50055 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 50056 | // (intrinsic_void 1156:{ *:[iPTR] }, (timm:{ *:[i64] })<<P:Predicate_i64_imm0_65535>>:$imm) => (TCANCEL (timm:{ *:[i64] }):$imm) |
| 50057 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TCANCEL, |
| 50058 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // imm |
| 50059 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 50060 | GIR_EraseFromParent, /*InsnID*/0, |
| 50061 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50062 | // GIR_Coverage, 70, |
| 50063 | GIR_Done, |
| 50064 | // Label 2666: @128760 |
| 50065 | GIM_Try, /*On fail goto*//*Label 2667*/ 128792, // Rule ID 68 // |
| 50066 | GIM_CheckFeatures, GIFBS_HasTME, |
| 50067 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_tstart, |
| 50068 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 50069 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 50070 | // (intrinsic_w_chain:{ *:[i64] } 1158:{ *:[iPTR] }) => (TSTART:{ *:[i64] }) |
| 50071 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TSTART, |
| 50072 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 50073 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 50074 | GIR_EraseFromParent, /*InsnID*/0, |
| 50075 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50076 | // GIR_Coverage, 68, |
| 50077 | GIR_Done, |
| 50078 | // Label 2667: @128792 |
| 50079 | GIM_Try, /*On fail goto*//*Label 2668*/ 128820, // Rule ID 71 // |
| 50080 | GIM_CheckFeatures, GIFBS_HasTME, |
| 50081 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ttest, |
| 50082 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 50083 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 50084 | // (intrinsic_w_chain:{ *:[i64] } 1159:{ *:[iPTR] }) => (TTEST:{ *:[i64] }) |
| 50085 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::TTEST, |
| 50086 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 50087 | GIR_EraseFromParent, /*InsnID*/0, |
| 50088 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50089 | // GIR_Coverage, 71, |
| 50090 | GIR_Done, |
| 50091 | // Label 2668: @128820 |
| 50092 | GIM_Try, /*On fail goto*//*Label 2669*/ 128849, // Rule ID 3451 // |
| 50093 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_get_fpcr, |
| 50094 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 50095 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 50096 | // (intrinsic_w_chain:{ *:[i64] } 345:{ *:[iPTR] }) => (MRS:{ *:[i64] } 55840:{ *:[i32] }) |
| 50097 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MRS, |
| 50098 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 50099 | GIR_AddImm, /*InsnID*/0, /*Imm*/55840, |
| 50100 | GIR_EraseFromParent, /*InsnID*/0, |
| 50101 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50102 | // GIR_Coverage, 3451, |
| 50103 | GIR_Done, |
| 50104 | // Label 2669: @128849 |
| 50105 | GIM_Reject, |
| 50106 | // Label 2661: @128850 |
| 50107 | GIM_Try, /*On fail goto*//*Label 2670*/ 129424, |
| 50108 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 50109 | GIM_Try, /*On fail goto*//*Label 2671*/ 128928, // Rule ID 5408 // |
| 50110 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ldxr, |
| 50111 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 50112 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 50113 | // MIs[0] addr |
| 50114 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, |
| 50115 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, |
| 50116 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_ldxr_1, |
| 50117 | // (intrinsic_w_chain:{ *:[i64] } 356:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_1>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) |
| 50118 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50119 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDXRB, |
| 50120 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 50121 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr |
| 50122 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 50123 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50124 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 50125 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 50126 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 50127 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 50128 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 50129 | GIR_EraseFromParent, /*InsnID*/0, |
| 50130 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 50131 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 50132 | // GIR_Coverage, 5408, |
| 50133 | GIR_Done, |
| 50134 | // Label 2671: @128928 |
| 50135 | GIM_Try, /*On fail goto*//*Label 2672*/ 129001, // Rule ID 5409 // |
| 50136 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ldxr, |
| 50137 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 50138 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 50139 | // MIs[0] addr |
| 50140 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, |
| 50141 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, |
| 50142 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_ldxr_2, |
| 50143 | // (intrinsic_w_chain:{ *:[i64] } 356:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_2>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) |
| 50144 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50145 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDXRH, |
| 50146 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 50147 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr |
| 50148 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 50149 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50150 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 50151 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 50152 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 50153 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 50154 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 50155 | GIR_EraseFromParent, /*InsnID*/0, |
| 50156 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 50157 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 50158 | // GIR_Coverage, 5409, |
| 50159 | GIR_Done, |
| 50160 | // Label 2672: @129001 |
| 50161 | GIM_Try, /*On fail goto*//*Label 2673*/ 129074, // Rule ID 5410 // |
| 50162 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ldxr, |
| 50163 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 50164 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 50165 | // MIs[0] addr |
| 50166 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, |
| 50167 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, |
| 50168 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_ldxr_4, |
| 50169 | // (intrinsic_w_chain:{ *:[i64] } 356:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_4>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) |
| 50170 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50171 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDXRW, |
| 50172 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 50173 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr |
| 50174 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 50175 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50176 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 50177 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 50178 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 50179 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 50180 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 50181 | GIR_EraseFromParent, /*InsnID*/0, |
| 50182 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 50183 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 50184 | // GIR_Coverage, 5410, |
| 50185 | GIR_Done, |
| 50186 | // Label 2673: @129074 |
| 50187 | GIM_Try, /*On fail goto*//*Label 2674*/ 129119, // Rule ID 5411 // |
| 50188 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ldxr, |
| 50189 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 50190 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 50191 | // MIs[0] addr |
| 50192 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, |
| 50193 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, |
| 50194 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_ldxr_8, |
| 50195 | // (intrinsic_w_chain:{ *:[i64] } 356:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_8>> => (LDXRX:{ *:[i64] } GPR64sp:{ *:[i64] }:$addr) |
| 50196 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDXRX, |
| 50197 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 50198 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr |
| 50199 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 50200 | GIR_EraseFromParent, /*InsnID*/0, |
| 50201 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50202 | // GIR_Coverage, 5411, |
| 50203 | GIR_Done, |
| 50204 | // Label 2674: @129119 |
| 50205 | GIM_Try, /*On fail goto*//*Label 2675*/ 129192, // Rule ID 5415 // |
| 50206 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ldaxr, |
| 50207 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 50208 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 50209 | // MIs[0] addr |
| 50210 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, |
| 50211 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, |
| 50212 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_ldaxr_1, |
| 50213 | // (intrinsic_w_chain:{ *:[i64] } 353:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_1>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) |
| 50214 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50215 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDAXRB, |
| 50216 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 50217 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr |
| 50218 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 50219 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50220 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 50221 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 50222 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 50223 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 50224 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 50225 | GIR_EraseFromParent, /*InsnID*/0, |
| 50226 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 50227 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 50228 | // GIR_Coverage, 5415, |
| 50229 | GIR_Done, |
| 50230 | // Label 2675: @129192 |
| 50231 | GIM_Try, /*On fail goto*//*Label 2676*/ 129265, // Rule ID 5416 // |
| 50232 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ldaxr, |
| 50233 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 50234 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 50235 | // MIs[0] addr |
| 50236 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, |
| 50237 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, |
| 50238 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_ldaxr_2, |
| 50239 | // (intrinsic_w_chain:{ *:[i64] } 353:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_2>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) |
| 50240 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50241 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDAXRH, |
| 50242 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 50243 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr |
| 50244 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 50245 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50246 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 50247 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 50248 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 50249 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 50250 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 50251 | GIR_EraseFromParent, /*InsnID*/0, |
| 50252 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 50253 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 50254 | // GIR_Coverage, 5416, |
| 50255 | GIR_Done, |
| 50256 | // Label 2676: @129265 |
| 50257 | GIM_Try, /*On fail goto*//*Label 2677*/ 129338, // Rule ID 5417 // |
| 50258 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ldaxr, |
| 50259 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 50260 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 50261 | // MIs[0] addr |
| 50262 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, |
| 50263 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, |
| 50264 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_ldaxr_4, |
| 50265 | // (intrinsic_w_chain:{ *:[i64] } 353:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_4>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] }) |
| 50266 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50267 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::LDAXRW, |
| 50268 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 50269 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr |
| 50270 | GIR_MergeMemOperands, /*InsnID*/1, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 50271 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 50272 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 50273 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 50274 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 50275 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 50276 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 50277 | GIR_EraseFromParent, /*InsnID*/0, |
| 50278 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 50279 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 50280 | // GIR_Coverage, 5417, |
| 50281 | GIR_Done, |
| 50282 | // Label 2677: @129338 |
| 50283 | GIM_Try, /*On fail goto*//*Label 2678*/ 129383, // Rule ID 5418 // |
| 50284 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_ldaxr, |
| 50285 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 50286 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 50287 | // MIs[0] addr |
| 50288 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, |
| 50289 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, |
| 50290 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_ldaxr_8, |
| 50291 | // (intrinsic_w_chain:{ *:[i64] } 353:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_8>> => (LDAXRX:{ *:[i64] } GPR64sp:{ *:[i64] }:$addr) |
| 50292 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LDAXRX, |
| 50293 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt |
| 50294 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr |
| 50295 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 50296 | GIR_EraseFromParent, /*InsnID*/0, |
| 50297 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50298 | // GIR_Coverage, 5418, |
| 50299 | GIR_Done, |
| 50300 | // Label 2678: @129383 |
| 50301 | GIM_Try, /*On fail goto*//*Label 2679*/ 129423, // Rule ID 3531 // |
| 50302 | GIM_CheckFeatures, GIFBS_HasMTE, |
| 50303 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_irg_sp, |
| 50304 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 50305 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 50306 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, |
| 50307 | // (intrinsic_w_chain:{ *:[i64] } 349:{ *:[iPTR] }, i64:{ *:[i64] }:$Rm) => (IRGstack:{ *:[i64] } SP:{ *:[i64] }, i64:{ *:[i64] }:$Rm) |
| 50308 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::IRGstack, |
| 50309 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 50310 | GIR_AddRegister, /*InsnID*/0, AArch64::SP, /*AddRegisterRegFlags*/0, |
| 50311 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 50312 | GIR_EraseFromParent, /*InsnID*/0, |
| 50313 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50314 | // GIR_Coverage, 3531, |
| 50315 | GIR_Done, |
| 50316 | // Label 2679: @129423 |
| 50317 | GIM_Reject, |
| 50318 | // Label 2670: @129424 |
| 50319 | GIM_Try, /*On fail goto*//*Label 2680*/ 131373, |
| 50320 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, |
| 50321 | GIM_Try, /*On fail goto*//*Label 2681*/ 129522, // Rule ID 5426 // |
| 50322 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, |
| 50323 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 50324 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 50325 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 50326 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 50327 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 50328 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 50329 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 50330 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 50331 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 50332 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 50333 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 50334 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 255, |
| 50335 | // MIs[0] addr |
| 50336 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, |
| 50337 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, |
| 50338 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_1, |
| 50339 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 50340 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 50341 | // (intrinsic_w_chain:{ *:[i32] } 549:{ *:[iPTR] }, (zext:{ *:[i64] } (and:{ *:[i32] } GPR32:{ *:[i32] }:$val, 255:{ *:[i32] })), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_1>> => (STXRB:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr) |
| 50342 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRB, |
| 50343 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws |
| 50344 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // val |
| 50345 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr |
| 50346 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, |
| 50347 | GIR_EraseFromParent, /*InsnID*/0, |
| 50348 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50349 | // GIR_Coverage, 5426, |
| 50350 | GIR_Done, |
| 50351 | // Label 2681: @129522 |
| 50352 | GIM_Try, /*On fail goto*//*Label 2682*/ 129615, // Rule ID 5427 // |
| 50353 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, |
| 50354 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 50355 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 50356 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 50357 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 50358 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 50359 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 50360 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 50361 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 50362 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 50363 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 50364 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 50365 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535, |
| 50366 | // MIs[0] addr |
| 50367 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, |
| 50368 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, |
| 50369 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_2, |
| 50370 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 50371 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 50372 | // (intrinsic_w_chain:{ *:[i32] } 549:{ *:[iPTR] }, (zext:{ *:[i64] } (and:{ *:[i32] } GPR32:{ *:[i32] }:$val, 65535:{ *:[i32] })), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_2>> => (STXRH:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr) |
| 50373 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRH, |
| 50374 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws |
| 50375 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // val |
| 50376 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr |
| 50377 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, |
| 50378 | GIR_EraseFromParent, /*InsnID*/0, |
| 50379 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50380 | // GIR_Coverage, 5427, |
| 50381 | GIR_Done, |
| 50382 | // Label 2682: @129615 |
| 50383 | GIM_Try, /*On fail goto*//*Label 2683*/ 129708, // Rule ID 5436 // |
| 50384 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, |
| 50385 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 50386 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 50387 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 50388 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 50389 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 50390 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 50391 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 50392 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 50393 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 50394 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 50395 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 50396 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 255, |
| 50397 | // MIs[0] addr |
| 50398 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, |
| 50399 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, |
| 50400 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_1, |
| 50401 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 50402 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 50403 | // (intrinsic_w_chain:{ *:[i32] } 547:{ *:[iPTR] }, (zext:{ *:[i64] } (and:{ *:[i32] } GPR32:{ *:[i32] }:$val, 255:{ *:[i32] })), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_1>> => (STLXRB:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr) |
| 50404 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRB, |
| 50405 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws |
| 50406 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // val |
| 50407 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr |
| 50408 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, |
| 50409 | GIR_EraseFromParent, /*InsnID*/0, |
| 50410 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50411 | // GIR_Coverage, 5436, |
| 50412 | GIR_Done, |
| 50413 | // Label 2683: @129708 |
| 50414 | GIM_Try, /*On fail goto*//*Label 2684*/ 129801, // Rule ID 5437 // |
| 50415 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, |
| 50416 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 50417 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 50418 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 50419 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 50420 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 50421 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 50422 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 50423 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, |
| 50424 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 50425 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 50426 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 50427 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535, |
| 50428 | // MIs[0] addr |
| 50429 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, |
| 50430 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, |
| 50431 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_2, |
| 50432 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 50433 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 50434 | // (intrinsic_w_chain:{ *:[i32] } 547:{ *:[iPTR] }, (zext:{ *:[i64] } (and:{ *:[i32] } GPR32:{ *:[i32] }:$val, 65535:{ *:[i32] })), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_2>> => (STLXRH:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr) |
| 50435 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRH, |
| 50436 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws |
| 50437 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // val |
| 50438 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr |
| 50439 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, |
| 50440 | GIR_EraseFromParent, /*InsnID*/0, |
| 50441 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50442 | // GIR_Coverage, 5437, |
| 50443 | GIR_Done, |
| 50444 | // Label 2684: @129801 |
| 50445 | GIM_Try, /*On fail goto*//*Label 2685*/ 129903, // Rule ID 5429 // |
| 50446 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, |
| 50447 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 50448 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 50449 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 50450 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 50451 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 50452 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 50453 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 50454 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 50455 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255, |
| 50456 | // MIs[0] addr |
| 50457 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, |
| 50458 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, |
| 50459 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_1, |
| 50460 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 50461 | // (intrinsic_w_chain:{ *:[i32] } 549:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 255:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_1>> => (STXRB:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) |
| 50462 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50463 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 50464 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 50465 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/15, // val |
| 50466 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, |
| 50467 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, |
| 50468 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRB, |
| 50469 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws |
| 50470 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 50471 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr |
| 50472 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 50473 | GIR_EraseFromParent, /*InsnID*/0, |
| 50474 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50475 | // GIR_Coverage, 5429, |
| 50476 | GIR_Done, |
| 50477 | // Label 2685: @129903 |
| 50478 | GIM_Try, /*On fail goto*//*Label 2686*/ 130005, // Rule ID 5430 // |
| 50479 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, |
| 50480 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 50481 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 50482 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 50483 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 50484 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 50485 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 50486 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 50487 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 50488 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535, |
| 50489 | // MIs[0] addr |
| 50490 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, |
| 50491 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, |
| 50492 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_2, |
| 50493 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 50494 | // (intrinsic_w_chain:{ *:[i32] } 549:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 65535:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_2>> => (STXRH:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) |
| 50495 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50496 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 50497 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 50498 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/15, // val |
| 50499 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, |
| 50500 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, |
| 50501 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRH, |
| 50502 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws |
| 50503 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 50504 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr |
| 50505 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 50506 | GIR_EraseFromParent, /*InsnID*/0, |
| 50507 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50508 | // GIR_Coverage, 5430, |
| 50509 | GIR_Done, |
| 50510 | // Label 2686: @130005 |
| 50511 | GIM_Try, /*On fail goto*//*Label 2687*/ 130107, // Rule ID 5431 // |
| 50512 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, |
| 50513 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 50514 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 50515 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 50516 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 50517 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 50518 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 50519 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 50520 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 50521 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294967295, |
| 50522 | // MIs[0] addr |
| 50523 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, |
| 50524 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, |
| 50525 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_4, |
| 50526 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 50527 | // (intrinsic_w_chain:{ *:[i32] } 549:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 4294967295:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_4>> => (STXRW:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) |
| 50528 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50529 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 50530 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 50531 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/15, // val |
| 50532 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, |
| 50533 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, |
| 50534 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRW, |
| 50535 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws |
| 50536 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 50537 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr |
| 50538 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 50539 | GIR_EraseFromParent, /*InsnID*/0, |
| 50540 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50541 | // GIR_Coverage, 5431, |
| 50542 | GIR_Done, |
| 50543 | // Label 2687: @130107 |
| 50544 | GIM_Try, /*On fail goto*//*Label 2688*/ 130209, // Rule ID 5439 // |
| 50545 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, |
| 50546 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 50547 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 50548 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 50549 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 50550 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 50551 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 50552 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 50553 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 50554 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255, |
| 50555 | // MIs[0] addr |
| 50556 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, |
| 50557 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, |
| 50558 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_1, |
| 50559 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 50560 | // (intrinsic_w_chain:{ *:[i32] } 547:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 255:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_1>> => (STLXRB:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) |
| 50561 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50562 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 50563 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 50564 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/15, // val |
| 50565 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, |
| 50566 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, |
| 50567 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRB, |
| 50568 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws |
| 50569 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 50570 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr |
| 50571 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 50572 | GIR_EraseFromParent, /*InsnID*/0, |
| 50573 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50574 | // GIR_Coverage, 5439, |
| 50575 | GIR_Done, |
| 50576 | // Label 2688: @130209 |
| 50577 | GIM_Try, /*On fail goto*//*Label 2689*/ 130311, // Rule ID 5440 // |
| 50578 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, |
| 50579 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 50580 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 50581 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 50582 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 50583 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 50584 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 50585 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 50586 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 50587 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535, |
| 50588 | // MIs[0] addr |
| 50589 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, |
| 50590 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, |
| 50591 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_2, |
| 50592 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 50593 | // (intrinsic_w_chain:{ *:[i32] } 547:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 65535:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_2>> => (STLXRH:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) |
| 50594 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50595 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 50596 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 50597 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/15, // val |
| 50598 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, |
| 50599 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, |
| 50600 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRH, |
| 50601 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws |
| 50602 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 50603 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr |
| 50604 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 50605 | GIR_EraseFromParent, /*InsnID*/0, |
| 50606 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50607 | // GIR_Coverage, 5440, |
| 50608 | GIR_Done, |
| 50609 | // Label 2689: @130311 |
| 50610 | GIM_Try, /*On fail goto*//*Label 2690*/ 130413, // Rule ID 5441 // |
| 50611 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, |
| 50612 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 50613 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 50614 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 50615 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 50616 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 50617 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 50618 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 50619 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 50620 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294967295, |
| 50621 | // MIs[0] addr |
| 50622 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, |
| 50623 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, |
| 50624 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_4, |
| 50625 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 50626 | // (intrinsic_w_chain:{ *:[i32] } 547:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 4294967295:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_4>> => (STLXRW:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) |
| 50627 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50628 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 50629 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 50630 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/15, // val |
| 50631 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, |
| 50632 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, |
| 50633 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRW, |
| 50634 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws |
| 50635 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 50636 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr |
| 50637 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 50638 | GIR_EraseFromParent, /*InsnID*/0, |
| 50639 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50640 | // GIR_Coverage, 5441, |
| 50641 | GIR_Done, |
| 50642 | // Label 2690: @130413 |
| 50643 | GIM_Try, /*On fail goto*//*Label 2691*/ 130484, // Rule ID 5428 // |
| 50644 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, |
| 50645 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 50646 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 50647 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 50648 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 50649 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 50650 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 50651 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 50652 | // MIs[0] addr |
| 50653 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, |
| 50654 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, |
| 50655 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_4, |
| 50656 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 50657 | // (intrinsic_w_chain:{ *:[i32] } 549:{ *:[iPTR] }, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$val), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_4>> => (STXRW:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr) |
| 50658 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRW, |
| 50659 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws |
| 50660 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val |
| 50661 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr |
| 50662 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 50663 | GIR_EraseFromParent, /*InsnID*/0, |
| 50664 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50665 | // GIR_Coverage, 5428, |
| 50666 | GIR_Done, |
| 50667 | // Label 2691: @130484 |
| 50668 | GIM_Try, /*On fail goto*//*Label 2692*/ 130555, // Rule ID 5438 // |
| 50669 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, |
| 50670 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 50671 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 50672 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 50673 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 50674 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 50675 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 50676 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 50677 | // MIs[0] addr |
| 50678 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, |
| 50679 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, |
| 50680 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_4, |
| 50681 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 50682 | // (intrinsic_w_chain:{ *:[i32] } 547:{ *:[iPTR] }, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$val), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_4>> => (STLXRW:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr) |
| 50683 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRW, |
| 50684 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws |
| 50685 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val |
| 50686 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr |
| 50687 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 50688 | GIR_EraseFromParent, /*InsnID*/0, |
| 50689 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50690 | // GIR_Coverage, 5438, |
| 50691 | GIR_Done, |
| 50692 | // Label 2692: @130555 |
| 50693 | GIM_Try, /*On fail goto*//*Label 2693*/ 130614, // Rule ID 14 // |
| 50694 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_space, |
| 50695 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 50696 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 50697 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 50698 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 50699 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 50700 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 50701 | // MIs[1] Operand 1 |
| 50702 | // No operand predicates |
| 50703 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, |
| 50704 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 50705 | // (intrinsic_w_chain:{ *:[i64] } 540:{ *:[iPTR] }, (imm:{ *:[i32] }):$size, GPR64:{ *:[i64] }:$Rn) => (SPACE:{ *:[i64] } (imm:{ *:[i32] }):$size, GPR64:{ *:[i64] }:$Rn) |
| 50706 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SPACE, |
| 50707 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 50708 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // size |
| 50709 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn |
| 50710 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 50711 | GIR_EraseFromParent, /*InsnID*/0, |
| 50712 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50713 | // GIR_Coverage, 14, |
| 50714 | GIR_Done, |
| 50715 | // Label 2693: @130614 |
| 50716 | GIM_Try, /*On fail goto*//*Label 2694*/ 130670, // Rule ID 66 // |
| 50717 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::hwasan_check_memaccess, |
| 50718 | // MIs[0] Operand 1 |
| 50719 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 50720 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64noip_and_tcGPR64RegClassID, |
| 50721 | // MIs[0] ptr |
| 50722 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, |
| 50723 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64noipRegClassID, |
| 50724 | // MIs[0] accessinfo |
| 50725 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 50726 | // (intrinsic_void 143:{ *:[iPTR] }, X9:{ *:[i64] }, GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo) => (HWASAN_CHECK_MEMACCESS:{ *:[i64] } GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo) |
| 50727 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 50728 | GIR_AddRegister, /*InsnID*/1, AArch64::X9, /*AddRegisterRegFlags*/RegState::Define, |
| 50729 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // X9 |
| 50730 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::HWASAN_CHECK_MEMACCESS, |
| 50731 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ptr |
| 50732 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // accessinfo |
| 50733 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 50734 | GIR_EraseFromParent, /*InsnID*/0, |
| 50735 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50736 | // GIR_Coverage, 66, |
| 50737 | GIR_Done, |
| 50738 | // Label 2694: @130670 |
| 50739 | GIM_Try, /*On fail goto*//*Label 2695*/ 130726, // Rule ID 67 // |
| 50740 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::hwasan_check_memaccess_shortgranules, |
| 50741 | // MIs[0] Operand 1 |
| 50742 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 50743 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64common_and_GPR64noipRegClassID, |
| 50744 | // MIs[0] ptr |
| 50745 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, |
| 50746 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64noipRegClassID, |
| 50747 | // MIs[0] accessinfo |
| 50748 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 50749 | // (intrinsic_void 144:{ *:[iPTR] }, X20:{ *:[i64] }, GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo) => (HWASAN_CHECK_MEMACCESS_SHORTGRANULES:{ *:[i64] } GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo) |
| 50750 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 50751 | GIR_AddRegister, /*InsnID*/1, AArch64::X20, /*AddRegisterRegFlags*/RegState::Define, |
| 50752 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // X20 |
| 50753 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::HWASAN_CHECK_MEMACCESS_SHORTGRANULES, |
| 50754 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ptr |
| 50755 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // accessinfo |
| 50756 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 50757 | GIR_EraseFromParent, /*InsnID*/0, |
| 50758 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50759 | // GIR_Coverage, 67, |
| 50760 | GIR_Done, |
| 50761 | // Label 2695: @130726 |
| 50762 | GIM_Try, /*On fail goto*//*Label 2696*/ 130806, // Rule ID 5422 // |
| 50763 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, |
| 50764 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 50765 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 50766 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 50767 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 50768 | // MIs[0] addr |
| 50769 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, |
| 50770 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, |
| 50771 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_1, |
| 50772 | // (intrinsic_w_chain:{ *:[i32] } 549:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_1>> => (STXRB:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) |
| 50773 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50774 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 50775 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 50776 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/15, // val |
| 50777 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, |
| 50778 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, |
| 50779 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRB, |
| 50780 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws |
| 50781 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 50782 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr |
| 50783 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 50784 | GIR_EraseFromParent, /*InsnID*/0, |
| 50785 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50786 | // GIR_Coverage, 5422, |
| 50787 | GIR_Done, |
| 50788 | // Label 2696: @130806 |
| 50789 | GIM_Try, /*On fail goto*//*Label 2697*/ 130886, // Rule ID 5423 // |
| 50790 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, |
| 50791 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 50792 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 50793 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 50794 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 50795 | // MIs[0] addr |
| 50796 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, |
| 50797 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, |
| 50798 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_2, |
| 50799 | // (intrinsic_w_chain:{ *:[i32] } 549:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_2>> => (STXRH:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) |
| 50800 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50801 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 50802 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 50803 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/15, // val |
| 50804 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, |
| 50805 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, |
| 50806 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRH, |
| 50807 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws |
| 50808 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 50809 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr |
| 50810 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 50811 | GIR_EraseFromParent, /*InsnID*/0, |
| 50812 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50813 | // GIR_Coverage, 5423, |
| 50814 | GIR_Done, |
| 50815 | // Label 2697: @130886 |
| 50816 | GIM_Try, /*On fail goto*//*Label 2698*/ 130966, // Rule ID 5424 // |
| 50817 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, |
| 50818 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 50819 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 50820 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 50821 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 50822 | // MIs[0] addr |
| 50823 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, |
| 50824 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, |
| 50825 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_4, |
| 50826 | // (intrinsic_w_chain:{ *:[i32] } 549:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_4>> => (STXRW:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) |
| 50827 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50828 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 50829 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 50830 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/15, // val |
| 50831 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, |
| 50832 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, |
| 50833 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRW, |
| 50834 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws |
| 50835 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 50836 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr |
| 50837 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 50838 | GIR_EraseFromParent, /*InsnID*/0, |
| 50839 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50840 | // GIR_Coverage, 5424, |
| 50841 | GIR_Done, |
| 50842 | // Label 2698: @130966 |
| 50843 | GIM_Try, /*On fail goto*//*Label 2699*/ 131023, // Rule ID 5425 // |
| 50844 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stxr, |
| 50845 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 50846 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 50847 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 50848 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 50849 | // MIs[0] addr |
| 50850 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, |
| 50851 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, |
| 50852 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stxr_8, |
| 50853 | // (intrinsic_w_chain:{ *:[i32] } 549:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_8>> => (STXRX:{ *:[i32] } GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr) |
| 50854 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STXRX, |
| 50855 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws |
| 50856 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val |
| 50857 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr |
| 50858 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 50859 | GIR_EraseFromParent, /*InsnID*/0, |
| 50860 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50861 | // GIR_Coverage, 5425, |
| 50862 | GIR_Done, |
| 50863 | // Label 2699: @131023 |
| 50864 | GIM_Try, /*On fail goto*//*Label 2700*/ 131103, // Rule ID 5432 // |
| 50865 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, |
| 50866 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 50867 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 50868 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 50869 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 50870 | // MIs[0] addr |
| 50871 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, |
| 50872 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, |
| 50873 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_1, |
| 50874 | // (intrinsic_w_chain:{ *:[i32] } 547:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_1>> => (STLXRB:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) |
| 50875 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50876 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 50877 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 50878 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/15, // val |
| 50879 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, |
| 50880 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, |
| 50881 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRB, |
| 50882 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws |
| 50883 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 50884 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr |
| 50885 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 50886 | GIR_EraseFromParent, /*InsnID*/0, |
| 50887 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50888 | // GIR_Coverage, 5432, |
| 50889 | GIR_Done, |
| 50890 | // Label 2700: @131103 |
| 50891 | GIM_Try, /*On fail goto*//*Label 2701*/ 131183, // Rule ID 5433 // |
| 50892 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, |
| 50893 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 50894 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 50895 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 50896 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 50897 | // MIs[0] addr |
| 50898 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, |
| 50899 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, |
| 50900 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_2, |
| 50901 | // (intrinsic_w_chain:{ *:[i32] } 547:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_2>> => (STLXRH:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) |
| 50902 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50903 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 50904 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 50905 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/15, // val |
| 50906 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, |
| 50907 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, |
| 50908 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRH, |
| 50909 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws |
| 50910 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 50911 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr |
| 50912 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 50913 | GIR_EraseFromParent, /*InsnID*/0, |
| 50914 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50915 | // GIR_Coverage, 5433, |
| 50916 | GIR_Done, |
| 50917 | // Label 2701: @131183 |
| 50918 | GIM_Try, /*On fail goto*//*Label 2702*/ 131263, // Rule ID 5434 // |
| 50919 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, |
| 50920 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 50921 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 50922 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 50923 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 50924 | // MIs[0] addr |
| 50925 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, |
| 50926 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, |
| 50927 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_4, |
| 50928 | // (intrinsic_w_chain:{ *:[i32] } 547:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_4>> => (STLXRW:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr) |
| 50929 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50930 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 50931 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 50932 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/15, // val |
| 50933 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR32RegClassID, |
| 50934 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64RegClassID, |
| 50935 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRW, |
| 50936 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws |
| 50937 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 50938 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr |
| 50939 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 50940 | GIR_EraseFromParent, /*InsnID*/0, |
| 50941 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50942 | // GIR_Coverage, 5434, |
| 50943 | GIR_Done, |
| 50944 | // Label 2702: @131263 |
| 50945 | GIM_Try, /*On fail goto*//*Label 2703*/ 131320, // Rule ID 5435 // |
| 50946 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_stlxr, |
| 50947 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 50948 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 50949 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 50950 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 50951 | // MIs[0] addr |
| 50952 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, |
| 50953 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64spRegClassID, |
| 50954 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_stlxr_8, |
| 50955 | // (intrinsic_w_chain:{ *:[i32] } 547:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_8>> => (STLXRX:{ *:[i32] } GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr) |
| 50956 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::STLXRX, |
| 50957 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Ws |
| 50958 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val |
| 50959 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // addr |
| 50960 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 50961 | GIR_EraseFromParent, /*InsnID*/0, |
| 50962 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50963 | // GIR_Coverage, 5435, |
| 50964 | GIR_Done, |
| 50965 | // Label 2703: @131320 |
| 50966 | GIM_Try, /*On fail goto*//*Label 2704*/ 131372, // Rule ID 128 // |
| 50967 | GIM_CheckFeatures, GIFBS_HasMTE, |
| 50968 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::aarch64_irg, |
| 50969 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 50970 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 50971 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, |
| 50972 | // MIs[0] Rn |
| 50973 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64, |
| 50974 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64spRegClassID, |
| 50975 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::GPR64RegClassID, |
| 50976 | // (intrinsic_w_chain:{ *:[i64] } 348:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (IRG:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) |
| 50977 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::IRG, |
| 50978 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 50979 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 50980 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm |
| 50981 | GIR_EraseFromParent, /*InsnID*/0, |
| 50982 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 50983 | // GIR_Coverage, 128, |
| 50984 | GIR_Done, |
| 50985 | // Label 2704: @131372 |
| 50986 | GIM_Reject, |
| 50987 | // Label 2680: @131373 |
| 50988 | GIM_Reject, |
| 50989 | // Label 32: @131374 |
| 50990 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 10, /*)*//*default:*//*Label 2709*/ 131550, |
| 50991 | /*GILLT_s64*//*Label 2705*/ 131388, 0, 0, |
| 50992 | /*GILLT_v2s64*//*Label 2706*/ 131448, 0, |
| 50993 | /*GILLT_v4s32*//*Label 2707*/ 131482, 0, |
| 50994 | /*GILLT_v8s16*//*Label 2708*/ 131516, |
| 50995 | // Label 2705: @131388 |
| 50996 | GIM_Try, /*On fail goto*//*Label 2710*/ 131447, // Rule ID 4895 // |
| 50997 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 50998 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 50999 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 51000 | // (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$src, sub_32:{ *:[i32] }) |
| 51001 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 51002 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 51003 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 51004 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51005 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 51006 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 51007 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 51008 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 51009 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 51010 | GIR_EraseFromParent, /*InsnID*/0, |
| 51011 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 51012 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::GPR64allRegClassID, |
| 51013 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 51014 | // GIR_Coverage, 4895, |
| 51015 | GIR_Done, |
| 51016 | // Label 2710: @131447 |
| 51017 | GIM_Reject, |
| 51018 | // Label 2706: @131448 |
| 51019 | GIM_Try, /*On fail goto*//*Label 2711*/ 131481, // Rule ID 4774 // |
| 51020 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 51021 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 51022 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 51023 | // (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn) => (USHLLv2i32_shift:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, 0:{ *:[i32] }) |
| 51024 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv2i32_shift, |
| 51025 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51026 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 51027 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 51028 | GIR_EraseFromParent, /*InsnID*/0, |
| 51029 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51030 | // GIR_Coverage, 4774, |
| 51031 | GIR_Done, |
| 51032 | // Label 2711: @131481 |
| 51033 | GIM_Reject, |
| 51034 | // Label 2707: @131482 |
| 51035 | GIM_Try, /*On fail goto*//*Label 2712*/ 131515, // Rule ID 4771 // |
| 51036 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 51037 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 51038 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 51039 | // (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn) => (USHLLv4i16_shift:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, 0:{ *:[i32] }) |
| 51040 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv4i16_shift, |
| 51041 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51042 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 51043 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 51044 | GIR_EraseFromParent, /*InsnID*/0, |
| 51045 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51046 | // GIR_Coverage, 4771, |
| 51047 | GIR_Done, |
| 51048 | // Label 2712: @131515 |
| 51049 | GIM_Reject, |
| 51050 | // Label 2708: @131516 |
| 51051 | GIM_Try, /*On fail goto*//*Label 2713*/ 131549, // Rule ID 4768 // |
| 51052 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 51053 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 51054 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 51055 | // (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn) => (USHLLv8i8_shift:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, 0:{ *:[i32] }) |
| 51056 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv8i8_shift, |
| 51057 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51058 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 51059 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 51060 | GIR_EraseFromParent, /*InsnID*/0, |
| 51061 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51062 | // GIR_Coverage, 4768, |
| 51063 | GIR_Done, |
| 51064 | // Label 2713: @131549 |
| 51065 | GIM_Reject, |
| 51066 | // Label 2709: @131550 |
| 51067 | GIM_Reject, |
| 51068 | // Label 33: @131551 |
| 51069 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 2718*/ 132374, |
| 51070 | /*GILLT_s32*//*Label 2714*/ 131565, 0, 0, |
| 51071 | /*GILLT_v2s32*//*Label 2715*/ 131603, 0, |
| 51072 | /*GILLT_v4s16*//*Label 2716*/ 131860, 0, |
| 51073 | /*GILLT_v8s8*//*Label 2717*/ 132117, |
| 51074 | // Label 2714: @131565 |
| 51075 | GIM_Try, /*On fail goto*//*Label 2719*/ 131602, // Rule ID 4915 // |
| 51076 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 51077 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64spRegClassID, |
| 51078 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 51079 | // (trunc:{ *:[i32] } GPR64sp:{ *:[i64] }:$src) => (EXTRACT_SUBREG:{ *:[i32] } GPR64sp:{ *:[i64] }:$src, sub_32:{ *:[i32] }) |
| 51080 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 51081 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 51082 | GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/15, // src |
| 51083 | GIR_EraseFromParent, /*InsnID*/0, |
| 51084 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR32spRegClassID, |
| 51085 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::GPR64spRegClassID, |
| 51086 | // GIR_Coverage, 4915, |
| 51087 | GIR_Done, |
| 51088 | // Label 2719: @131602 |
| 51089 | GIM_Reject, |
| 51090 | // Label 2715: @131603 |
| 51091 | GIM_Try, /*On fail goto*//*Label 2720*/ 131859, |
| 51092 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 51093 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 51094 | GIM_Try, /*On fail goto*//*Label 2721*/ 131677, // Rule ID 4258 // |
| 51095 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 51096 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 51097 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 51098 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 51099 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, |
| 51100 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 51101 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, |
| 51102 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 51103 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 51104 | // MIs[1] Operand 2 |
| 51105 | GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, 32, |
| 51106 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 51107 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 51108 | // (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm), 32:{ *:[i32] })) => (ADDHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 51109 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv2i64_v2i32, |
| 51110 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51111 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 51112 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm |
| 51113 | GIR_EraseFromParent, /*InsnID*/0, |
| 51114 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51115 | // GIR_Coverage, 4258, |
| 51116 | GIR_Done, |
| 51117 | // Label 2721: @131677 |
| 51118 | GIM_Try, /*On fail goto*//*Label 2722*/ 131741, // Rule ID 4264 // |
| 51119 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 51120 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 51121 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 51122 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 51123 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SUB, |
| 51124 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 51125 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64, |
| 51126 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 51127 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 51128 | // MIs[1] Operand 2 |
| 51129 | GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, 32, |
| 51130 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 51131 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 51132 | // (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm), 32:{ *:[i32] })) => (SUBHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 51133 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv2i64_v2i32, |
| 51134 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51135 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 51136 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm |
| 51137 | GIR_EraseFromParent, /*InsnID*/0, |
| 51138 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51139 | // GIR_Coverage, 4264, |
| 51140 | GIR_Done, |
| 51141 | // Label 2722: @131741 |
| 51142 | GIM_Try, /*On fail goto*//*Label 2723*/ 131793, // Rule ID 1814 // |
| 51143 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 51144 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 51145 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, |
| 51146 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 51147 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 51148 | // MIs[1] imm |
| 51149 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 51150 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 51151 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, |
| 51152 | // MIs[2] Operand 1 |
| 51153 | // No operand predicates |
| 51154 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 51155 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 51156 | // (trunc:{ *:[v2i32] } (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)) => (SHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 51157 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHRNv2i32_shift, |
| 51158 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51159 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 51160 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 51161 | GIR_EraseFromParent, /*InsnID*/0, |
| 51162 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51163 | // GIR_Coverage, 1814, |
| 51164 | GIR_Done, |
| 51165 | // Label 2723: @131793 |
| 51166 | GIM_Try, /*On fail goto*//*Label 2724*/ 131843, // Rule ID 4762 // |
| 51167 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 51168 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 51169 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 51170 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 51171 | // MIs[1] imm |
| 51172 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 51173 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 51174 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64Narrow, |
| 51175 | // MIs[2] Operand 1 |
| 51176 | // No operand predicates |
| 51177 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 51178 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 51179 | // (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)) => (SHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) |
| 51180 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHRNv2i32_shift, |
| 51181 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51182 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 51183 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 51184 | GIR_EraseFromParent, /*InsnID*/0, |
| 51185 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51186 | // GIR_Coverage, 4762, |
| 51187 | GIR_Done, |
| 51188 | // Label 2724: @131843 |
| 51189 | GIM_Try, /*On fail goto*//*Label 2725*/ 131858, // Rule ID 889 // |
| 51190 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 51191 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 51192 | // (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn) => (XTNv2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn) |
| 51193 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::XTNv2i32, |
| 51194 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51195 | // GIR_Coverage, 889, |
| 51196 | GIR_Done, |
| 51197 | // Label 2725: @131858 |
| 51198 | GIM_Reject, |
| 51199 | // Label 2720: @131859 |
| 51200 | GIM_Reject, |
| 51201 | // Label 2716: @131860 |
| 51202 | GIM_Try, /*On fail goto*//*Label 2726*/ 132116, |
| 51203 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 51204 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 51205 | GIM_Try, /*On fail goto*//*Label 2727*/ 131934, // Rule ID 4257 // |
| 51206 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 51207 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 51208 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 51209 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 51210 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, |
| 51211 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 51212 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 51213 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 51214 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 51215 | // MIs[1] Operand 2 |
| 51216 | GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, 16, |
| 51217 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 51218 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 51219 | // (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), 16:{ *:[i32] })) => (ADDHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 51220 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv4i32_v4i16, |
| 51221 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51222 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 51223 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm |
| 51224 | GIR_EraseFromParent, /*InsnID*/0, |
| 51225 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51226 | // GIR_Coverage, 4257, |
| 51227 | GIR_Done, |
| 51228 | // Label 2727: @131934 |
| 51229 | GIM_Try, /*On fail goto*//*Label 2728*/ 131998, // Rule ID 4263 // |
| 51230 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 51231 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 51232 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 51233 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 51234 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SUB, |
| 51235 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 51236 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 51237 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 51238 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 51239 | // MIs[1] Operand 2 |
| 51240 | GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, 16, |
| 51241 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 51242 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 51243 | // (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), 16:{ *:[i32] })) => (SUBHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 51244 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv4i32_v4i16, |
| 51245 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51246 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 51247 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm |
| 51248 | GIR_EraseFromParent, /*InsnID*/0, |
| 51249 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51250 | // GIR_Coverage, 4263, |
| 51251 | GIR_Done, |
| 51252 | // Label 2728: @131998 |
| 51253 | GIM_Try, /*On fail goto*//*Label 2729*/ 132050, // Rule ID 1813 // |
| 51254 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 51255 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 51256 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, |
| 51257 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 51258 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 51259 | // MIs[1] imm |
| 51260 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 51261 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 51262 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, |
| 51263 | // MIs[2] Operand 1 |
| 51264 | // No operand predicates |
| 51265 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 51266 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 51267 | // (trunc:{ *:[v4i16] } (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)) => (SHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 51268 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHRNv4i16_shift, |
| 51269 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51270 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 51271 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 51272 | GIR_EraseFromParent, /*InsnID*/0, |
| 51273 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51274 | // GIR_Coverage, 1813, |
| 51275 | GIR_Done, |
| 51276 | // Label 2729: @132050 |
| 51277 | GIM_Try, /*On fail goto*//*Label 2730*/ 132100, // Rule ID 4761 // |
| 51278 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 51279 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 51280 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 51281 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 51282 | // MIs[1] imm |
| 51283 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 51284 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 51285 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32Narrow, |
| 51286 | // MIs[2] Operand 1 |
| 51287 | // No operand predicates |
| 51288 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 51289 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 51290 | // (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)) => (SHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) |
| 51291 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHRNv4i16_shift, |
| 51292 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51293 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 51294 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 51295 | GIR_EraseFromParent, /*InsnID*/0, |
| 51296 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51297 | // GIR_Coverage, 4761, |
| 51298 | GIR_Done, |
| 51299 | // Label 2730: @132100 |
| 51300 | GIM_Try, /*On fail goto*//*Label 2731*/ 132115, // Rule ID 888 // |
| 51301 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 51302 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 51303 | // (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn) => (XTNv4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn) |
| 51304 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::XTNv4i16, |
| 51305 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51306 | // GIR_Coverage, 888, |
| 51307 | GIR_Done, |
| 51308 | // Label 2731: @132115 |
| 51309 | GIM_Reject, |
| 51310 | // Label 2726: @132116 |
| 51311 | GIM_Reject, |
| 51312 | // Label 2717: @132117 |
| 51313 | GIM_Try, /*On fail goto*//*Label 2732*/ 132373, |
| 51314 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 51315 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 51316 | GIM_Try, /*On fail goto*//*Label 2733*/ 132191, // Rule ID 4256 // |
| 51317 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 51318 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 51319 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 51320 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 51321 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, |
| 51322 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 51323 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 51324 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 51325 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 51326 | // MIs[1] Operand 2 |
| 51327 | GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, 8, |
| 51328 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 51329 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 51330 | // (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), 8:{ *:[i32] })) => (ADDHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 51331 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDHNv8i16_v8i8, |
| 51332 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51333 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 51334 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm |
| 51335 | GIR_EraseFromParent, /*InsnID*/0, |
| 51336 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51337 | // GIR_Coverage, 4256, |
| 51338 | GIR_Done, |
| 51339 | // Label 2733: @132191 |
| 51340 | GIM_Try, /*On fail goto*//*Label 2734*/ 132255, // Rule ID 4262 // |
| 51341 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 51342 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 51343 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 51344 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 51345 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SUB, |
| 51346 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 51347 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 51348 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 51349 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 51350 | // MIs[1] Operand 2 |
| 51351 | GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, 8, |
| 51352 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 51353 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 51354 | // (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), 8:{ *:[i32] })) => (SUBHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 51355 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBHNv8i16_v8i8, |
| 51356 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51357 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 51358 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm |
| 51359 | GIR_EraseFromParent, /*InsnID*/0, |
| 51360 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51361 | // GIR_Coverage, 4262, |
| 51362 | GIR_Done, |
| 51363 | // Label 2734: @132255 |
| 51364 | GIM_Try, /*On fail goto*//*Label 2735*/ 132307, // Rule ID 1812 // |
| 51365 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 51366 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 51367 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VASHR, |
| 51368 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 51369 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 51370 | // MIs[1] imm |
| 51371 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 51372 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 51373 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, |
| 51374 | // MIs[2] Operand 1 |
| 51375 | // No operand predicates |
| 51376 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 51377 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 51378 | // (trunc:{ *:[v8i8] } (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)) => (SHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 51379 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHRNv8i8_shift, |
| 51380 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51381 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 51382 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 51383 | GIR_EraseFromParent, /*InsnID*/0, |
| 51384 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51385 | // GIR_Coverage, 1812, |
| 51386 | GIR_Done, |
| 51387 | // Label 2735: @132307 |
| 51388 | GIM_Try, /*On fail goto*//*Label 2736*/ 132357, // Rule ID 4760 // |
| 51389 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 51390 | GIM_CheckOpcode, /*MI*/1, AArch64::G_VLSHR, |
| 51391 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 51392 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 51393 | // MIs[1] imm |
| 51394 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 51395 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 51396 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16Narrow, |
| 51397 | // MIs[2] Operand 1 |
| 51398 | // No operand predicates |
| 51399 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 51400 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 51401 | // (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)) => (SHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) |
| 51402 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SHRNv8i8_shift, |
| 51403 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51404 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 51405 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 51406 | GIR_EraseFromParent, /*InsnID*/0, |
| 51407 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51408 | // GIR_Coverage, 4760, |
| 51409 | GIR_Done, |
| 51410 | // Label 2736: @132357 |
| 51411 | GIM_Try, /*On fail goto*//*Label 2737*/ 132372, // Rule ID 887 // |
| 51412 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 51413 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 51414 | // (trunc:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn) => (XTNv8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn) |
| 51415 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::XTNv8i8, |
| 51416 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51417 | // GIR_Coverage, 887, |
| 51418 | GIR_Done, |
| 51419 | // Label 2737: @132372 |
| 51420 | GIM_Reject, |
| 51421 | // Label 2732: @132373 |
| 51422 | GIM_Reject, |
| 51423 | // Label 2718: @132374 |
| 51424 | GIM_Reject, |
| 51425 | // Label 34: @132375 |
| 51426 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 2740*/ 132482, |
| 51427 | /*GILLT_s32*//*Label 2738*/ 132383, |
| 51428 | /*GILLT_s64*//*Label 2739*/ 132405, |
| 51429 | // Label 2738: @132383 |
| 51430 | GIM_Try, /*On fail goto*//*Label 2741*/ 132404, // Rule ID 72 // |
| 51431 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 51432 | // MIs[0] Operand 1 |
| 51433 | // No operand predicates |
| 51434 | // (imm:{ *:[i32] }):$src => (MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src) |
| 51435 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MOVi32imm, |
| 51436 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 51437 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src |
| 51438 | GIR_EraseFromParent, /*InsnID*/0, |
| 51439 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51440 | // GIR_Coverage, 72, |
| 51441 | GIR_Done, |
| 51442 | // Label 2741: @132404 |
| 51443 | GIM_Reject, |
| 51444 | // Label 2739: @132405 |
| 51445 | GIM_Try, /*On fail goto*//*Label 2742*/ 132460, // Rule ID 3452 // |
| 51446 | GIM_CheckFeatures, GIFBS_OptimizedGISelOrOtherSelector, |
| 51447 | GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_i64imm_32bit, |
| 51448 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64allRegClassID, |
| 51449 | // MIs[0] Operand 1 |
| 51450 | // No operand predicates |
| 51451 | // (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$src => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$src)), sub_32:{ *:[i32] }) |
| 51452 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 51453 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::MOVi32imm, |
| 51454 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 51455 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/0, /*Renderer*/GICR_renderTruncImm, // src |
| 51456 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 51457 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 51458 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 51459 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 51460 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 51461 | GIR_AddImm, /*InsnID*/0, /*Imm*/15, |
| 51462 | GIR_EraseFromParent, /*InsnID*/0, |
| 51463 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::GPR64allRegClassID, |
| 51464 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, AArch64::GPR32RegClassID, |
| 51465 | // GIR_Coverage, 3452, |
| 51466 | GIR_Done, |
| 51467 | // Label 2742: @132460 |
| 51468 | GIM_Try, /*On fail goto*//*Label 2743*/ 132481, // Rule ID 73 // |
| 51469 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 51470 | // MIs[0] Operand 1 |
| 51471 | // No operand predicates |
| 51472 | // (imm:{ *:[i64] }):$src => (MOVi64imm:{ *:[i64] } (imm:{ *:[i64] }):$src) |
| 51473 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::MOVi64imm, |
| 51474 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 51475 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src |
| 51476 | GIR_EraseFromParent, /*InsnID*/0, |
| 51477 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51478 | // GIR_Coverage, 73, |
| 51479 | GIR_Done, |
| 51480 | // Label 2743: @132481 |
| 51481 | GIM_Reject, |
| 51482 | // Label 2740: @132482 |
| 51483 | GIM_Reject, |
| 51484 | // Label 35: @132483 |
| 51485 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 2747*/ 132560, |
| 51486 | /*GILLT_s16*//*Label 2744*/ 132492, |
| 51487 | /*GILLT_s32*//*Label 2745*/ 132516, |
| 51488 | /*GILLT_s64*//*Label 2746*/ 132538, |
| 51489 | // Label 2744: @132492 |
| 51490 | GIM_Try, /*On fail goto*//*Label 2748*/ 132515, // Rule ID 474 // |
| 51491 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 51492 | GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm0, |
| 51493 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 51494 | // MIs[0] Operand 1 |
| 51495 | // No operand predicates |
| 51496 | // (fpimm:{ *:[f16] })<<P:Predicate_fpimm0>> => (FMOVH0:{ *:[f16] }) |
| 51497 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMOVH0, |
| 51498 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51499 | GIR_EraseFromParent, /*InsnID*/0, |
| 51500 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51501 | // GIR_Coverage, 474, |
| 51502 | GIR_Done, |
| 51503 | // Label 2748: @132515 |
| 51504 | GIM_Reject, |
| 51505 | // Label 2745: @132516 |
| 51506 | GIM_Try, /*On fail goto*//*Label 2749*/ 132537, // Rule ID 475 // |
| 51507 | GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm0, |
| 51508 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 51509 | // MIs[0] Operand 1 |
| 51510 | // No operand predicates |
| 51511 | // (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>> => (FMOVS0:{ *:[f32] }) |
| 51512 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMOVS0, |
| 51513 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51514 | GIR_EraseFromParent, /*InsnID*/0, |
| 51515 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51516 | // GIR_Coverage, 475, |
| 51517 | GIR_Done, |
| 51518 | // Label 2749: @132537 |
| 51519 | GIM_Reject, |
| 51520 | // Label 2746: @132538 |
| 51521 | GIM_Try, /*On fail goto*//*Label 2750*/ 132559, // Rule ID 476 // |
| 51522 | GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm0, |
| 51523 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 51524 | // MIs[0] Operand 1 |
| 51525 | // No operand predicates |
| 51526 | // (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>> => (FMOVD0:{ *:[f64] }) |
| 51527 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMOVD0, |
| 51528 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51529 | GIR_EraseFromParent, /*InsnID*/0, |
| 51530 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51531 | // GIR_Coverage, 476, |
| 51532 | GIR_Done, |
| 51533 | // Label 2750: @132559 |
| 51534 | GIM_Reject, |
| 51535 | // Label 2747: @132560 |
| 51536 | GIM_Reject, |
| 51537 | // Label 36: @132561 |
| 51538 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 10, /*)*//*default:*//*Label 2755*/ 132816, |
| 51539 | /*GILLT_s64*//*Label 2751*/ 132575, 0, 0, |
| 51540 | /*GILLT_v2s64*//*Label 2752*/ 132714, 0, |
| 51541 | /*GILLT_v4s32*//*Label 2753*/ 132748, 0, |
| 51542 | /*GILLT_v8s16*//*Label 2754*/ 132782, |
| 51543 | // Label 2751: @132575 |
| 51544 | GIM_Try, /*On fail goto*//*Label 2756*/ 132713, |
| 51545 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 51546 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 51547 | GIM_Try, /*On fail goto*//*Label 2757*/ 132639, // Rule ID 4400 // |
| 51548 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 51549 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 51550 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 51551 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 51552 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 51553 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 51554 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 51555 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 51556 | // MIs[2] Operand 1 |
| 51557 | // No operand predicates |
| 51558 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 51559 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 51560 | // (sext:{ *:[i64] } (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (SMOVvi32to64:{ *:[i64] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 51561 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SMOVvi32to64, |
| 51562 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51563 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 51564 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 51565 | GIR_EraseFromParent, /*InsnID*/0, |
| 51566 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51567 | // GIR_Coverage, 4400, |
| 51568 | GIR_Done, |
| 51569 | // Label 2757: @132639 |
| 51570 | GIM_Try, /*On fail goto*//*Label 2758*/ 132712, // Rule ID 4897 // |
| 51571 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 51572 | // (sext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (SBFMXri:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$src, sub_32:{ *:[i32] }), 0:{ *:[i64] }, 31:{ *:[i64] }) |
| 51573 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 51574 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 51575 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 51576 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 51577 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 51578 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 51579 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 51580 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 51581 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 51582 | GIR_AddImm, /*InsnID*/1, /*Imm*/15, |
| 51583 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR64allRegClassID, |
| 51584 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64allRegClassID, |
| 51585 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::GPR32RegClassID, |
| 51586 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SBFMXri, |
| 51587 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51588 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 51589 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 51590 | GIR_AddImm, /*InsnID*/0, /*Imm*/31, |
| 51591 | GIR_EraseFromParent, /*InsnID*/0, |
| 51592 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51593 | // GIR_Coverage, 4897, |
| 51594 | GIR_Done, |
| 51595 | // Label 2758: @132712 |
| 51596 | GIM_Reject, |
| 51597 | // Label 2756: @132713 |
| 51598 | GIM_Reject, |
| 51599 | // Label 2752: @132714 |
| 51600 | GIM_Try, /*On fail goto*//*Label 2759*/ 132747, // Rule ID 4772 // |
| 51601 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 51602 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 51603 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 51604 | // (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn) => (SSHLLv2i32_shift:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, 0:{ *:[i32] }) |
| 51605 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLLv2i32_shift, |
| 51606 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51607 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 51608 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 51609 | GIR_EraseFromParent, /*InsnID*/0, |
| 51610 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51611 | // GIR_Coverage, 4772, |
| 51612 | GIR_Done, |
| 51613 | // Label 2759: @132747 |
| 51614 | GIM_Reject, |
| 51615 | // Label 2753: @132748 |
| 51616 | GIM_Try, /*On fail goto*//*Label 2760*/ 132781, // Rule ID 4769 // |
| 51617 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 51618 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 51619 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 51620 | // (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn) => (SSHLLv4i16_shift:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, 0:{ *:[i32] }) |
| 51621 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLLv4i16_shift, |
| 51622 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51623 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 51624 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 51625 | GIR_EraseFromParent, /*InsnID*/0, |
| 51626 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51627 | // GIR_Coverage, 4769, |
| 51628 | GIR_Done, |
| 51629 | // Label 2760: @132781 |
| 51630 | GIM_Reject, |
| 51631 | // Label 2754: @132782 |
| 51632 | GIM_Try, /*On fail goto*//*Label 2761*/ 132815, // Rule ID 4766 // |
| 51633 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 51634 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 51635 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 51636 | // (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn) => (SSHLLv8i8_shift:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, 0:{ *:[i32] }) |
| 51637 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHLLv8i8_shift, |
| 51638 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51639 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 51640 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 51641 | GIR_EraseFromParent, /*InsnID*/0, |
| 51642 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51643 | // GIR_Coverage, 4766, |
| 51644 | GIR_Done, |
| 51645 | // Label 2761: @132815 |
| 51646 | GIM_Reject, |
| 51647 | // Label 2755: @132816 |
| 51648 | GIM_Reject, |
| 51649 | // Label 37: @132817 |
| 51650 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 10, /*)*//*default:*//*Label 2765*/ 133275, |
| 51651 | /*GILLT_v2s64*//*Label 2762*/ 132828, 0, |
| 51652 | /*GILLT_v4s32*//*Label 2763*/ 132977, 0, |
| 51653 | /*GILLT_v8s16*//*Label 2764*/ 133126, |
| 51654 | // Label 2762: @132828 |
| 51655 | GIM_Try, /*On fail goto*//*Label 2766*/ 132976, |
| 51656 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 51657 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 51658 | GIM_Try, /*On fail goto*//*Label 2767*/ 132894, // Rule ID 594 // |
| 51659 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 51660 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 51661 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 51662 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 51663 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 51664 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 51665 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 51666 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 51667 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 51668 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 51669 | // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 489:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (UABDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 51670 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv2i32_v2i64, |
| 51671 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51672 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 51673 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 51674 | GIR_EraseFromParent, /*InsnID*/0, |
| 51675 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51676 | // GIR_Coverage, 594, |
| 51677 | GIR_Done, |
| 51678 | // Label 2767: @132894 |
| 51679 | GIM_Try, /*On fail goto*//*Label 2768*/ 132950, // Rule ID 1426 // |
| 51680 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 51681 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 51682 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 51683 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 51684 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 51685 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 51686 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 51687 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 51688 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 51689 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 51690 | // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 426:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SABDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 51691 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDLv2i32_v2i64, |
| 51692 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51693 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 51694 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 51695 | GIR_EraseFromParent, /*InsnID*/0, |
| 51696 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51697 | // GIR_Coverage, 1426, |
| 51698 | GIR_Done, |
| 51699 | // Label 2768: @132950 |
| 51700 | GIM_Try, /*On fail goto*//*Label 2769*/ 132975, // Rule ID 4773 // |
| 51701 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 51702 | // (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn) => (USHLLv2i32_shift:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, 0:{ *:[i32] }) |
| 51703 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv2i32_shift, |
| 51704 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51705 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 51706 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 51707 | GIR_EraseFromParent, /*InsnID*/0, |
| 51708 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51709 | // GIR_Coverage, 4773, |
| 51710 | GIR_Done, |
| 51711 | // Label 2769: @132975 |
| 51712 | GIM_Reject, |
| 51713 | // Label 2766: @132976 |
| 51714 | GIM_Reject, |
| 51715 | // Label 2763: @132977 |
| 51716 | GIM_Try, /*On fail goto*//*Label 2770*/ 133125, |
| 51717 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 51718 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 51719 | GIM_Try, /*On fail goto*//*Label 2771*/ 133043, // Rule ID 590 // |
| 51720 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 51721 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 51722 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 51723 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 51724 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 51725 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 51726 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 51727 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 51728 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 51729 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 51730 | // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 489:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (UABDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 51731 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv4i16_v4i32, |
| 51732 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51733 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 51734 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 51735 | GIR_EraseFromParent, /*InsnID*/0, |
| 51736 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51737 | // GIR_Coverage, 590, |
| 51738 | GIR_Done, |
| 51739 | // Label 2771: @133043 |
| 51740 | GIM_Try, /*On fail goto*//*Label 2772*/ 133099, // Rule ID 1422 // |
| 51741 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 51742 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 51743 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 51744 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 51745 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 51746 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 51747 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 51748 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 51749 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 51750 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 51751 | // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 426:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SABDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 51752 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDLv4i16_v4i32, |
| 51753 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51754 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 51755 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 51756 | GIR_EraseFromParent, /*InsnID*/0, |
| 51757 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51758 | // GIR_Coverage, 1422, |
| 51759 | GIR_Done, |
| 51760 | // Label 2772: @133099 |
| 51761 | GIM_Try, /*On fail goto*//*Label 2773*/ 133124, // Rule ID 4770 // |
| 51762 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 51763 | // (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn) => (USHLLv4i16_shift:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, 0:{ *:[i32] }) |
| 51764 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv4i16_shift, |
| 51765 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51766 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 51767 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 51768 | GIR_EraseFromParent, /*InsnID*/0, |
| 51769 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51770 | // GIR_Coverage, 4770, |
| 51771 | GIR_Done, |
| 51772 | // Label 2773: @133124 |
| 51773 | GIM_Reject, |
| 51774 | // Label 2770: @133125 |
| 51775 | GIM_Reject, |
| 51776 | // Label 2764: @133126 |
| 51777 | GIM_Try, /*On fail goto*//*Label 2774*/ 133274, |
| 51778 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 51779 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 51780 | GIM_Try, /*On fail goto*//*Label 2775*/ 133192, // Rule ID 586 // |
| 51781 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 51782 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 51783 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 51784 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 51785 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_uabd, |
| 51786 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 51787 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, |
| 51788 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 51789 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 51790 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 51791 | // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 489:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (UABDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 51792 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv8i8_v8i16, |
| 51793 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51794 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 51795 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 51796 | GIR_EraseFromParent, /*InsnID*/0, |
| 51797 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51798 | // GIR_Coverage, 586, |
| 51799 | GIR_Done, |
| 51800 | // Label 2775: @133192 |
| 51801 | GIM_Try, /*On fail goto*//*Label 2776*/ 133248, // Rule ID 1418 // |
| 51802 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 51803 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 51804 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, |
| 51805 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 51806 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::aarch64_neon_sabd, |
| 51807 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 51808 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, |
| 51809 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 51810 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 51811 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 51812 | // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 426:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (SABDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 51813 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SABDLv8i8_v8i16, |
| 51814 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51815 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 51816 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm |
| 51817 | GIR_EraseFromParent, /*InsnID*/0, |
| 51818 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51819 | // GIR_Coverage, 1418, |
| 51820 | GIR_Done, |
| 51821 | // Label 2776: @133248 |
| 51822 | GIM_Try, /*On fail goto*//*Label 2777*/ 133273, // Rule ID 4767 // |
| 51823 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 51824 | // (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn) => (USHLLv8i8_shift:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, 0:{ *:[i32] }) |
| 51825 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHLLv8i8_shift, |
| 51826 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51827 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 51828 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 51829 | GIR_EraseFromParent, /*InsnID*/0, |
| 51830 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51831 | // GIR_Coverage, 4767, |
| 51832 | GIR_Done, |
| 51833 | // Label 2777: @133273 |
| 51834 | GIM_Reject, |
| 51835 | // Label 2774: @133274 |
| 51836 | GIM_Reject, |
| 51837 | // Label 2765: @133275 |
| 51838 | GIM_Reject, |
| 51839 | // Label 38: @133276 |
| 51840 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 2780*/ 133588, |
| 51841 | /*GILLT_s32*//*Label 2778*/ 133284, |
| 51842 | /*GILLT_s64*//*Label 2779*/ 133421, |
| 51843 | // Label 2778: @133284 |
| 51844 | GIM_Try, /*On fail goto*//*Label 2781*/ 133420, |
| 51845 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 51846 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 51847 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 51848 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 51849 | GIM_Try, /*On fail goto*//*Label 2782*/ 133341, // Rule ID 3481 // |
| 51850 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 51851 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, |
| 51852 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 51853 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 51854 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 51855 | // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSLVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 51856 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSLVWr, |
| 51857 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51858 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 51859 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 51860 | GIR_EraseFromParent, /*InsnID*/0, |
| 51861 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51862 | // GIR_Coverage, 3481, |
| 51863 | GIR_Done, |
| 51864 | // Label 2782: @133341 |
| 51865 | GIM_Try, /*On fail goto*//*Label 2783*/ 133380, // Rule ID 3482 // |
| 51866 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 51867 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, |
| 51868 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 51869 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 51870 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 51871 | // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSLVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 51872 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSLVWr, |
| 51873 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51874 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 51875 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 51876 | GIR_EraseFromParent, /*InsnID*/0, |
| 51877 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51878 | // GIR_Coverage, 3482, |
| 51879 | GIR_Done, |
| 51880 | // Label 2783: @133380 |
| 51881 | GIM_Try, /*On fail goto*//*Label 2784*/ 133419, // Rule ID 3480 // |
| 51882 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 51883 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 51884 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 51885 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 51886 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 51887 | // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSLVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 51888 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSLVWr, |
| 51889 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51890 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 51891 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 51892 | GIR_EraseFromParent, /*InsnID*/0, |
| 51893 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51894 | // GIR_Coverage, 3480, |
| 51895 | GIR_Done, |
| 51896 | // Label 2784: @133419 |
| 51897 | GIM_Reject, |
| 51898 | // Label 2781: @133420 |
| 51899 | GIM_Reject, |
| 51900 | // Label 2779: @133421 |
| 51901 | GIM_Try, /*On fail goto*//*Label 2785*/ 133587, |
| 51902 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 51903 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 51904 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 51905 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 51906 | GIM_Try, /*On fail goto*//*Label 2786*/ 133506, // Rule ID 3483 // |
| 51907 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 51908 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, |
| 51909 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 51910 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 51911 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 51912 | // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSLVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] })) |
| 51913 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 51914 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 51915 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 51916 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 51917 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 51918 | GIR_AddImm, /*InsnID*/1, /*Imm*/15, |
| 51919 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR64allRegClassID, |
| 51920 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::GPR32RegClassID, |
| 51921 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSLVXr, |
| 51922 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51923 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 51924 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 51925 | GIR_EraseFromParent, /*InsnID*/0, |
| 51926 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51927 | // GIR_Coverage, 3483, |
| 51928 | GIR_Done, |
| 51929 | // Label 2786: @133506 |
| 51930 | GIM_Try, /*On fail goto*//*Label 2787*/ 133573, // Rule ID 3484 // |
| 51931 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 51932 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 51933 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 51934 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 51935 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 51936 | // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSLVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] })) |
| 51937 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 51938 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 51939 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 51940 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 51941 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 51942 | GIR_AddImm, /*InsnID*/1, /*Imm*/15, |
| 51943 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR64allRegClassID, |
| 51944 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::GPR32RegClassID, |
| 51945 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSLVXr, |
| 51946 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51947 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 51948 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 51949 | GIR_EraseFromParent, /*InsnID*/0, |
| 51950 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51951 | // GIR_Coverage, 3484, |
| 51952 | GIR_Done, |
| 51953 | // Label 2787: @133573 |
| 51954 | GIM_Try, /*On fail goto*//*Label 2788*/ 133586, // Rule ID 111 // |
| 51955 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 51956 | // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (LSLVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) |
| 51957 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LSLVXr, |
| 51958 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51959 | // GIR_Coverage, 111, |
| 51960 | GIR_Done, |
| 51961 | // Label 2788: @133586 |
| 51962 | GIM_Reject, |
| 51963 | // Label 2785: @133587 |
| 51964 | GIM_Reject, |
| 51965 | // Label 2780: @133588 |
| 51966 | GIM_Reject, |
| 51967 | // Label 39: @133589 |
| 51968 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 2791*/ 133973, |
| 51969 | /*GILLT_s32*//*Label 2789*/ 133597, |
| 51970 | /*GILLT_s64*//*Label 2790*/ 133770, |
| 51971 | // Label 2789: @133597 |
| 51972 | GIM_Try, /*On fail goto*//*Label 2792*/ 133769, |
| 51973 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 51974 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 51975 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 51976 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 51977 | GIM_Try, /*On fail goto*//*Label 2793*/ 133651, // Rule ID 3548 // |
| 51978 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 51979 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 51980 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31, |
| 51981 | // MIs[1] Operand 1 |
| 51982 | // No operand predicates |
| 51983 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 51984 | // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm) => (UBFMWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm, 31:{ *:[i64] }) |
| 51985 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UBFMWri, |
| 51986 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 51987 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 51988 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 51989 | GIR_AddImm, /*InsnID*/0, /*Imm*/31, |
| 51990 | GIR_EraseFromParent, /*InsnID*/0, |
| 51991 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 51992 | // GIR_Coverage, 3548, |
| 51993 | GIR_Done, |
| 51994 | // Label 2793: @133651 |
| 51995 | GIM_Try, /*On fail goto*//*Label 2794*/ 133690, // Rule ID 3487 // |
| 51996 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 51997 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, |
| 51998 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 51999 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 52000 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 52001 | // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 52002 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSRVWr, |
| 52003 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 52004 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 52005 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 52006 | GIR_EraseFromParent, /*InsnID*/0, |
| 52007 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52008 | // GIR_Coverage, 3487, |
| 52009 | GIR_Done, |
| 52010 | // Label 2794: @133690 |
| 52011 | GIM_Try, /*On fail goto*//*Label 2795*/ 133729, // Rule ID 3488 // |
| 52012 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 52013 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, |
| 52014 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 52015 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 52016 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 52017 | // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 52018 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSRVWr, |
| 52019 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 52020 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 52021 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 52022 | GIR_EraseFromParent, /*InsnID*/0, |
| 52023 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52024 | // GIR_Coverage, 3488, |
| 52025 | GIR_Done, |
| 52026 | // Label 2795: @133729 |
| 52027 | GIM_Try, /*On fail goto*//*Label 2796*/ 133768, // Rule ID 3486 // |
| 52028 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 52029 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 52030 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 52031 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 52032 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 52033 | // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 52034 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSRVWr, |
| 52035 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 52036 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 52037 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 52038 | GIR_EraseFromParent, /*InsnID*/0, |
| 52039 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52040 | // GIR_Coverage, 3486, |
| 52041 | GIR_Done, |
| 52042 | // Label 2796: @133768 |
| 52043 | GIM_Reject, |
| 52044 | // Label 2792: @133769 |
| 52045 | GIM_Reject, |
| 52046 | // Label 2790: @133770 |
| 52047 | GIM_Try, /*On fail goto*//*Label 2797*/ 133972, |
| 52048 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 52049 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 52050 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 52051 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 52052 | GIM_Try, /*On fail goto*//*Label 2798*/ 133824, // Rule ID 3549 // |
| 52053 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 52054 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 52055 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_63, |
| 52056 | // MIs[1] Operand 1 |
| 52057 | // No operand predicates |
| 52058 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 52059 | // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm) => (UBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm, 63:{ *:[i64] }) |
| 52060 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UBFMXri, |
| 52061 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 52062 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 52063 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 52064 | GIR_AddImm, /*InsnID*/0, /*Imm*/63, |
| 52065 | GIR_EraseFromParent, /*InsnID*/0, |
| 52066 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52067 | // GIR_Coverage, 3549, |
| 52068 | GIR_Done, |
| 52069 | // Label 2798: @133824 |
| 52070 | GIM_Try, /*On fail goto*//*Label 2799*/ 133891, // Rule ID 3489 // |
| 52071 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 52072 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, |
| 52073 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 52074 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 52075 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 52076 | // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] })) |
| 52077 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 52078 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 52079 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 52080 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 52081 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 52082 | GIR_AddImm, /*InsnID*/1, /*Imm*/15, |
| 52083 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR64allRegClassID, |
| 52084 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::GPR32RegClassID, |
| 52085 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSRVXr, |
| 52086 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 52087 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 52088 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 52089 | GIR_EraseFromParent, /*InsnID*/0, |
| 52090 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52091 | // GIR_Coverage, 3489, |
| 52092 | GIR_Done, |
| 52093 | // Label 2799: @133891 |
| 52094 | GIM_Try, /*On fail goto*//*Label 2800*/ 133958, // Rule ID 3490 // |
| 52095 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 52096 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 52097 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 52098 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 52099 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 52100 | // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] })) |
| 52101 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 52102 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 52103 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 52104 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 52105 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 52106 | GIR_AddImm, /*InsnID*/1, /*Imm*/15, |
| 52107 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR64allRegClassID, |
| 52108 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::GPR32RegClassID, |
| 52109 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSRVXr, |
| 52110 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 52111 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 52112 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 52113 | GIR_EraseFromParent, /*InsnID*/0, |
| 52114 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52115 | // GIR_Coverage, 3490, |
| 52116 | GIR_Done, |
| 52117 | // Label 2800: @133958 |
| 52118 | GIM_Try, /*On fail goto*//*Label 2801*/ 133971, // Rule ID 112 // |
| 52119 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 52120 | // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (LSRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) |
| 52121 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::LSRVXr, |
| 52122 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52123 | // GIR_Coverage, 112, |
| 52124 | GIR_Done, |
| 52125 | // Label 2801: @133971 |
| 52126 | GIM_Reject, |
| 52127 | // Label 2797: @133972 |
| 52128 | GIM_Reject, |
| 52129 | // Label 2791: @133973 |
| 52130 | GIM_Reject, |
| 52131 | // Label 40: @133974 |
| 52132 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 2804*/ 134468, |
| 52133 | /*GILLT_s32*//*Label 2802*/ 133982, |
| 52134 | /*GILLT_s64*//*Label 2803*/ 134155, |
| 52135 | // Label 2802: @133982 |
| 52136 | GIM_Try, /*On fail goto*//*Label 2805*/ 134154, |
| 52137 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 52138 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 52139 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 52140 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 52141 | GIM_Try, /*On fail goto*//*Label 2806*/ 134036, // Rule ID 3546 // |
| 52142 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 52143 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 52144 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31, |
| 52145 | // MIs[1] Operand 1 |
| 52146 | // No operand predicates |
| 52147 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 52148 | // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm) => (SBFMWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm, 31:{ *:[i64] }) |
| 52149 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SBFMWri, |
| 52150 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 52151 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 52152 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 52153 | GIR_AddImm, /*InsnID*/0, /*Imm*/31, |
| 52154 | GIR_EraseFromParent, /*InsnID*/0, |
| 52155 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52156 | // GIR_Coverage, 3546, |
| 52157 | GIR_Done, |
| 52158 | // Label 2806: @134036 |
| 52159 | GIM_Try, /*On fail goto*//*Label 2807*/ 134075, // Rule ID 2665 // |
| 52160 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 52161 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT, |
| 52162 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 52163 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 52164 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 52165 | // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (ASRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 52166 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ASRVWr, |
| 52167 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 52168 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 52169 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 52170 | GIR_EraseFromParent, /*InsnID*/0, |
| 52171 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52172 | // GIR_Coverage, 2665, |
| 52173 | GIR_Done, |
| 52174 | // Label 2807: @134075 |
| 52175 | GIM_Try, /*On fail goto*//*Label 2808*/ 134114, // Rule ID 2666 // |
| 52176 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 52177 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, |
| 52178 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 52179 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 52180 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 52181 | // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (ASRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 52182 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ASRVWr, |
| 52183 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 52184 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 52185 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 52186 | GIR_EraseFromParent, /*InsnID*/0, |
| 52187 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52188 | // GIR_Coverage, 2666, |
| 52189 | GIR_Done, |
| 52190 | // Label 2808: @134114 |
| 52191 | GIM_Try, /*On fail goto*//*Label 2809*/ 134153, // Rule ID 2664 // |
| 52192 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 52193 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 52194 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 52195 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 52196 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 52197 | // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (ASRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) |
| 52198 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ASRVWr, |
| 52199 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 52200 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 52201 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 52202 | GIR_EraseFromParent, /*InsnID*/0, |
| 52203 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52204 | // GIR_Coverage, 2664, |
| 52205 | GIR_Done, |
| 52206 | // Label 2809: @134153 |
| 52207 | GIM_Reject, |
| 52208 | // Label 2805: @134154 |
| 52209 | GIM_Reject, |
| 52210 | // Label 2803: @134155 |
| 52211 | GIM_Try, /*On fail goto*//*Label 2810*/ 134467, |
| 52212 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 52213 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 52214 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 52215 | GIM_Try, /*On fail goto*//*Label 2811*/ 134267, // Rule ID 4914 // |
| 52216 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 52217 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, |
| 52218 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 52219 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 52220 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 52221 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 52222 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm0_31, |
| 52223 | // MIs[2] Operand 1 |
| 52224 | // No operand predicates |
| 52225 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 52226 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 52227 | // (sra:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm) => (SBFMXri:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm, 31:{ *:[i64] }) |
| 52228 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 52229 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 52230 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 52231 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 52232 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 52233 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 52234 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 52235 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 52236 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 52237 | GIR_AddImm, /*InsnID*/1, /*Imm*/15, |
| 52238 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR64allRegClassID, |
| 52239 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::GPR64allRegClassID, |
| 52240 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::GPR32RegClassID, |
| 52241 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SBFMXri, |
| 52242 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 52243 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 52244 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 52245 | GIR_AddImm, /*InsnID*/0, /*Imm*/31, |
| 52246 | GIR_EraseFromParent, /*InsnID*/0, |
| 52247 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52248 | // GIR_Coverage, 4914, |
| 52249 | GIR_Done, |
| 52250 | // Label 2811: @134267 |
| 52251 | GIM_Try, /*On fail goto*//*Label 2812*/ 134307, // Rule ID 3547 // |
| 52252 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 52253 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 52254 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 52255 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_63, |
| 52256 | // MIs[1] Operand 1 |
| 52257 | // No operand predicates |
| 52258 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 52259 | // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm) => (SBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm, 63:{ *:[i64] }) |
| 52260 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SBFMXri, |
| 52261 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 52262 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 52263 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 52264 | GIR_AddImm, /*InsnID*/0, /*Imm*/63, |
| 52265 | GIR_EraseFromParent, /*InsnID*/0, |
| 52266 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52267 | // GIR_Coverage, 3547, |
| 52268 | GIR_Done, |
| 52269 | // Label 2812: @134307 |
| 52270 | GIM_Try, /*On fail goto*//*Label 2813*/ 134378, // Rule ID 2667 // |
| 52271 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 52272 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 52273 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, |
| 52274 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 52275 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 52276 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 52277 | // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (ASRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] })) |
| 52278 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 52279 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 52280 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 52281 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 52282 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 52283 | GIR_AddImm, /*InsnID*/1, /*Imm*/15, |
| 52284 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR64allRegClassID, |
| 52285 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::GPR32RegClassID, |
| 52286 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ASRVXr, |
| 52287 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 52288 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 52289 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 52290 | GIR_EraseFromParent, /*InsnID*/0, |
| 52291 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52292 | // GIR_Coverage, 2667, |
| 52293 | GIR_Done, |
| 52294 | // Label 2813: @134378 |
| 52295 | GIM_Try, /*On fail goto*//*Label 2814*/ 134449, // Rule ID 2668 // |
| 52296 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 52297 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 52298 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, |
| 52299 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 52300 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 52301 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 52302 | // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (ASRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] })) |
| 52303 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 52304 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 52305 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 52306 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 52307 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 52308 | GIR_AddImm, /*InsnID*/1, /*Imm*/15, |
| 52309 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::GPR64allRegClassID, |
| 52310 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::GPR32RegClassID, |
| 52311 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ASRVXr, |
| 52312 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 52313 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 52314 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 52315 | GIR_EraseFromParent, /*InsnID*/0, |
| 52316 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52317 | // GIR_Coverage, 2668, |
| 52318 | GIR_Done, |
| 52319 | // Label 2814: @134449 |
| 52320 | GIM_Try, /*On fail goto*//*Label 2815*/ 134466, // Rule ID 110 // |
| 52321 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 52322 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 52323 | // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (ASRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) |
| 52324 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ASRVXr, |
| 52325 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52326 | // GIR_Coverage, 110, |
| 52327 | GIR_Done, |
| 52328 | // Label 2815: @134466 |
| 52329 | GIM_Reject, |
| 52330 | // Label 2810: @134467 |
| 52331 | GIM_Reject, |
| 52332 | // Label 2804: @134468 |
| 52333 | GIM_Reject, |
| 52334 | // Label 41: @134469 |
| 52335 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 11, /*)*//*default:*//*Label 2820*/ 134901, |
| 52336 | /*GILLT_s64*//*Label 2816*/ 134484, 0, 0, 0, 0, |
| 52337 | /*GILLT_v4s32*//*Label 2817*/ 134514, 0, |
| 52338 | /*GILLT_v8s16*//*Label 2818*/ 134643, |
| 52339 | /*GILLT_v16s8*//*Label 2819*/ 134772, |
| 52340 | // Label 2816: @134484 |
| 52341 | GIM_Try, /*On fail goto*//*Label 2821*/ 134513, // Rule ID 119 // |
| 52342 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 52343 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 52344 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 52345 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 52346 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 52347 | // (mulhu:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (UMULHrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) |
| 52348 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMULHrr, |
| 52349 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52350 | // GIR_Coverage, 119, |
| 52351 | GIR_Done, |
| 52352 | // Label 2821: @134513 |
| 52353 | GIM_Reject, |
| 52354 | // Label 2817: @134514 |
| 52355 | GIM_Try, /*On fail goto*//*Label 2822*/ 134642, // Rule ID 4924 // |
| 52356 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 52357 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 52358 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 52359 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 52360 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 52361 | // (mulhu:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UZP2v4i32:{ *:[v4i32] } (UMULLv2i32_v2i64:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v4i32] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v4i32] }:$Rm, dsub:{ *:[i32] })), (UMULLv4i32_v2i64:{ *:[f128] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) |
| 52362 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 52363 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 52364 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 52365 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, |
| 52366 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::UMULLv4i32_v2i64, |
| 52367 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 52368 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 52369 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 52370 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 52371 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, |
| 52372 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 52373 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/2, // Rm |
| 52374 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, |
| 52375 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, |
| 52376 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 52377 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 52378 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/2, // Rn |
| 52379 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::FPR64RegClassID, |
| 52380 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::FPR128RegClassID, |
| 52381 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::UMULLv2i32_v2i64, |
| 52382 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 52383 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 52384 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 52385 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52386 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v4i32, |
| 52387 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 52388 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 52389 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, |
| 52390 | GIR_EraseFromParent, /*InsnID*/0, |
| 52391 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52392 | // GIR_Coverage, 4924, |
| 52393 | GIR_Done, |
| 52394 | // Label 2822: @134642 |
| 52395 | GIM_Reject, |
| 52396 | // Label 2818: @134643 |
| 52397 | GIM_Try, /*On fail goto*//*Label 2823*/ 134771, // Rule ID 4923 // |
| 52398 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 52399 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 52400 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 52401 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 52402 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 52403 | // (mulhu:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UZP2v8i16:{ *:[v8i16] } (UMULLv4i16_v4i32:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v8i16] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v8i16] }:$Rm, dsub:{ *:[i32] })), (UMULLv8i16_v4i32:{ *:[f128] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) |
| 52404 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 52405 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 52406 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 52407 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, |
| 52408 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::UMULLv8i16_v4i32, |
| 52409 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 52410 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 52411 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 52412 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 52413 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, |
| 52414 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 52415 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/2, // Rm |
| 52416 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, |
| 52417 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, |
| 52418 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 52419 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 52420 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/2, // Rn |
| 52421 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::FPR64RegClassID, |
| 52422 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::FPR128RegClassID, |
| 52423 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::UMULLv4i16_v4i32, |
| 52424 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 52425 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 52426 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 52427 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52428 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v8i16, |
| 52429 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 52430 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 52431 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, |
| 52432 | GIR_EraseFromParent, /*InsnID*/0, |
| 52433 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52434 | // GIR_Coverage, 4923, |
| 52435 | GIR_Done, |
| 52436 | // Label 2823: @134771 |
| 52437 | GIM_Reject, |
| 52438 | // Label 2819: @134772 |
| 52439 | GIM_Try, /*On fail goto*//*Label 2824*/ 134900, // Rule ID 4922 // |
| 52440 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 52441 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 52442 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 52443 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 52444 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 52445 | // (mulhu:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UZP2v16i8:{ *:[v16i8] } (UMULLv8i8_v8i16:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v16i8] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v16i8] }:$Rm, dsub:{ *:[i32] })), (UMULLv16i8_v8i16:{ *:[f128] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)) |
| 52446 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 52447 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 52448 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 52449 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, |
| 52450 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::UMULLv16i8_v8i16, |
| 52451 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 52452 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 52453 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 52454 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 52455 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, |
| 52456 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 52457 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/2, // Rm |
| 52458 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, |
| 52459 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, |
| 52460 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 52461 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 52462 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/2, // Rn |
| 52463 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::FPR64RegClassID, |
| 52464 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::FPR128RegClassID, |
| 52465 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::UMULLv8i8_v8i16, |
| 52466 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 52467 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 52468 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 52469 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52470 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v16i8, |
| 52471 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 52472 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 52473 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, |
| 52474 | GIR_EraseFromParent, /*InsnID*/0, |
| 52475 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52476 | // GIR_Coverage, 4922, |
| 52477 | GIR_Done, |
| 52478 | // Label 2824: @134900 |
| 52479 | GIM_Reject, |
| 52480 | // Label 2820: @134901 |
| 52481 | GIM_Reject, |
| 52482 | // Label 42: @134902 |
| 52483 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 11, /*)*//*default:*//*Label 2829*/ 135334, |
| 52484 | /*GILLT_s64*//*Label 2825*/ 134917, 0, 0, 0, 0, |
| 52485 | /*GILLT_v4s32*//*Label 2826*/ 134947, 0, |
| 52486 | /*GILLT_v8s16*//*Label 2827*/ 135076, |
| 52487 | /*GILLT_v16s8*//*Label 2828*/ 135205, |
| 52488 | // Label 2825: @134917 |
| 52489 | GIM_Try, /*On fail goto*//*Label 2830*/ 134946, // Rule ID 118 // |
| 52490 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 52491 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 52492 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 52493 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 52494 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR64RegClassID, |
| 52495 | // (mulhs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (SMULHrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) |
| 52496 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMULHrr, |
| 52497 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52498 | // GIR_Coverage, 118, |
| 52499 | GIR_Done, |
| 52500 | // Label 2830: @134946 |
| 52501 | GIM_Reject, |
| 52502 | // Label 2826: @134947 |
| 52503 | GIM_Try, /*On fail goto*//*Label 2831*/ 135075, // Rule ID 4921 // |
| 52504 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 52505 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 52506 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 52507 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 52508 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 52509 | // (mulhs:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UZP2v4i32:{ *:[v4i32] } (SMULLv2i32_v2i64:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v4i32] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v4i32] }:$Rm, dsub:{ *:[i32] })), (SMULLv4i32_v2i64:{ *:[f128] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) |
| 52510 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 52511 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 52512 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 52513 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, |
| 52514 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::SMULLv4i32_v2i64, |
| 52515 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 52516 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 52517 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 52518 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 52519 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, |
| 52520 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 52521 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/2, // Rm |
| 52522 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, |
| 52523 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, |
| 52524 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 52525 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 52526 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/2, // Rn |
| 52527 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::FPR64RegClassID, |
| 52528 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::FPR128RegClassID, |
| 52529 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SMULLv2i32_v2i64, |
| 52530 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 52531 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 52532 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 52533 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52534 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v4i32, |
| 52535 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 52536 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 52537 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, |
| 52538 | GIR_EraseFromParent, /*InsnID*/0, |
| 52539 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52540 | // GIR_Coverage, 4921, |
| 52541 | GIR_Done, |
| 52542 | // Label 2831: @135075 |
| 52543 | GIM_Reject, |
| 52544 | // Label 2827: @135076 |
| 52545 | GIM_Try, /*On fail goto*//*Label 2832*/ 135204, // Rule ID 4920 // |
| 52546 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 52547 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 52548 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 52549 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 52550 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 52551 | // (mulhs:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UZP2v8i16:{ *:[v8i16] } (SMULLv4i16_v4i32:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v8i16] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v8i16] }:$Rm, dsub:{ *:[i32] })), (SMULLv8i16_v4i32:{ *:[f128] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) |
| 52552 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 52553 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 52554 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 52555 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, |
| 52556 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::SMULLv8i16_v4i32, |
| 52557 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 52558 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 52559 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 52560 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 52561 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, |
| 52562 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 52563 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/2, // Rm |
| 52564 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, |
| 52565 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, |
| 52566 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 52567 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 52568 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/2, // Rn |
| 52569 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::FPR64RegClassID, |
| 52570 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::FPR128RegClassID, |
| 52571 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SMULLv4i16_v4i32, |
| 52572 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 52573 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 52574 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 52575 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52576 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v8i16, |
| 52577 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 52578 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 52579 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, |
| 52580 | GIR_EraseFromParent, /*InsnID*/0, |
| 52581 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52582 | // GIR_Coverage, 4920, |
| 52583 | GIR_Done, |
| 52584 | // Label 2832: @135204 |
| 52585 | GIM_Reject, |
| 52586 | // Label 2828: @135205 |
| 52587 | GIM_Try, /*On fail goto*//*Label 2833*/ 135333, // Rule ID 4919 // |
| 52588 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 52589 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 52590 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 52591 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 52592 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 52593 | // (mulhs:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UZP2v16i8:{ *:[v16i8] } (SMULLv8i8_v8i16:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v16i8] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v16i8] }:$Rm, dsub:{ *:[i32] })), (SMULLv16i8_v8i16:{ *:[f128] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)) |
| 52594 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 52595 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 52596 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 52597 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, |
| 52598 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::SMULLv16i8_v8i16, |
| 52599 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 52600 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 52601 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 52602 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 52603 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, |
| 52604 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 52605 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/2, // Rm |
| 52606 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, |
| 52607 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, |
| 52608 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 52609 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 52610 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/2, // Rn |
| 52611 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, AArch64::FPR64RegClassID, |
| 52612 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, AArch64::FPR128RegClassID, |
| 52613 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SMULLv8i8_v8i16, |
| 52614 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 52615 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 52616 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 52617 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 52618 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UZP2v16i8, |
| 52619 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 52620 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 52621 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/3, /*TempRegFlags*/0, |
| 52622 | GIR_EraseFromParent, /*InsnID*/0, |
| 52623 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52624 | // GIR_Coverage, 4919, |
| 52625 | GIR_Done, |
| 52626 | // Label 2833: @135333 |
| 52627 | GIM_Reject, |
| 52628 | // Label 2829: @135334 |
| 52629 | GIM_Reject, |
| 52630 | // Label 43: @135335 |
| 52631 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 11, /*)*//*default:*//*Label 2841*/ 135572, |
| 52632 | /*GILLT_v2s32*//*Label 2834*/ 135348, |
| 52633 | /*GILLT_v2s64*//*Label 2835*/ 135380, |
| 52634 | /*GILLT_v4s16*//*Label 2836*/ 135412, |
| 52635 | /*GILLT_v4s32*//*Label 2837*/ 135444, |
| 52636 | /*GILLT_v8s8*//*Label 2838*/ 135476, |
| 52637 | /*GILLT_v8s16*//*Label 2839*/ 135508, |
| 52638 | /*GILLT_v16s8*//*Label 2840*/ 135540, |
| 52639 | // Label 2834: @135348 |
| 52640 | GIM_Try, /*On fail goto*//*Label 2842*/ 135379, // Rule ID 4048 // |
| 52641 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 52642 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 52643 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 52644 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 52645 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 52646 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 52647 | // (uaddsat:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (UQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) |
| 52648 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQADDv2i32, |
| 52649 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52650 | // GIR_Coverage, 4048, |
| 52651 | GIR_Done, |
| 52652 | // Label 2842: @135379 |
| 52653 | GIM_Reject, |
| 52654 | // Label 2835: @135380 |
| 52655 | GIM_Try, /*On fail goto*//*Label 2843*/ 135411, // Rule ID 4052 // |
| 52656 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 52657 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 52658 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 52659 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 52660 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 52661 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 52662 | // (uaddsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (UQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) |
| 52663 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQADDv2i64, |
| 52664 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52665 | // GIR_Coverage, 4052, |
| 52666 | GIR_Done, |
| 52667 | // Label 2843: @135411 |
| 52668 | GIM_Reject, |
| 52669 | // Label 2836: @135412 |
| 52670 | GIM_Try, /*On fail goto*//*Label 2844*/ 135443, // Rule ID 4047 // |
| 52671 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 52672 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 52673 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 52674 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 52675 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 52676 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 52677 | // (uaddsat:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (UQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) |
| 52678 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQADDv4i16, |
| 52679 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52680 | // GIR_Coverage, 4047, |
| 52681 | GIR_Done, |
| 52682 | // Label 2844: @135443 |
| 52683 | GIM_Reject, |
| 52684 | // Label 2837: @135444 |
| 52685 | GIM_Try, /*On fail goto*//*Label 2845*/ 135475, // Rule ID 4051 // |
| 52686 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 52687 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 52688 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 52689 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 52690 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 52691 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 52692 | // (uaddsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (UQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) |
| 52693 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQADDv4i32, |
| 52694 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52695 | // GIR_Coverage, 4051, |
| 52696 | GIR_Done, |
| 52697 | // Label 2845: @135475 |
| 52698 | GIM_Reject, |
| 52699 | // Label 2838: @135476 |
| 52700 | GIM_Try, /*On fail goto*//*Label 2846*/ 135507, // Rule ID 4046 // |
| 52701 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 52702 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 52703 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 52704 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 52705 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 52706 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 52707 | // (uaddsat:{ *:[v8i8] } V64:{ *:[v8i8] }:$LHS, V64:{ *:[v8i8] }:$RHS) => (UQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$LHS, V64:{ *:[v8i8] }:$RHS) |
| 52708 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQADDv8i8, |
| 52709 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52710 | // GIR_Coverage, 4046, |
| 52711 | GIR_Done, |
| 52712 | // Label 2846: @135507 |
| 52713 | GIM_Reject, |
| 52714 | // Label 2839: @135508 |
| 52715 | GIM_Try, /*On fail goto*//*Label 2847*/ 135539, // Rule ID 4050 // |
| 52716 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 52717 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 52718 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 52719 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 52720 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 52721 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 52722 | // (uaddsat:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (UQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) |
| 52723 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQADDv8i16, |
| 52724 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52725 | // GIR_Coverage, 4050, |
| 52726 | GIR_Done, |
| 52727 | // Label 2847: @135539 |
| 52728 | GIM_Reject, |
| 52729 | // Label 2840: @135540 |
| 52730 | GIM_Try, /*On fail goto*//*Label 2848*/ 135571, // Rule ID 4049 // |
| 52731 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 52732 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 52733 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 52734 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 52735 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 52736 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 52737 | // (uaddsat:{ *:[v16i8] } V128:{ *:[v16i8] }:$LHS, V128:{ *:[v16i8] }:$RHS) => (UQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$LHS, V128:{ *:[v16i8] }:$RHS) |
| 52738 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQADDv16i8, |
| 52739 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52740 | // GIR_Coverage, 4049, |
| 52741 | GIR_Done, |
| 52742 | // Label 2848: @135571 |
| 52743 | GIM_Reject, |
| 52744 | // Label 2841: @135572 |
| 52745 | GIM_Reject, |
| 52746 | // Label 44: @135573 |
| 52747 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 11, /*)*//*default:*//*Label 2856*/ 135810, |
| 52748 | /*GILLT_v2s32*//*Label 2849*/ 135586, |
| 52749 | /*GILLT_v2s64*//*Label 2850*/ 135618, |
| 52750 | /*GILLT_v4s16*//*Label 2851*/ 135650, |
| 52751 | /*GILLT_v4s32*//*Label 2852*/ 135682, |
| 52752 | /*GILLT_v8s8*//*Label 2853*/ 135714, |
| 52753 | /*GILLT_v8s16*//*Label 2854*/ 135746, |
| 52754 | /*GILLT_v16s8*//*Label 2855*/ 135778, |
| 52755 | // Label 2849: @135586 |
| 52756 | GIM_Try, /*On fail goto*//*Label 2857*/ 135617, // Rule ID 2679 // |
| 52757 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 52758 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 52759 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 52760 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 52761 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 52762 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 52763 | // (saddsat:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (SQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) |
| 52764 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQADDv2i32, |
| 52765 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52766 | // GIR_Coverage, 2679, |
| 52767 | GIR_Done, |
| 52768 | // Label 2857: @135617 |
| 52769 | GIM_Reject, |
| 52770 | // Label 2850: @135618 |
| 52771 | GIM_Try, /*On fail goto*//*Label 2858*/ 135649, // Rule ID 2683 // |
| 52772 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 52773 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 52774 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 52775 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 52776 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 52777 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 52778 | // (saddsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (SQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) |
| 52779 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQADDv2i64, |
| 52780 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52781 | // GIR_Coverage, 2683, |
| 52782 | GIR_Done, |
| 52783 | // Label 2858: @135649 |
| 52784 | GIM_Reject, |
| 52785 | // Label 2851: @135650 |
| 52786 | GIM_Try, /*On fail goto*//*Label 2859*/ 135681, // Rule ID 2678 // |
| 52787 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 52788 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 52789 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 52790 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 52791 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 52792 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 52793 | // (saddsat:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (SQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) |
| 52794 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQADDv4i16, |
| 52795 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52796 | // GIR_Coverage, 2678, |
| 52797 | GIR_Done, |
| 52798 | // Label 2859: @135681 |
| 52799 | GIM_Reject, |
| 52800 | // Label 2852: @135682 |
| 52801 | GIM_Try, /*On fail goto*//*Label 2860*/ 135713, // Rule ID 2682 // |
| 52802 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 52803 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 52804 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 52805 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 52806 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 52807 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 52808 | // (saddsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (SQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) |
| 52809 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQADDv4i32, |
| 52810 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52811 | // GIR_Coverage, 2682, |
| 52812 | GIR_Done, |
| 52813 | // Label 2860: @135713 |
| 52814 | GIM_Reject, |
| 52815 | // Label 2853: @135714 |
| 52816 | GIM_Try, /*On fail goto*//*Label 2861*/ 135745, // Rule ID 2677 // |
| 52817 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 52818 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 52819 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 52820 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 52821 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 52822 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 52823 | // (saddsat:{ *:[v8i8] } V64:{ *:[v8i8] }:$LHS, V64:{ *:[v8i8] }:$RHS) => (SQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$LHS, V64:{ *:[v8i8] }:$RHS) |
| 52824 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQADDv8i8, |
| 52825 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52826 | // GIR_Coverage, 2677, |
| 52827 | GIR_Done, |
| 52828 | // Label 2861: @135745 |
| 52829 | GIM_Reject, |
| 52830 | // Label 2854: @135746 |
| 52831 | GIM_Try, /*On fail goto*//*Label 2862*/ 135777, // Rule ID 2681 // |
| 52832 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 52833 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 52834 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 52835 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 52836 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 52837 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 52838 | // (saddsat:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (SQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) |
| 52839 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQADDv8i16, |
| 52840 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52841 | // GIR_Coverage, 2681, |
| 52842 | GIR_Done, |
| 52843 | // Label 2862: @135777 |
| 52844 | GIM_Reject, |
| 52845 | // Label 2855: @135778 |
| 52846 | GIM_Try, /*On fail goto*//*Label 2863*/ 135809, // Rule ID 2680 // |
| 52847 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 52848 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 52849 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 52850 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 52851 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 52852 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 52853 | // (saddsat:{ *:[v16i8] } V128:{ *:[v16i8] }:$LHS, V128:{ *:[v16i8] }:$RHS) => (SQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$LHS, V128:{ *:[v16i8] }:$RHS) |
| 52854 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQADDv16i8, |
| 52855 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52856 | // GIR_Coverage, 2680, |
| 52857 | GIR_Done, |
| 52858 | // Label 2863: @135809 |
| 52859 | GIM_Reject, |
| 52860 | // Label 2856: @135810 |
| 52861 | GIM_Reject, |
| 52862 | // Label 45: @135811 |
| 52863 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 11, /*)*//*default:*//*Label 2871*/ 136048, |
| 52864 | /*GILLT_v2s32*//*Label 2864*/ 135824, |
| 52865 | /*GILLT_v2s64*//*Label 2865*/ 135856, |
| 52866 | /*GILLT_v4s16*//*Label 2866*/ 135888, |
| 52867 | /*GILLT_v4s32*//*Label 2867*/ 135920, |
| 52868 | /*GILLT_v8s8*//*Label 2868*/ 135952, |
| 52869 | /*GILLT_v8s16*//*Label 2869*/ 135984, |
| 52870 | /*GILLT_v16s8*//*Label 2870*/ 136016, |
| 52871 | // Label 2864: @135824 |
| 52872 | GIM_Try, /*On fail goto*//*Label 2872*/ 135855, // Rule ID 4062 // |
| 52873 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 52874 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 52875 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 52876 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 52877 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 52878 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 52879 | // (usubsat:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (UQSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) |
| 52880 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQSUBv2i32, |
| 52881 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52882 | // GIR_Coverage, 4062, |
| 52883 | GIR_Done, |
| 52884 | // Label 2872: @135855 |
| 52885 | GIM_Reject, |
| 52886 | // Label 2865: @135856 |
| 52887 | GIM_Try, /*On fail goto*//*Label 2873*/ 135887, // Rule ID 4066 // |
| 52888 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 52889 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 52890 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 52891 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 52892 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 52893 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 52894 | // (usubsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (UQSUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) |
| 52895 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQSUBv2i64, |
| 52896 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52897 | // GIR_Coverage, 4066, |
| 52898 | GIR_Done, |
| 52899 | // Label 2873: @135887 |
| 52900 | GIM_Reject, |
| 52901 | // Label 2866: @135888 |
| 52902 | GIM_Try, /*On fail goto*//*Label 2874*/ 135919, // Rule ID 4061 // |
| 52903 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 52904 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 52905 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 52906 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 52907 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 52908 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 52909 | // (usubsat:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (UQSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) |
| 52910 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQSUBv4i16, |
| 52911 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52912 | // GIR_Coverage, 4061, |
| 52913 | GIR_Done, |
| 52914 | // Label 2874: @135919 |
| 52915 | GIM_Reject, |
| 52916 | // Label 2867: @135920 |
| 52917 | GIM_Try, /*On fail goto*//*Label 2875*/ 135951, // Rule ID 4065 // |
| 52918 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 52919 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 52920 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 52921 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 52922 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 52923 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 52924 | // (usubsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (UQSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) |
| 52925 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQSUBv4i32, |
| 52926 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52927 | // GIR_Coverage, 4065, |
| 52928 | GIR_Done, |
| 52929 | // Label 2875: @135951 |
| 52930 | GIM_Reject, |
| 52931 | // Label 2868: @135952 |
| 52932 | GIM_Try, /*On fail goto*//*Label 2876*/ 135983, // Rule ID 4060 // |
| 52933 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 52934 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 52935 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 52936 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 52937 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 52938 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 52939 | // (usubsat:{ *:[v8i8] } V64:{ *:[v8i8] }:$LHS, V64:{ *:[v8i8] }:$RHS) => (UQSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$LHS, V64:{ *:[v8i8] }:$RHS) |
| 52940 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQSUBv8i8, |
| 52941 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52942 | // GIR_Coverage, 4060, |
| 52943 | GIR_Done, |
| 52944 | // Label 2876: @135983 |
| 52945 | GIM_Reject, |
| 52946 | // Label 2869: @135984 |
| 52947 | GIM_Try, /*On fail goto*//*Label 2877*/ 136015, // Rule ID 4064 // |
| 52948 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 52949 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 52950 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 52951 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 52952 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 52953 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 52954 | // (usubsat:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (UQSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) |
| 52955 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQSUBv8i16, |
| 52956 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52957 | // GIR_Coverage, 4064, |
| 52958 | GIR_Done, |
| 52959 | // Label 2877: @136015 |
| 52960 | GIM_Reject, |
| 52961 | // Label 2870: @136016 |
| 52962 | GIM_Try, /*On fail goto*//*Label 2878*/ 136047, // Rule ID 4063 // |
| 52963 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 52964 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 52965 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 52966 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 52967 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 52968 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 52969 | // (usubsat:{ *:[v16i8] } V128:{ *:[v16i8] }:$LHS, V128:{ *:[v16i8] }:$RHS) => (UQSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$LHS, V128:{ *:[v16i8] }:$RHS) |
| 52970 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UQSUBv16i8, |
| 52971 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52972 | // GIR_Coverage, 4063, |
| 52973 | GIR_Done, |
| 52974 | // Label 2878: @136047 |
| 52975 | GIM_Reject, |
| 52976 | // Label 2871: @136048 |
| 52977 | GIM_Reject, |
| 52978 | // Label 46: @136049 |
| 52979 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 11, /*)*//*default:*//*Label 2886*/ 136286, |
| 52980 | /*GILLT_v2s32*//*Label 2879*/ 136062, |
| 52981 | /*GILLT_v2s64*//*Label 2880*/ 136094, |
| 52982 | /*GILLT_v4s16*//*Label 2881*/ 136126, |
| 52983 | /*GILLT_v4s32*//*Label 2882*/ 136158, |
| 52984 | /*GILLT_v8s8*//*Label 2883*/ 136190, |
| 52985 | /*GILLT_v8s16*//*Label 2884*/ 136222, |
| 52986 | /*GILLT_v16s8*//*Label 2885*/ 136254, |
| 52987 | // Label 2879: @136062 |
| 52988 | GIM_Try, /*On fail goto*//*Label 2887*/ 136093, // Rule ID 4055 // |
| 52989 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 52990 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 52991 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 52992 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 52993 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 52994 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 52995 | // (ssubsat:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (SQSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) |
| 52996 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQSUBv2i32, |
| 52997 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 52998 | // GIR_Coverage, 4055, |
| 52999 | GIR_Done, |
| 53000 | // Label 2887: @136093 |
| 53001 | GIM_Reject, |
| 53002 | // Label 2880: @136094 |
| 53003 | GIM_Try, /*On fail goto*//*Label 2888*/ 136125, // Rule ID 4059 // |
| 53004 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 53005 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 53006 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 53007 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 53008 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 53009 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 53010 | // (ssubsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (SQSUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) |
| 53011 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQSUBv2i64, |
| 53012 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53013 | // GIR_Coverage, 4059, |
| 53014 | GIR_Done, |
| 53015 | // Label 2888: @136125 |
| 53016 | GIM_Reject, |
| 53017 | // Label 2881: @136126 |
| 53018 | GIM_Try, /*On fail goto*//*Label 2889*/ 136157, // Rule ID 4054 // |
| 53019 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 53020 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 53021 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 53022 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 53023 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 53024 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 53025 | // (ssubsat:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (SQSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) |
| 53026 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQSUBv4i16, |
| 53027 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53028 | // GIR_Coverage, 4054, |
| 53029 | GIR_Done, |
| 53030 | // Label 2889: @136157 |
| 53031 | GIM_Reject, |
| 53032 | // Label 2882: @136158 |
| 53033 | GIM_Try, /*On fail goto*//*Label 2890*/ 136189, // Rule ID 4058 // |
| 53034 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 53035 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 53036 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 53037 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 53038 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 53039 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 53040 | // (ssubsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (SQSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) |
| 53041 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQSUBv4i32, |
| 53042 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53043 | // GIR_Coverage, 4058, |
| 53044 | GIR_Done, |
| 53045 | // Label 2890: @136189 |
| 53046 | GIM_Reject, |
| 53047 | // Label 2883: @136190 |
| 53048 | GIM_Try, /*On fail goto*//*Label 2891*/ 136221, // Rule ID 4053 // |
| 53049 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 53050 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 53051 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 53052 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 53053 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 53054 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 53055 | // (ssubsat:{ *:[v8i8] } V64:{ *:[v8i8] }:$LHS, V64:{ *:[v8i8] }:$RHS) => (SQSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$LHS, V64:{ *:[v8i8] }:$RHS) |
| 53056 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQSUBv8i8, |
| 53057 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53058 | // GIR_Coverage, 4053, |
| 53059 | GIR_Done, |
| 53060 | // Label 2891: @136221 |
| 53061 | GIM_Reject, |
| 53062 | // Label 2884: @136222 |
| 53063 | GIM_Try, /*On fail goto*//*Label 2892*/ 136253, // Rule ID 4057 // |
| 53064 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 53065 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 53066 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 53067 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 53068 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 53069 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 53070 | // (ssubsat:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (SQSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) |
| 53071 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQSUBv8i16, |
| 53072 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53073 | // GIR_Coverage, 4057, |
| 53074 | GIR_Done, |
| 53075 | // Label 2892: @136253 |
| 53076 | GIM_Reject, |
| 53077 | // Label 2885: @136254 |
| 53078 | GIM_Try, /*On fail goto*//*Label 2893*/ 136285, // Rule ID 4056 // |
| 53079 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 53080 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 53081 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 53082 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 53083 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 53084 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 53085 | // (ssubsat:{ *:[v16i8] } V128:{ *:[v16i8] }:$LHS, V128:{ *:[v16i8] }:$RHS) => (SQSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$LHS, V128:{ *:[v16i8] }:$RHS) |
| 53086 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SQSUBv16i8, |
| 53087 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53088 | // GIR_Coverage, 4056, |
| 53089 | GIR_Done, |
| 53090 | // Label 2893: @136285 |
| 53091 | GIM_Reject, |
| 53092 | // Label 2886: @136286 |
| 53093 | GIM_Reject, |
| 53094 | // Label 47: @136287 |
| 53095 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 2902*/ 137180, |
| 53096 | /*GILLT_s16*//*Label 2894*/ 136303, |
| 53097 | /*GILLT_s32*//*Label 2895*/ 136514, |
| 53098 | /*GILLT_s64*//*Label 2896*/ 136855, 0, |
| 53099 | /*GILLT_v2s32*//*Label 2897*/ 137020, |
| 53100 | /*GILLT_v2s64*//*Label 2898*/ 137052, |
| 53101 | /*GILLT_v4s16*//*Label 2899*/ 137084, |
| 53102 | /*GILLT_v4s32*//*Label 2900*/ 137116, 0, |
| 53103 | /*GILLT_v8s16*//*Label 2901*/ 137148, |
| 53104 | // Label 2894: @136303 |
| 53105 | GIM_Try, /*On fail goto*//*Label 2903*/ 136513, |
| 53106 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 53107 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 53108 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 53109 | GIM_Try, /*On fail goto*//*Label 2904*/ 136405, // Rule ID 5334 // |
| 53110 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 53111 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 53112 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 53113 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 53114 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 53115 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 0, |
| 53116 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 53117 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 53118 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 53119 | // MIs[2] Rn |
| 53120 | GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 53121 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, |
| 53122 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 53123 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 53124 | // (fadd:{ *:[f16] } (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 1:{ *:[i64] })) => (FADDPv2i16p:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })) |
| 53125 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 53126 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 53127 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 53128 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/2, // Rn |
| 53129 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, |
| 53130 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 53131 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i16p, |
| 53132 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 53133 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 53134 | GIR_EraseFromParent, /*InsnID*/0, |
| 53135 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53136 | // GIR_Coverage, 5334, |
| 53137 | GIR_Done, |
| 53138 | // Label 2904: @136405 |
| 53139 | GIM_Try, /*On fail goto*//*Label 2905*/ 136493, // Rule ID 8019 // |
| 53140 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 53141 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 53142 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 53143 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 53144 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 53145 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, |
| 53146 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 53147 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 53148 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 53149 | // MIs[2] Rn |
| 53150 | GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 53151 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 0, |
| 53152 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 53153 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 53154 | // (fadd:{ *:[f16] } (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] })) => (FADDPv2i16p:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })) |
| 53155 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 53156 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 53157 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 53158 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/2, // Rn |
| 53159 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, |
| 53160 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 53161 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i16p, |
| 53162 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 53163 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 53164 | GIR_EraseFromParent, /*InsnID*/0, |
| 53165 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53166 | // GIR_Coverage, 8019, |
| 53167 | GIR_Done, |
| 53168 | // Label 2905: @136493 |
| 53169 | GIM_Try, /*On fail goto*//*Label 2906*/ 136512, // Rule ID 516 // |
| 53170 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 53171 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 53172 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 53173 | // (fadd:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FADDHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) |
| 53174 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDHrr, |
| 53175 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53176 | // GIR_Coverage, 516, |
| 53177 | GIR_Done, |
| 53178 | // Label 2906: @136512 |
| 53179 | GIM_Reject, |
| 53180 | // Label 2903: @136513 |
| 53181 | GIM_Reject, |
| 53182 | // Label 2895: @136514 |
| 53183 | GIM_Try, /*On fail goto*//*Label 2907*/ 136854, |
| 53184 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 53185 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 53186 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 53187 | GIM_Try, /*On fail goto*//*Label 2908*/ 136593, // Rule ID 2661 // |
| 53188 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 53189 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 53190 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 53191 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 53192 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 53193 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 0, |
| 53194 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 53195 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 53196 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 53197 | // MIs[2] Rn |
| 53198 | GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 53199 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, |
| 53200 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 53201 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 53202 | // (fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn, 1:{ *:[i64] })) => (FADDPv2i32p:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn) |
| 53203 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i32p, |
| 53204 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 53205 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 53206 | GIR_EraseFromParent, /*InsnID*/0, |
| 53207 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53208 | // GIR_Coverage, 2661, |
| 53209 | GIR_Done, |
| 53210 | // Label 2908: @136593 |
| 53211 | GIM_Try, /*On fail goto*//*Label 2909*/ 136681, // Rule ID 5333 // |
| 53212 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 53213 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 53214 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 53215 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 53216 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 53217 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 0, |
| 53218 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 53219 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 53220 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 53221 | // MIs[2] Rn |
| 53222 | GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 53223 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, |
| 53224 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 53225 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 53226 | // (fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 1:{ *:[i64] })) => (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v4f32] }:$Rn, dsub:{ *:[i32] })) |
| 53227 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 53228 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 53229 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 53230 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/2, // Rn |
| 53231 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, |
| 53232 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 53233 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i32p, |
| 53234 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 53235 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 53236 | GIR_EraseFromParent, /*InsnID*/0, |
| 53237 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53238 | // GIR_Coverage, 5333, |
| 53239 | GIR_Done, |
| 53240 | // Label 2909: @136681 |
| 53241 | GIM_Try, /*On fail goto*//*Label 2910*/ 136746, // Rule ID 7814 // |
| 53242 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 53243 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 53244 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 53245 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 53246 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 53247 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, |
| 53248 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 53249 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 53250 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 53251 | // MIs[2] Rn |
| 53252 | GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 53253 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 0, |
| 53254 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 53255 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 53256 | // (fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn, 0:{ *:[i64] })) => (FADDPv2i32p:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn) |
| 53257 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i32p, |
| 53258 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 53259 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 53260 | GIR_EraseFromParent, /*InsnID*/0, |
| 53261 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53262 | // GIR_Coverage, 7814, |
| 53263 | GIR_Done, |
| 53264 | // Label 2910: @136746 |
| 53265 | GIM_Try, /*On fail goto*//*Label 2911*/ 136834, // Rule ID 8018 // |
| 53266 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 53267 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 53268 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 53269 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 53270 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 53271 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, |
| 53272 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 53273 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 53274 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 53275 | // MIs[2] Rn |
| 53276 | GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 53277 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 0, |
| 53278 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 53279 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 53280 | // (fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] })) => (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v4f32] }:$Rn, dsub:{ *:[i32] })) |
| 53281 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 53282 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 53283 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 53284 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/2, // Rn |
| 53285 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, |
| 53286 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 53287 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i32p, |
| 53288 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 53289 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 53290 | GIR_EraseFromParent, /*InsnID*/0, |
| 53291 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53292 | // GIR_Coverage, 8018, |
| 53293 | GIR_Done, |
| 53294 | // Label 2911: @136834 |
| 53295 | GIM_Try, /*On fail goto*//*Label 2912*/ 136853, // Rule ID 517 // |
| 53296 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 53297 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 53298 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 53299 | // (fadd:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FADDSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) |
| 53300 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDSrr, |
| 53301 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53302 | // GIR_Coverage, 517, |
| 53303 | GIR_Done, |
| 53304 | // Label 2912: @136853 |
| 53305 | GIM_Reject, |
| 53306 | // Label 2907: @136854 |
| 53307 | GIM_Reject, |
| 53308 | // Label 2896: @136855 |
| 53309 | GIM_Try, /*On fail goto*//*Label 2913*/ 137019, |
| 53310 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 53311 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 53312 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 53313 | GIM_Try, /*On fail goto*//*Label 2914*/ 136934, // Rule ID 5332 // |
| 53314 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 53315 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 53316 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 53317 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 53318 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 53319 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 0, |
| 53320 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 53321 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 53322 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 53323 | // MIs[2] Rn |
| 53324 | GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 53325 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, |
| 53326 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 53327 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 53328 | // (fadd:{ *:[f64] } (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 1:{ *:[i64] })) => (FADDPv2i64p:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn) |
| 53329 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i64p, |
| 53330 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 53331 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 53332 | GIR_EraseFromParent, /*InsnID*/0, |
| 53333 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53334 | // GIR_Coverage, 5332, |
| 53335 | GIR_Done, |
| 53336 | // Label 2914: @136934 |
| 53337 | GIM_Try, /*On fail goto*//*Label 2915*/ 136999, // Rule ID 8017 // |
| 53338 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 53339 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 53340 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 53341 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 53342 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 53343 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, |
| 53344 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 53345 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 53346 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 53347 | // MIs[2] Rn |
| 53348 | GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 53349 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 0, |
| 53350 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 53351 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 53352 | // (fadd:{ *:[f64] } (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] })) => (FADDPv2i64p:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn) |
| 53353 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FADDPv2i64p, |
| 53354 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 53355 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 53356 | GIR_EraseFromParent, /*InsnID*/0, |
| 53357 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53358 | // GIR_Coverage, 8017, |
| 53359 | GIR_Done, |
| 53360 | // Label 2915: @136999 |
| 53361 | GIM_Try, /*On fail goto*//*Label 2916*/ 137018, // Rule ID 518 // |
| 53362 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 53363 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 53364 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 53365 | // (fadd:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FADDDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) |
| 53366 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDDrr, |
| 53367 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53368 | // GIR_Coverage, 518, |
| 53369 | GIR_Done, |
| 53370 | // Label 2916: @137018 |
| 53371 | GIM_Reject, |
| 53372 | // Label 2913: @137019 |
| 53373 | GIM_Reject, |
| 53374 | // Label 2897: @137020 |
| 53375 | GIM_Try, /*On fail goto*//*Label 2917*/ 137051, // Rule ID 968 // |
| 53376 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 53377 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 53378 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 53379 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 53380 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 53381 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 53382 | // (fadd:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FADDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) |
| 53383 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDv2f32, |
| 53384 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53385 | // GIR_Coverage, 968, |
| 53386 | GIR_Done, |
| 53387 | // Label 2917: @137051 |
| 53388 | GIM_Reject, |
| 53389 | // Label 2898: @137052 |
| 53390 | GIM_Try, /*On fail goto*//*Label 2918*/ 137083, // Rule ID 970 // |
| 53391 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 53392 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 53393 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 53394 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 53395 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 53396 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 53397 | // (fadd:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FADDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) |
| 53398 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDv2f64, |
| 53399 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53400 | // GIR_Coverage, 970, |
| 53401 | GIR_Done, |
| 53402 | // Label 2918: @137083 |
| 53403 | GIM_Reject, |
| 53404 | // Label 2899: @137084 |
| 53405 | GIM_Try, /*On fail goto*//*Label 2919*/ 137115, // Rule ID 966 // |
| 53406 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 53407 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 53408 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 53409 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 53410 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 53411 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 53412 | // (fadd:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FADDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 53413 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDv4f16, |
| 53414 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53415 | // GIR_Coverage, 966, |
| 53416 | GIR_Done, |
| 53417 | // Label 2919: @137115 |
| 53418 | GIM_Reject, |
| 53419 | // Label 2900: @137116 |
| 53420 | GIM_Try, /*On fail goto*//*Label 2920*/ 137147, // Rule ID 969 // |
| 53421 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 53422 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 53423 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 53424 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 53425 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 53426 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 53427 | // (fadd:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FADDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) |
| 53428 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDv4f32, |
| 53429 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53430 | // GIR_Coverage, 969, |
| 53431 | GIR_Done, |
| 53432 | // Label 2920: @137147 |
| 53433 | GIM_Reject, |
| 53434 | // Label 2901: @137148 |
| 53435 | GIM_Try, /*On fail goto*//*Label 2921*/ 137179, // Rule ID 967 // |
| 53436 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 53437 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 53438 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 53439 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 53440 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 53441 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 53442 | // (fadd:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FADDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 53443 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FADDv8f16, |
| 53444 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53445 | // GIR_Coverage, 967, |
| 53446 | GIR_Done, |
| 53447 | // Label 2921: @137179 |
| 53448 | GIM_Reject, |
| 53449 | // Label 2902: @137180 |
| 53450 | GIM_Reject, |
| 53451 | // Label 48: @137181 |
| 53452 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 2930*/ 137453, |
| 53453 | /*GILLT_s16*//*Label 2922*/ 137197, |
| 53454 | /*GILLT_s32*//*Label 2923*/ 137229, |
| 53455 | /*GILLT_s64*//*Label 2924*/ 137261, 0, |
| 53456 | /*GILLT_v2s32*//*Label 2925*/ 137293, |
| 53457 | /*GILLT_v2s64*//*Label 2926*/ 137325, |
| 53458 | /*GILLT_v4s16*//*Label 2927*/ 137357, |
| 53459 | /*GILLT_v4s32*//*Label 2928*/ 137389, 0, |
| 53460 | /*GILLT_v8s16*//*Label 2929*/ 137421, |
| 53461 | // Label 2922: @137197 |
| 53462 | GIM_Try, /*On fail goto*//*Label 2931*/ 137228, // Rule ID 540 // |
| 53463 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 53464 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 53465 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 53466 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 53467 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 53468 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 53469 | // (fsub:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FSUBHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) |
| 53470 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBHrr, |
| 53471 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53472 | // GIR_Coverage, 540, |
| 53473 | GIR_Done, |
| 53474 | // Label 2931: @137228 |
| 53475 | GIM_Reject, |
| 53476 | // Label 2923: @137229 |
| 53477 | GIM_Try, /*On fail goto*//*Label 2932*/ 137260, // Rule ID 541 // |
| 53478 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 53479 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 53480 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 53481 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 53482 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 53483 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 53484 | // (fsub:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FSUBSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) |
| 53485 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBSrr, |
| 53486 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53487 | // GIR_Coverage, 541, |
| 53488 | GIR_Done, |
| 53489 | // Label 2932: @137260 |
| 53490 | GIM_Reject, |
| 53491 | // Label 2924: @137261 |
| 53492 | GIM_Try, /*On fail goto*//*Label 2933*/ 137292, // Rule ID 542 // |
| 53493 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 53494 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 53495 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 53496 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 53497 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 53498 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 53499 | // (fsub:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FSUBDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) |
| 53500 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBDrr, |
| 53501 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53502 | // GIR_Coverage, 542, |
| 53503 | GIR_Done, |
| 53504 | // Label 2933: @137292 |
| 53505 | GIM_Reject, |
| 53506 | // Label 2925: @137293 |
| 53507 | GIM_Try, /*On fail goto*//*Label 2934*/ 137324, // Rule ID 1063 // |
| 53508 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 53509 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 53510 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 53511 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 53512 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 53513 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 53514 | // (fsub:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FSUBv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) |
| 53515 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBv2f32, |
| 53516 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53517 | // GIR_Coverage, 1063, |
| 53518 | GIR_Done, |
| 53519 | // Label 2934: @137324 |
| 53520 | GIM_Reject, |
| 53521 | // Label 2926: @137325 |
| 53522 | GIM_Try, /*On fail goto*//*Label 2935*/ 137356, // Rule ID 1065 // |
| 53523 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 53524 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 53525 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 53526 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 53527 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 53528 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 53529 | // (fsub:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FSUBv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) |
| 53530 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBv2f64, |
| 53531 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53532 | // GIR_Coverage, 1065, |
| 53533 | GIR_Done, |
| 53534 | // Label 2935: @137356 |
| 53535 | GIM_Reject, |
| 53536 | // Label 2927: @137357 |
| 53537 | GIM_Try, /*On fail goto*//*Label 2936*/ 137388, // Rule ID 1061 // |
| 53538 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 53539 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 53540 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 53541 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 53542 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 53543 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 53544 | // (fsub:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FSUBv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 53545 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBv4f16, |
| 53546 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53547 | // GIR_Coverage, 1061, |
| 53548 | GIR_Done, |
| 53549 | // Label 2936: @137388 |
| 53550 | GIM_Reject, |
| 53551 | // Label 2928: @137389 |
| 53552 | GIM_Try, /*On fail goto*//*Label 2937*/ 137420, // Rule ID 1064 // |
| 53553 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 53554 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 53555 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 53556 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 53557 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 53558 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 53559 | // (fsub:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FSUBv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) |
| 53560 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBv4f32, |
| 53561 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53562 | // GIR_Coverage, 1064, |
| 53563 | GIR_Done, |
| 53564 | // Label 2937: @137420 |
| 53565 | GIM_Reject, |
| 53566 | // Label 2929: @137421 |
| 53567 | GIM_Try, /*On fail goto*//*Label 2938*/ 137452, // Rule ID 1062 // |
| 53568 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 53569 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 53570 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 53571 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 53572 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 53573 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 53574 | // (fsub:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FSUBv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 53575 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSUBv8f16, |
| 53576 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53577 | // GIR_Coverage, 1062, |
| 53578 | GIR_Done, |
| 53579 | // Label 2938: @137452 |
| 53580 | GIM_Reject, |
| 53581 | // Label 2930: @137453 |
| 53582 | GIM_Reject, |
| 53583 | // Label 49: @137454 |
| 53584 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 2947*/ 139320, |
| 53585 | /*GILLT_s16*//*Label 2939*/ 137470, |
| 53586 | /*GILLT_s32*//*Label 2940*/ 137633, |
| 53587 | /*GILLT_s64*//*Label 2941*/ 137796, 0, |
| 53588 | /*GILLT_v2s32*//*Label 2942*/ 137959, |
| 53589 | /*GILLT_v2s64*//*Label 2943*/ 138304, |
| 53590 | /*GILLT_v4s16*//*Label 2944*/ 138649, |
| 53591 | /*GILLT_v4s32*//*Label 2945*/ 138812, 0, |
| 53592 | /*GILLT_v8s16*//*Label 2946*/ 139157, |
| 53593 | // Label 2939: @137470 |
| 53594 | GIM_Try, /*On fail goto*//*Label 2948*/ 137632, |
| 53595 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 53596 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 53597 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 53598 | GIM_Try, /*On fail goto*//*Label 2949*/ 137548, // Rule ID 7767 // |
| 53599 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 53600 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 53601 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 53602 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 53603 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 53604 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 53605 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 53606 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 53607 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 53608 | // MIs[2] Operand 1 |
| 53609 | // No operand predicates |
| 53610 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 53611 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 53612 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 53613 | // (fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16Op:{ *:[f16] }:$Rn) => (FMULv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 53614 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i16_indexed, |
| 53615 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 53616 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 53617 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 53618 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 53619 | GIR_EraseFromParent, /*InsnID*/0, |
| 53620 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53621 | // GIR_Coverage, 7767, |
| 53622 | GIR_Done, |
| 53623 | // Label 2949: @137548 |
| 53624 | GIM_Try, /*On fail goto*//*Label 2950*/ 137612, // Rule ID 1701 // |
| 53625 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 53626 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 53627 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 53628 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 53629 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 53630 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 53631 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 53632 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 53633 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 53634 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 53635 | // MIs[2] Operand 1 |
| 53636 | // No operand predicates |
| 53637 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 53638 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 53639 | // (fmul:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMULv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 53640 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i16_indexed, |
| 53641 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 53642 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 53643 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 53644 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 53645 | GIR_EraseFromParent, /*InsnID*/0, |
| 53646 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53647 | // GIR_Coverage, 1701, |
| 53648 | GIR_Done, |
| 53649 | // Label 2950: @137612 |
| 53650 | GIM_Try, /*On fail goto*//*Label 2951*/ 137631, // Rule ID 534 // |
| 53651 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 53652 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 53653 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 53654 | // (fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) |
| 53655 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULHrr, |
| 53656 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53657 | // GIR_Coverage, 534, |
| 53658 | GIR_Done, |
| 53659 | // Label 2951: @137631 |
| 53660 | GIM_Reject, |
| 53661 | // Label 2948: @137632 |
| 53662 | GIM_Reject, |
| 53663 | // Label 2940: @137633 |
| 53664 | GIM_Try, /*On fail goto*//*Label 2952*/ 137795, |
| 53665 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 53666 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 53667 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 53668 | GIM_Try, /*On fail goto*//*Label 2953*/ 137711, // Rule ID 7768 // |
| 53669 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 53670 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 53671 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 53672 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 53673 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 53674 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 53675 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 53676 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 53677 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 53678 | // MIs[2] Operand 1 |
| 53679 | // No operand predicates |
| 53680 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 53681 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 53682 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 53683 | // (fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32Op:{ *:[f32] }:$Rn) => (FMULv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 53684 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i32_indexed, |
| 53685 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 53686 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 53687 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 53688 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 53689 | GIR_EraseFromParent, /*InsnID*/0, |
| 53690 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53691 | // GIR_Coverage, 7768, |
| 53692 | GIR_Done, |
| 53693 | // Label 2953: @137711 |
| 53694 | GIM_Try, /*On fail goto*//*Label 2954*/ 137775, // Rule ID 1702 // |
| 53695 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 53696 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 53697 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 53698 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 53699 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 53700 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 53701 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 53702 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 53703 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 53704 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 53705 | // MIs[2] Operand 1 |
| 53706 | // No operand predicates |
| 53707 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 53708 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 53709 | // (fmul:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (FMULv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 53710 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i32_indexed, |
| 53711 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 53712 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 53713 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 53714 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 53715 | GIR_EraseFromParent, /*InsnID*/0, |
| 53716 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53717 | // GIR_Coverage, 1702, |
| 53718 | GIR_Done, |
| 53719 | // Label 2954: @137775 |
| 53720 | GIM_Try, /*On fail goto*//*Label 2955*/ 137794, // Rule ID 535 // |
| 53721 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 53722 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 53723 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 53724 | // (fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) |
| 53725 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULSrr, |
| 53726 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53727 | // GIR_Coverage, 535, |
| 53728 | GIR_Done, |
| 53729 | // Label 2955: @137794 |
| 53730 | GIM_Reject, |
| 53731 | // Label 2952: @137795 |
| 53732 | GIM_Reject, |
| 53733 | // Label 2941: @137796 |
| 53734 | GIM_Try, /*On fail goto*//*Label 2956*/ 137958, |
| 53735 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 53736 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 53737 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 53738 | GIM_Try, /*On fail goto*//*Label 2957*/ 137874, // Rule ID 7769 // |
| 53739 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 53740 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 53741 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 53742 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 53743 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 53744 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 53745 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 53746 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 53747 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 53748 | // MIs[2] Operand 1 |
| 53749 | // No operand predicates |
| 53750 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 53751 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 53752 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 53753 | // (fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64Op:{ *:[f64] }:$Rn) => (FMULv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 53754 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i64_indexed, |
| 53755 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 53756 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 53757 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 53758 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 53759 | GIR_EraseFromParent, /*InsnID*/0, |
| 53760 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53761 | // GIR_Coverage, 7769, |
| 53762 | GIR_Done, |
| 53763 | // Label 2957: @137874 |
| 53764 | GIM_Try, /*On fail goto*//*Label 2958*/ 137938, // Rule ID 1703 // |
| 53765 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 53766 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 53767 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 53768 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 53769 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 53770 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 53771 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 53772 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 53773 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 53774 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 53775 | // MIs[2] Operand 1 |
| 53776 | // No operand predicates |
| 53777 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 53778 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 53779 | // (fmul:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)) => (FMULv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 53780 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv1i64_indexed, |
| 53781 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 53782 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 53783 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 53784 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 53785 | GIR_EraseFromParent, /*InsnID*/0, |
| 53786 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53787 | // GIR_Coverage, 1703, |
| 53788 | GIR_Done, |
| 53789 | // Label 2958: @137938 |
| 53790 | GIM_Try, /*On fail goto*//*Label 2959*/ 137957, // Rule ID 536 // |
| 53791 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 53792 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 53793 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 53794 | // (fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) |
| 53795 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULDrr, |
| 53796 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53797 | // GIR_Coverage, 536, |
| 53798 | GIR_Done, |
| 53799 | // Label 2959: @137957 |
| 53800 | GIM_Reject, |
| 53801 | // Label 2956: @137958 |
| 53802 | GIM_Reject, |
| 53803 | // Label 2942: @137959 |
| 53804 | GIM_Try, /*On fail goto*//*Label 2960*/ 138303, |
| 53805 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 53806 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 53807 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 53808 | GIM_Try, /*On fail goto*//*Label 2961*/ 138037, // Rule ID 7764 // |
| 53809 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 53810 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 53811 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 53812 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 53813 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 53814 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 53815 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 53816 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 53817 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 53818 | // MIs[2] Operand 1 |
| 53819 | // No operand predicates |
| 53820 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 53821 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 53822 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 53823 | // (fmul:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rn) => (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 53824 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv2i32_indexed, |
| 53825 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 53826 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 53827 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 53828 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 53829 | GIR_EraseFromParent, /*InsnID*/0, |
| 53830 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53831 | // GIR_Coverage, 7764, |
| 53832 | GIR_Done, |
| 53833 | // Label 2961: @138037 |
| 53834 | GIM_Try, /*On fail goto*//*Label 2962*/ 138101, // Rule ID 1698 // |
| 53835 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 53836 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 53837 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 53838 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 53839 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 53840 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 53841 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 53842 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 53843 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 53844 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 53845 | // MIs[2] Operand 1 |
| 53846 | // No operand predicates |
| 53847 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 53848 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 53849 | // (fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 53850 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv2i32_indexed, |
| 53851 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 53852 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 53853 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 53854 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 53855 | GIR_EraseFromParent, /*InsnID*/0, |
| 53856 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53857 | // GIR_Coverage, 1698, |
| 53858 | GIR_Done, |
| 53859 | // Label 2962: @138101 |
| 53860 | GIM_Try, /*On fail goto*//*Label 2963*/ 138192, // Rule ID 8009 // |
| 53861 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 53862 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 53863 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 53864 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 53865 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 53866 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 53867 | // (fmul:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rn) => (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) |
| 53868 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 53869 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 53870 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 53871 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 53872 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 53873 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 53874 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 53875 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 53876 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 53877 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 53878 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 53879 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 53880 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 53881 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv2i32_indexed, |
| 53882 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 53883 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 53884 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 53885 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 53886 | GIR_EraseFromParent, /*InsnID*/0, |
| 53887 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53888 | // GIR_Coverage, 8009, |
| 53889 | GIR_Done, |
| 53890 | // Label 2963: @138192 |
| 53891 | GIM_Try, /*On fail goto*//*Label 2964*/ 138283, // Rule ID 4689 // |
| 53892 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 53893 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 53894 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 53895 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 53896 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 53897 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 53898 | // (fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } FPR32:{ *:[f32] }:$Rm)) => (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) |
| 53899 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 53900 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 53901 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 53902 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 53903 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 53904 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 53905 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 53906 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 53907 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 53908 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 53909 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 53910 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 53911 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 53912 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv2i32_indexed, |
| 53913 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 53914 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 53915 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 53916 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 53917 | GIR_EraseFromParent, /*InsnID*/0, |
| 53918 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53919 | // GIR_Coverage, 4689, |
| 53920 | GIR_Done, |
| 53921 | // Label 2964: @138283 |
| 53922 | GIM_Try, /*On fail goto*//*Label 2965*/ 138302, // Rule ID 1048 // |
| 53923 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 53924 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 53925 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 53926 | // (fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMULv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) |
| 53927 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULv2f32, |
| 53928 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53929 | // GIR_Coverage, 1048, |
| 53930 | GIR_Done, |
| 53931 | // Label 2965: @138302 |
| 53932 | GIM_Reject, |
| 53933 | // Label 2960: @138303 |
| 53934 | GIM_Reject, |
| 53935 | // Label 2943: @138304 |
| 53936 | GIM_Try, /*On fail goto*//*Label 2966*/ 138648, |
| 53937 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 53938 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 53939 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 53940 | GIM_Try, /*On fail goto*//*Label 2967*/ 138382, // Rule ID 7766 // |
| 53941 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 53942 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 53943 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE64, |
| 53944 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 53945 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 53946 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 53947 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 53948 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 53949 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 53950 | // MIs[2] Operand 1 |
| 53951 | // No operand predicates |
| 53952 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 53953 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 53954 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 53955 | // (fmul:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rn) => (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 53956 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv2i64_indexed, |
| 53957 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 53958 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 53959 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 53960 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 53961 | GIR_EraseFromParent, /*InsnID*/0, |
| 53962 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53963 | // GIR_Coverage, 7766, |
| 53964 | GIR_Done, |
| 53965 | // Label 2967: @138382 |
| 53966 | GIM_Try, /*On fail goto*//*Label 2968*/ 138446, // Rule ID 1700 // |
| 53967 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 53968 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 53969 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 53970 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE64, |
| 53971 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 53972 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 53973 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 53974 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 53975 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 53976 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 53977 | // MIs[2] Operand 1 |
| 53978 | // No operand predicates |
| 53979 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 53980 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 53981 | // (fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)) => (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 53982 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv2i64_indexed, |
| 53983 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 53984 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 53985 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 53986 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 53987 | GIR_EraseFromParent, /*InsnID*/0, |
| 53988 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 53989 | // GIR_Coverage, 1700, |
| 53990 | GIR_Done, |
| 53991 | // Label 2968: @138446 |
| 53992 | GIM_Try, /*On fail goto*//*Label 2969*/ 138537, // Rule ID 8011 // |
| 53993 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 53994 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 53995 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 53996 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 53997 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 53998 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 53999 | // (fmul:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rn) => (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR64:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 54000 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 54001 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 54002 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 54003 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 54004 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 54005 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 54006 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 54007 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 54008 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 54009 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 54010 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 54011 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 54012 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 54013 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv2i64_indexed, |
| 54014 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 54015 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 54016 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 54017 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 54018 | GIR_EraseFromParent, /*InsnID*/0, |
| 54019 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54020 | // GIR_Coverage, 8011, |
| 54021 | GIR_Done, |
| 54022 | // Label 2969: @138537 |
| 54023 | GIM_Try, /*On fail goto*//*Label 2970*/ 138628, // Rule ID 4691 // |
| 54024 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 54025 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 54026 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 54027 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 54028 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 54029 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54030 | // (fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } FPR64:{ *:[f64] }:$Rm)) => (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR64:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 54031 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 54032 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 54033 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 54034 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 54035 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 54036 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 54037 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 54038 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 54039 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 54040 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 54041 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 54042 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 54043 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 54044 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv2i64_indexed, |
| 54045 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 54046 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 54047 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 54048 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 54049 | GIR_EraseFromParent, /*InsnID*/0, |
| 54050 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54051 | // GIR_Coverage, 4691, |
| 54052 | GIR_Done, |
| 54053 | // Label 2970: @138628 |
| 54054 | GIM_Try, /*On fail goto*//*Label 2971*/ 138647, // Rule ID 1050 // |
| 54055 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 54056 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 54057 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 54058 | // (fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMULv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) |
| 54059 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULv2f64, |
| 54060 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54061 | // GIR_Coverage, 1050, |
| 54062 | GIR_Done, |
| 54063 | // Label 2971: @138647 |
| 54064 | GIM_Reject, |
| 54065 | // Label 2966: @138648 |
| 54066 | GIM_Reject, |
| 54067 | // Label 2944: @138649 |
| 54068 | GIM_Try, /*On fail goto*//*Label 2972*/ 138811, |
| 54069 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 54070 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 54071 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 54072 | GIM_Try, /*On fail goto*//*Label 2973*/ 138727, // Rule ID 7762 // |
| 54073 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 54074 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 54075 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 54076 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 54077 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 54078 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 54079 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 54080 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 54081 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 54082 | // MIs[2] Operand 1 |
| 54083 | // No operand predicates |
| 54084 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 54085 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54086 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 54087 | // (fmul:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rn) => (FMULv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 54088 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv4i16_indexed, |
| 54089 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 54090 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 54091 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 54092 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 54093 | GIR_EraseFromParent, /*InsnID*/0, |
| 54094 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54095 | // GIR_Coverage, 7762, |
| 54096 | GIR_Done, |
| 54097 | // Label 2973: @138727 |
| 54098 | GIM_Try, /*On fail goto*//*Label 2974*/ 138791, // Rule ID 1696 // |
| 54099 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 54100 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 54101 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 54102 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 54103 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 54104 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 54105 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 54106 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 54107 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 54108 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 54109 | // MIs[2] Operand 1 |
| 54110 | // No operand predicates |
| 54111 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54112 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 54113 | // (fmul:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMULv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 54114 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv4i16_indexed, |
| 54115 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 54116 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 54117 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 54118 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 54119 | GIR_EraseFromParent, /*InsnID*/0, |
| 54120 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54121 | // GIR_Coverage, 1696, |
| 54122 | GIR_Done, |
| 54123 | // Label 2974: @138791 |
| 54124 | GIM_Try, /*On fail goto*//*Label 2975*/ 138810, // Rule ID 1046 // |
| 54125 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 54126 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 54127 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 54128 | // (fmul:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMULv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 54129 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULv4f16, |
| 54130 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54131 | // GIR_Coverage, 1046, |
| 54132 | GIR_Done, |
| 54133 | // Label 2975: @138810 |
| 54134 | GIM_Reject, |
| 54135 | // Label 2972: @138811 |
| 54136 | GIM_Reject, |
| 54137 | // Label 2945: @138812 |
| 54138 | GIM_Try, /*On fail goto*//*Label 2976*/ 139156, |
| 54139 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 54140 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 54141 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 54142 | GIM_Try, /*On fail goto*//*Label 2977*/ 138890, // Rule ID 7765 // |
| 54143 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 54144 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 54145 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 54146 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 54147 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 54148 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 54149 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 54150 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 54151 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 54152 | // MIs[2] Operand 1 |
| 54153 | // No operand predicates |
| 54154 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 54155 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54156 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 54157 | // (fmul:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rn) => (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 54158 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv4i32_indexed, |
| 54159 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 54160 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 54161 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 54162 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 54163 | GIR_EraseFromParent, /*InsnID*/0, |
| 54164 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54165 | // GIR_Coverage, 7765, |
| 54166 | GIR_Done, |
| 54167 | // Label 2977: @138890 |
| 54168 | GIM_Try, /*On fail goto*//*Label 2978*/ 138954, // Rule ID 1699 // |
| 54169 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 54170 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 54171 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 54172 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 54173 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 54174 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 54175 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 54176 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 54177 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 54178 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 54179 | // MIs[2] Operand 1 |
| 54180 | // No operand predicates |
| 54181 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54182 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 54183 | // (fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 54184 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv4i32_indexed, |
| 54185 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 54186 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 54187 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 54188 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 54189 | GIR_EraseFromParent, /*InsnID*/0, |
| 54190 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54191 | // GIR_Coverage, 1699, |
| 54192 | GIR_Done, |
| 54193 | // Label 2978: @138954 |
| 54194 | GIM_Try, /*On fail goto*//*Label 2979*/ 139045, // Rule ID 8010 // |
| 54195 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 54196 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 54197 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 54198 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 54199 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 54200 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54201 | // (fmul:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rn) => (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) |
| 54202 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 54203 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 54204 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 54205 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 54206 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 54207 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 54208 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 54209 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 54210 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 54211 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 54212 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 54213 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 54214 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 54215 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv4i32_indexed, |
| 54216 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 54217 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 54218 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 54219 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 54220 | GIR_EraseFromParent, /*InsnID*/0, |
| 54221 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54222 | // GIR_Coverage, 8010, |
| 54223 | GIR_Done, |
| 54224 | // Label 2979: @139045 |
| 54225 | GIM_Try, /*On fail goto*//*Label 2980*/ 139136, // Rule ID 4690 // |
| 54226 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 54227 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 54228 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 54229 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 54230 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 54231 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54232 | // (fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } FPR32:{ *:[f32] }:$Rm)) => (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) |
| 54233 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 54234 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 54235 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 54236 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 54237 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 54238 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 54239 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 54240 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 54241 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 54242 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 54243 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 54244 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 54245 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 54246 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv4i32_indexed, |
| 54247 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 54248 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 54249 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 54250 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 54251 | GIR_EraseFromParent, /*InsnID*/0, |
| 54252 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54253 | // GIR_Coverage, 4690, |
| 54254 | GIR_Done, |
| 54255 | // Label 2980: @139136 |
| 54256 | GIM_Try, /*On fail goto*//*Label 2981*/ 139155, // Rule ID 1049 // |
| 54257 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 54258 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 54259 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 54260 | // (fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMULv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) |
| 54261 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULv4f32, |
| 54262 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54263 | // GIR_Coverage, 1049, |
| 54264 | GIR_Done, |
| 54265 | // Label 2981: @139155 |
| 54266 | GIM_Reject, |
| 54267 | // Label 2976: @139156 |
| 54268 | GIM_Reject, |
| 54269 | // Label 2946: @139157 |
| 54270 | GIM_Try, /*On fail goto*//*Label 2982*/ 139319, |
| 54271 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 54272 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 54273 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 54274 | GIM_Try, /*On fail goto*//*Label 2983*/ 139235, // Rule ID 7763 // |
| 54275 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 54276 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 54277 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 54278 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 54279 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 54280 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 54281 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 54282 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 54283 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 54284 | // MIs[2] Operand 1 |
| 54285 | // No operand predicates |
| 54286 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 54287 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54288 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 54289 | // (fmul:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rn) => (FMULv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 54290 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv8i16_indexed, |
| 54291 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 54292 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 54293 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 54294 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 54295 | GIR_EraseFromParent, /*InsnID*/0, |
| 54296 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54297 | // GIR_Coverage, 7763, |
| 54298 | GIR_Done, |
| 54299 | // Label 2983: @139235 |
| 54300 | GIM_Try, /*On fail goto*//*Label 2984*/ 139299, // Rule ID 1697 // |
| 54301 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 54302 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 54303 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 54304 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 54305 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 54306 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 54307 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 54308 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 54309 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 54310 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 54311 | // MIs[2] Operand 1 |
| 54312 | // No operand predicates |
| 54313 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54314 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 54315 | // (fmul:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMULv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx) |
| 54316 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMULv8i16_indexed, |
| 54317 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 54318 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 54319 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 54320 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 54321 | GIR_EraseFromParent, /*InsnID*/0, |
| 54322 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54323 | // GIR_Coverage, 1697, |
| 54324 | GIR_Done, |
| 54325 | // Label 2984: @139299 |
| 54326 | GIM_Try, /*On fail goto*//*Label 2985*/ 139318, // Rule ID 1047 // |
| 54327 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 54328 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 54329 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 54330 | // (fmul:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMULv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 54331 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMULv8f16, |
| 54332 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54333 | // GIR_Coverage, 1047, |
| 54334 | GIR_Done, |
| 54335 | // Label 2985: @139318 |
| 54336 | GIM_Reject, |
| 54337 | // Label 2982: @139319 |
| 54338 | GIM_Reject, |
| 54339 | // Label 2947: @139320 |
| 54340 | GIM_Reject, |
| 54341 | // Label 50: @139321 |
| 54342 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 2994*/ 149523, |
| 54343 | /*GILLT_s16*//*Label 2986*/ 139337, |
| 54344 | /*GILLT_s32*//*Label 2987*/ 140261, |
| 54345 | /*GILLT_s64*//*Label 2988*/ 141343, 0, |
| 54346 | /*GILLT_v2s32*//*Label 2989*/ 142425, |
| 54347 | /*GILLT_v2s64*//*Label 2990*/ 143987, |
| 54348 | /*GILLT_v4s16*//*Label 2991*/ 145549, |
| 54349 | /*GILLT_v4s32*//*Label 2992*/ 146755, 0, |
| 54350 | /*GILLT_v8s16*//*Label 2993*/ 148317, |
| 54351 | // Label 2986: @139337 |
| 54352 | GIM_Try, /*On fail goto*//*Label 2995*/ 140260, |
| 54353 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 54354 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 54355 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, |
| 54356 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 54357 | GIM_Try, /*On fail goto*//*Label 2996*/ 139440, // Rule ID 4632 // |
| 54358 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 54359 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 54360 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 54361 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 54362 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 54363 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 54364 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 54365 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 54366 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 54367 | // MIs[2] Operand 1 |
| 54368 | // No operand predicates |
| 54369 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 54370 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, |
| 54371 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s16, |
| 54372 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 54373 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, |
| 54374 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54375 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 54376 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 54377 | // (fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), FPR16:{ *:[f16] }:$Rd) => (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) |
| 54378 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i16_indexed, |
| 54379 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 54380 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 54381 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 54382 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 54383 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 54384 | GIR_EraseFromParent, /*InsnID*/0, |
| 54385 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54386 | // GIR_Coverage, 4632, |
| 54387 | GIR_Done, |
| 54388 | // Label 2996: @139440 |
| 54389 | GIM_Try, /*On fail goto*//*Label 2997*/ 139525, // Rule ID 4645 // |
| 54390 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 54391 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 54392 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 54393 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 54394 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 54395 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 54396 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 54397 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 54398 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 54399 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 54400 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 54401 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 54402 | // MIs[3] Operand 1 |
| 54403 | // No operand predicates |
| 54404 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 54405 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, |
| 54406 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54407 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 54408 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 54409 | // (fma:{ *:[f16] } (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rd) => (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) |
| 54410 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i16_indexed, |
| 54411 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 54412 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 54413 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 54414 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 54415 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 54416 | GIR_EraseFromParent, /*InsnID*/0, |
| 54417 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54418 | // GIR_Coverage, 4645, |
| 54419 | GIR_Done, |
| 54420 | // Label 2997: @139525 |
| 54421 | GIM_Try, /*On fail goto*//*Label 2998*/ 139610, // Rule ID 4658 // |
| 54422 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 54423 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 54424 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 54425 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 54426 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 54427 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 54428 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 54429 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 54430 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 54431 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 54432 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 54433 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 54434 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 54435 | // MIs[3] Operand 1 |
| 54436 | // No operand predicates |
| 54437 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, |
| 54438 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54439 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 54440 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 54441 | // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rd) => (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) |
| 54442 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i16_indexed, |
| 54443 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 54444 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 54445 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 54446 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 54447 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 54448 | GIR_EraseFromParent, /*InsnID*/0, |
| 54449 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54450 | // GIR_Coverage, 4658, |
| 54451 | GIR_Done, |
| 54452 | // Label 2998: @139610 |
| 54453 | GIM_Try, /*On fail goto*//*Label 2999*/ 139695, // Rule ID 4619 // |
| 54454 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 54455 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 54456 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 54457 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 54458 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 54459 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 54460 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 54461 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 54462 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 54463 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 54464 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 54465 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 54466 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 54467 | // MIs[3] Operand 1 |
| 54468 | // No operand predicates |
| 54469 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, |
| 54470 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54471 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 54472 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 54473 | // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), FPR16:{ *:[f16] }:$Rd) => (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) |
| 54474 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i16_indexed, |
| 54475 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 54476 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 54477 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 54478 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 54479 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 54480 | GIR_EraseFromParent, /*InsnID*/0, |
| 54481 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54482 | // GIR_Coverage, 4619, |
| 54483 | GIR_Done, |
| 54484 | // Label 2999: @139695 |
| 54485 | GIM_Try, /*On fail goto*//*Label 3000*/ 139767, // Rule ID 2717 // |
| 54486 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 54487 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 54488 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 54489 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 54490 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 54491 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 54492 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 54493 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 54494 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 54495 | // MIs[2] Operand 1 |
| 54496 | // No operand predicates |
| 54497 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 54498 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, |
| 54499 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54500 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 54501 | // (fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rd) => (FMLAv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) |
| 54502 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i16_indexed, |
| 54503 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 54504 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 54505 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 54506 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 54507 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 54508 | GIR_EraseFromParent, /*InsnID*/0, |
| 54509 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54510 | // GIR_Coverage, 2717, |
| 54511 | GIR_Done, |
| 54512 | // Label 3000: @139767 |
| 54513 | GIM_Try, /*On fail goto*//*Label 3001*/ 139839, // Rule ID 4606 // |
| 54514 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 54515 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 54516 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 54517 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 54518 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 54519 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 54520 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 54521 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 54522 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 54523 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 54524 | // MIs[2] Operand 1 |
| 54525 | // No operand predicates |
| 54526 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, |
| 54527 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54528 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 54529 | // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rd) => (FMLAv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) |
| 54530 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i16_indexed, |
| 54531 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 54532 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 54533 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 54534 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 54535 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 54536 | GIR_EraseFromParent, /*InsnID*/0, |
| 54537 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54538 | // GIR_Coverage, 4606, |
| 54539 | GIR_Done, |
| 54540 | // Label 3001: @139839 |
| 54541 | GIM_Try, /*On fail goto*//*Label 3002*/ 139905, // Rule ID 3961 // |
| 54542 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 54543 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 54544 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 54545 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 54546 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 54547 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 54548 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 54549 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 54550 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 54551 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 54552 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54553 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 54554 | // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra)) => (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) |
| 54555 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDHrrr, |
| 54556 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 54557 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 54558 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 54559 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra |
| 54560 | GIR_EraseFromParent, /*InsnID*/0, |
| 54561 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54562 | // GIR_Coverage, 3961, |
| 54563 | GIR_Done, |
| 54564 | // Label 3002: @139905 |
| 54565 | GIM_Try, /*On fail goto*//*Label 3003*/ 139971, // Rule ID 7946 // |
| 54566 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 54567 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 54568 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 54569 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 54570 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 54571 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 54572 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 54573 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 54574 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 54575 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 54576 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54577 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 54578 | // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra)) => (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) |
| 54579 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDHrrr, |
| 54580 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 54581 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 54582 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm |
| 54583 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra |
| 54584 | GIR_EraseFromParent, /*InsnID*/0, |
| 54585 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54586 | // GIR_Coverage, 7946, |
| 54587 | GIR_Done, |
| 54588 | // Label 3003: @139971 |
| 54589 | GIM_Try, /*On fail goto*//*Label 3004*/ 140024, // Rule ID 3958 // |
| 54590 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 54591 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 54592 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 54593 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 54594 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 54595 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 54596 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, |
| 54597 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54598 | // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) |
| 54599 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBHrrr, |
| 54600 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 54601 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 54602 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 54603 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra |
| 54604 | GIR_EraseFromParent, /*InsnID*/0, |
| 54605 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54606 | // GIR_Coverage, 3958, |
| 54607 | GIR_Done, |
| 54608 | // Label 3004: @140024 |
| 54609 | GIM_Try, /*On fail goto*//*Label 3005*/ 140077, // Rule ID 7604 // |
| 54610 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 54611 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 54612 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 54613 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 54614 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 54615 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 54616 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, |
| 54617 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54618 | // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) |
| 54619 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBHrrr, |
| 54620 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 54621 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 54622 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 54623 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra |
| 54624 | GIR_EraseFromParent, /*InsnID*/0, |
| 54625 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54626 | // GIR_Coverage, 7604, |
| 54627 | GIR_Done, |
| 54628 | // Label 3005: @140077 |
| 54629 | GIM_Try, /*On fail goto*//*Label 3006*/ 140130, // Rule ID 546 // |
| 54630 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 54631 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 54632 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 54633 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 54634 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 54635 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 54636 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, |
| 54637 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54638 | // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) |
| 54639 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBHrrr, |
| 54640 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 54641 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 54642 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 54643 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra |
| 54644 | GIR_EraseFromParent, /*InsnID*/0, |
| 54645 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54646 | // GIR_Coverage, 546, |
| 54647 | GIR_Done, |
| 54648 | // Label 3006: @140130 |
| 54649 | GIM_Try, /*On fail goto*//*Label 3007*/ 140183, // Rule ID 7943 // |
| 54650 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 54651 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 54652 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 54653 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 54654 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 54655 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 54656 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, |
| 54657 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54658 | // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) |
| 54659 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBHrrr, |
| 54660 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 54661 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 54662 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm |
| 54663 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra |
| 54664 | GIR_EraseFromParent, /*InsnID*/0, |
| 54665 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54666 | // GIR_Coverage, 7943, |
| 54667 | GIR_Done, |
| 54668 | // Label 3007: @140183 |
| 54669 | GIM_Try, /*On fail goto*//*Label 3008*/ 140236, // Rule ID 552 // |
| 54670 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 54671 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 54672 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 54673 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 54674 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 54675 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 54676 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 54677 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54678 | // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra)) => (FNMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) |
| 54679 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMSUBHrrr, |
| 54680 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 54681 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 54682 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 54683 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra |
| 54684 | GIR_EraseFromParent, /*InsnID*/0, |
| 54685 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54686 | // GIR_Coverage, 552, |
| 54687 | GIR_Done, |
| 54688 | // Label 3008: @140236 |
| 54689 | GIM_Try, /*On fail goto*//*Label 3009*/ 140259, // Rule ID 543 // |
| 54690 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 54691 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 54692 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 54693 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, |
| 54694 | // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) => (FMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) |
| 54695 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMADDHrrr, |
| 54696 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54697 | // GIR_Coverage, 543, |
| 54698 | GIR_Done, |
| 54699 | // Label 3009: @140259 |
| 54700 | GIM_Reject, |
| 54701 | // Label 2995: @140260 |
| 54702 | GIM_Reject, |
| 54703 | // Label 2987: @140261 |
| 54704 | GIM_Try, /*On fail goto*//*Label 3010*/ 141342, |
| 54705 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 54706 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 54707 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 54708 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 54709 | GIM_Try, /*On fail goto*//*Label 3011*/ 140362, // Rule ID 4675 // |
| 54710 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 54711 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 54712 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 54713 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 54714 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 54715 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 54716 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 54717 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 54718 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 54719 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 54720 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 54721 | // MIs[3] Operand 1 |
| 54722 | // No operand predicates |
| 54723 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 54724 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 54725 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54726 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 54727 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 54728 | // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 54729 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, |
| 54730 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 54731 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 54732 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 54733 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 54734 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 54735 | GIR_EraseFromParent, /*InsnID*/0, |
| 54736 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54737 | // GIR_Coverage, 4675, |
| 54738 | GIR_Done, |
| 54739 | // Label 3011: @140362 |
| 54740 | GIM_Try, /*On fail goto*//*Label 3012*/ 140447, // Rule ID 4639 // |
| 54741 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 54742 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 54743 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 54744 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 54745 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 54746 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 54747 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 54748 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 54749 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 54750 | // MIs[2] Operand 1 |
| 54751 | // No operand predicates |
| 54752 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 54753 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, |
| 54754 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 54755 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 54756 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 54757 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54758 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 54759 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 54760 | // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 54761 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, |
| 54762 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 54763 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 54764 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 54765 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 54766 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 54767 | GIR_EraseFromParent, /*InsnID*/0, |
| 54768 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54769 | // GIR_Coverage, 4639, |
| 54770 | GIR_Done, |
| 54771 | // Label 3012: @140447 |
| 54772 | GIM_Try, /*On fail goto*//*Label 3013*/ 140532, // Rule ID 4652 // |
| 54773 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 54774 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 54775 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 54776 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 54777 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 54778 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 54779 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 54780 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 54781 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 54782 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 54783 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 54784 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 54785 | // MIs[3] Operand 1 |
| 54786 | // No operand predicates |
| 54787 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 54788 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 54789 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54790 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 54791 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 54792 | // (fma:{ *:[f32] } (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 54793 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, |
| 54794 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 54795 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 54796 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 54797 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 54798 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 54799 | GIR_EraseFromParent, /*InsnID*/0, |
| 54800 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54801 | // GIR_Coverage, 4652, |
| 54802 | GIR_Done, |
| 54803 | // Label 3013: @140532 |
| 54804 | GIM_Try, /*On fail goto*//*Label 3014*/ 140617, // Rule ID 4665 // |
| 54805 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 54806 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 54807 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 54808 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 54809 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 54810 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 54811 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 54812 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 54813 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 54814 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 54815 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 54816 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 54817 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 54818 | // MIs[3] Operand 1 |
| 54819 | // No operand predicates |
| 54820 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 54821 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54822 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 54823 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 54824 | // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 54825 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, |
| 54826 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 54827 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 54828 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 54829 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 54830 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 54831 | GIR_EraseFromParent, /*InsnID*/0, |
| 54832 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54833 | // GIR_Coverage, 4665, |
| 54834 | GIR_Done, |
| 54835 | // Label 3014: @140617 |
| 54836 | GIM_Try, /*On fail goto*//*Label 3015*/ 140700, // Rule ID 4686 // |
| 54837 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 54838 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 54839 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 54840 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 54841 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 54842 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 54843 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 54844 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 54845 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 54846 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 54847 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 54848 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 54849 | // MIs[3] Operand 1 |
| 54850 | // No operand predicates |
| 54851 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 54852 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54853 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 54854 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 54855 | // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 54856 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, |
| 54857 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 54858 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 54859 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 54860 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 54861 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 54862 | GIR_EraseFromParent, /*InsnID*/0, |
| 54863 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54864 | // GIR_Coverage, 4686, |
| 54865 | GIR_Done, |
| 54866 | // Label 3015: @140700 |
| 54867 | GIM_Try, /*On fail goto*//*Label 3016*/ 140785, // Rule ID 4626 // |
| 54868 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 54869 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 54870 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 54871 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 54872 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 54873 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 54874 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 54875 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 54876 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 54877 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 54878 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 54879 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 54880 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 54881 | // MIs[3] Operand 1 |
| 54882 | // No operand predicates |
| 54883 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 54884 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54885 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 54886 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 54887 | // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 54888 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed, |
| 54889 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 54890 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 54891 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 54892 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 54893 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 54894 | GIR_EraseFromParent, /*InsnID*/0, |
| 54895 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54896 | // GIR_Coverage, 4626, |
| 54897 | GIR_Done, |
| 54898 | // Label 3016: @140785 |
| 54899 | GIM_Try, /*On fail goto*//*Label 3017*/ 140857, // Rule ID 2724 // |
| 54900 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 54901 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 54902 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 54903 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 54904 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 54905 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 54906 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 54907 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 54908 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 54909 | // MIs[2] Operand 1 |
| 54910 | // No operand predicates |
| 54911 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 54912 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 54913 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54914 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 54915 | // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd) => (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 54916 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i32_indexed, |
| 54917 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 54918 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 54919 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 54920 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 54921 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 54922 | GIR_EraseFromParent, /*InsnID*/0, |
| 54923 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54924 | // GIR_Coverage, 2724, |
| 54925 | GIR_Done, |
| 54926 | // Label 3017: @140857 |
| 54927 | GIM_Try, /*On fail goto*//*Label 3018*/ 140929, // Rule ID 4613 // |
| 54928 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 54929 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 54930 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 54931 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 54932 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 54933 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 54934 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 54935 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 54936 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 54937 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 54938 | // MIs[2] Operand 1 |
| 54939 | // No operand predicates |
| 54940 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 54941 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54942 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 54943 | // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd) => (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 54944 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i32_indexed, |
| 54945 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 54946 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 54947 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 54948 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 54949 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 54950 | GIR_EraseFromParent, /*InsnID*/0, |
| 54951 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54952 | // GIR_Coverage, 4613, |
| 54953 | GIR_Done, |
| 54954 | // Label 3018: @140929 |
| 54955 | GIM_Try, /*On fail goto*//*Label 3019*/ 140993, // Rule ID 3962 // |
| 54956 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 54957 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 54958 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 54959 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 54960 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 54961 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 54962 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 54963 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 54964 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 54965 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54966 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 54967 | // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra)) => (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) |
| 54968 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDSrrr, |
| 54969 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 54970 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 54971 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 54972 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra |
| 54973 | GIR_EraseFromParent, /*InsnID*/0, |
| 54974 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54975 | // GIR_Coverage, 3962, |
| 54976 | GIR_Done, |
| 54977 | // Label 3019: @140993 |
| 54978 | GIM_Try, /*On fail goto*//*Label 3020*/ 141057, // Rule ID 7947 // |
| 54979 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 54980 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 54981 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 54982 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 54983 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 54984 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 54985 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 54986 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 54987 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 54988 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 54989 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 54990 | // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra)) => (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) |
| 54991 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDSrrr, |
| 54992 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 54993 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 54994 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm |
| 54995 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra |
| 54996 | GIR_EraseFromParent, /*InsnID*/0, |
| 54997 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 54998 | // GIR_Coverage, 7947, |
| 54999 | GIR_Done, |
| 55000 | // Label 3020: @141057 |
| 55001 | GIM_Try, /*On fail goto*//*Label 3021*/ 141108, // Rule ID 3959 // |
| 55002 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 55003 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 55004 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 55005 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 55006 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 55007 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 55008 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55009 | // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) |
| 55010 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBSrrr, |
| 55011 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 55012 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 55013 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 55014 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra |
| 55015 | GIR_EraseFromParent, /*InsnID*/0, |
| 55016 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55017 | // GIR_Coverage, 3959, |
| 55018 | GIR_Done, |
| 55019 | // Label 3021: @141108 |
| 55020 | GIM_Try, /*On fail goto*//*Label 3022*/ 141161, // Rule ID 7605 // |
| 55021 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 55022 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 55023 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 55024 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 55025 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 55026 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 55027 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 55028 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55029 | // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) |
| 55030 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBSrrr, |
| 55031 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 55032 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 55033 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 55034 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra |
| 55035 | GIR_EraseFromParent, /*InsnID*/0, |
| 55036 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55037 | // GIR_Coverage, 7605, |
| 55038 | GIR_Done, |
| 55039 | // Label 3022: @141161 |
| 55040 | GIM_Try, /*On fail goto*//*Label 3023*/ 141214, // Rule ID 547 // |
| 55041 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 55042 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 55043 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 55044 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 55045 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 55046 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 55047 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 55048 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55049 | // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) |
| 55050 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBSrrr, |
| 55051 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 55052 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 55053 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 55054 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra |
| 55055 | GIR_EraseFromParent, /*InsnID*/0, |
| 55056 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55057 | // GIR_Coverage, 547, |
| 55058 | GIR_Done, |
| 55059 | // Label 3023: @141214 |
| 55060 | GIM_Try, /*On fail goto*//*Label 3024*/ 141265, // Rule ID 7944 // |
| 55061 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 55062 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 55063 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 55064 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 55065 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 55066 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 55067 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55068 | // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) |
| 55069 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBSrrr, |
| 55070 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 55071 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 55072 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm |
| 55073 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra |
| 55074 | GIR_EraseFromParent, /*InsnID*/0, |
| 55075 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55076 | // GIR_Coverage, 7944, |
| 55077 | GIR_Done, |
| 55078 | // Label 3024: @141265 |
| 55079 | GIM_Try, /*On fail goto*//*Label 3025*/ 141318, // Rule ID 553 // |
| 55080 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 55081 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 55082 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 55083 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 55084 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 55085 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 55086 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 55087 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55088 | // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra)) => (FNMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) |
| 55089 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMSUBSrrr, |
| 55090 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 55091 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 55092 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 55093 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra |
| 55094 | GIR_EraseFromParent, /*InsnID*/0, |
| 55095 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55096 | // GIR_Coverage, 553, |
| 55097 | GIR_Done, |
| 55098 | // Label 3025: @141318 |
| 55099 | GIM_Try, /*On fail goto*//*Label 3026*/ 141341, // Rule ID 544 // |
| 55100 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 55101 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 55102 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 55103 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 55104 | // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) => (FMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) |
| 55105 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMADDSrrr, |
| 55106 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55107 | // GIR_Coverage, 544, |
| 55108 | GIR_Done, |
| 55109 | // Label 3026: @141341 |
| 55110 | GIM_Reject, |
| 55111 | // Label 3010: @141342 |
| 55112 | GIM_Reject, |
| 55113 | // Label 2988: @141343 |
| 55114 | GIM_Try, /*On fail goto*//*Label 3027*/ 142424, |
| 55115 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 55116 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 55117 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 55118 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 55119 | GIM_Try, /*On fail goto*//*Label 3028*/ 141444, // Rule ID 4677 // |
| 55120 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 55121 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 55122 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 55123 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 55124 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 55125 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 55126 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 55127 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 55128 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 55129 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 55130 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 55131 | // MIs[3] Operand 1 |
| 55132 | // No operand predicates |
| 55133 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 55134 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55135 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55136 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 55137 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 55138 | // (fma:{ *:[f64] } (vector_extract:{ *:[f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 55139 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed, |
| 55140 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 55141 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 55142 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 55143 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 55144 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 55145 | GIR_EraseFromParent, /*InsnID*/0, |
| 55146 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55147 | // GIR_Coverage, 4677, |
| 55148 | GIR_Done, |
| 55149 | // Label 3028: @141444 |
| 55150 | GIM_Try, /*On fail goto*//*Label 3029*/ 141529, // Rule ID 4640 // |
| 55151 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 55152 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 55153 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 55154 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 55155 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 55156 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 55157 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 55158 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 55159 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 55160 | // MIs[2] Operand 1 |
| 55161 | // No operand predicates |
| 55162 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 55163 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, |
| 55164 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64, |
| 55165 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55166 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55167 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55168 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 55169 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 55170 | // (fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx) |
| 55171 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed, |
| 55172 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 55173 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 55174 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 55175 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 55176 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 55177 | GIR_EraseFromParent, /*InsnID*/0, |
| 55178 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55179 | // GIR_Coverage, 4640, |
| 55180 | GIR_Done, |
| 55181 | // Label 3029: @141529 |
| 55182 | GIM_Try, /*On fail goto*//*Label 3030*/ 141614, // Rule ID 4653 // |
| 55183 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 55184 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 55185 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 55186 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 55187 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 55188 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 55189 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 55190 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 55191 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 55192 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 55193 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 55194 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 55195 | // MIs[3] Operand 1 |
| 55196 | // No operand predicates |
| 55197 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 55198 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55199 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55200 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 55201 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 55202 | // (fma:{ *:[f64] } (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx) |
| 55203 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed, |
| 55204 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 55205 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 55206 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 55207 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 55208 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 55209 | GIR_EraseFromParent, /*InsnID*/0, |
| 55210 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55211 | // GIR_Coverage, 4653, |
| 55212 | GIR_Done, |
| 55213 | // Label 3030: @141614 |
| 55214 | GIM_Try, /*On fail goto*//*Label 3031*/ 141699, // Rule ID 4666 // |
| 55215 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 55216 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 55217 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 55218 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 55219 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55220 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 55221 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 55222 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 55223 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 55224 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 55225 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 55226 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 55227 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 55228 | // MIs[3] Operand 1 |
| 55229 | // No operand predicates |
| 55230 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55231 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55232 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 55233 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 55234 | // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx) |
| 55235 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed, |
| 55236 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 55237 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 55238 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 55239 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 55240 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 55241 | GIR_EraseFromParent, /*InsnID*/0, |
| 55242 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55243 | // GIR_Coverage, 4666, |
| 55244 | GIR_Done, |
| 55245 | // Label 3031: @141699 |
| 55246 | GIM_Try, /*On fail goto*//*Label 3032*/ 141782, // Rule ID 4688 // |
| 55247 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55248 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 55249 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 55250 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 55251 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 55252 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 55253 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 55254 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 55255 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 55256 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 55257 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 55258 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 55259 | // MIs[3] Operand 1 |
| 55260 | // No operand predicates |
| 55261 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55262 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55263 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 55264 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 55265 | // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 55266 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed, |
| 55267 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 55268 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 55269 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 55270 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 55271 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 55272 | GIR_EraseFromParent, /*InsnID*/0, |
| 55273 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55274 | // GIR_Coverage, 4688, |
| 55275 | GIR_Done, |
| 55276 | // Label 3032: @141782 |
| 55277 | GIM_Try, /*On fail goto*//*Label 3033*/ 141867, // Rule ID 4627 // |
| 55278 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 55279 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55280 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 55281 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 55282 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 55283 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 55284 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 55285 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 55286 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 55287 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 55288 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 55289 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 55290 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 55291 | // MIs[3] Operand 1 |
| 55292 | // No operand predicates |
| 55293 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55294 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55295 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 55296 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 55297 | // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx) |
| 55298 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i64_indexed, |
| 55299 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 55300 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 55301 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 55302 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 55303 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 55304 | GIR_EraseFromParent, /*InsnID*/0, |
| 55305 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55306 | // GIR_Coverage, 4627, |
| 55307 | GIR_Done, |
| 55308 | // Label 3033: @141867 |
| 55309 | GIM_Try, /*On fail goto*//*Label 3034*/ 141939, // Rule ID 2725 // |
| 55310 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 55311 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 55312 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 55313 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 55314 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 55315 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 55316 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 55317 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 55318 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 55319 | // MIs[2] Operand 1 |
| 55320 | // No operand predicates |
| 55321 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 55322 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55323 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55324 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 55325 | // (fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd) => (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx) |
| 55326 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i64_indexed, |
| 55327 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 55328 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 55329 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 55330 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 55331 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 55332 | GIR_EraseFromParent, /*InsnID*/0, |
| 55333 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55334 | // GIR_Coverage, 2725, |
| 55335 | GIR_Done, |
| 55336 | // Label 3034: @141939 |
| 55337 | GIM_Try, /*On fail goto*//*Label 3035*/ 142011, // Rule ID 4614 // |
| 55338 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 55339 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55340 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 55341 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_EXTRACT_VECTOR_ELT, |
| 55342 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 55343 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 55344 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 55345 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 55346 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 55347 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 55348 | // MIs[2] Operand 1 |
| 55349 | // No operand predicates |
| 55350 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55351 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55352 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 55353 | // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rd) => (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx) |
| 55354 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv1i64_indexed, |
| 55355 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 55356 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 55357 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 55358 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 55359 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 55360 | GIR_EraseFromParent, /*InsnID*/0, |
| 55361 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55362 | // GIR_Coverage, 4614, |
| 55363 | GIR_Done, |
| 55364 | // Label 3035: @142011 |
| 55365 | GIM_Try, /*On fail goto*//*Label 3036*/ 142075, // Rule ID 3963 // |
| 55366 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 55367 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 55368 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 55369 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55370 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 55371 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 55372 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 55373 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 55374 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55375 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55376 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 55377 | // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra)) => (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) |
| 55378 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDDrrr, |
| 55379 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 55380 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 55381 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 55382 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra |
| 55383 | GIR_EraseFromParent, /*InsnID*/0, |
| 55384 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55385 | // GIR_Coverage, 3963, |
| 55386 | GIR_Done, |
| 55387 | // Label 3036: @142075 |
| 55388 | GIM_Try, /*On fail goto*//*Label 3037*/ 142139, // Rule ID 7948 // |
| 55389 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55390 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 55391 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 55392 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 55393 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55394 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 55395 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 55396 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 55397 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55398 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55399 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 55400 | // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra)) => (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) |
| 55401 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDDrrr, |
| 55402 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 55403 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 55404 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm |
| 55405 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra |
| 55406 | GIR_EraseFromParent, /*InsnID*/0, |
| 55407 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55408 | // GIR_Coverage, 7948, |
| 55409 | GIR_Done, |
| 55410 | // Label 3037: @142139 |
| 55411 | GIM_Try, /*On fail goto*//*Label 3038*/ 142190, // Rule ID 3960 // |
| 55412 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 55413 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 55414 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 55415 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55416 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 55417 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55418 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55419 | // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) |
| 55420 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBDrrr, |
| 55421 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 55422 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 55423 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 55424 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra |
| 55425 | GIR_EraseFromParent, /*InsnID*/0, |
| 55426 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55427 | // GIR_Coverage, 3960, |
| 55428 | GIR_Done, |
| 55429 | // Label 3038: @142190 |
| 55430 | GIM_Try, /*On fail goto*//*Label 3039*/ 142243, // Rule ID 7606 // |
| 55431 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 55432 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 55433 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 55434 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 55435 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55436 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 55437 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55438 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55439 | // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) |
| 55440 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBDrrr, |
| 55441 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 55442 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 55443 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 55444 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra |
| 55445 | GIR_EraseFromParent, /*InsnID*/0, |
| 55446 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55447 | // GIR_Coverage, 7606, |
| 55448 | GIR_Done, |
| 55449 | // Label 3039: @142243 |
| 55450 | GIM_Try, /*On fail goto*//*Label 3040*/ 142296, // Rule ID 548 // |
| 55451 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 55452 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55453 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 55454 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 55455 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 55456 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55457 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55458 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55459 | // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) |
| 55460 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBDrrr, |
| 55461 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 55462 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 55463 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 55464 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra |
| 55465 | GIR_EraseFromParent, /*InsnID*/0, |
| 55466 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55467 | // GIR_Coverage, 548, |
| 55468 | GIR_Done, |
| 55469 | // Label 3040: @142296 |
| 55470 | GIM_Try, /*On fail goto*//*Label 3041*/ 142347, // Rule ID 7945 // |
| 55471 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55472 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 55473 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 55474 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 55475 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55476 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55477 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55478 | // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) |
| 55479 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMSUBDrrr, |
| 55480 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 55481 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 55482 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm |
| 55483 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ra |
| 55484 | GIR_EraseFromParent, /*InsnID*/0, |
| 55485 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55486 | // GIR_Coverage, 7945, |
| 55487 | GIR_Done, |
| 55488 | // Label 3041: @142347 |
| 55489 | GIM_Try, /*On fail goto*//*Label 3042*/ 142400, // Rule ID 554 // |
| 55490 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 55491 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55492 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 55493 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 55494 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 55495 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 55496 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55497 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55498 | // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra)) => (FNMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) |
| 55499 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMSUBDrrr, |
| 55500 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 55501 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 55502 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 55503 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra |
| 55504 | GIR_EraseFromParent, /*InsnID*/0, |
| 55505 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55506 | // GIR_Coverage, 554, |
| 55507 | GIR_Done, |
| 55508 | // Label 3042: @142400 |
| 55509 | GIM_Try, /*On fail goto*//*Label 3043*/ 142423, // Rule ID 545 // |
| 55510 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 55511 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55512 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 55513 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55514 | // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) => (FMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) |
| 55515 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMADDDrrr, |
| 55516 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55517 | // GIR_Coverage, 545, |
| 55518 | GIR_Done, |
| 55519 | // Label 3043: @142423 |
| 55520 | GIM_Reject, |
| 55521 | // Label 3027: @142424 |
| 55522 | GIM_Reject, |
| 55523 | // Label 2989: @142425 |
| 55524 | GIM_Try, /*On fail goto*//*Label 3044*/ 143986, |
| 55525 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 55526 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 55527 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, |
| 55528 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 55529 | GIM_Try, /*On fail goto*//*Label 3045*/ 142526, // Rule ID 4667 // |
| 55530 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 55531 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 55532 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 55533 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 55534 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 55535 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 55536 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 55537 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 55538 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 55539 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 55540 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 55541 | // MIs[3] Operand 1 |
| 55542 | // No operand predicates |
| 55543 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 55544 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55545 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55546 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 55547 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 55548 | // (fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 55549 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, |
| 55550 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 55551 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 55552 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 55553 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 55554 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 55555 | GIR_EraseFromParent, /*InsnID*/0, |
| 55556 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55557 | // GIR_Coverage, 4667, |
| 55558 | GIR_Done, |
| 55559 | // Label 3045: @142526 |
| 55560 | GIM_Try, /*On fail goto*//*Label 3046*/ 142611, // Rule ID 4633 // |
| 55561 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 55562 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 55563 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 55564 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 55565 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 55566 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 55567 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 55568 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 55569 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 55570 | // MIs[2] Operand 1 |
| 55571 | // No operand predicates |
| 55572 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 55573 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, |
| 55574 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s32, |
| 55575 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55576 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55577 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55578 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 55579 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 55580 | // (fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 55581 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, |
| 55582 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 55583 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 55584 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 55585 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 55586 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 55587 | GIR_EraseFromParent, /*InsnID*/0, |
| 55588 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55589 | // GIR_Coverage, 4633, |
| 55590 | GIR_Done, |
| 55591 | // Label 3046: @142611 |
| 55592 | GIM_Try, /*On fail goto*//*Label 3047*/ 142696, // Rule ID 4646 // |
| 55593 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 55594 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 55595 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 55596 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 55597 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 55598 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 55599 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 55600 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 55601 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 55602 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 55603 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 55604 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 55605 | // MIs[3] Operand 1 |
| 55606 | // No operand predicates |
| 55607 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 55608 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55609 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55610 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 55611 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 55612 | // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 55613 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, |
| 55614 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 55615 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 55616 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 55617 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 55618 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 55619 | GIR_EraseFromParent, /*InsnID*/0, |
| 55620 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55621 | // GIR_Coverage, 4646, |
| 55622 | GIR_Done, |
| 55623 | // Label 3047: @142696 |
| 55624 | GIM_Try, /*On fail goto*//*Label 3048*/ 142781, // Rule ID 4659 // |
| 55625 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 55626 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 55627 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 55628 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 55629 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55630 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 55631 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 55632 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 55633 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 55634 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 55635 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 55636 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 55637 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 55638 | // MIs[3] Operand 1 |
| 55639 | // No operand predicates |
| 55640 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55641 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55642 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 55643 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 55644 | // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 55645 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, |
| 55646 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 55647 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 55648 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 55649 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 55650 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 55651 | GIR_EraseFromParent, /*InsnID*/0, |
| 55652 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55653 | // GIR_Coverage, 4659, |
| 55654 | GIR_Done, |
| 55655 | // Label 3048: @142781 |
| 55656 | GIM_Try, /*On fail goto*//*Label 3049*/ 142864, // Rule ID 4678 // |
| 55657 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55658 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 55659 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 55660 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 55661 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 55662 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 55663 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 55664 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 55665 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 55666 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 55667 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 55668 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 55669 | // MIs[3] Operand 1 |
| 55670 | // No operand predicates |
| 55671 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55672 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55673 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 55674 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 55675 | // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 55676 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, |
| 55677 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 55678 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 55679 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 55680 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 55681 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 55682 | GIR_EraseFromParent, /*InsnID*/0, |
| 55683 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55684 | // GIR_Coverage, 4678, |
| 55685 | GIR_Done, |
| 55686 | // Label 3049: @142864 |
| 55687 | GIM_Try, /*On fail goto*//*Label 3050*/ 142949, // Rule ID 4620 // |
| 55688 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 55689 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55690 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 55691 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 55692 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 55693 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 55694 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 55695 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 55696 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 55697 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 55698 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 55699 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 55700 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 55701 | // MIs[3] Operand 1 |
| 55702 | // No operand predicates |
| 55703 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55704 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55705 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 55706 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 55707 | // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 55708 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, |
| 55709 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 55710 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 55711 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 55712 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 55713 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 55714 | GIR_EraseFromParent, /*InsnID*/0, |
| 55715 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55716 | // GIR_Coverage, 4620, |
| 55717 | GIR_Done, |
| 55718 | // Label 3050: @142949 |
| 55719 | GIM_Try, /*On fail goto*//*Label 3051*/ 143021, // Rule ID 2718 // |
| 55720 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 55721 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 55722 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 55723 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 55724 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 55725 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 55726 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 55727 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 55728 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 55729 | // MIs[2] Operand 1 |
| 55730 | // No operand predicates |
| 55731 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 55732 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55733 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55734 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 55735 | // (fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 55736 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2i32_indexed, |
| 55737 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 55738 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 55739 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 55740 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 55741 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 55742 | GIR_EraseFromParent, /*InsnID*/0, |
| 55743 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55744 | // GIR_Coverage, 2718, |
| 55745 | GIR_Done, |
| 55746 | // Label 3051: @143021 |
| 55747 | GIM_Try, /*On fail goto*//*Label 3052*/ 143093, // Rule ID 4607 // |
| 55748 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 55749 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55750 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 55751 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 55752 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 55753 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 55754 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 55755 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 55756 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 55757 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 55758 | // MIs[2] Operand 1 |
| 55759 | // No operand predicates |
| 55760 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55761 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55762 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 55763 | // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rd) => (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 55764 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2i32_indexed, |
| 55765 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 55766 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 55767 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 55768 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 55769 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 55770 | GIR_EraseFromParent, /*InsnID*/0, |
| 55771 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55772 | // GIR_Coverage, 4607, |
| 55773 | GIR_Done, |
| 55774 | // Label 3052: @143093 |
| 55775 | GIM_Try, /*On fail goto*//*Label 3053*/ 143188, // Rule ID 4669 // |
| 55776 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 55777 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 55778 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 55779 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 55780 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 55781 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 55782 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 55783 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 55784 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55785 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55786 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 55787 | // (fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) |
| 55788 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 55789 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 55790 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 55791 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 55792 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 55793 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 55794 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 55795 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 55796 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, |
| 55797 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 55798 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 55799 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 55800 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 55801 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 55802 | GIR_EraseFromParent, /*InsnID*/0, |
| 55803 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55804 | // GIR_Coverage, 4669, |
| 55805 | GIR_Done, |
| 55806 | // Label 3053: @143188 |
| 55807 | GIM_Try, /*On fail goto*//*Label 3054*/ 143285, // Rule ID 4634 // |
| 55808 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 55809 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 55810 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 55811 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 55812 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 55813 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 55814 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 55815 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 55816 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55817 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55818 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55819 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 55820 | // (fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) |
| 55821 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 55822 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 55823 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 55824 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 55825 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 55826 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 55827 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 55828 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 55829 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, |
| 55830 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 55831 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 55832 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 55833 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 55834 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 55835 | GIR_EraseFromParent, /*InsnID*/0, |
| 55836 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55837 | // GIR_Coverage, 4634, |
| 55838 | GIR_Done, |
| 55839 | // Label 3054: @143285 |
| 55840 | GIM_Try, /*On fail goto*//*Label 3055*/ 143382, // Rule ID 4647 // |
| 55841 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 55842 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 55843 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 55844 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 55845 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 55846 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, |
| 55847 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 55848 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 55849 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 55850 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55851 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55852 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 55853 | // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) |
| 55854 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 55855 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 55856 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 55857 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 55858 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 55859 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 55860 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 55861 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 55862 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, |
| 55863 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 55864 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 55865 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 55866 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 55867 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 55868 | GIR_EraseFromParent, /*InsnID*/0, |
| 55869 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55870 | // GIR_Coverage, 4647, |
| 55871 | GIR_Done, |
| 55872 | // Label 3055: @143382 |
| 55873 | GIM_Try, /*On fail goto*//*Label 3056*/ 143479, // Rule ID 4660 // |
| 55874 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 55875 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 55876 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 55877 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 55878 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55879 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 55880 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, |
| 55881 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 55882 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 55883 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55884 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55885 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 55886 | // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) |
| 55887 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 55888 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 55889 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 55890 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 55891 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 55892 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 55893 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 55894 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 55895 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, |
| 55896 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 55897 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 55898 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 55899 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 55900 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 55901 | GIR_EraseFromParent, /*InsnID*/0, |
| 55902 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55903 | // GIR_Coverage, 4660, |
| 55904 | GIR_Done, |
| 55905 | // Label 3056: @143479 |
| 55906 | GIM_Try, /*On fail goto*//*Label 3057*/ 143574, // Rule ID 4680 // |
| 55907 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55908 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 55909 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 55910 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 55911 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 55912 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 55913 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 55914 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 55915 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55916 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55917 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 55918 | // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) |
| 55919 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 55920 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 55921 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 55922 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 55923 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 55924 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 55925 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 55926 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 55927 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, |
| 55928 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 55929 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 55930 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 55931 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 55932 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 55933 | GIR_EraseFromParent, /*InsnID*/0, |
| 55934 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55935 | // GIR_Coverage, 4680, |
| 55936 | GIR_Done, |
| 55937 | // Label 3057: @143574 |
| 55938 | GIM_Try, /*On fail goto*//*Label 3058*/ 143671, // Rule ID 4621 // |
| 55939 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 55940 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 55941 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 55942 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 55943 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 55944 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 55945 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, |
| 55946 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 55947 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 55948 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55949 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55950 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 55951 | // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) |
| 55952 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 55953 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 55954 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 55955 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 55956 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 55957 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 55958 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 55959 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 55960 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i32_indexed, |
| 55961 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 55962 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 55963 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 55964 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 55965 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 55966 | GIR_EraseFromParent, /*InsnID*/0, |
| 55967 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55968 | // GIR_Coverage, 4621, |
| 55969 | GIR_Done, |
| 55970 | // Label 3058: @143671 |
| 55971 | GIM_Try, /*On fail goto*//*Label 3059*/ 143755, // Rule ID 2719 // |
| 55972 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 55973 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 55974 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 55975 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 55976 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 55977 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 55978 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 55979 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 55980 | // (fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) |
| 55981 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 55982 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 55983 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 55984 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 55985 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 55986 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 55987 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 55988 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 55989 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2i32_indexed, |
| 55990 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 55991 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 55992 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 55993 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 55994 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 55995 | GIR_EraseFromParent, /*InsnID*/0, |
| 55996 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 55997 | // GIR_Coverage, 2719, |
| 55998 | GIR_Done, |
| 55999 | // Label 3059: @143755 |
| 56000 | GIM_Try, /*On fail goto*//*Label 3060*/ 143808, // Rule ID 7630 // |
| 56001 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 56002 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 56003 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 56004 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 56005 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 56006 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 56007 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 56008 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56009 | // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) |
| 56010 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2f32, |
| 56011 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56012 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56013 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 56014 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 56015 | GIR_EraseFromParent, /*InsnID*/0, |
| 56016 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56017 | // GIR_Coverage, 7630, |
| 56018 | GIR_Done, |
| 56019 | // Label 3060: @143808 |
| 56020 | GIM_Try, /*On fail goto*//*Label 3061*/ 143892, // Rule ID 4608 // |
| 56021 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 56022 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 56023 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 56024 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 56025 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 56026 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 56027 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 56028 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56029 | // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rd) => (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) |
| 56030 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 56031 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 56032 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 56033 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 56034 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 56035 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 56036 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 56037 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 56038 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2i32_indexed, |
| 56039 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56040 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56041 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 56042 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 56043 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 56044 | GIR_EraseFromParent, /*InsnID*/0, |
| 56045 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56046 | // GIR_Coverage, 4608, |
| 56047 | GIR_Done, |
| 56048 | // Label 3061: @143892 |
| 56049 | GIM_Try, /*On fail goto*//*Label 3062*/ 143945, // Rule ID 1038 // |
| 56050 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 56051 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 56052 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 56053 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 56054 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 56055 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 56056 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 56057 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56058 | // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm), V64:{ *:[v2f32] }:$Rd) => (FMLSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) |
| 56059 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2f32, |
| 56060 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56061 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56062 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 56063 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 56064 | GIR_EraseFromParent, /*InsnID*/0, |
| 56065 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56066 | // GIR_Coverage, 1038, |
| 56067 | GIR_Done, |
| 56068 | // Label 3062: @143945 |
| 56069 | GIM_Try, /*On fail goto*//*Label 3063*/ 143985, // Rule ID 1033 // |
| 56070 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 56071 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 56072 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 56073 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 56074 | // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLAv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) |
| 56075 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2f32, |
| 56076 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56077 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56078 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 56079 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm |
| 56080 | GIR_EraseFromParent, /*InsnID*/0, |
| 56081 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56082 | // GIR_Coverage, 1033, |
| 56083 | GIR_Done, |
| 56084 | // Label 3063: @143985 |
| 56085 | GIM_Reject, |
| 56086 | // Label 3044: @143986 |
| 56087 | GIM_Reject, |
| 56088 | // Label 2990: @143987 |
| 56089 | GIM_Try, /*On fail goto*//*Label 3064*/ 145548, |
| 56090 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 56091 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 56092 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 56093 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 56094 | GIM_Try, /*On fail goto*//*Label 3065*/ 144088, // Rule ID 4673 // |
| 56095 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 56096 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE64, |
| 56097 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 56098 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 56099 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 56100 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 56101 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 56102 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 56103 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 56104 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 56105 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 56106 | // MIs[3] Operand 1 |
| 56107 | // No operand predicates |
| 56108 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 56109 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 56110 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56111 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 56112 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 56113 | // (fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 56114 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, |
| 56115 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56116 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56117 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 56118 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 56119 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 56120 | GIR_EraseFromParent, /*InsnID*/0, |
| 56121 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56122 | // GIR_Coverage, 4673, |
| 56123 | GIR_Done, |
| 56124 | // Label 3065: @144088 |
| 56125 | GIM_Try, /*On fail goto*//*Label 3066*/ 144173, // Rule ID 4637 // |
| 56126 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 56127 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 56128 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE64, |
| 56129 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 56130 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 56131 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 56132 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 56133 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 56134 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 56135 | // MIs[2] Operand 1 |
| 56136 | // No operand predicates |
| 56137 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 56138 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, |
| 56139 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64, |
| 56140 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 56141 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 56142 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56143 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 56144 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 56145 | // (fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 56146 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, |
| 56147 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56148 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56149 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 56150 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 56151 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 56152 | GIR_EraseFromParent, /*InsnID*/0, |
| 56153 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56154 | // GIR_Coverage, 4637, |
| 56155 | GIR_Done, |
| 56156 | // Label 3066: @144173 |
| 56157 | GIM_Try, /*On fail goto*//*Label 3067*/ 144258, // Rule ID 4650 // |
| 56158 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 56159 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 56160 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 56161 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 56162 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 56163 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE64, |
| 56164 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 56165 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 56166 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 56167 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 56168 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 56169 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 56170 | // MIs[3] Operand 1 |
| 56171 | // No operand predicates |
| 56172 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 56173 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 56174 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56175 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 56176 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 56177 | // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 56178 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, |
| 56179 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56180 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56181 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 56182 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 56183 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 56184 | GIR_EraseFromParent, /*InsnID*/0, |
| 56185 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56186 | // GIR_Coverage, 4650, |
| 56187 | GIR_Done, |
| 56188 | // Label 3067: @144258 |
| 56189 | GIM_Try, /*On fail goto*//*Label 3068*/ 144343, // Rule ID 4663 // |
| 56190 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 56191 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 56192 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 56193 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 56194 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 56195 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 56196 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE64, |
| 56197 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 56198 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 56199 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 56200 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 56201 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 56202 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 56203 | // MIs[3] Operand 1 |
| 56204 | // No operand predicates |
| 56205 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 56206 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56207 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 56208 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 56209 | // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 56210 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, |
| 56211 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56212 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56213 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 56214 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 56215 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 56216 | GIR_EraseFromParent, /*InsnID*/0, |
| 56217 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56218 | // GIR_Coverage, 4663, |
| 56219 | GIR_Done, |
| 56220 | // Label 3068: @144343 |
| 56221 | GIM_Try, /*On fail goto*//*Label 3069*/ 144426, // Rule ID 4684 // |
| 56222 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 56223 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 56224 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE64, |
| 56225 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 56226 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 56227 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 56228 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 56229 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 56230 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 56231 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 56232 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 56233 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 56234 | // MIs[3] Operand 1 |
| 56235 | // No operand predicates |
| 56236 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 56237 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56238 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 56239 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 56240 | // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 56241 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, |
| 56242 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56243 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56244 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 56245 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 56246 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 56247 | GIR_EraseFromParent, /*InsnID*/0, |
| 56248 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56249 | // GIR_Coverage, 4684, |
| 56250 | GIR_Done, |
| 56251 | // Label 3069: @144426 |
| 56252 | GIM_Try, /*On fail goto*//*Label 3070*/ 144511, // Rule ID 4624 // |
| 56253 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 56254 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 56255 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 56256 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 56257 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 56258 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 56259 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE64, |
| 56260 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 56261 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 56262 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 56263 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 56264 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 56265 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 56266 | // MIs[3] Operand 1 |
| 56267 | // No operand predicates |
| 56268 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 56269 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56270 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 56271 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 56272 | // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 56273 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, |
| 56274 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56275 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56276 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 56277 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 56278 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 56279 | GIR_EraseFromParent, /*InsnID*/0, |
| 56280 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56281 | // GIR_Coverage, 4624, |
| 56282 | GIR_Done, |
| 56283 | // Label 3070: @144511 |
| 56284 | GIM_Try, /*On fail goto*//*Label 3071*/ 144583, // Rule ID 2722 // |
| 56285 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 56286 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 56287 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE64, |
| 56288 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 56289 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 56290 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 56291 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 56292 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 56293 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 56294 | // MIs[2] Operand 1 |
| 56295 | // No operand predicates |
| 56296 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 56297 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 56298 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56299 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 56300 | // (fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 56301 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2i64_indexed, |
| 56302 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56303 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56304 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 56305 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 56306 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 56307 | GIR_EraseFromParent, /*InsnID*/0, |
| 56308 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56309 | // GIR_Coverage, 2722, |
| 56310 | GIR_Done, |
| 56311 | // Label 3071: @144583 |
| 56312 | GIM_Try, /*On fail goto*//*Label 3072*/ 144655, // Rule ID 4611 // |
| 56313 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 56314 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 56315 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 56316 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE64, |
| 56317 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 56318 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 56319 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 56320 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 56321 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 56322 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 56323 | // MIs[2] Operand 1 |
| 56324 | // No operand predicates |
| 56325 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 56326 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56327 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 56328 | // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rd) => (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 56329 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2i64_indexed, |
| 56330 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56331 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56332 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 56333 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 56334 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 56335 | GIR_EraseFromParent, /*InsnID*/0, |
| 56336 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56337 | // GIR_Coverage, 4611, |
| 56338 | GIR_Done, |
| 56339 | // Label 3072: @144655 |
| 56340 | GIM_Try, /*On fail goto*//*Label 3073*/ 144750, // Rule ID 4674 // |
| 56341 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 56342 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 56343 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 56344 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 56345 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 56346 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 56347 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 56348 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 56349 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 56350 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56351 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 56352 | // (fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } (fneg:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 56353 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 56354 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 56355 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 56356 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 56357 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 56358 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 56359 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 56360 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 56361 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, |
| 56362 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56363 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56364 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 56365 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 56366 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 56367 | GIR_EraseFromParent, /*InsnID*/0, |
| 56368 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56369 | // GIR_Coverage, 4674, |
| 56370 | GIR_Done, |
| 56371 | // Label 3073: @144750 |
| 56372 | GIM_Try, /*On fail goto*//*Label 3074*/ 144847, // Rule ID 4638 // |
| 56373 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 56374 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 56375 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 56376 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 56377 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 56378 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 56379 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 56380 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 56381 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 56382 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 56383 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56384 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 56385 | // (fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 56386 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 56387 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 56388 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 56389 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 56390 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 56391 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 56392 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 56393 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 56394 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, |
| 56395 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56396 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56397 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 56398 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 56399 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 56400 | GIR_EraseFromParent, /*InsnID*/0, |
| 56401 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56402 | // GIR_Coverage, 4638, |
| 56403 | GIR_Done, |
| 56404 | // Label 3074: @144847 |
| 56405 | GIM_Try, /*On fail goto*//*Label 3075*/ 144944, // Rule ID 4651 // |
| 56406 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 56407 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 56408 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 56409 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 56410 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 56411 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, |
| 56412 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 56413 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 56414 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 56415 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 56416 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56417 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 56418 | // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 56419 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 56420 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 56421 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 56422 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 56423 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 56424 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 56425 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 56426 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 56427 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, |
| 56428 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56429 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56430 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 56431 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 56432 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 56433 | GIR_EraseFromParent, /*InsnID*/0, |
| 56434 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56435 | // GIR_Coverage, 4651, |
| 56436 | GIR_Done, |
| 56437 | // Label 3075: @144944 |
| 56438 | GIM_Try, /*On fail goto*//*Label 3076*/ 145041, // Rule ID 4664 // |
| 56439 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 56440 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 56441 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 56442 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 56443 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 56444 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 56445 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, |
| 56446 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 56447 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 56448 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 56449 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56450 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 56451 | // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 56452 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 56453 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 56454 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 56455 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 56456 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 56457 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 56458 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 56459 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 56460 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, |
| 56461 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56462 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56463 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 56464 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 56465 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 56466 | GIR_EraseFromParent, /*InsnID*/0, |
| 56467 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56468 | // GIR_Coverage, 4664, |
| 56469 | GIR_Done, |
| 56470 | // Label 3076: @145041 |
| 56471 | GIM_Try, /*On fail goto*//*Label 3077*/ 145136, // Rule ID 4685 // |
| 56472 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 56473 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 56474 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 56475 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 56476 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 56477 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 56478 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 56479 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 56480 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 56481 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56482 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 56483 | // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } (fneg:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 56484 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 56485 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 56486 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 56487 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 56488 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 56489 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 56490 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 56491 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 56492 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, |
| 56493 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56494 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56495 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 56496 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 56497 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 56498 | GIR_EraseFromParent, /*InsnID*/0, |
| 56499 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56500 | // GIR_Coverage, 4685, |
| 56501 | GIR_Done, |
| 56502 | // Label 3077: @145136 |
| 56503 | GIM_Try, /*On fail goto*//*Label 3078*/ 145233, // Rule ID 4625 // |
| 56504 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 56505 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 56506 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 56507 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 56508 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 56509 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 56510 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, |
| 56511 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 56512 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 56513 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 56514 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56515 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 56516 | // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 56517 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 56518 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 56519 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 56520 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 56521 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 56522 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 56523 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 56524 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 56525 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2i64_indexed, |
| 56526 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56527 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56528 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 56529 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 56530 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 56531 | GIR_EraseFromParent, /*InsnID*/0, |
| 56532 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56533 | // GIR_Coverage, 4625, |
| 56534 | GIR_Done, |
| 56535 | // Label 3078: @145233 |
| 56536 | GIM_Try, /*On fail goto*//*Label 3079*/ 145317, // Rule ID 2723 // |
| 56537 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 56538 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 56539 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 56540 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 56541 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 56542 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 56543 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 56544 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56545 | // (fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 56546 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 56547 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 56548 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 56549 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 56550 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 56551 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 56552 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 56553 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 56554 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2i64_indexed, |
| 56555 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56556 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56557 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 56558 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 56559 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 56560 | GIR_EraseFromParent, /*InsnID*/0, |
| 56561 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56562 | // GIR_Coverage, 2723, |
| 56563 | GIR_Done, |
| 56564 | // Label 3079: @145317 |
| 56565 | GIM_Try, /*On fail goto*//*Label 3080*/ 145370, // Rule ID 7632 // |
| 56566 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 56567 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 56568 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 56569 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 56570 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 56571 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 56572 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 56573 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56574 | // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) |
| 56575 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2f64, |
| 56576 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56577 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56578 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 56579 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 56580 | GIR_EraseFromParent, /*InsnID*/0, |
| 56581 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56582 | // GIR_Coverage, 7632, |
| 56583 | GIR_Done, |
| 56584 | // Label 3080: @145370 |
| 56585 | GIM_Try, /*On fail goto*//*Label 3081*/ 145454, // Rule ID 4612 // |
| 56586 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 56587 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 56588 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 56589 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 56590 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 56591 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 56592 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 56593 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56594 | // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rd) => (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 56595 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 56596 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 56597 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 56598 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 56599 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 56600 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 56601 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 56602 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 56603 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2i64_indexed, |
| 56604 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56605 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56606 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 56607 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 56608 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 56609 | GIR_EraseFromParent, /*InsnID*/0, |
| 56610 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56611 | // GIR_Coverage, 4612, |
| 56612 | GIR_Done, |
| 56613 | // Label 3081: @145454 |
| 56614 | GIM_Try, /*On fail goto*//*Label 3082*/ 145507, // Rule ID 1040 // |
| 56615 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 56616 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 56617 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 56618 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 56619 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 56620 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 56621 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 56622 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56623 | // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), V128:{ *:[v2f64] }:$Rd) => (FMLSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) |
| 56624 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv2f64, |
| 56625 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56626 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56627 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 56628 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 56629 | GIR_EraseFromParent, /*InsnID*/0, |
| 56630 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56631 | // GIR_Coverage, 1040, |
| 56632 | GIR_Done, |
| 56633 | // Label 3082: @145507 |
| 56634 | GIM_Try, /*On fail goto*//*Label 3083*/ 145547, // Rule ID 1035 // |
| 56635 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 56636 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 56637 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 56638 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 56639 | // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLAv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) |
| 56640 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv2f64, |
| 56641 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56642 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56643 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 56644 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm |
| 56645 | GIR_EraseFromParent, /*InsnID*/0, |
| 56646 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56647 | // GIR_Coverage, 1035, |
| 56648 | GIR_Done, |
| 56649 | // Label 3083: @145547 |
| 56650 | GIM_Reject, |
| 56651 | // Label 3064: @145548 |
| 56652 | GIM_Reject, |
| 56653 | // Label 2991: @145549 |
| 56654 | GIM_Try, /*On fail goto*//*Label 3084*/ 146754, |
| 56655 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 56656 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 56657 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, |
| 56658 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 56659 | GIM_Try, /*On fail goto*//*Label 3085*/ 145652, // Rule ID 4630 // |
| 56660 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 56661 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 56662 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 56663 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 56664 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 56665 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 56666 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 56667 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 56668 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 56669 | // MIs[2] Operand 1 |
| 56670 | // No operand predicates |
| 56671 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 56672 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, |
| 56673 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s16, |
| 56674 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 56675 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 56676 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56677 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 56678 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 56679 | // (fma:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) |
| 56680 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i16_indexed, |
| 56681 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56682 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56683 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 56684 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 56685 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 56686 | GIR_EraseFromParent, /*InsnID*/0, |
| 56687 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56688 | // GIR_Coverage, 4630, |
| 56689 | GIR_Done, |
| 56690 | // Label 3085: @145652 |
| 56691 | GIM_Try, /*On fail goto*//*Label 3086*/ 145737, // Rule ID 4643 // |
| 56692 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 56693 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 56694 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 56695 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 56696 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 56697 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, |
| 56698 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 56699 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 56700 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 56701 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 56702 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 56703 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 56704 | // MIs[3] Operand 1 |
| 56705 | // No operand predicates |
| 56706 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 56707 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 56708 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56709 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 56710 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 56711 | // (fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) |
| 56712 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i16_indexed, |
| 56713 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56714 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56715 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 56716 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 56717 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 56718 | GIR_EraseFromParent, /*InsnID*/0, |
| 56719 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56720 | // GIR_Coverage, 4643, |
| 56721 | GIR_Done, |
| 56722 | // Label 3086: @145737 |
| 56723 | GIM_Try, /*On fail goto*//*Label 3087*/ 145822, // Rule ID 4656 // |
| 56724 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 56725 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 56726 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 56727 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 56728 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 56729 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 56730 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, |
| 56731 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 56732 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 56733 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 56734 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 56735 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 56736 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 56737 | // MIs[3] Operand 1 |
| 56738 | // No operand predicates |
| 56739 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 56740 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56741 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 56742 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 56743 | // (fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) |
| 56744 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i16_indexed, |
| 56745 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56746 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56747 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 56748 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 56749 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 56750 | GIR_EraseFromParent, /*InsnID*/0, |
| 56751 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56752 | // GIR_Coverage, 4656, |
| 56753 | GIR_Done, |
| 56754 | // Label 3087: @145822 |
| 56755 | GIM_Try, /*On fail goto*//*Label 3088*/ 145907, // Rule ID 4617 // |
| 56756 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 56757 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 56758 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 56759 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 56760 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 56761 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 56762 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, |
| 56763 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 56764 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 56765 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 56766 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 56767 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 56768 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 56769 | // MIs[3] Operand 1 |
| 56770 | // No operand predicates |
| 56771 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 56772 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56773 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 56774 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 56775 | // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) |
| 56776 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i16_indexed, |
| 56777 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56778 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56779 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 56780 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 56781 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 56782 | GIR_EraseFromParent, /*InsnID*/0, |
| 56783 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56784 | // GIR_Coverage, 4617, |
| 56785 | GIR_Done, |
| 56786 | // Label 3088: @145907 |
| 56787 | GIM_Try, /*On fail goto*//*Label 3089*/ 145979, // Rule ID 2715 // |
| 56788 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 56789 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 56790 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 56791 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 56792 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 56793 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 56794 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 56795 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 56796 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 56797 | // MIs[2] Operand 1 |
| 56798 | // No operand predicates |
| 56799 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 56800 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 56801 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56802 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 56803 | // (fma:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) |
| 56804 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4i16_indexed, |
| 56805 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56806 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56807 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 56808 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 56809 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 56810 | GIR_EraseFromParent, /*InsnID*/0, |
| 56811 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56812 | // GIR_Coverage, 2715, |
| 56813 | GIR_Done, |
| 56814 | // Label 3089: @145979 |
| 56815 | GIM_Try, /*On fail goto*//*Label 3090*/ 146051, // Rule ID 4604 // |
| 56816 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 56817 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 56818 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 56819 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 56820 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 56821 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 56822 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 56823 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 56824 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 56825 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 56826 | // MIs[2] Operand 1 |
| 56827 | // No operand predicates |
| 56828 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 56829 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56830 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 56831 | // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rd) => (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) |
| 56832 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4i16_indexed, |
| 56833 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56834 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56835 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 56836 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 56837 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 56838 | GIR_EraseFromParent, /*InsnID*/0, |
| 56839 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56840 | // GIR_Coverage, 4604, |
| 56841 | GIR_Done, |
| 56842 | // Label 3090: @146051 |
| 56843 | GIM_Try, /*On fail goto*//*Label 3091*/ 146148, // Rule ID 4631 // |
| 56844 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 56845 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 56846 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 56847 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 56848 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, |
| 56849 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 56850 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 56851 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 56852 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 56853 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 56854 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56855 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 56856 | // (fma:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 56857 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 56858 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 56859 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 56860 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 56861 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 56862 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 56863 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 56864 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, |
| 56865 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i16_indexed, |
| 56866 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56867 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56868 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 56869 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 56870 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 56871 | GIR_EraseFromParent, /*InsnID*/0, |
| 56872 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56873 | // GIR_Coverage, 4631, |
| 56874 | GIR_Done, |
| 56875 | // Label 3091: @146148 |
| 56876 | GIM_Try, /*On fail goto*//*Label 3092*/ 146245, // Rule ID 4644 // |
| 56877 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 56878 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 56879 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 56880 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 56881 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 56882 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, |
| 56883 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 56884 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, |
| 56885 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 56886 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 56887 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56888 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 56889 | // (fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 56890 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 56891 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 56892 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 56893 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 56894 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 56895 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 56896 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 56897 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, |
| 56898 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i16_indexed, |
| 56899 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56900 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56901 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 56902 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 56903 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 56904 | GIR_EraseFromParent, /*InsnID*/0, |
| 56905 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56906 | // GIR_Coverage, 4644, |
| 56907 | GIR_Done, |
| 56908 | // Label 3092: @146245 |
| 56909 | GIM_Try, /*On fail goto*//*Label 3093*/ 146342, // Rule ID 4657 // |
| 56910 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 56911 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 56912 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 56913 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 56914 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 56915 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 56916 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, |
| 56917 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 56918 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, |
| 56919 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 56920 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56921 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 56922 | // (fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 56923 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 56924 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 56925 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 56926 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 56927 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 56928 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 56929 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 56930 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, |
| 56931 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i16_indexed, |
| 56932 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56933 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56934 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 56935 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 56936 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 56937 | GIR_EraseFromParent, /*InsnID*/0, |
| 56938 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56939 | // GIR_Coverage, 4657, |
| 56940 | GIR_Done, |
| 56941 | // Label 3093: @146342 |
| 56942 | GIM_Try, /*On fail goto*//*Label 3094*/ 146439, // Rule ID 4618 // |
| 56943 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 56944 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 56945 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 56946 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 56947 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 56948 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 56949 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, |
| 56950 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 56951 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, |
| 56952 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 56953 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56954 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 56955 | // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 56956 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 56957 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 56958 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 56959 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 56960 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 56961 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 56962 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 56963 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, |
| 56964 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i16_indexed, |
| 56965 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56966 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56967 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 56968 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 56969 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 56970 | GIR_EraseFromParent, /*InsnID*/0, |
| 56971 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 56972 | // GIR_Coverage, 4618, |
| 56973 | GIR_Done, |
| 56974 | // Label 3094: @146439 |
| 56975 | GIM_Try, /*On fail goto*//*Label 3095*/ 146523, // Rule ID 2716 // |
| 56976 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 56977 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 56978 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 56979 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 56980 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, |
| 56981 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 56982 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 56983 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 56984 | // (fma:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 56985 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 56986 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 56987 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 56988 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 56989 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 56990 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 56991 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 56992 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, |
| 56993 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4i16_indexed, |
| 56994 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 56995 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 56996 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 56997 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 56998 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 56999 | GIR_EraseFromParent, /*InsnID*/0, |
| 57000 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57001 | // GIR_Coverage, 2716, |
| 57002 | GIR_Done, |
| 57003 | // Label 3095: @146523 |
| 57004 | GIM_Try, /*On fail goto*//*Label 3096*/ 146576, // Rule ID 7628 // |
| 57005 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 57006 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 57007 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 57008 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 57009 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 57010 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 57011 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 57012 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57013 | // (fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 57014 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4f16, |
| 57015 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57016 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57017 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 57018 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 57019 | GIR_EraseFromParent, /*InsnID*/0, |
| 57020 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57021 | // GIR_Coverage, 7628, |
| 57022 | GIR_Done, |
| 57023 | // Label 3096: @146576 |
| 57024 | GIM_Try, /*On fail goto*//*Label 3097*/ 146660, // Rule ID 4605 // |
| 57025 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 57026 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 57027 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 57028 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 57029 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 57030 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, |
| 57031 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 57032 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57033 | // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rd) => (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 57034 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 57035 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 57036 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 57037 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 57038 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 57039 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 57040 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 57041 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, |
| 57042 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4i16_indexed, |
| 57043 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57044 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57045 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 57046 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 57047 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 57048 | GIR_EraseFromParent, /*InsnID*/0, |
| 57049 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57050 | // GIR_Coverage, 4605, |
| 57051 | GIR_Done, |
| 57052 | // Label 3097: @146660 |
| 57053 | GIM_Try, /*On fail goto*//*Label 3098*/ 146713, // Rule ID 1036 // |
| 57054 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 57055 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 57056 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 57057 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 57058 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 57059 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 57060 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 57061 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57062 | // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm), V64:{ *:[v4f16] }:$Rd) => (FMLSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 57063 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4f16, |
| 57064 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57065 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57066 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 57067 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 57068 | GIR_EraseFromParent, /*InsnID*/0, |
| 57069 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57070 | // GIR_Coverage, 1036, |
| 57071 | GIR_Done, |
| 57072 | // Label 3098: @146713 |
| 57073 | GIM_Try, /*On fail goto*//*Label 3099*/ 146753, // Rule ID 1031 // |
| 57074 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 57075 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 57076 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 57077 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 57078 | // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLAv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 57079 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4f16, |
| 57080 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57081 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57082 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 57083 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm |
| 57084 | GIR_EraseFromParent, /*InsnID*/0, |
| 57085 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57086 | // GIR_Coverage, 1031, |
| 57087 | GIR_Done, |
| 57088 | // Label 3099: @146753 |
| 57089 | GIM_Reject, |
| 57090 | // Label 3084: @146754 |
| 57091 | GIM_Reject, |
| 57092 | // Label 2992: @146755 |
| 57093 | GIM_Try, /*On fail goto*//*Label 3100*/ 148316, |
| 57094 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 57095 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 57096 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 57097 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 57098 | GIM_Try, /*On fail goto*//*Label 3101*/ 146856, // Rule ID 4670 // |
| 57099 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 57100 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 57101 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 57102 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 57103 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 57104 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 57105 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 57106 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57107 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 57108 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 57109 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 57110 | // MIs[3] Operand 1 |
| 57111 | // No operand predicates |
| 57112 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 57113 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57114 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57115 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 57116 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 57117 | // (fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 57118 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, |
| 57119 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57120 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57121 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 57122 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 57123 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 57124 | GIR_EraseFromParent, /*InsnID*/0, |
| 57125 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57126 | // GIR_Coverage, 4670, |
| 57127 | GIR_Done, |
| 57128 | // Label 3101: @146856 |
| 57129 | GIM_Try, /*On fail goto*//*Label 3102*/ 146941, // Rule ID 4635 // |
| 57130 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 57131 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 57132 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 57133 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 57134 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 57135 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57136 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 57137 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 57138 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 57139 | // MIs[2] Operand 1 |
| 57140 | // No operand predicates |
| 57141 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 57142 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, |
| 57143 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32, |
| 57144 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57145 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57146 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57147 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 57148 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 57149 | // (fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 57150 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, |
| 57151 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57152 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57153 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 57154 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 57155 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 57156 | GIR_EraseFromParent, /*InsnID*/0, |
| 57157 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57158 | // GIR_Coverage, 4635, |
| 57159 | GIR_Done, |
| 57160 | // Label 3102: @146941 |
| 57161 | GIM_Try, /*On fail goto*//*Label 3103*/ 147026, // Rule ID 4648 // |
| 57162 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 57163 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 57164 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 57165 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 57166 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 57167 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 57168 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 57169 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 57170 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57171 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 57172 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 57173 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 57174 | // MIs[3] Operand 1 |
| 57175 | // No operand predicates |
| 57176 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 57177 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57178 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57179 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 57180 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 57181 | // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 57182 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, |
| 57183 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57184 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57185 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 57186 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 57187 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 57188 | GIR_EraseFromParent, /*InsnID*/0, |
| 57189 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57190 | // GIR_Coverage, 4648, |
| 57191 | GIR_Done, |
| 57192 | // Label 3103: @147026 |
| 57193 | GIM_Try, /*On fail goto*//*Label 3104*/ 147111, // Rule ID 4661 // |
| 57194 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 57195 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 57196 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 57197 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 57198 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57199 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 57200 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 57201 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 57202 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 57203 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57204 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 57205 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 57206 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 57207 | // MIs[3] Operand 1 |
| 57208 | // No operand predicates |
| 57209 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57210 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57211 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 57212 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 57213 | // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 57214 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, |
| 57215 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57216 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57217 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 57218 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 57219 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 57220 | GIR_EraseFromParent, /*InsnID*/0, |
| 57221 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57222 | // GIR_Coverage, 4661, |
| 57223 | GIR_Done, |
| 57224 | // Label 3104: @147111 |
| 57225 | GIM_Try, /*On fail goto*//*Label 3105*/ 147194, // Rule ID 4681 // |
| 57226 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57227 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 57228 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 57229 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 57230 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 57231 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 57232 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 57233 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 57234 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57235 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 57236 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 57237 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 57238 | // MIs[3] Operand 1 |
| 57239 | // No operand predicates |
| 57240 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57241 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57242 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 57243 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 57244 | // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 57245 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, |
| 57246 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57247 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57248 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 57249 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 57250 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 57251 | GIR_EraseFromParent, /*InsnID*/0, |
| 57252 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57253 | // GIR_Coverage, 4681, |
| 57254 | GIR_Done, |
| 57255 | // Label 3105: @147194 |
| 57256 | GIM_Try, /*On fail goto*//*Label 3106*/ 147279, // Rule ID 4622 // |
| 57257 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 57258 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57259 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 57260 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 57261 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 57262 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 57263 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE32, |
| 57264 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 57265 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 57266 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57267 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 57268 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 57269 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 57270 | // MIs[3] Operand 1 |
| 57271 | // No operand predicates |
| 57272 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57273 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57274 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 57275 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 57276 | // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 57277 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, |
| 57278 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57279 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57280 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 57281 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 57282 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 57283 | GIR_EraseFromParent, /*InsnID*/0, |
| 57284 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57285 | // GIR_Coverage, 4622, |
| 57286 | GIR_Done, |
| 57287 | // Label 3106: @147279 |
| 57288 | GIM_Try, /*On fail goto*//*Label 3107*/ 147351, // Rule ID 2720 // |
| 57289 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 57290 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 57291 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 57292 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 57293 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 57294 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57295 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 57296 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 57297 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 57298 | // MIs[2] Operand 1 |
| 57299 | // No operand predicates |
| 57300 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 57301 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57302 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57303 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 57304 | // (fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 57305 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4i32_indexed, |
| 57306 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57307 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57308 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 57309 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 57310 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 57311 | GIR_EraseFromParent, /*InsnID*/0, |
| 57312 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57313 | // GIR_Coverage, 2720, |
| 57314 | GIR_Done, |
| 57315 | // Label 3107: @147351 |
| 57316 | GIM_Try, /*On fail goto*//*Label 3108*/ 147423, // Rule ID 4609 // |
| 57317 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 57318 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57319 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 57320 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE32, |
| 57321 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 57322 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 57323 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57324 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 57325 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 57326 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 57327 | // MIs[2] Operand 1 |
| 57328 | // No operand predicates |
| 57329 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57330 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57331 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 57332 | // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rd) => (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 57333 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4i32_indexed, |
| 57334 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57335 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57336 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 57337 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 57338 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 57339 | GIR_EraseFromParent, /*InsnID*/0, |
| 57340 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57341 | // GIR_Coverage, 4609, |
| 57342 | GIR_Done, |
| 57343 | // Label 3108: @147423 |
| 57344 | GIM_Try, /*On fail goto*//*Label 3109*/ 147518, // Rule ID 4672 // |
| 57345 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 57346 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 57347 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 57348 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 57349 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 57350 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 57351 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 57352 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 57353 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57354 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57355 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 57356 | // (fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) |
| 57357 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 57358 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 57359 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 57360 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 57361 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 57362 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 57363 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 57364 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 57365 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, |
| 57366 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57367 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57368 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 57369 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 57370 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 57371 | GIR_EraseFromParent, /*InsnID*/0, |
| 57372 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57373 | // GIR_Coverage, 4672, |
| 57374 | GIR_Done, |
| 57375 | // Label 3109: @147518 |
| 57376 | GIM_Try, /*On fail goto*//*Label 3110*/ 147615, // Rule ID 4636 // |
| 57377 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 57378 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 57379 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 57380 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 57381 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 57382 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 57383 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 57384 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 57385 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57386 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57387 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57388 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 57389 | // (fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) |
| 57390 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 57391 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 57392 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 57393 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 57394 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 57395 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 57396 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 57397 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 57398 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, |
| 57399 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57400 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57401 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 57402 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 57403 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 57404 | GIR_EraseFromParent, /*InsnID*/0, |
| 57405 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57406 | // GIR_Coverage, 4636, |
| 57407 | GIR_Done, |
| 57408 | // Label 3110: @147615 |
| 57409 | GIM_Try, /*On fail goto*//*Label 3111*/ 147712, // Rule ID 4649 // |
| 57410 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 57411 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 57412 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 57413 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 57414 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 57415 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, |
| 57416 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 57417 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 57418 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 57419 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57420 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57421 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 57422 | // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) |
| 57423 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 57424 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 57425 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 57426 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 57427 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 57428 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 57429 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 57430 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 57431 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, |
| 57432 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57433 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57434 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 57435 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 57436 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 57437 | GIR_EraseFromParent, /*InsnID*/0, |
| 57438 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57439 | // GIR_Coverage, 4649, |
| 57440 | GIR_Done, |
| 57441 | // Label 3111: @147712 |
| 57442 | GIM_Try, /*On fail goto*//*Label 3112*/ 147809, // Rule ID 4662 // |
| 57443 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 57444 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 57445 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 57446 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 57447 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57448 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 57449 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, |
| 57450 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 57451 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 57452 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57453 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57454 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 57455 | // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) |
| 57456 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 57457 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 57458 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 57459 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 57460 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 57461 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 57462 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 57463 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 57464 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, |
| 57465 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57466 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57467 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 57468 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 57469 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 57470 | GIR_EraseFromParent, /*InsnID*/0, |
| 57471 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57472 | // GIR_Coverage, 4662, |
| 57473 | GIR_Done, |
| 57474 | // Label 3112: @147809 |
| 57475 | GIM_Try, /*On fail goto*//*Label 3113*/ 147904, // Rule ID 4683 // |
| 57476 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57477 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 57478 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 57479 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 57480 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 57481 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 57482 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 57483 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 57484 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57485 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57486 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 57487 | // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) |
| 57488 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 57489 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 57490 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 57491 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 57492 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 57493 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 57494 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 57495 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 57496 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, |
| 57497 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57498 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57499 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 57500 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 57501 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 57502 | GIR_EraseFromParent, /*InsnID*/0, |
| 57503 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57504 | // GIR_Coverage, 4683, |
| 57505 | GIR_Done, |
| 57506 | // Label 3113: @147904 |
| 57507 | GIM_Try, /*On fail goto*//*Label 3114*/ 148001, // Rule ID 4623 // |
| 57508 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 57509 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57510 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 57511 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 57512 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 57513 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 57514 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, |
| 57515 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 57516 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 57517 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57518 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57519 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 57520 | // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) |
| 57521 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 57522 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 57523 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 57524 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 57525 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 57526 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 57527 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 57528 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 57529 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4i32_indexed, |
| 57530 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57531 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57532 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 57533 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 57534 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 57535 | GIR_EraseFromParent, /*InsnID*/0, |
| 57536 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57537 | // GIR_Coverage, 4623, |
| 57538 | GIR_Done, |
| 57539 | // Label 3114: @148001 |
| 57540 | GIM_Try, /*On fail goto*//*Label 3115*/ 148085, // Rule ID 2721 // |
| 57541 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 57542 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 57543 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 57544 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 57545 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 57546 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 57547 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57548 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57549 | // (fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) |
| 57550 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 57551 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 57552 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 57553 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 57554 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 57555 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 57556 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 57557 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 57558 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4i32_indexed, |
| 57559 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57560 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57561 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 57562 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 57563 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 57564 | GIR_EraseFromParent, /*InsnID*/0, |
| 57565 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57566 | // GIR_Coverage, 2721, |
| 57567 | GIR_Done, |
| 57568 | // Label 3115: @148085 |
| 57569 | GIM_Try, /*On fail goto*//*Label 3116*/ 148138, // Rule ID 7631 // |
| 57570 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 57571 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 57572 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 57573 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 57574 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57575 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 57576 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57577 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57578 | // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) |
| 57579 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4f32, |
| 57580 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57581 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57582 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 57583 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 57584 | GIR_EraseFromParent, /*InsnID*/0, |
| 57585 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57586 | // GIR_Coverage, 7631, |
| 57587 | GIR_Done, |
| 57588 | // Label 3116: @148138 |
| 57589 | GIM_Try, /*On fail goto*//*Label 3117*/ 148222, // Rule ID 4610 // |
| 57590 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 57591 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57592 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 57593 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 57594 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 57595 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 57596 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57597 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57598 | // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rd) => (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }) |
| 57599 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 57600 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 57601 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 57602 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 57603 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 57604 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 57605 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 57606 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 57607 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4i32_indexed, |
| 57608 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57609 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57610 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 57611 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 57612 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 57613 | GIR_EraseFromParent, /*InsnID*/0, |
| 57614 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57615 | // GIR_Coverage, 4610, |
| 57616 | GIR_Done, |
| 57617 | // Label 3117: @148222 |
| 57618 | GIM_Try, /*On fail goto*//*Label 3118*/ 148275, // Rule ID 1039 // |
| 57619 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 57620 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57621 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 57622 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 57623 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 57624 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57625 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57626 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57627 | // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), V128:{ *:[v4f32] }:$Rd) => (FMLSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) |
| 57628 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv4f32, |
| 57629 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57630 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57631 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 57632 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 57633 | GIR_EraseFromParent, /*InsnID*/0, |
| 57634 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57635 | // GIR_Coverage, 1039, |
| 57636 | GIR_Done, |
| 57637 | // Label 3118: @148275 |
| 57638 | GIM_Try, /*On fail goto*//*Label 3119*/ 148315, // Rule ID 1034 // |
| 57639 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 57640 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57641 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 57642 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57643 | // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLAv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) |
| 57644 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv4f32, |
| 57645 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57646 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57647 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 57648 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm |
| 57649 | GIR_EraseFromParent, /*InsnID*/0, |
| 57650 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57651 | // GIR_Coverage, 1034, |
| 57652 | GIR_Done, |
| 57653 | // Label 3119: @148315 |
| 57654 | GIM_Reject, |
| 57655 | // Label 3100: @148316 |
| 57656 | GIM_Reject, |
| 57657 | // Label 2993: @148317 |
| 57658 | GIM_Try, /*On fail goto*//*Label 3120*/ 149522, |
| 57659 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 57660 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 57661 | GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 57662 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 57663 | GIM_Try, /*On fail goto*//*Label 3121*/ 148420, // Rule ID 4628 // |
| 57664 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 57665 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 57666 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 57667 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 57668 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 57669 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 57670 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 57671 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 57672 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 57673 | // MIs[2] Operand 1 |
| 57674 | // No operand predicates |
| 57675 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 57676 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_FNEG, |
| 57677 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16, |
| 57678 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57679 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57680 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57681 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 57682 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 57683 | // (fma:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) |
| 57684 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8i16_indexed, |
| 57685 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57686 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57687 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 57688 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 57689 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 57690 | GIR_EraseFromParent, /*InsnID*/0, |
| 57691 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57692 | // GIR_Coverage, 4628, |
| 57693 | GIR_Done, |
| 57694 | // Label 3121: @148420 |
| 57695 | GIM_Try, /*On fail goto*//*Label 3122*/ 148505, // Rule ID 4641 // |
| 57696 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 57697 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 57698 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 57699 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 57700 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 57701 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, |
| 57702 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 57703 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 57704 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 57705 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 57706 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 57707 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 57708 | // MIs[3] Operand 1 |
| 57709 | // No operand predicates |
| 57710 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 57711 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57712 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57713 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 57714 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 57715 | // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) |
| 57716 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8i16_indexed, |
| 57717 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57718 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57719 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 57720 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 57721 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 57722 | GIR_EraseFromParent, /*InsnID*/0, |
| 57723 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57724 | // GIR_Coverage, 4641, |
| 57725 | GIR_Done, |
| 57726 | // Label 3122: @148505 |
| 57727 | GIM_Try, /*On fail goto*//*Label 3123*/ 148590, // Rule ID 4654 // |
| 57728 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 57729 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 57730 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 57731 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 57732 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57733 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 57734 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, |
| 57735 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 57736 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 57737 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 57738 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 57739 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 57740 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 57741 | // MIs[3] Operand 1 |
| 57742 | // No operand predicates |
| 57743 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57744 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57745 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 57746 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 57747 | // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) |
| 57748 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8i16_indexed, |
| 57749 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57750 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57751 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 57752 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 57753 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 57754 | GIR_EraseFromParent, /*InsnID*/0, |
| 57755 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57756 | // GIR_Coverage, 4654, |
| 57757 | GIR_Done, |
| 57758 | // Label 3123: @148590 |
| 57759 | GIM_Try, /*On fail goto*//*Label 3124*/ 148675, // Rule ID 4615 // |
| 57760 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 57761 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57762 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 57763 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 57764 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 57765 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 57766 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUPLANE16, |
| 57767 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 57768 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 57769 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 57770 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 57771 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 57772 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 57773 | // MIs[3] Operand 1 |
| 57774 | // No operand predicates |
| 57775 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57776 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57777 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 57778 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 57779 | // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) |
| 57780 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8i16_indexed, |
| 57781 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57782 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57783 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 57784 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 57785 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx |
| 57786 | GIR_EraseFromParent, /*InsnID*/0, |
| 57787 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57788 | // GIR_Coverage, 4615, |
| 57789 | GIR_Done, |
| 57790 | // Label 3124: @148675 |
| 57791 | GIM_Try, /*On fail goto*//*Label 3125*/ 148747, // Rule ID 2713 // |
| 57792 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 57793 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 57794 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 57795 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 57796 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 57797 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 57798 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 57799 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 57800 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 57801 | // MIs[2] Operand 1 |
| 57802 | // No operand predicates |
| 57803 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 57804 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57805 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57806 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 57807 | // (fma:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) |
| 57808 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv8i16_indexed, |
| 57809 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57810 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57811 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 57812 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 57813 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 57814 | GIR_EraseFromParent, /*InsnID*/0, |
| 57815 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57816 | // GIR_Coverage, 2713, |
| 57817 | GIR_Done, |
| 57818 | // Label 3125: @148747 |
| 57819 | GIM_Try, /*On fail goto*//*Label 3126*/ 148819, // Rule ID 4602 // |
| 57820 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 57821 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57822 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 57823 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUPLANE16, |
| 57824 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 57825 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 57826 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128_loRegClassID, |
| 57827 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 57828 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 57829 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 57830 | // MIs[2] Operand 1 |
| 57831 | // No operand predicates |
| 57832 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57833 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57834 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 57835 | // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rd) => (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) |
| 57836 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv8i16_indexed, |
| 57837 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57838 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57839 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 57840 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 57841 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx |
| 57842 | GIR_EraseFromParent, /*InsnID*/0, |
| 57843 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57844 | // GIR_Coverage, 4602, |
| 57845 | GIR_Done, |
| 57846 | // Label 3126: @148819 |
| 57847 | GIM_Try, /*On fail goto*//*Label 3127*/ 148916, // Rule ID 4629 // |
| 57848 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 57849 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 57850 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 57851 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 57852 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, |
| 57853 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 57854 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, |
| 57855 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 57856 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57857 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57858 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57859 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 57860 | // (fma:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 57861 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 57862 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 57863 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 57864 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 57865 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 57866 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 57867 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 57868 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, |
| 57869 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8i16_indexed, |
| 57870 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57871 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57872 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 57873 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 57874 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 57875 | GIR_EraseFromParent, /*InsnID*/0, |
| 57876 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57877 | // GIR_Coverage, 4629, |
| 57878 | GIR_Done, |
| 57879 | // Label 3127: @148916 |
| 57880 | GIM_Try, /*On fail goto*//*Label 3128*/ 149013, // Rule ID 4642 // |
| 57881 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 57882 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 57883 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 57884 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 57885 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 57886 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, |
| 57887 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 57888 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, |
| 57889 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 57890 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57891 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57892 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 57893 | // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 57894 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 57895 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 57896 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 57897 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 57898 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 57899 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 57900 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 57901 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, |
| 57902 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8i16_indexed, |
| 57903 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57904 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57905 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 57906 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 57907 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 57908 | GIR_EraseFromParent, /*InsnID*/0, |
| 57909 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57910 | // GIR_Coverage, 4642, |
| 57911 | GIR_Done, |
| 57912 | // Label 3128: @149013 |
| 57913 | GIM_Try, /*On fail goto*//*Label 3129*/ 149110, // Rule ID 4655 // |
| 57914 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 57915 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 57916 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 57917 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 57918 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57919 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 57920 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, |
| 57921 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 57922 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, |
| 57923 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57924 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57925 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 57926 | // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 57927 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 57928 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 57929 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 57930 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 57931 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 57932 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 57933 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 57934 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, |
| 57935 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8i16_indexed, |
| 57936 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57937 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57938 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 57939 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 57940 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 57941 | GIR_EraseFromParent, /*InsnID*/0, |
| 57942 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57943 | // GIR_Coverage, 4655, |
| 57944 | GIR_Done, |
| 57945 | // Label 3129: @149110 |
| 57946 | GIM_Try, /*On fail goto*//*Label 3130*/ 149207, // Rule ID 4616 // |
| 57947 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 57948 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 57949 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 57950 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 57951 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 57952 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 57953 | GIM_CheckOpcode, /*MI*/2, AArch64::G_DUP, |
| 57954 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 57955 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, |
| 57956 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57957 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57958 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 57959 | // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 57960 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 57961 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 57962 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 57963 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 57964 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 57965 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 57966 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 57967 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, |
| 57968 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8i16_indexed, |
| 57969 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57970 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 57971 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 57972 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 57973 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 57974 | GIR_EraseFromParent, /*InsnID*/0, |
| 57975 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 57976 | // GIR_Coverage, 4616, |
| 57977 | GIR_Done, |
| 57978 | // Label 3130: @149207 |
| 57979 | GIM_Try, /*On fail goto*//*Label 3131*/ 149291, // Rule ID 2714 // |
| 57980 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 57981 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 57982 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 57983 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 57984 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, |
| 57985 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 57986 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 57987 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 57988 | // (fma:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 57989 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 57990 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 57991 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 57992 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 57993 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 57994 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 57995 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 57996 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, |
| 57997 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv8i16_indexed, |
| 57998 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 57999 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 58000 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 58001 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 58002 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 58003 | GIR_EraseFromParent, /*InsnID*/0, |
| 58004 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58005 | // GIR_Coverage, 2714, |
| 58006 | GIR_Done, |
| 58007 | // Label 3131: @149291 |
| 58008 | GIM_Try, /*On fail goto*//*Label 3132*/ 149344, // Rule ID 7629 // |
| 58009 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 58010 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 58011 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 58012 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 58013 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 58014 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 58015 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 58016 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 58017 | // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 58018 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8f16, |
| 58019 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 58020 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 58021 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 58022 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 58023 | GIR_EraseFromParent, /*InsnID*/0, |
| 58024 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58025 | // GIR_Coverage, 7629, |
| 58026 | GIR_Done, |
| 58027 | // Label 3132: @149344 |
| 58028 | GIM_Try, /*On fail goto*//*Label 3133*/ 149428, // Rule ID 4603 // |
| 58029 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 58030 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 58031 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 58032 | GIM_CheckOpcode, /*MI*/1, AArch64::G_DUP, |
| 58033 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 58034 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16_loRegClassID, |
| 58035 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 58036 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 58037 | // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rd) => (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 58038 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 58039 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, |
| 58040 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 58041 | GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 58042 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 58043 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 58044 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 58045 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16_loRegClassID, |
| 58046 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv8i16_indexed, |
| 58047 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 58048 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 58049 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 58050 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 58051 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 58052 | GIR_EraseFromParent, /*InsnID*/0, |
| 58053 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58054 | // GIR_Coverage, 4603, |
| 58055 | GIR_Done, |
| 58056 | // Label 3133: @149428 |
| 58057 | GIM_Try, /*On fail goto*//*Label 3134*/ 149481, // Rule ID 1037 // |
| 58058 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 58059 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 58060 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 58061 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, |
| 58062 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 58063 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 58064 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 58065 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 58066 | // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm), V128:{ *:[v8f16] }:$Rd) => (FMLSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 58067 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv8f16, |
| 58068 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 58069 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 58070 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 58071 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 58072 | GIR_EraseFromParent, /*InsnID*/0, |
| 58073 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58074 | // GIR_Coverage, 1037, |
| 58075 | GIR_Done, |
| 58076 | // Label 3134: @149481 |
| 58077 | GIM_Try, /*On fail goto*//*Label 3135*/ 149521, // Rule ID 1032 // |
| 58078 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 58079 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 58080 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 58081 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AArch64::FPR128RegClassID, |
| 58082 | // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLAv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 58083 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLAv8f16, |
| 58084 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 58085 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rd |
| 58086 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 58087 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm |
| 58088 | GIR_EraseFromParent, /*InsnID*/0, |
| 58089 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58090 | // GIR_Coverage, 1032, |
| 58091 | GIR_Done, |
| 58092 | // Label 3135: @149521 |
| 58093 | GIM_Reject, |
| 58094 | // Label 3120: @149522 |
| 58095 | GIM_Reject, |
| 58096 | // Label 2994: @149523 |
| 58097 | GIM_Reject, |
| 58098 | // Label 51: @149524 |
| 58099 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 3144*/ 149796, |
| 58100 | /*GILLT_s16*//*Label 3136*/ 149540, |
| 58101 | /*GILLT_s32*//*Label 3137*/ 149572, |
| 58102 | /*GILLT_s64*//*Label 3138*/ 149604, 0, |
| 58103 | /*GILLT_v2s32*//*Label 3139*/ 149636, |
| 58104 | /*GILLT_v2s64*//*Label 3140*/ 149668, |
| 58105 | /*GILLT_v4s16*//*Label 3141*/ 149700, |
| 58106 | /*GILLT_v4s32*//*Label 3142*/ 149732, 0, |
| 58107 | /*GILLT_v8s16*//*Label 3143*/ 149764, |
| 58108 | // Label 3136: @149540 |
| 58109 | GIM_Try, /*On fail goto*//*Label 3145*/ 149571, // Rule ID 519 // |
| 58110 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 58111 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 58112 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 58113 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 58114 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 58115 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 58116 | // (fdiv:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FDIVHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) |
| 58117 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVHrr, |
| 58118 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58119 | // GIR_Coverage, 519, |
| 58120 | GIR_Done, |
| 58121 | // Label 3145: @149571 |
| 58122 | GIM_Reject, |
| 58123 | // Label 3137: @149572 |
| 58124 | GIM_Try, /*On fail goto*//*Label 3146*/ 149603, // Rule ID 520 // |
| 58125 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 58126 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 58127 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 58128 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 58129 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 58130 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 58131 | // (fdiv:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FDIVSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) |
| 58132 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVSrr, |
| 58133 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58134 | // GIR_Coverage, 520, |
| 58135 | GIR_Done, |
| 58136 | // Label 3146: @149603 |
| 58137 | GIM_Reject, |
| 58138 | // Label 3138: @149604 |
| 58139 | GIM_Try, /*On fail goto*//*Label 3147*/ 149635, // Rule ID 521 // |
| 58140 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 58141 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 58142 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 58143 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 58144 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 58145 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 58146 | // (fdiv:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FDIVDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) |
| 58147 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVDrr, |
| 58148 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58149 | // GIR_Coverage, 521, |
| 58150 | GIR_Done, |
| 58151 | // Label 3147: @149635 |
| 58152 | GIM_Reject, |
| 58153 | // Label 3139: @149636 |
| 58154 | GIM_Try, /*On fail goto*//*Label 3148*/ 149667, // Rule ID 988 // |
| 58155 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 58156 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 58157 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 58158 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 58159 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 58160 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 58161 | // (fdiv:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FDIVv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) |
| 58162 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVv2f32, |
| 58163 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58164 | // GIR_Coverage, 988, |
| 58165 | GIR_Done, |
| 58166 | // Label 3148: @149667 |
| 58167 | GIM_Reject, |
| 58168 | // Label 3140: @149668 |
| 58169 | GIM_Try, /*On fail goto*//*Label 3149*/ 149699, // Rule ID 990 // |
| 58170 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 58171 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 58172 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 58173 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 58174 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 58175 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 58176 | // (fdiv:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FDIVv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) |
| 58177 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVv2f64, |
| 58178 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58179 | // GIR_Coverage, 990, |
| 58180 | GIR_Done, |
| 58181 | // Label 3149: @149699 |
| 58182 | GIM_Reject, |
| 58183 | // Label 3141: @149700 |
| 58184 | GIM_Try, /*On fail goto*//*Label 3150*/ 149731, // Rule ID 986 // |
| 58185 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 58186 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 58187 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 58188 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 58189 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 58190 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 58191 | // (fdiv:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FDIVv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 58192 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVv4f16, |
| 58193 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58194 | // GIR_Coverage, 986, |
| 58195 | GIR_Done, |
| 58196 | // Label 3150: @149731 |
| 58197 | GIM_Reject, |
| 58198 | // Label 3142: @149732 |
| 58199 | GIM_Try, /*On fail goto*//*Label 3151*/ 149763, // Rule ID 989 // |
| 58200 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 58201 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 58202 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 58203 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 58204 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 58205 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 58206 | // (fdiv:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FDIVv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) |
| 58207 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVv4f32, |
| 58208 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58209 | // GIR_Coverage, 989, |
| 58210 | GIR_Done, |
| 58211 | // Label 3151: @149763 |
| 58212 | GIM_Reject, |
| 58213 | // Label 3143: @149764 |
| 58214 | GIM_Try, /*On fail goto*//*Label 3152*/ 149795, // Rule ID 987 // |
| 58215 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 58216 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 58217 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 58218 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 58219 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 58220 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 58221 | // (fdiv:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FDIVv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 58222 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FDIVv8f16, |
| 58223 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58224 | // GIR_Coverage, 987, |
| 58225 | GIR_Done, |
| 58226 | // Label 3152: @149795 |
| 58227 | GIM_Reject, |
| 58228 | // Label 3144: @149796 |
| 58229 | GIM_Reject, |
| 58230 | // Label 52: @149797 |
| 58231 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 3161*/ 150344, |
| 58232 | /*GILLT_s16*//*Label 3153*/ 149813, |
| 58233 | /*GILLT_s32*//*Label 3154*/ 149950, |
| 58234 | /*GILLT_s64*//*Label 3155*/ 150087, 0, |
| 58235 | /*GILLT_v2s32*//*Label 3156*/ 150224, |
| 58236 | /*GILLT_v2s64*//*Label 3157*/ 150248, |
| 58237 | /*GILLT_v4s16*//*Label 3158*/ 150272, |
| 58238 | /*GILLT_v4s32*//*Label 3159*/ 150296, 0, |
| 58239 | /*GILLT_v8s16*//*Label 3160*/ 150320, |
| 58240 | // Label 3153: @149813 |
| 58241 | GIM_Try, /*On fail goto*//*Label 3162*/ 149949, |
| 58242 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 58243 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 58244 | GIM_Try, /*On fail goto*//*Label 3163*/ 149884, // Rule ID 549 // |
| 58245 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 58246 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 58247 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, |
| 58248 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 58249 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 58250 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, |
| 58251 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 58252 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 58253 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR16RegClassID, |
| 58254 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 58255 | // (fneg:{ *:[f16] } (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)) => (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) |
| 58256 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDHrrr, |
| 58257 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 58258 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 58259 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 58260 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra |
| 58261 | GIR_EraseFromParent, /*InsnID*/0, |
| 58262 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58263 | // GIR_Coverage, 549, |
| 58264 | GIR_Done, |
| 58265 | // Label 3163: @149884 |
| 58266 | GIM_Try, /*On fail goto*//*Label 3164*/ 149933, // Rule ID 537 // |
| 58267 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 58268 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 58269 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
| 58270 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 58271 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 58272 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 58273 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 58274 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 58275 | // (fneg:{ *:[f16] } (fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)) => (FNMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) |
| 58276 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMULHrr, |
| 58277 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 58278 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 58279 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 58280 | GIR_EraseFromParent, /*InsnID*/0, |
| 58281 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58282 | // GIR_Coverage, 537, |
| 58283 | GIR_Done, |
| 58284 | // Label 3164: @149933 |
| 58285 | GIM_Try, /*On fail goto*//*Label 3165*/ 149948, // Rule ID 489 // |
| 58286 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 58287 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 58288 | // (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FNEGHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) |
| 58289 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGHr, |
| 58290 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58291 | // GIR_Coverage, 489, |
| 58292 | GIR_Done, |
| 58293 | // Label 3165: @149948 |
| 58294 | GIM_Reject, |
| 58295 | // Label 3162: @149949 |
| 58296 | GIM_Reject, |
| 58297 | // Label 3154: @149950 |
| 58298 | GIM_Try, /*On fail goto*//*Label 3166*/ 150086, |
| 58299 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 58300 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 58301 | GIM_Try, /*On fail goto*//*Label 3167*/ 150021, // Rule ID 550 // |
| 58302 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 58303 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 58304 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, |
| 58305 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 58306 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 58307 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 58308 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 58309 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 58310 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR32RegClassID, |
| 58311 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 58312 | // (fneg:{ *:[f32] } (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)) => (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) |
| 58313 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDSrrr, |
| 58314 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 58315 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 58316 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 58317 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra |
| 58318 | GIR_EraseFromParent, /*InsnID*/0, |
| 58319 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58320 | // GIR_Coverage, 550, |
| 58321 | GIR_Done, |
| 58322 | // Label 3167: @150021 |
| 58323 | GIM_Try, /*On fail goto*//*Label 3168*/ 150070, // Rule ID 538 // |
| 58324 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 58325 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 58326 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
| 58327 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 58328 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 58329 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 58330 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 58331 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 58332 | // (fneg:{ *:[f32] } (fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)) => (FNMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) |
| 58333 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMULSrr, |
| 58334 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 58335 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 58336 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 58337 | GIR_EraseFromParent, /*InsnID*/0, |
| 58338 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58339 | // GIR_Coverage, 538, |
| 58340 | GIR_Done, |
| 58341 | // Label 3168: @150070 |
| 58342 | GIM_Try, /*On fail goto*//*Label 3169*/ 150085, // Rule ID 490 // |
| 58343 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 58344 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 58345 | // (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FNEGSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) |
| 58346 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGSr, |
| 58347 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58348 | // GIR_Coverage, 490, |
| 58349 | GIR_Done, |
| 58350 | // Label 3169: @150085 |
| 58351 | GIM_Reject, |
| 58352 | // Label 3166: @150086 |
| 58353 | GIM_Reject, |
| 58354 | // Label 3155: @150087 |
| 58355 | GIM_Try, /*On fail goto*//*Label 3170*/ 150223, |
| 58356 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 58357 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 58358 | GIM_Try, /*On fail goto*//*Label 3171*/ 150158, // Rule ID 551 // |
| 58359 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 58360 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 58361 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, |
| 58362 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 58363 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 58364 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 58365 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 58366 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 58367 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/AArch64::FPR64RegClassID, |
| 58368 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 58369 | // (fneg:{ *:[f64] } (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)) => (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) |
| 58370 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMADDDrrr, |
| 58371 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 58372 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 58373 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 58374 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra |
| 58375 | GIR_EraseFromParent, /*InsnID*/0, |
| 58376 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58377 | // GIR_Coverage, 551, |
| 58378 | GIR_Done, |
| 58379 | // Label 3171: @150158 |
| 58380 | GIM_Try, /*On fail goto*//*Label 3172*/ 150207, // Rule ID 539 // |
| 58381 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 58382 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 58383 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
| 58384 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 58385 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 58386 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 58387 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 58388 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 58389 | // (fneg:{ *:[f64] } (fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)) => (FNMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) |
| 58390 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FNMULDrr, |
| 58391 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 58392 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 58393 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 58394 | GIR_EraseFromParent, /*InsnID*/0, |
| 58395 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58396 | // GIR_Coverage, 539, |
| 58397 | GIR_Done, |
| 58398 | // Label 3172: @150207 |
| 58399 | GIM_Try, /*On fail goto*//*Label 3173*/ 150222, // Rule ID 491 // |
| 58400 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 58401 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 58402 | // (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FNEGDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) |
| 58403 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGDr, |
| 58404 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58405 | // GIR_Coverage, 491, |
| 58406 | GIR_Done, |
| 58407 | // Label 3173: @150222 |
| 58408 | GIM_Reject, |
| 58409 | // Label 3170: @150223 |
| 58410 | GIM_Reject, |
| 58411 | // Label 3156: @150224 |
| 58412 | GIM_Try, /*On fail goto*//*Label 3174*/ 150247, // Rule ID 736 // |
| 58413 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 58414 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 58415 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 58416 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 58417 | // (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FNEGv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) |
| 58418 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGv2f32, |
| 58419 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58420 | // GIR_Coverage, 736, |
| 58421 | GIR_Done, |
| 58422 | // Label 3174: @150247 |
| 58423 | GIM_Reject, |
| 58424 | // Label 3157: @150248 |
| 58425 | GIM_Try, /*On fail goto*//*Label 3175*/ 150271, // Rule ID 738 // |
| 58426 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 58427 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 58428 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 58429 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 58430 | // (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FNEGv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) |
| 58431 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGv2f64, |
| 58432 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58433 | // GIR_Coverage, 738, |
| 58434 | GIR_Done, |
| 58435 | // Label 3175: @150271 |
| 58436 | GIM_Reject, |
| 58437 | // Label 3158: @150272 |
| 58438 | GIM_Try, /*On fail goto*//*Label 3176*/ 150295, // Rule ID 734 // |
| 58439 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 58440 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 58441 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 58442 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 58443 | // (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FNEGv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) |
| 58444 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGv4f16, |
| 58445 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58446 | // GIR_Coverage, 734, |
| 58447 | GIR_Done, |
| 58448 | // Label 3176: @150295 |
| 58449 | GIM_Reject, |
| 58450 | // Label 3159: @150296 |
| 58451 | GIM_Try, /*On fail goto*//*Label 3177*/ 150319, // Rule ID 737 // |
| 58452 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 58453 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 58454 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 58455 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 58456 | // (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FNEGv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) |
| 58457 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGv4f32, |
| 58458 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58459 | // GIR_Coverage, 737, |
| 58460 | GIR_Done, |
| 58461 | // Label 3177: @150319 |
| 58462 | GIM_Reject, |
| 58463 | // Label 3160: @150320 |
| 58464 | GIM_Try, /*On fail goto*//*Label 3178*/ 150343, // Rule ID 735 // |
| 58465 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 58466 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 58467 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 58468 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 58469 | // (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FNEGv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) |
| 58470 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FNEGv8f16, |
| 58471 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58472 | // GIR_Coverage, 735, |
| 58473 | GIR_Done, |
| 58474 | // Label 3178: @150343 |
| 58475 | GIM_Reject, |
| 58476 | // Label 3161: @150344 |
| 58477 | GIM_Reject, |
| 58478 | // Label 53: @150345 |
| 58479 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 8, /*)*//*default:*//*Label 3183*/ 150473, |
| 58480 | /*GILLT_s32*//*Label 3179*/ 150358, |
| 58481 | /*GILLT_s64*//*Label 3180*/ 150382, 0, 0, |
| 58482 | /*GILLT_v2s64*//*Label 3181*/ 150429, 0, |
| 58483 | /*GILLT_v4s32*//*Label 3182*/ 150451, |
| 58484 | // Label 3179: @150358 |
| 58485 | GIM_Try, /*On fail goto*//*Label 3184*/ 150381, // Rule ID 482 // |
| 58486 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 58487 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 58488 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 58489 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 58490 | // (fpextend:{ *:[f32] } FPR16:{ *:[f16] }:$Rn) => (FCVTSHr:{ *:[f32] } FPR16:{ *:[f16] }:$Rn) |
| 58491 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTSHr, |
| 58492 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58493 | // GIR_Coverage, 482, |
| 58494 | GIR_Done, |
| 58495 | // Label 3184: @150381 |
| 58496 | GIM_Reject, |
| 58497 | // Label 3180: @150382 |
| 58498 | GIM_Try, /*On fail goto*//*Label 3185*/ 150405, // Rule ID 481 // |
| 58499 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 58500 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 58501 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 58502 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 58503 | // (fpextend:{ *:[f64] } FPR16:{ *:[f16] }:$Rn) => (FCVTDHr:{ *:[f64] } FPR16:{ *:[f16] }:$Rn) |
| 58504 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTDHr, |
| 58505 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58506 | // GIR_Coverage, 481, |
| 58507 | GIR_Done, |
| 58508 | // Label 3185: @150405 |
| 58509 | GIM_Try, /*On fail goto*//*Label 3186*/ 150428, // Rule ID 483 // |
| 58510 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 58511 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 58512 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 58513 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 58514 | // (fpextend:{ *:[f64] } FPR32:{ *:[f32] }:$Rn) => (FCVTDSr:{ *:[f64] } FPR32:{ *:[f32] }:$Rn) |
| 58515 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTDSr, |
| 58516 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58517 | // GIR_Coverage, 483, |
| 58518 | GIR_Done, |
| 58519 | // Label 3186: @150428 |
| 58520 | GIM_Reject, |
| 58521 | // Label 3181: @150429 |
| 58522 | GIM_Try, /*On fail goto*//*Label 3187*/ 150450, // Rule ID 3974 // |
| 58523 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 58524 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 58525 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 58526 | // (fpextend:{ *:[v2f64] } V64:{ *:[v2f32] }:$Rn) => (FCVTLv2i32:{ *:[v2f64] } V64:{ *:[v2f32] }:$Rn) |
| 58527 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTLv2i32, |
| 58528 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58529 | // GIR_Coverage, 3974, |
| 58530 | GIR_Done, |
| 58531 | // Label 3187: @150450 |
| 58532 | GIM_Reject, |
| 58533 | // Label 3182: @150451 |
| 58534 | GIM_Try, /*On fail goto*//*Label 3188*/ 150472, // Rule ID 3975 // |
| 58535 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 58536 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 58537 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 58538 | // (fpextend:{ *:[v4f32] } V64:{ *:[v4f16] }:$Rn) => (FCVTLv4i16:{ *:[v4f32] } V64:{ *:[v4f16] }:$Rn) |
| 58539 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTLv4i16, |
| 58540 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58541 | // GIR_Coverage, 3975, |
| 58542 | GIR_Done, |
| 58543 | // Label 3188: @150472 |
| 58544 | GIM_Reject, |
| 58545 | // Label 3183: @150473 |
| 58546 | GIM_Reject, |
| 58547 | // Label 54: @150474 |
| 58548 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 7, /*)*//*default:*//*Label 3193*/ 150602, |
| 58549 | /*GILLT_s16*//*Label 3189*/ 150487, |
| 58550 | /*GILLT_s32*//*Label 3190*/ 150534, 0, 0, |
| 58551 | /*GILLT_v2s32*//*Label 3191*/ 150558, 0, |
| 58552 | /*GILLT_v4s16*//*Label 3192*/ 150580, |
| 58553 | // Label 3189: @150487 |
| 58554 | GIM_Try, /*On fail goto*//*Label 3194*/ 150510, // Rule ID 478 // |
| 58555 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 58556 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 58557 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 58558 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 58559 | // (fpround:{ *:[f16] } FPR64:{ *:[f64] }:$Rn) => (FCVTHDr:{ *:[f16] } FPR64:{ *:[f64] }:$Rn) |
| 58560 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTHDr, |
| 58561 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58562 | // GIR_Coverage, 478, |
| 58563 | GIR_Done, |
| 58564 | // Label 3194: @150510 |
| 58565 | GIM_Try, /*On fail goto*//*Label 3195*/ 150533, // Rule ID 485 // |
| 58566 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 58567 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 58568 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 58569 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 58570 | // (fpround:{ *:[f16] } FPR32:{ *:[f32] }:$Rn) => (FCVTHSr:{ *:[f16] } FPR32:{ *:[f32] }:$Rn) |
| 58571 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTHSr, |
| 58572 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58573 | // GIR_Coverage, 485, |
| 58574 | GIR_Done, |
| 58575 | // Label 3195: @150533 |
| 58576 | GIM_Reject, |
| 58577 | // Label 3190: @150534 |
| 58578 | GIM_Try, /*On fail goto*//*Label 3196*/ 150557, // Rule ID 480 // |
| 58579 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 58580 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 58581 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 58582 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 58583 | // (fpround:{ *:[f32] } FPR64:{ *:[f64] }:$Rn) => (FCVTSDr:{ *:[f32] } FPR64:{ *:[f64] }:$Rn) |
| 58584 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTSDr, |
| 58585 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58586 | // GIR_Coverage, 480, |
| 58587 | GIR_Done, |
| 58588 | // Label 3196: @150557 |
| 58589 | GIM_Reject, |
| 58590 | // Label 3191: @150558 |
| 58591 | GIM_Try, /*On fail goto*//*Label 3197*/ 150579, // Rule ID 3978 // |
| 58592 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 58593 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 58594 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 58595 | // (fpround:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn) => (FCVTNv2i32:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn) |
| 58596 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTNv2i32, |
| 58597 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58598 | // GIR_Coverage, 3978, |
| 58599 | GIR_Done, |
| 58600 | // Label 3197: @150579 |
| 58601 | GIM_Reject, |
| 58602 | // Label 3192: @150580 |
| 58603 | GIM_Try, /*On fail goto*//*Label 3198*/ 150601, // Rule ID 3979 // |
| 58604 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 58605 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 58606 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 58607 | // (fpround:{ *:[v4f16] } V128:{ *:[v4f32] }:$Rn) => (FCVTNv4i16:{ *:[v4f16] } V128:{ *:[v4f32] }:$Rn) |
| 58608 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTNv4i16, |
| 58609 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58610 | // GIR_Coverage, 3979, |
| 58611 | GIR_Done, |
| 58612 | // Label 3198: @150601 |
| 58613 | GIM_Reject, |
| 58614 | // Label 3193: @150602 |
| 58615 | GIM_Reject, |
| 58616 | // Label 55: @150603 |
| 58617 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 10, /*)*//*default:*//*Label 3206*/ 151502, |
| 58618 | /*GILLT_s32*//*Label 3199*/ 150618, |
| 58619 | /*GILLT_s64*//*Label 3200*/ 151000, 0, |
| 58620 | /*GILLT_v2s32*//*Label 3201*/ 151382, |
| 58621 | /*GILLT_v2s64*//*Label 3202*/ 151406, |
| 58622 | /*GILLT_v4s16*//*Label 3203*/ 151430, |
| 58623 | /*GILLT_v4s32*//*Label 3204*/ 151454, 0, |
| 58624 | /*GILLT_v8s16*//*Label 3205*/ 151478, |
| 58625 | // Label 3199: @150618 |
| 58626 | GIM_Try, /*On fail goto*//*Label 3207*/ 150657, // Rule ID 3903 // |
| 58627 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 58628 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 58629 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 58630 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, |
| 58631 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 58632 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 58633 | // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTPSUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn) |
| 58634 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUWSr, |
| 58635 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 58636 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 58637 | GIR_EraseFromParent, /*InsnID*/0, |
| 58638 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58639 | // GIR_Coverage, 3903, |
| 58640 | GIR_Done, |
| 58641 | // Label 3207: @150657 |
| 58642 | GIM_Try, /*On fail goto*//*Label 3208*/ 150696, // Rule ID 3905 // |
| 58643 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 58644 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 58645 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 58646 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, |
| 58647 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 58648 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 58649 | // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTPSUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn) |
| 58650 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUWDr, |
| 58651 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 58652 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 58653 | GIR_EraseFromParent, /*InsnID*/0, |
| 58654 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58655 | // GIR_Coverage, 3905, |
| 58656 | GIR_Done, |
| 58657 | // Label 3208: @150696 |
| 58658 | GIM_Try, /*On fail goto*//*Label 3209*/ 150735, // Rule ID 3911 // |
| 58659 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 58660 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 58661 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 58662 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, |
| 58663 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 58664 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 58665 | // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTMSUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn) |
| 58666 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUWSr, |
| 58667 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 58668 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 58669 | GIR_EraseFromParent, /*InsnID*/0, |
| 58670 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58671 | // GIR_Coverage, 3911, |
| 58672 | GIR_Done, |
| 58673 | // Label 3209: @150735 |
| 58674 | GIM_Try, /*On fail goto*//*Label 3210*/ 150774, // Rule ID 3913 // |
| 58675 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 58676 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 58677 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 58678 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, |
| 58679 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 58680 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 58681 | // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTMSUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn) |
| 58682 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUWDr, |
| 58683 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 58684 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 58685 | GIR_EraseFromParent, /*InsnID*/0, |
| 58686 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58687 | // GIR_Coverage, 3913, |
| 58688 | GIR_Done, |
| 58689 | // Label 3210: @150774 |
| 58690 | GIM_Try, /*On fail goto*//*Label 3211*/ 150813, // Rule ID 3927 // |
| 58691 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 58692 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 58693 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 58694 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, |
| 58695 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 58696 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 58697 | // (fp_to_sint:{ *:[i32] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTASUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn) |
| 58698 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUWSr, |
| 58699 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 58700 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 58701 | GIR_EraseFromParent, /*InsnID*/0, |
| 58702 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58703 | // GIR_Coverage, 3927, |
| 58704 | GIR_Done, |
| 58705 | // Label 3211: @150813 |
| 58706 | GIM_Try, /*On fail goto*//*Label 3212*/ 150852, // Rule ID 3929 // |
| 58707 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 58708 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 58709 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 58710 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, |
| 58711 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 58712 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 58713 | // (fp_to_sint:{ *:[i32] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTASUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn) |
| 58714 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUWDr, |
| 58715 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 58716 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 58717 | GIR_EraseFromParent, /*InsnID*/0, |
| 58718 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58719 | // GIR_Coverage, 3929, |
| 58720 | GIR_Done, |
| 58721 | // Label 3212: @150852 |
| 58722 | GIM_Try, /*On fail goto*//*Label 3213*/ 150891, // Rule ID 3919 // |
| 58723 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 58724 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 58725 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 58726 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_TRUNC, |
| 58727 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 58728 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 58729 | // (fp_to_sint:{ *:[i32] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTZSUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn) |
| 58730 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSUWSr, |
| 58731 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 58732 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 58733 | GIR_EraseFromParent, /*InsnID*/0, |
| 58734 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58735 | // GIR_Coverage, 3919, |
| 58736 | GIR_Done, |
| 58737 | // Label 3213: @150891 |
| 58738 | GIM_Try, /*On fail goto*//*Label 3214*/ 150930, // Rule ID 3921 // |
| 58739 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 58740 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 58741 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 58742 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_TRUNC, |
| 58743 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 58744 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 58745 | // (fp_to_sint:{ *:[i32] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTZSUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn) |
| 58746 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSUWDr, |
| 58747 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 58748 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 58749 | GIR_EraseFromParent, /*InsnID*/0, |
| 58750 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58751 | // GIR_Coverage, 3921, |
| 58752 | GIR_Done, |
| 58753 | // Label 3214: @150930 |
| 58754 | GIM_Try, /*On fail goto*//*Label 3215*/ 150953, // Rule ID 379 // |
| 58755 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 58756 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 58757 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 58758 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 58759 | // (fp_to_sint:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) => (FCVTZSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) |
| 58760 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSUWHr, |
| 58761 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58762 | // GIR_Coverage, 379, |
| 58763 | GIR_Done, |
| 58764 | // Label 3215: @150953 |
| 58765 | GIM_Try, /*On fail goto*//*Label 3216*/ 150976, // Rule ID 383 // |
| 58766 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 58767 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 58768 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 58769 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 58770 | // (fp_to_sint:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) => (FCVTZSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) |
| 58771 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSUWSr, |
| 58772 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58773 | // GIR_Coverage, 383, |
| 58774 | GIR_Done, |
| 58775 | // Label 3216: @150976 |
| 58776 | GIM_Try, /*On fail goto*//*Label 3217*/ 150999, // Rule ID 387 // |
| 58777 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 58778 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 58779 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 58780 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 58781 | // (fp_to_sint:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) => (FCVTZSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) |
| 58782 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSUWDr, |
| 58783 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58784 | // GIR_Coverage, 387, |
| 58785 | GIR_Done, |
| 58786 | // Label 3217: @150999 |
| 58787 | GIM_Reject, |
| 58788 | // Label 3200: @151000 |
| 58789 | GIM_Try, /*On fail goto*//*Label 3218*/ 151039, // Rule ID 3904 // |
| 58790 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 58791 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 58792 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 58793 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, |
| 58794 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 58795 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 58796 | // (fp_to_sint:{ *:[i64] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTPSUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn) |
| 58797 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUXSr, |
| 58798 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 58799 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 58800 | GIR_EraseFromParent, /*InsnID*/0, |
| 58801 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58802 | // GIR_Coverage, 3904, |
| 58803 | GIR_Done, |
| 58804 | // Label 3218: @151039 |
| 58805 | GIM_Try, /*On fail goto*//*Label 3219*/ 151078, // Rule ID 3906 // |
| 58806 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 58807 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 58808 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 58809 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, |
| 58810 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 58811 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 58812 | // (fp_to_sint:{ *:[i64] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTPSUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn) |
| 58813 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPSUXDr, |
| 58814 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 58815 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 58816 | GIR_EraseFromParent, /*InsnID*/0, |
| 58817 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58818 | // GIR_Coverage, 3906, |
| 58819 | GIR_Done, |
| 58820 | // Label 3219: @151078 |
| 58821 | GIM_Try, /*On fail goto*//*Label 3220*/ 151117, // Rule ID 3912 // |
| 58822 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 58823 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 58824 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 58825 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, |
| 58826 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 58827 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 58828 | // (fp_to_sint:{ *:[i64] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTMSUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn) |
| 58829 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUXSr, |
| 58830 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 58831 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 58832 | GIR_EraseFromParent, /*InsnID*/0, |
| 58833 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58834 | // GIR_Coverage, 3912, |
| 58835 | GIR_Done, |
| 58836 | // Label 3220: @151117 |
| 58837 | GIM_Try, /*On fail goto*//*Label 3221*/ 151156, // Rule ID 3914 // |
| 58838 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 58839 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 58840 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 58841 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, |
| 58842 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 58843 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 58844 | // (fp_to_sint:{ *:[i64] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTMSUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn) |
| 58845 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMSUXDr, |
| 58846 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 58847 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 58848 | GIR_EraseFromParent, /*InsnID*/0, |
| 58849 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58850 | // GIR_Coverage, 3914, |
| 58851 | GIR_Done, |
| 58852 | // Label 3221: @151156 |
| 58853 | GIM_Try, /*On fail goto*//*Label 3222*/ 151195, // Rule ID 3928 // |
| 58854 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 58855 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 58856 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 58857 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, |
| 58858 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 58859 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 58860 | // (fp_to_sint:{ *:[i64] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTASUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn) |
| 58861 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUXSr, |
| 58862 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 58863 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 58864 | GIR_EraseFromParent, /*InsnID*/0, |
| 58865 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58866 | // GIR_Coverage, 3928, |
| 58867 | GIR_Done, |
| 58868 | // Label 3222: @151195 |
| 58869 | GIM_Try, /*On fail goto*//*Label 3223*/ 151234, // Rule ID 3930 // |
| 58870 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 58871 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 58872 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 58873 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, |
| 58874 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 58875 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 58876 | // (fp_to_sint:{ *:[i64] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTASUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn) |
| 58877 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTASUXDr, |
| 58878 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 58879 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 58880 | GIR_EraseFromParent, /*InsnID*/0, |
| 58881 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58882 | // GIR_Coverage, 3930, |
| 58883 | GIR_Done, |
| 58884 | // Label 3223: @151234 |
| 58885 | GIM_Try, /*On fail goto*//*Label 3224*/ 151273, // Rule ID 3920 // |
| 58886 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 58887 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 58888 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 58889 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_TRUNC, |
| 58890 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 58891 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 58892 | // (fp_to_sint:{ *:[i64] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTZSUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn) |
| 58893 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSUXSr, |
| 58894 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 58895 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 58896 | GIR_EraseFromParent, /*InsnID*/0, |
| 58897 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58898 | // GIR_Coverage, 3920, |
| 58899 | GIR_Done, |
| 58900 | // Label 3224: @151273 |
| 58901 | GIM_Try, /*On fail goto*//*Label 3225*/ 151312, // Rule ID 3922 // |
| 58902 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 58903 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 58904 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 58905 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_TRUNC, |
| 58906 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 58907 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 58908 | // (fp_to_sint:{ *:[i64] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTZSUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn) |
| 58909 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZSUXDr, |
| 58910 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 58911 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 58912 | GIR_EraseFromParent, /*InsnID*/0, |
| 58913 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58914 | // GIR_Coverage, 3922, |
| 58915 | GIR_Done, |
| 58916 | // Label 3225: @151312 |
| 58917 | GIM_Try, /*On fail goto*//*Label 3226*/ 151335, // Rule ID 381 // |
| 58918 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 58919 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 58920 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 58921 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 58922 | // (fp_to_sint:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) => (FCVTZSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) |
| 58923 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSUXHr, |
| 58924 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58925 | // GIR_Coverage, 381, |
| 58926 | GIR_Done, |
| 58927 | // Label 3226: @151335 |
| 58928 | GIM_Try, /*On fail goto*//*Label 3227*/ 151358, // Rule ID 385 // |
| 58929 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 58930 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 58931 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 58932 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 58933 | // (fp_to_sint:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) => (FCVTZSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) |
| 58934 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSUXSr, |
| 58935 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58936 | // GIR_Coverage, 385, |
| 58937 | GIR_Done, |
| 58938 | // Label 3227: @151358 |
| 58939 | GIM_Try, /*On fail goto*//*Label 3228*/ 151381, // Rule ID 389 // |
| 58940 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 58941 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 58942 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 58943 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 58944 | // (fp_to_sint:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) => (FCVTZSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) |
| 58945 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSUXDr, |
| 58946 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58947 | // GIR_Coverage, 389, |
| 58948 | GIR_Done, |
| 58949 | // Label 3228: @151381 |
| 58950 | GIM_Reject, |
| 58951 | // Label 3201: @151382 |
| 58952 | GIM_Try, /*On fail goto*//*Label 3229*/ 151405, // Rule ID 726 // |
| 58953 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 58954 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 58955 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 58956 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 58957 | // (fp_to_sint:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) => (FCVTZSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) |
| 58958 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSv2f32, |
| 58959 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58960 | // GIR_Coverage, 726, |
| 58961 | GIR_Done, |
| 58962 | // Label 3229: @151405 |
| 58963 | GIM_Reject, |
| 58964 | // Label 3202: @151406 |
| 58965 | GIM_Try, /*On fail goto*//*Label 3230*/ 151429, // Rule ID 728 // |
| 58966 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 58967 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 58968 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 58969 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 58970 | // (fp_to_sint:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) => (FCVTZSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) |
| 58971 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSv2f64, |
| 58972 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58973 | // GIR_Coverage, 728, |
| 58974 | GIR_Done, |
| 58975 | // Label 3230: @151429 |
| 58976 | GIM_Reject, |
| 58977 | // Label 3203: @151430 |
| 58978 | GIM_Try, /*On fail goto*//*Label 3231*/ 151453, // Rule ID 724 // |
| 58979 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 58980 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 58981 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 58982 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 58983 | // (fp_to_sint:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) => (FCVTZSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) |
| 58984 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSv4f16, |
| 58985 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58986 | // GIR_Coverage, 724, |
| 58987 | GIR_Done, |
| 58988 | // Label 3231: @151453 |
| 58989 | GIM_Reject, |
| 58990 | // Label 3204: @151454 |
| 58991 | GIM_Try, /*On fail goto*//*Label 3232*/ 151477, // Rule ID 727 // |
| 58992 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 58993 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 58994 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 58995 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 58996 | // (fp_to_sint:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) => (FCVTZSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) |
| 58997 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSv4f32, |
| 58998 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 58999 | // GIR_Coverage, 727, |
| 59000 | GIR_Done, |
| 59001 | // Label 3232: @151477 |
| 59002 | GIM_Reject, |
| 59003 | // Label 3205: @151478 |
| 59004 | GIM_Try, /*On fail goto*//*Label 3233*/ 151501, // Rule ID 725 // |
| 59005 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 59006 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 59007 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 59008 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 59009 | // (fp_to_sint:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) => (FCVTZSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) |
| 59010 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZSv8f16, |
| 59011 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59012 | // GIR_Coverage, 725, |
| 59013 | GIR_Done, |
| 59014 | // Label 3233: @151501 |
| 59015 | GIM_Reject, |
| 59016 | // Label 3206: @151502 |
| 59017 | GIM_Reject, |
| 59018 | // Label 56: @151503 |
| 59019 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 10, /*)*//*default:*//*Label 3241*/ 152402, |
| 59020 | /*GILLT_s32*//*Label 3234*/ 151518, |
| 59021 | /*GILLT_s64*//*Label 3235*/ 151900, 0, |
| 59022 | /*GILLT_v2s32*//*Label 3236*/ 152282, |
| 59023 | /*GILLT_v2s64*//*Label 3237*/ 152306, |
| 59024 | /*GILLT_v4s16*//*Label 3238*/ 152330, |
| 59025 | /*GILLT_v4s32*//*Label 3239*/ 152354, 0, |
| 59026 | /*GILLT_v8s16*//*Label 3240*/ 152378, |
| 59027 | // Label 3234: @151518 |
| 59028 | GIM_Try, /*On fail goto*//*Label 3242*/ 151557, // Rule ID 3907 // |
| 59029 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 59030 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 59031 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 59032 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, |
| 59033 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 59034 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 59035 | // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTPUUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn) |
| 59036 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUWSr, |
| 59037 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 59038 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 59039 | GIR_EraseFromParent, /*InsnID*/0, |
| 59040 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59041 | // GIR_Coverage, 3907, |
| 59042 | GIR_Done, |
| 59043 | // Label 3242: @151557 |
| 59044 | GIM_Try, /*On fail goto*//*Label 3243*/ 151596, // Rule ID 3909 // |
| 59045 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 59046 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 59047 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 59048 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, |
| 59049 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 59050 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 59051 | // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTPUUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn) |
| 59052 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUWDr, |
| 59053 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 59054 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 59055 | GIR_EraseFromParent, /*InsnID*/0, |
| 59056 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59057 | // GIR_Coverage, 3909, |
| 59058 | GIR_Done, |
| 59059 | // Label 3243: @151596 |
| 59060 | GIM_Try, /*On fail goto*//*Label 3244*/ 151635, // Rule ID 3915 // |
| 59061 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 59062 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 59063 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 59064 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, |
| 59065 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 59066 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 59067 | // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTMUUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn) |
| 59068 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUWSr, |
| 59069 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 59070 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 59071 | GIR_EraseFromParent, /*InsnID*/0, |
| 59072 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59073 | // GIR_Coverage, 3915, |
| 59074 | GIR_Done, |
| 59075 | // Label 3244: @151635 |
| 59076 | GIM_Try, /*On fail goto*//*Label 3245*/ 151674, // Rule ID 3917 // |
| 59077 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 59078 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 59079 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 59080 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, |
| 59081 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 59082 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 59083 | // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTMUUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn) |
| 59084 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUWDr, |
| 59085 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 59086 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 59087 | GIR_EraseFromParent, /*InsnID*/0, |
| 59088 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59089 | // GIR_Coverage, 3917, |
| 59090 | GIR_Done, |
| 59091 | // Label 3245: @151674 |
| 59092 | GIM_Try, /*On fail goto*//*Label 3246*/ 151713, // Rule ID 3931 // |
| 59093 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 59094 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 59095 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 59096 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, |
| 59097 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 59098 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 59099 | // (fp_to_uint:{ *:[i32] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTAUUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn) |
| 59100 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUWSr, |
| 59101 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 59102 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 59103 | GIR_EraseFromParent, /*InsnID*/0, |
| 59104 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59105 | // GIR_Coverage, 3931, |
| 59106 | GIR_Done, |
| 59107 | // Label 3246: @151713 |
| 59108 | GIM_Try, /*On fail goto*//*Label 3247*/ 151752, // Rule ID 3933 // |
| 59109 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 59110 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 59111 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 59112 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, |
| 59113 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 59114 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 59115 | // (fp_to_uint:{ *:[i32] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTAUUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn) |
| 59116 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUWDr, |
| 59117 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 59118 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 59119 | GIR_EraseFromParent, /*InsnID*/0, |
| 59120 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59121 | // GIR_Coverage, 3933, |
| 59122 | GIR_Done, |
| 59123 | // Label 3247: @151752 |
| 59124 | GIM_Try, /*On fail goto*//*Label 3248*/ 151791, // Rule ID 3923 // |
| 59125 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 59126 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 59127 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 59128 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_TRUNC, |
| 59129 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 59130 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 59131 | // (fp_to_uint:{ *:[i32] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTZUUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn) |
| 59132 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUUWSr, |
| 59133 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 59134 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 59135 | GIR_EraseFromParent, /*InsnID*/0, |
| 59136 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59137 | // GIR_Coverage, 3923, |
| 59138 | GIR_Done, |
| 59139 | // Label 3248: @151791 |
| 59140 | GIM_Try, /*On fail goto*//*Label 3249*/ 151830, // Rule ID 3925 // |
| 59141 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 59142 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 59143 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 59144 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_TRUNC, |
| 59145 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 59146 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 59147 | // (fp_to_uint:{ *:[i32] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTZUUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn) |
| 59148 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUUWDr, |
| 59149 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 59150 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 59151 | GIR_EraseFromParent, /*InsnID*/0, |
| 59152 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59153 | // GIR_Coverage, 3925, |
| 59154 | GIR_Done, |
| 59155 | // Label 3249: @151830 |
| 59156 | GIM_Try, /*On fail goto*//*Label 3250*/ 151853, // Rule ID 391 // |
| 59157 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 59158 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 59159 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 59160 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 59161 | // (fp_to_uint:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) => (FCVTZUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) |
| 59162 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUUWHr, |
| 59163 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59164 | // GIR_Coverage, 391, |
| 59165 | GIR_Done, |
| 59166 | // Label 3250: @151853 |
| 59167 | GIM_Try, /*On fail goto*//*Label 3251*/ 151876, // Rule ID 395 // |
| 59168 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 59169 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 59170 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 59171 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 59172 | // (fp_to_uint:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) => (FCVTZUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) |
| 59173 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUUWSr, |
| 59174 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59175 | // GIR_Coverage, 395, |
| 59176 | GIR_Done, |
| 59177 | // Label 3251: @151876 |
| 59178 | GIM_Try, /*On fail goto*//*Label 3252*/ 151899, // Rule ID 399 // |
| 59179 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 59180 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 59181 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 59182 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 59183 | // (fp_to_uint:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) => (FCVTZUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) |
| 59184 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUUWDr, |
| 59185 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59186 | // GIR_Coverage, 399, |
| 59187 | GIR_Done, |
| 59188 | // Label 3252: @151899 |
| 59189 | GIM_Reject, |
| 59190 | // Label 3235: @151900 |
| 59191 | GIM_Try, /*On fail goto*//*Label 3253*/ 151939, // Rule ID 3908 // |
| 59192 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 59193 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 59194 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 59195 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, |
| 59196 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 59197 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 59198 | // (fp_to_uint:{ *:[i64] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTPUUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn) |
| 59199 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUXSr, |
| 59200 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 59201 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 59202 | GIR_EraseFromParent, /*InsnID*/0, |
| 59203 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59204 | // GIR_Coverage, 3908, |
| 59205 | GIR_Done, |
| 59206 | // Label 3253: @151939 |
| 59207 | GIM_Try, /*On fail goto*//*Label 3254*/ 151978, // Rule ID 3910 // |
| 59208 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 59209 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 59210 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 59211 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, |
| 59212 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 59213 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 59214 | // (fp_to_uint:{ *:[i64] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTPUUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn) |
| 59215 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTPUUXDr, |
| 59216 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 59217 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 59218 | GIR_EraseFromParent, /*InsnID*/0, |
| 59219 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59220 | // GIR_Coverage, 3910, |
| 59221 | GIR_Done, |
| 59222 | // Label 3254: @151978 |
| 59223 | GIM_Try, /*On fail goto*//*Label 3255*/ 152017, // Rule ID 3916 // |
| 59224 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 59225 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 59226 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 59227 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, |
| 59228 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 59229 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 59230 | // (fp_to_uint:{ *:[i64] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTMUUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn) |
| 59231 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUXSr, |
| 59232 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 59233 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 59234 | GIR_EraseFromParent, /*InsnID*/0, |
| 59235 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59236 | // GIR_Coverage, 3916, |
| 59237 | GIR_Done, |
| 59238 | // Label 3255: @152017 |
| 59239 | GIM_Try, /*On fail goto*//*Label 3256*/ 152056, // Rule ID 3918 // |
| 59240 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 59241 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 59242 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 59243 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, |
| 59244 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 59245 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 59246 | // (fp_to_uint:{ *:[i64] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTMUUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn) |
| 59247 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTMUUXDr, |
| 59248 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 59249 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 59250 | GIR_EraseFromParent, /*InsnID*/0, |
| 59251 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59252 | // GIR_Coverage, 3918, |
| 59253 | GIR_Done, |
| 59254 | // Label 3256: @152056 |
| 59255 | GIM_Try, /*On fail goto*//*Label 3257*/ 152095, // Rule ID 3932 // |
| 59256 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 59257 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 59258 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 59259 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, |
| 59260 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 59261 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 59262 | // (fp_to_uint:{ *:[i64] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTAUUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn) |
| 59263 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUXSr, |
| 59264 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 59265 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 59266 | GIR_EraseFromParent, /*InsnID*/0, |
| 59267 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59268 | // GIR_Coverage, 3932, |
| 59269 | GIR_Done, |
| 59270 | // Label 3257: @152095 |
| 59271 | GIM_Try, /*On fail goto*//*Label 3258*/ 152134, // Rule ID 3934 // |
| 59272 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 59273 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 59274 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 59275 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, |
| 59276 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 59277 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 59278 | // (fp_to_uint:{ *:[i64] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTAUUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn) |
| 59279 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTAUUXDr, |
| 59280 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 59281 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 59282 | GIR_EraseFromParent, /*InsnID*/0, |
| 59283 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59284 | // GIR_Coverage, 3934, |
| 59285 | GIR_Done, |
| 59286 | // Label 3258: @152134 |
| 59287 | GIM_Try, /*On fail goto*//*Label 3259*/ 152173, // Rule ID 3924 // |
| 59288 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 59289 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 59290 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 59291 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_TRUNC, |
| 59292 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 59293 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 59294 | // (fp_to_uint:{ *:[i64] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTZUUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn) |
| 59295 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUUXSr, |
| 59296 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 59297 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 59298 | GIR_EraseFromParent, /*InsnID*/0, |
| 59299 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59300 | // GIR_Coverage, 3924, |
| 59301 | GIR_Done, |
| 59302 | // Label 3259: @152173 |
| 59303 | GIM_Try, /*On fail goto*//*Label 3260*/ 152212, // Rule ID 3926 // |
| 59304 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 59305 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 59306 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 59307 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_TRUNC, |
| 59308 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 59309 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 59310 | // (fp_to_uint:{ *:[i64] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTZUUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn) |
| 59311 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FCVTZUUXDr, |
| 59312 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 59313 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 59314 | GIR_EraseFromParent, /*InsnID*/0, |
| 59315 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59316 | // GIR_Coverage, 3926, |
| 59317 | GIR_Done, |
| 59318 | // Label 3260: @152212 |
| 59319 | GIM_Try, /*On fail goto*//*Label 3261*/ 152235, // Rule ID 393 // |
| 59320 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 59321 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 59322 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 59323 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 59324 | // (fp_to_uint:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) => (FCVTZUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) |
| 59325 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUUXHr, |
| 59326 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59327 | // GIR_Coverage, 393, |
| 59328 | GIR_Done, |
| 59329 | // Label 3261: @152235 |
| 59330 | GIM_Try, /*On fail goto*//*Label 3262*/ 152258, // Rule ID 397 // |
| 59331 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 59332 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 59333 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 59334 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 59335 | // (fp_to_uint:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) => (FCVTZUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) |
| 59336 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUUXSr, |
| 59337 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59338 | // GIR_Coverage, 397, |
| 59339 | GIR_Done, |
| 59340 | // Label 3262: @152258 |
| 59341 | GIM_Try, /*On fail goto*//*Label 3263*/ 152281, // Rule ID 401 // |
| 59342 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 59343 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 59344 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 59345 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 59346 | // (fp_to_uint:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) => (FCVTZUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) |
| 59347 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUUXDr, |
| 59348 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59349 | // GIR_Coverage, 401, |
| 59350 | GIR_Done, |
| 59351 | // Label 3263: @152281 |
| 59352 | GIM_Reject, |
| 59353 | // Label 3236: @152282 |
| 59354 | GIM_Try, /*On fail goto*//*Label 3264*/ 152305, // Rule ID 731 // |
| 59355 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 59356 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 59357 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 59358 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 59359 | // (fp_to_uint:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) => (FCVTZUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) |
| 59360 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUv2f32, |
| 59361 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59362 | // GIR_Coverage, 731, |
| 59363 | GIR_Done, |
| 59364 | // Label 3264: @152305 |
| 59365 | GIM_Reject, |
| 59366 | // Label 3237: @152306 |
| 59367 | GIM_Try, /*On fail goto*//*Label 3265*/ 152329, // Rule ID 733 // |
| 59368 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 59369 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 59370 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 59371 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 59372 | // (fp_to_uint:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) => (FCVTZUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) |
| 59373 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUv2f64, |
| 59374 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59375 | // GIR_Coverage, 733, |
| 59376 | GIR_Done, |
| 59377 | // Label 3265: @152329 |
| 59378 | GIM_Reject, |
| 59379 | // Label 3238: @152330 |
| 59380 | GIM_Try, /*On fail goto*//*Label 3266*/ 152353, // Rule ID 729 // |
| 59381 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 59382 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 59383 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 59384 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 59385 | // (fp_to_uint:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) => (FCVTZUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) |
| 59386 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUv4f16, |
| 59387 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59388 | // GIR_Coverage, 729, |
| 59389 | GIR_Done, |
| 59390 | // Label 3266: @152353 |
| 59391 | GIM_Reject, |
| 59392 | // Label 3239: @152354 |
| 59393 | GIM_Try, /*On fail goto*//*Label 3267*/ 152377, // Rule ID 732 // |
| 59394 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 59395 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 59396 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 59397 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 59398 | // (fp_to_uint:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) => (FCVTZUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) |
| 59399 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUv4f32, |
| 59400 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59401 | // GIR_Coverage, 732, |
| 59402 | GIR_Done, |
| 59403 | // Label 3267: @152377 |
| 59404 | GIM_Reject, |
| 59405 | // Label 3240: @152378 |
| 59406 | GIM_Try, /*On fail goto*//*Label 3268*/ 152401, // Rule ID 730 // |
| 59407 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 59408 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 59409 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 59410 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 59411 | // (fp_to_uint:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) => (FCVTZUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) |
| 59412 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FCVTZUv8f16, |
| 59413 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59414 | // GIR_Coverage, 730, |
| 59415 | GIR_Done, |
| 59416 | // Label 3268: @152401 |
| 59417 | GIM_Reject, |
| 59418 | // Label 3241: @152402 |
| 59419 | GIM_Reject, |
| 59420 | // Label 57: @152403 |
| 59421 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 3277*/ 154852, |
| 59422 | /*GILLT_s16*//*Label 3269*/ 152419, |
| 59423 | /*GILLT_s32*//*Label 3270*/ 152466, |
| 59424 | /*GILLT_s64*//*Label 3271*/ 153181, 0, |
| 59425 | /*GILLT_v2s32*//*Label 3272*/ 154732, |
| 59426 | /*GILLT_v2s64*//*Label 3273*/ 154756, |
| 59427 | /*GILLT_v4s16*//*Label 3274*/ 154780, |
| 59428 | /*GILLT_v4s32*//*Label 3275*/ 154804, 0, |
| 59429 | /*GILLT_v8s16*//*Label 3276*/ 154828, |
| 59430 | // Label 3269: @152419 |
| 59431 | GIM_Try, /*On fail goto*//*Label 3278*/ 152442, // Rule ID 427 // |
| 59432 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 59433 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 59434 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 59435 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 59436 | // (sint_to_fp:{ *:[f16] } GPR32:{ *:[i32] }:$Rn) => (SCVTFUWHri:{ *:[f16] } GPR32:{ *:[i32] }:$Rn) |
| 59437 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFUWHri, |
| 59438 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59439 | // GIR_Coverage, 427, |
| 59440 | GIR_Done, |
| 59441 | // Label 3278: @152442 |
| 59442 | GIM_Try, /*On fail goto*//*Label 3279*/ 152465, // Rule ID 433 // |
| 59443 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 59444 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 59445 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 59446 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 59447 | // (sint_to_fp:{ *:[f16] } GPR64:{ *:[i64] }:$Rn) => (SCVTFUXHri:{ *:[f16] } GPR64:{ *:[i64] }:$Rn) |
| 59448 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFUXHri, |
| 59449 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59450 | // GIR_Coverage, 433, |
| 59451 | GIR_Done, |
| 59452 | // Label 3279: @152465 |
| 59453 | GIM_Reject, |
| 59454 | // Label 3270: @152466 |
| 59455 | GIM_Try, /*On fail goto*//*Label 3280*/ 152635, // Rule ID 4788 // |
| 59456 | GIM_CheckFeatures, GIFBS_NotForCodeSize, |
| 59457 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 59458 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 59459 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 59460 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXTLOAD, |
| 59461 | GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, |
| 59462 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 59463 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, |
| 59464 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 59465 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, |
| 59466 | // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>) => (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroW:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$ext), hsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] })) |
| 59467 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 59468 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 59469 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 59470 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, |
| 59471 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 59472 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/AArch64::LDRHroW, |
| 59473 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, |
| 59474 | GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 59475 | GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 59476 | GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/2, // ext |
| 59477 | GIR_MergeMemOperands, /*InsnID*/5, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 59478 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 59479 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 59480 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 59481 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 59482 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 59483 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 59484 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, |
| 59485 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/4, /*TempRegFlags*/0, |
| 59486 | GIR_AddImm, /*InsnID*/3, /*Imm*/7, |
| 59487 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, |
| 59488 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR64RegClassID, |
| 59489 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR16RegClassID, |
| 59490 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::SSHLLv4i16_shift, |
| 59491 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 59492 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, |
| 59493 | GIR_AddImm, /*InsnID*/2, /*Imm*/0, |
| 59494 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 59495 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 59496 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 59497 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, AArch64::ssub, |
| 59498 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR32RegClassID, |
| 59499 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 59500 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i32, |
| 59501 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 59502 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 59503 | GIR_EraseFromParent, /*InsnID*/0, |
| 59504 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59505 | // GIR_Coverage, 4788, |
| 59506 | GIR_Done, |
| 59507 | // Label 3280: @152635 |
| 59508 | GIM_Try, /*On fail goto*//*Label 3281*/ 152804, // Rule ID 4789 // |
| 59509 | GIM_CheckFeatures, GIFBS_NotForCodeSize, |
| 59510 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 59511 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 59512 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 59513 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXTLOAD, |
| 59514 | GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, |
| 59515 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 59516 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, |
| 59517 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 59518 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, |
| 59519 | // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>) => (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroX:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$ext), hsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] })) |
| 59520 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 59521 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 59522 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 59523 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, |
| 59524 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 59525 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/AArch64::LDRHroX, |
| 59526 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, |
| 59527 | GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 59528 | GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 59529 | GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/2, // ext |
| 59530 | GIR_MergeMemOperands, /*InsnID*/5, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 59531 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 59532 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 59533 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 59534 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 59535 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 59536 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 59537 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, |
| 59538 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/4, /*TempRegFlags*/0, |
| 59539 | GIR_AddImm, /*InsnID*/3, /*Imm*/7, |
| 59540 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, |
| 59541 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR64RegClassID, |
| 59542 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR16RegClassID, |
| 59543 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::SSHLLv4i16_shift, |
| 59544 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 59545 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, |
| 59546 | GIR_AddImm, /*InsnID*/2, /*Imm*/0, |
| 59547 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 59548 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 59549 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 59550 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, AArch64::ssub, |
| 59551 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR32RegClassID, |
| 59552 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 59553 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i32, |
| 59554 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 59555 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 59556 | GIR_EraseFromParent, /*InsnID*/0, |
| 59557 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59558 | // GIR_Coverage, 4789, |
| 59559 | GIR_Done, |
| 59560 | // Label 3281: @152804 |
| 59561 | GIM_Try, /*On fail goto*//*Label 3282*/ 152969, // Rule ID 4790 // |
| 59562 | GIM_CheckFeatures, GIFBS_NotForCodeSize, |
| 59563 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 59564 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 59565 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 59566 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXTLOAD, |
| 59567 | GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, |
| 59568 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 59569 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, |
| 59570 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 59571 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, |
| 59572 | // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>) => (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHui:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] })) |
| 59573 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 59574 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 59575 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 59576 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, |
| 59577 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 59578 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/AArch64::LDRHui, |
| 59579 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, |
| 59580 | GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 59581 | GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/1, // offset |
| 59582 | GIR_MergeMemOperands, /*InsnID*/5, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 59583 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 59584 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 59585 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 59586 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 59587 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 59588 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 59589 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, |
| 59590 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/4, /*TempRegFlags*/0, |
| 59591 | GIR_AddImm, /*InsnID*/3, /*Imm*/7, |
| 59592 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, |
| 59593 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR64RegClassID, |
| 59594 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR16RegClassID, |
| 59595 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::SSHLLv4i16_shift, |
| 59596 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 59597 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, |
| 59598 | GIR_AddImm, /*InsnID*/2, /*Imm*/0, |
| 59599 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 59600 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 59601 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 59602 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, AArch64::ssub, |
| 59603 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR32RegClassID, |
| 59604 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 59605 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i32, |
| 59606 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 59607 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 59608 | GIR_EraseFromParent, /*InsnID*/0, |
| 59609 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59610 | // GIR_Coverage, 4790, |
| 59611 | GIR_Done, |
| 59612 | // Label 3282: @152969 |
| 59613 | GIM_Try, /*On fail goto*//*Label 3283*/ 153134, // Rule ID 4791 // |
| 59614 | GIM_CheckFeatures, GIFBS_NotForCodeSize, |
| 59615 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 59616 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 59617 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 59618 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXTLOAD, |
| 59619 | GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, |
| 59620 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 59621 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, |
| 59622 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 59623 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, |
| 59624 | // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>) => (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURHi:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] })) |
| 59625 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 59626 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 59627 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 59628 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, |
| 59629 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 59630 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/AArch64::LDURHi, |
| 59631 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, |
| 59632 | GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 59633 | GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/1, // offset |
| 59634 | GIR_MergeMemOperands, /*InsnID*/5, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 59635 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 59636 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 59637 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 59638 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 59639 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 59640 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 59641 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, |
| 59642 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/4, /*TempRegFlags*/0, |
| 59643 | GIR_AddImm, /*InsnID*/3, /*Imm*/7, |
| 59644 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, |
| 59645 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR64RegClassID, |
| 59646 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR16RegClassID, |
| 59647 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::SSHLLv4i16_shift, |
| 59648 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 59649 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, |
| 59650 | GIR_AddImm, /*InsnID*/2, /*Imm*/0, |
| 59651 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 59652 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 59653 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 59654 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, AArch64::ssub, |
| 59655 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR32RegClassID, |
| 59656 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 59657 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i32, |
| 59658 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 59659 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 59660 | GIR_EraseFromParent, /*InsnID*/0, |
| 59661 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59662 | // GIR_Coverage, 4791, |
| 59663 | GIR_Done, |
| 59664 | // Label 3283: @153134 |
| 59665 | GIM_Try, /*On fail goto*//*Label 3284*/ 153157, // Rule ID 429 // |
| 59666 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 59667 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 59668 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 59669 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 59670 | // (sint_to_fp:{ *:[f32] } GPR32:{ *:[i32] }:$Rn) => (SCVTFUWSri:{ *:[f32] } GPR32:{ *:[i32] }:$Rn) |
| 59671 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFUWSri, |
| 59672 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59673 | // GIR_Coverage, 429, |
| 59674 | GIR_Done, |
| 59675 | // Label 3284: @153157 |
| 59676 | GIM_Try, /*On fail goto*//*Label 3285*/ 153180, // Rule ID 435 // |
| 59677 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 59678 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 59679 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 59680 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 59681 | // (sint_to_fp:{ *:[f32] } GPR64:{ *:[i64] }:$Rn) => (SCVTFUXSri:{ *:[f32] } GPR64:{ *:[i64] }:$Rn) |
| 59682 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFUXSri, |
| 59683 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59684 | // GIR_Coverage, 435, |
| 59685 | GIR_Done, |
| 59686 | // Label 3285: @153180 |
| 59687 | GIM_Reject, |
| 59688 | // Label 3271: @153181 |
| 59689 | GIM_Try, /*On fail goto*//*Label 3286*/ 153350, // Rule ID 4796 // |
| 59690 | GIM_CheckFeatures, GIFBS_NotForCodeSize, |
| 59691 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 59692 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 59693 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 59694 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, |
| 59695 | GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, |
| 59696 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 59697 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, |
| 59698 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 59699 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, |
| 59700 | // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$ext), ssub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] })) |
| 59701 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 59702 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 59703 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 59704 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, |
| 59705 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 59706 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/AArch64::LDRSroW, |
| 59707 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, |
| 59708 | GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 59709 | GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 59710 | GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/2, // ext |
| 59711 | GIR_MergeMemOperands, /*InsnID*/5, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 59712 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 59713 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 59714 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 59715 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 59716 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 59717 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 59718 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, |
| 59719 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/4, /*TempRegFlags*/0, |
| 59720 | GIR_AddImm, /*InsnID*/3, /*Imm*/14, |
| 59721 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, |
| 59722 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR64RegClassID, |
| 59723 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR32RegClassID, |
| 59724 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::SSHLLv2i32_shift, |
| 59725 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 59726 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, |
| 59727 | GIR_AddImm, /*InsnID*/2, /*Imm*/0, |
| 59728 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 59729 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 59730 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 59731 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, AArch64::dsub, |
| 59732 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, |
| 59733 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 59734 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i64, |
| 59735 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 59736 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 59737 | GIR_EraseFromParent, /*InsnID*/0, |
| 59738 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59739 | // GIR_Coverage, 4796, |
| 59740 | GIR_Done, |
| 59741 | // Label 3286: @153350 |
| 59742 | GIM_Try, /*On fail goto*//*Label 3287*/ 153519, // Rule ID 4797 // |
| 59743 | GIM_CheckFeatures, GIFBS_NotForCodeSize, |
| 59744 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 59745 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 59746 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 59747 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, |
| 59748 | GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, |
| 59749 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 59750 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, |
| 59751 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 59752 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, |
| 59753 | // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$ext), ssub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] })) |
| 59754 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 59755 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 59756 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 59757 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, |
| 59758 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 59759 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/AArch64::LDRSroX, |
| 59760 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, |
| 59761 | GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 59762 | GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 59763 | GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/2, // ext |
| 59764 | GIR_MergeMemOperands, /*InsnID*/5, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 59765 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 59766 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 59767 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 59768 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 59769 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 59770 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 59771 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, |
| 59772 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/4, /*TempRegFlags*/0, |
| 59773 | GIR_AddImm, /*InsnID*/3, /*Imm*/14, |
| 59774 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, |
| 59775 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR64RegClassID, |
| 59776 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR32RegClassID, |
| 59777 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::SSHLLv2i32_shift, |
| 59778 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 59779 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, |
| 59780 | GIR_AddImm, /*InsnID*/2, /*Imm*/0, |
| 59781 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 59782 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 59783 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 59784 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, AArch64::dsub, |
| 59785 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, |
| 59786 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 59787 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i64, |
| 59788 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 59789 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 59790 | GIR_EraseFromParent, /*InsnID*/0, |
| 59791 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59792 | // GIR_Coverage, 4797, |
| 59793 | GIR_Done, |
| 59794 | // Label 3287: @153519 |
| 59795 | GIM_Try, /*On fail goto*//*Label 3288*/ 153730, // Rule ID 4792 // |
| 59796 | GIM_CheckFeatures, GIFBS_NotForCodeSize_UseAlternateSExtLoadCVTF32, |
| 59797 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 59798 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 59799 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 59800 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXTLOAD, |
| 59801 | GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, |
| 59802 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 59803 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, |
| 59804 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 59805 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, |
| 59806 | // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>) => (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroW:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$ext), hsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] })) |
| 59807 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 59808 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 59809 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 59810 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, |
| 59811 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64, |
| 59812 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64, |
| 59813 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16, |
| 59814 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/AArch64::LDRHroW, |
| 59815 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define, |
| 59816 | GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 59817 | GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 59818 | GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/0, /*SubOperand*/2, // ext |
| 59819 | GIR_MergeMemOperands, /*InsnID*/7, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 59820 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 59821 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 59822 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define, |
| 59823 | GIR_ConstrainSelectedInstOperands, /*InsnID*/6, |
| 59824 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 59825 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, |
| 59826 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/5, /*TempRegFlags*/0, |
| 59827 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/6, /*TempRegFlags*/0, |
| 59828 | GIR_AddImm, /*InsnID*/5, /*Imm*/7, |
| 59829 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, AArch64::FPR64RegClassID, |
| 59830 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, AArch64::FPR64RegClassID, |
| 59831 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, AArch64::FPR16RegClassID, |
| 59832 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::SSHLLv4i16_shift, |
| 59833 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 59834 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, |
| 59835 | GIR_AddImm, /*InsnID*/4, /*Imm*/0, |
| 59836 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 59837 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, |
| 59838 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 59839 | GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, AArch64::dsub, |
| 59840 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, |
| 59841 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, |
| 59842 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::SSHLLv2i32_shift, |
| 59843 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 59844 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, |
| 59845 | GIR_AddImm, /*InsnID*/2, /*Imm*/0, |
| 59846 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 59847 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 59848 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 59849 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, AArch64::dsub, |
| 59850 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, |
| 59851 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 59852 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i64, |
| 59853 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 59854 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 59855 | GIR_EraseFromParent, /*InsnID*/0, |
| 59856 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59857 | // GIR_Coverage, 4792, |
| 59858 | GIR_Done, |
| 59859 | // Label 3288: @153730 |
| 59860 | GIM_Try, /*On fail goto*//*Label 3289*/ 153941, // Rule ID 4793 // |
| 59861 | GIM_CheckFeatures, GIFBS_NotForCodeSize_UseAlternateSExtLoadCVTF32, |
| 59862 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 59863 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 59864 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 59865 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXTLOAD, |
| 59866 | GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, |
| 59867 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 59868 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, |
| 59869 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 59870 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, |
| 59871 | // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>) => (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroX:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$ext), hsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] })) |
| 59872 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 59873 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 59874 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 59875 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, |
| 59876 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64, |
| 59877 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64, |
| 59878 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16, |
| 59879 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/AArch64::LDRHroX, |
| 59880 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define, |
| 59881 | GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 59882 | GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 59883 | GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/0, /*SubOperand*/2, // ext |
| 59884 | GIR_MergeMemOperands, /*InsnID*/7, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 59885 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 59886 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 59887 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define, |
| 59888 | GIR_ConstrainSelectedInstOperands, /*InsnID*/6, |
| 59889 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 59890 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, |
| 59891 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/5, /*TempRegFlags*/0, |
| 59892 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/6, /*TempRegFlags*/0, |
| 59893 | GIR_AddImm, /*InsnID*/5, /*Imm*/7, |
| 59894 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, AArch64::FPR64RegClassID, |
| 59895 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, AArch64::FPR64RegClassID, |
| 59896 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, AArch64::FPR16RegClassID, |
| 59897 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::SSHLLv4i16_shift, |
| 59898 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 59899 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, |
| 59900 | GIR_AddImm, /*InsnID*/4, /*Imm*/0, |
| 59901 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 59902 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, |
| 59903 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 59904 | GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, AArch64::dsub, |
| 59905 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, |
| 59906 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, |
| 59907 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::SSHLLv2i32_shift, |
| 59908 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 59909 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, |
| 59910 | GIR_AddImm, /*InsnID*/2, /*Imm*/0, |
| 59911 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 59912 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 59913 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 59914 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, AArch64::dsub, |
| 59915 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, |
| 59916 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 59917 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i64, |
| 59918 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 59919 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 59920 | GIR_EraseFromParent, /*InsnID*/0, |
| 59921 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59922 | // GIR_Coverage, 4793, |
| 59923 | GIR_Done, |
| 59924 | // Label 3289: @153941 |
| 59925 | GIM_Try, /*On fail goto*//*Label 3290*/ 154106, // Rule ID 4798 // |
| 59926 | GIM_CheckFeatures, GIFBS_NotForCodeSize, |
| 59927 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 59928 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 59929 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 59930 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, |
| 59931 | GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, |
| 59932 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 59933 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, |
| 59934 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 59935 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, |
| 59936 | // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] })) |
| 59937 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 59938 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 59939 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 59940 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, |
| 59941 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 59942 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/AArch64::LDRSui, |
| 59943 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, |
| 59944 | GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 59945 | GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/1, // offset |
| 59946 | GIR_MergeMemOperands, /*InsnID*/5, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 59947 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 59948 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 59949 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 59950 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 59951 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 59952 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 59953 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, |
| 59954 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/4, /*TempRegFlags*/0, |
| 59955 | GIR_AddImm, /*InsnID*/3, /*Imm*/14, |
| 59956 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, |
| 59957 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR64RegClassID, |
| 59958 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR32RegClassID, |
| 59959 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::SSHLLv2i32_shift, |
| 59960 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 59961 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, |
| 59962 | GIR_AddImm, /*InsnID*/2, /*Imm*/0, |
| 59963 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 59964 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 59965 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 59966 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, AArch64::dsub, |
| 59967 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, |
| 59968 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 59969 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i64, |
| 59970 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 59971 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 59972 | GIR_EraseFromParent, /*InsnID*/0, |
| 59973 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 59974 | // GIR_Coverage, 4798, |
| 59975 | GIR_Done, |
| 59976 | // Label 3290: @154106 |
| 59977 | GIM_Try, /*On fail goto*//*Label 3291*/ 154271, // Rule ID 4799 // |
| 59978 | GIM_CheckFeatures, GIFBS_NotForCodeSize, |
| 59979 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 59980 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 59981 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 59982 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, |
| 59983 | GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, |
| 59984 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 59985 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, |
| 59986 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 59987 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, |
| 59988 | // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] })) |
| 59989 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 59990 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 59991 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 59992 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, |
| 59993 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 59994 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/AArch64::LDURSi, |
| 59995 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, |
| 59996 | GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 59997 | GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/0, /*SubOperand*/1, // offset |
| 59998 | GIR_MergeMemOperands, /*InsnID*/5, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 59999 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 60000 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 60001 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 60002 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 60003 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 60004 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 60005 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, |
| 60006 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/4, /*TempRegFlags*/0, |
| 60007 | GIR_AddImm, /*InsnID*/3, /*Imm*/14, |
| 60008 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, |
| 60009 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR64RegClassID, |
| 60010 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, AArch64::FPR32RegClassID, |
| 60011 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::SSHLLv2i32_shift, |
| 60012 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 60013 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, |
| 60014 | GIR_AddImm, /*InsnID*/2, /*Imm*/0, |
| 60015 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 60016 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 60017 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 60018 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, AArch64::dsub, |
| 60019 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, |
| 60020 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 60021 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i64, |
| 60022 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 60023 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 60024 | GIR_EraseFromParent, /*InsnID*/0, |
| 60025 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60026 | // GIR_Coverage, 4799, |
| 60027 | GIR_Done, |
| 60028 | // Label 3291: @154271 |
| 60029 | GIM_Try, /*On fail goto*//*Label 3292*/ 154478, // Rule ID 4794 // |
| 60030 | GIM_CheckFeatures, GIFBS_NotForCodeSize_UseAlternateSExtLoadCVTF32, |
| 60031 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 60032 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 60033 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 60034 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXTLOAD, |
| 60035 | GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, |
| 60036 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 60037 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, |
| 60038 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 60039 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, |
| 60040 | // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>) => (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHui:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] })) |
| 60041 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 60042 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 60043 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 60044 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, |
| 60045 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64, |
| 60046 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64, |
| 60047 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16, |
| 60048 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/AArch64::LDRHui, |
| 60049 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define, |
| 60050 | GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 60051 | GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/0, /*SubOperand*/1, // offset |
| 60052 | GIR_MergeMemOperands, /*InsnID*/7, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 60053 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 60054 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 60055 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define, |
| 60056 | GIR_ConstrainSelectedInstOperands, /*InsnID*/6, |
| 60057 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 60058 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, |
| 60059 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/5, /*TempRegFlags*/0, |
| 60060 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/6, /*TempRegFlags*/0, |
| 60061 | GIR_AddImm, /*InsnID*/5, /*Imm*/7, |
| 60062 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, AArch64::FPR64RegClassID, |
| 60063 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, AArch64::FPR64RegClassID, |
| 60064 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, AArch64::FPR16RegClassID, |
| 60065 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::SSHLLv4i16_shift, |
| 60066 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 60067 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, |
| 60068 | GIR_AddImm, /*InsnID*/4, /*Imm*/0, |
| 60069 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 60070 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, |
| 60071 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 60072 | GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, AArch64::dsub, |
| 60073 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, |
| 60074 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, |
| 60075 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::SSHLLv2i32_shift, |
| 60076 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 60077 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, |
| 60078 | GIR_AddImm, /*InsnID*/2, /*Imm*/0, |
| 60079 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 60080 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 60081 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 60082 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, AArch64::dsub, |
| 60083 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, |
| 60084 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 60085 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i64, |
| 60086 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 60087 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 60088 | GIR_EraseFromParent, /*InsnID*/0, |
| 60089 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60090 | // GIR_Coverage, 4794, |
| 60091 | GIR_Done, |
| 60092 | // Label 3292: @154478 |
| 60093 | GIM_Try, /*On fail goto*//*Label 3293*/ 154685, // Rule ID 4795 // |
| 60094 | GIM_CheckFeatures, GIFBS_NotForCodeSize_UseAlternateSExtLoadCVTF32, |
| 60095 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 60096 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 60097 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 60098 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXTLOAD, |
| 60099 | GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, |
| 60100 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 60101 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, |
| 60102 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 60103 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, |
| 60104 | // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>) => (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURHi:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] })) |
| 60105 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 60106 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 60107 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 60108 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128, |
| 60109 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64, |
| 60110 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64, |
| 60111 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16, |
| 60112 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/AArch64::LDURHi, |
| 60113 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define, |
| 60114 | GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 60115 | GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/0, /*SubOperand*/1, // offset |
| 60116 | GIR_MergeMemOperands, /*InsnID*/7, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 60117 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 60118 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 60119 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define, |
| 60120 | GIR_ConstrainSelectedInstOperands, /*InsnID*/6, |
| 60121 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 60122 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define, |
| 60123 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/5, /*TempRegFlags*/0, |
| 60124 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/6, /*TempRegFlags*/0, |
| 60125 | GIR_AddImm, /*InsnID*/5, /*Imm*/7, |
| 60126 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, AArch64::FPR64RegClassID, |
| 60127 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, AArch64::FPR64RegClassID, |
| 60128 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, AArch64::FPR16RegClassID, |
| 60129 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/AArch64::SSHLLv4i16_shift, |
| 60130 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 60131 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0, |
| 60132 | GIR_AddImm, /*InsnID*/4, /*Imm*/0, |
| 60133 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 60134 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, |
| 60135 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 60136 | GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, AArch64::dsub, |
| 60137 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, AArch64::FPR64RegClassID, |
| 60138 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, AArch64::FPR128RegClassID, |
| 60139 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/AArch64::SSHLLv2i32_shift, |
| 60140 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 60141 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, |
| 60142 | GIR_AddImm, /*InsnID*/2, /*Imm*/0, |
| 60143 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 60144 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 60145 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 60146 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, AArch64::dsub, |
| 60147 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, |
| 60148 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 60149 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SCVTFv1i64, |
| 60150 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 60151 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 60152 | GIR_EraseFromParent, /*InsnID*/0, |
| 60153 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60154 | // GIR_Coverage, 4795, |
| 60155 | GIR_Done, |
| 60156 | // Label 3293: @154685 |
| 60157 | GIM_Try, /*On fail goto*//*Label 3294*/ 154708, // Rule ID 431 // |
| 60158 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 60159 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 60160 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 60161 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 60162 | // (sint_to_fp:{ *:[f64] } GPR32:{ *:[i32] }:$Rn) => (SCVTFUWDri:{ *:[f64] } GPR32:{ *:[i32] }:$Rn) |
| 60163 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFUWDri, |
| 60164 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60165 | // GIR_Coverage, 431, |
| 60166 | GIR_Done, |
| 60167 | // Label 3294: @154708 |
| 60168 | GIM_Try, /*On fail goto*//*Label 3295*/ 154731, // Rule ID 437 // |
| 60169 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 60170 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 60171 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 60172 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 60173 | // (sint_to_fp:{ *:[f64] } GPR64:{ *:[i64] }:$Rn) => (SCVTFUXDri:{ *:[f64] } GPR64:{ *:[i64] }:$Rn) |
| 60174 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFUXDri, |
| 60175 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60176 | // GIR_Coverage, 437, |
| 60177 | GIR_Done, |
| 60178 | // Label 3295: @154731 |
| 60179 | GIM_Reject, |
| 60180 | // Label 3272: @154732 |
| 60181 | GIM_Try, /*On fail goto*//*Label 3296*/ 154755, // Rule ID 826 // |
| 60182 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 60183 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 60184 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 60185 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 60186 | // (sint_to_fp:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn) => (SCVTFv2f32:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn) |
| 60187 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFv2f32, |
| 60188 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60189 | // GIR_Coverage, 826, |
| 60190 | GIR_Done, |
| 60191 | // Label 3296: @154755 |
| 60192 | GIM_Reject, |
| 60193 | // Label 3273: @154756 |
| 60194 | GIM_Try, /*On fail goto*//*Label 3297*/ 154779, // Rule ID 828 // |
| 60195 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 60196 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 60197 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 60198 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 60199 | // (sint_to_fp:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn) => (SCVTFv2f64:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn) |
| 60200 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFv2f64, |
| 60201 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60202 | // GIR_Coverage, 828, |
| 60203 | GIR_Done, |
| 60204 | // Label 3297: @154779 |
| 60205 | GIM_Reject, |
| 60206 | // Label 3274: @154780 |
| 60207 | GIM_Try, /*On fail goto*//*Label 3298*/ 154803, // Rule ID 824 // |
| 60208 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 60209 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 60210 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 60211 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 60212 | // (sint_to_fp:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn) => (SCVTFv4f16:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn) |
| 60213 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFv4f16, |
| 60214 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60215 | // GIR_Coverage, 824, |
| 60216 | GIR_Done, |
| 60217 | // Label 3298: @154803 |
| 60218 | GIM_Reject, |
| 60219 | // Label 3275: @154804 |
| 60220 | GIM_Try, /*On fail goto*//*Label 3299*/ 154827, // Rule ID 827 // |
| 60221 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 60222 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 60223 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 60224 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 60225 | // (sint_to_fp:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn) => (SCVTFv4f32:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn) |
| 60226 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFv4f32, |
| 60227 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60228 | // GIR_Coverage, 827, |
| 60229 | GIR_Done, |
| 60230 | // Label 3299: @154827 |
| 60231 | GIM_Reject, |
| 60232 | // Label 3276: @154828 |
| 60233 | GIM_Try, /*On fail goto*//*Label 3300*/ 154851, // Rule ID 825 // |
| 60234 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 60235 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 60236 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 60237 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 60238 | // (sint_to_fp:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn) => (SCVTFv8f16:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn) |
| 60239 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFv8f16, |
| 60240 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60241 | // GIR_Coverage, 825, |
| 60242 | GIR_Done, |
| 60243 | // Label 3300: @154851 |
| 60244 | GIM_Reject, |
| 60245 | // Label 3277: @154852 |
| 60246 | GIM_Reject, |
| 60247 | // Label 58: @154853 |
| 60248 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 3309*/ 156606, |
| 60249 | /*GILLT_s16*//*Label 3301*/ 154869, |
| 60250 | /*GILLT_s32*//*Label 3302*/ 154916, |
| 60251 | /*GILLT_s64*//*Label 3303*/ 155455, 0, |
| 60252 | /*GILLT_v2s32*//*Label 3304*/ 156486, |
| 60253 | /*GILLT_v2s64*//*Label 3305*/ 156510, |
| 60254 | /*GILLT_v4s16*//*Label 3306*/ 156534, |
| 60255 | /*GILLT_v4s32*//*Label 3307*/ 156558, 0, |
| 60256 | /*GILLT_v8s16*//*Label 3308*/ 156582, |
| 60257 | // Label 3301: @154869 |
| 60258 | GIM_Try, /*On fail goto*//*Label 3310*/ 154892, // Rule ID 451 // |
| 60259 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 60260 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 60261 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 60262 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 60263 | // (uint_to_fp:{ *:[f16] } GPR32:{ *:[i32] }:$Rn) => (UCVTFUWHri:{ *:[f16] } GPR32:{ *:[i32] }:$Rn) |
| 60264 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFUWHri, |
| 60265 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60266 | // GIR_Coverage, 451, |
| 60267 | GIR_Done, |
| 60268 | // Label 3310: @154892 |
| 60269 | GIM_Try, /*On fail goto*//*Label 3311*/ 154915, // Rule ID 457 // |
| 60270 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 60271 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 60272 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 60273 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 60274 | // (uint_to_fp:{ *:[f16] } GPR64:{ *:[i64] }:$Rn) => (UCVTFUXHri:{ *:[f16] } GPR64:{ *:[i64] }:$Rn) |
| 60275 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFUXHri, |
| 60276 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60277 | // GIR_Coverage, 457, |
| 60278 | GIR_Done, |
| 60279 | // Label 3311: @154915 |
| 60280 | GIM_Reject, |
| 60281 | // Label 3302: @154916 |
| 60282 | GIM_Try, /*On fail goto*//*Label 3312*/ 155041, // Rule ID 4193 // |
| 60283 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 60284 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 60285 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 60286 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXTLOAD, |
| 60287 | GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, |
| 60288 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 60289 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, |
| 60290 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 60291 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, |
| 60292 | // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>) => (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRHroW:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })) |
| 60293 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 60294 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 60295 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 60296 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRHroW, |
| 60297 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 60298 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 60299 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 60300 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/2, // extend |
| 60301 | GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 60302 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 60303 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 60304 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 60305 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 60306 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 60307 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 60308 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 60309 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 60310 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 60311 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR32RegClassID, |
| 60312 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR32RegClassID, |
| 60313 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, |
| 60314 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i32, |
| 60315 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 60316 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 60317 | GIR_EraseFromParent, /*InsnID*/0, |
| 60318 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60319 | // GIR_Coverage, 4193, |
| 60320 | GIR_Done, |
| 60321 | // Label 3312: @155041 |
| 60322 | GIM_Try, /*On fail goto*//*Label 3313*/ 155166, // Rule ID 4194 // |
| 60323 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 60324 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 60325 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 60326 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXTLOAD, |
| 60327 | GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, |
| 60328 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 60329 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, |
| 60330 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 60331 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, |
| 60332 | // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>) => (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRHroX:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })) |
| 60333 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 60334 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 60335 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 60336 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRHroX, |
| 60337 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 60338 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 60339 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 60340 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/2, // extend |
| 60341 | GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 60342 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 60343 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 60344 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 60345 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 60346 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 60347 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 60348 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 60349 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 60350 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 60351 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR32RegClassID, |
| 60352 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR32RegClassID, |
| 60353 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, |
| 60354 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i32, |
| 60355 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 60356 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 60357 | GIR_EraseFromParent, /*InsnID*/0, |
| 60358 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60359 | // GIR_Coverage, 4194, |
| 60360 | GIR_Done, |
| 60361 | // Label 3313: @155166 |
| 60362 | GIM_Try, /*On fail goto*//*Label 3314*/ 155287, // Rule ID 4195 // |
| 60363 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 60364 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 60365 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 60366 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXTLOAD, |
| 60367 | GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, |
| 60368 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 60369 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, |
| 60370 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 60371 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, |
| 60372 | // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>) => (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRHui:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })) |
| 60373 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 60374 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 60375 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 60376 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRHui, |
| 60377 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 60378 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 60379 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // offset |
| 60380 | GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 60381 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 60382 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 60383 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 60384 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 60385 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 60386 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 60387 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 60388 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 60389 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 60390 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR32RegClassID, |
| 60391 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR32RegClassID, |
| 60392 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, |
| 60393 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i32, |
| 60394 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 60395 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 60396 | GIR_EraseFromParent, /*InsnID*/0, |
| 60397 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60398 | // GIR_Coverage, 4195, |
| 60399 | GIR_Done, |
| 60400 | // Label 3314: @155287 |
| 60401 | GIM_Try, /*On fail goto*//*Label 3315*/ 155408, // Rule ID 4196 // |
| 60402 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 60403 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 60404 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 60405 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXTLOAD, |
| 60406 | GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, |
| 60407 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 60408 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, |
| 60409 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 60410 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, |
| 60411 | // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>) => (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDURHi:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })) |
| 60412 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 60413 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 60414 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 60415 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDURHi, |
| 60416 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 60417 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 60418 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // offset |
| 60419 | GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 60420 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 60421 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 60422 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 60423 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 60424 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 60425 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 60426 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 60427 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 60428 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 60429 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR32RegClassID, |
| 60430 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR32RegClassID, |
| 60431 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, |
| 60432 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i32, |
| 60433 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 60434 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 60435 | GIR_EraseFromParent, /*InsnID*/0, |
| 60436 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60437 | // GIR_Coverage, 4196, |
| 60438 | GIR_Done, |
| 60439 | // Label 3315: @155408 |
| 60440 | GIM_Try, /*On fail goto*//*Label 3316*/ 155431, // Rule ID 453 // |
| 60441 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 60442 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 60443 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 60444 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 60445 | // (uint_to_fp:{ *:[f32] } GPR32:{ *:[i32] }:$Rn) => (UCVTFUWSri:{ *:[f32] } GPR32:{ *:[i32] }:$Rn) |
| 60446 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFUWSri, |
| 60447 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60448 | // GIR_Coverage, 453, |
| 60449 | GIR_Done, |
| 60450 | // Label 3316: @155431 |
| 60451 | GIM_Try, /*On fail goto*//*Label 3317*/ 155454, // Rule ID 459 // |
| 60452 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 60453 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 60454 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 60455 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 60456 | // (uint_to_fp:{ *:[f32] } GPR64:{ *:[i64] }:$Rn) => (UCVTFUXSri:{ *:[f32] } GPR64:{ *:[i64] }:$Rn) |
| 60457 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFUXSri, |
| 60458 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60459 | // GIR_Coverage, 459, |
| 60460 | GIR_Done, |
| 60461 | // Label 3317: @155454 |
| 60462 | GIM_Reject, |
| 60463 | // Label 3303: @155455 |
| 60464 | GIM_Try, /*On fail goto*//*Label 3318*/ 155580, // Rule ID 4205 // |
| 60465 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 60466 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 60467 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 60468 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, |
| 60469 | GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, |
| 60470 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 60471 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, |
| 60472 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 60473 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed32, |
| 60474 | // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })) |
| 60475 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 60476 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 60477 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 60478 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRSroW, |
| 60479 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 60480 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 60481 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 60482 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/2, // extend |
| 60483 | GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 60484 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 60485 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 60486 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 60487 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 60488 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 60489 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 60490 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 60491 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 60492 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 60493 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, |
| 60494 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR64RegClassID, |
| 60495 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 60496 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, |
| 60497 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 60498 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 60499 | GIR_EraseFromParent, /*InsnID*/0, |
| 60500 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60501 | // GIR_Coverage, 4205, |
| 60502 | GIR_Done, |
| 60503 | // Label 3318: @155580 |
| 60504 | GIM_Try, /*On fail goto*//*Label 3319*/ 155705, // Rule ID 4206 // |
| 60505 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 60506 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 60507 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 60508 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, |
| 60509 | GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, |
| 60510 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 60511 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, |
| 60512 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 60513 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed32, |
| 60514 | // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })) |
| 60515 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 60516 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 60517 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 60518 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRSroX, |
| 60519 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 60520 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 60521 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 60522 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/2, // extend |
| 60523 | GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 60524 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 60525 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 60526 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 60527 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 60528 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 60529 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 60530 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 60531 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 60532 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 60533 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, |
| 60534 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR64RegClassID, |
| 60535 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 60536 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, |
| 60537 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 60538 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 60539 | GIR_EraseFromParent, /*InsnID*/0, |
| 60540 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60541 | // GIR_Coverage, 4206, |
| 60542 | GIR_Done, |
| 60543 | // Label 3319: @155705 |
| 60544 | GIM_Try, /*On fail goto*//*Label 3320*/ 155830, // Rule ID 4201 // |
| 60545 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 60546 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 60547 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 60548 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXTLOAD, |
| 60549 | GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, |
| 60550 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 60551 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, |
| 60552 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 60553 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Windexed16, |
| 60554 | // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroW:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })) |
| 60555 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 60556 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 60557 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 60558 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRHroW, |
| 60559 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 60560 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 60561 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 60562 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/2, // extend |
| 60563 | GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 60564 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 60565 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 60566 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 60567 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 60568 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 60569 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 60570 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 60571 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 60572 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 60573 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, |
| 60574 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR64RegClassID, |
| 60575 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, |
| 60576 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, |
| 60577 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 60578 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 60579 | GIR_EraseFromParent, /*InsnID*/0, |
| 60580 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60581 | // GIR_Coverage, 4201, |
| 60582 | GIR_Done, |
| 60583 | // Label 3320: @155830 |
| 60584 | GIM_Try, /*On fail goto*//*Label 3321*/ 155955, // Rule ID 4202 // |
| 60585 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 60586 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 60587 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 60588 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXTLOAD, |
| 60589 | GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, |
| 60590 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 60591 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, |
| 60592 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 60593 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_ro_Xindexed16, |
| 60594 | // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroX:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })) |
| 60595 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 60596 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 60597 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 60598 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRHroX, |
| 60599 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 60600 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 60601 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // Rm |
| 60602 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/2, // extend |
| 60603 | GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 60604 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 60605 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 60606 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 60607 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 60608 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 60609 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 60610 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 60611 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 60612 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 60613 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, |
| 60614 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR64RegClassID, |
| 60615 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, |
| 60616 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, |
| 60617 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 60618 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 60619 | GIR_EraseFromParent, /*InsnID*/0, |
| 60620 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60621 | // GIR_Coverage, 4202, |
| 60622 | GIR_Done, |
| 60623 | // Label 3321: @155955 |
| 60624 | GIM_Try, /*On fail goto*//*Label 3322*/ 156076, // Rule ID 4207 // |
| 60625 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 60626 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 60627 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 60628 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, |
| 60629 | GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, |
| 60630 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 60631 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, |
| 60632 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 60633 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed32, |
| 60634 | // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })) |
| 60635 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 60636 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 60637 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 60638 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRSui, |
| 60639 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 60640 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 60641 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // offset |
| 60642 | GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 60643 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 60644 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 60645 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 60646 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 60647 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 60648 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 60649 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 60650 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 60651 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 60652 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, |
| 60653 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR64RegClassID, |
| 60654 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 60655 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, |
| 60656 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 60657 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 60658 | GIR_EraseFromParent, /*InsnID*/0, |
| 60659 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60660 | // GIR_Coverage, 4207, |
| 60661 | GIR_Done, |
| 60662 | // Label 3322: @156076 |
| 60663 | GIM_Try, /*On fail goto*//*Label 3323*/ 156197, // Rule ID 4208 // |
| 60664 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 60665 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 60666 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 60667 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, |
| 60668 | GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, |
| 60669 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 60670 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, |
| 60671 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 60672 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled32, |
| 60673 | // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })) |
| 60674 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 60675 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 60676 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 60677 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDURSi, |
| 60678 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 60679 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 60680 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // offset |
| 60681 | GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 60682 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 60683 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 60684 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 60685 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 60686 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 60687 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 60688 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 60689 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 60690 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 60691 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, |
| 60692 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR64RegClassID, |
| 60693 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 60694 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, |
| 60695 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 60696 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 60697 | GIR_EraseFromParent, /*InsnID*/0, |
| 60698 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60699 | // GIR_Coverage, 4208, |
| 60700 | GIR_Done, |
| 60701 | // Label 3323: @156197 |
| 60702 | GIM_Try, /*On fail goto*//*Label 3324*/ 156318, // Rule ID 4203 // |
| 60703 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 60704 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 60705 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 60706 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXTLOAD, |
| 60707 | GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, |
| 60708 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 60709 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, |
| 60710 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 60711 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_indexed16, |
| 60712 | // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHui:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })) |
| 60713 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 60714 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 60715 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 60716 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDRHui, |
| 60717 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 60718 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 60719 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // offset |
| 60720 | GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 60721 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 60722 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 60723 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 60724 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 60725 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 60726 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 60727 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 60728 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 60729 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 60730 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, |
| 60731 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR64RegClassID, |
| 60732 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, |
| 60733 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, |
| 60734 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 60735 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 60736 | GIR_EraseFromParent, /*InsnID*/0, |
| 60737 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60738 | // GIR_Coverage, 4203, |
| 60739 | GIR_Done, |
| 60740 | // Label 3324: @156318 |
| 60741 | GIM_Try, /*On fail goto*//*Label 3325*/ 156439, // Rule ID 4204 // |
| 60742 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 60743 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 60744 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 60745 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXTLOAD, |
| 60746 | GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, |
| 60747 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 60748 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0, |
| 60749 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 60750 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/0, GICP_gi_am_unscaled16, |
| 60751 | // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURHi:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })) |
| 60752 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 60753 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 60754 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 60755 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/AArch64::LDURHi, |
| 60756 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 60757 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/0, // Rn |
| 60758 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/0, /*SubOperand*/1, // offset |
| 60759 | GIR_MergeMemOperands, /*InsnID*/3, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 60760 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 60761 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 60762 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 60763 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 60764 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 60765 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 60766 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 60767 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, |
| 60768 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 60769 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR64RegClassID, |
| 60770 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR64RegClassID, |
| 60771 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, |
| 60772 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, |
| 60773 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 60774 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 60775 | GIR_EraseFromParent, /*InsnID*/0, |
| 60776 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60777 | // GIR_Coverage, 4204, |
| 60778 | GIR_Done, |
| 60779 | // Label 3325: @156439 |
| 60780 | GIM_Try, /*On fail goto*//*Label 3326*/ 156462, // Rule ID 455 // |
| 60781 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 60782 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 60783 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 60784 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 60785 | // (uint_to_fp:{ *:[f64] } GPR32:{ *:[i32] }:$Rn) => (UCVTFUWDri:{ *:[f64] } GPR32:{ *:[i32] }:$Rn) |
| 60786 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFUWDri, |
| 60787 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60788 | // GIR_Coverage, 455, |
| 60789 | GIR_Done, |
| 60790 | // Label 3326: @156462 |
| 60791 | GIM_Try, /*On fail goto*//*Label 3327*/ 156485, // Rule ID 461 // |
| 60792 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 60793 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 60794 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 60795 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 60796 | // (uint_to_fp:{ *:[f64] } GPR64:{ *:[i64] }:$Rn) => (UCVTFUXDri:{ *:[f64] } GPR64:{ *:[i64] }:$Rn) |
| 60797 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFUXDri, |
| 60798 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60799 | // GIR_Coverage, 461, |
| 60800 | GIR_Done, |
| 60801 | // Label 3327: @156485 |
| 60802 | GIM_Reject, |
| 60803 | // Label 3304: @156486 |
| 60804 | GIM_Try, /*On fail goto*//*Label 3328*/ 156509, // Rule ID 870 // |
| 60805 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 60806 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 60807 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 60808 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 60809 | // (uint_to_fp:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn) => (UCVTFv2f32:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn) |
| 60810 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFv2f32, |
| 60811 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60812 | // GIR_Coverage, 870, |
| 60813 | GIR_Done, |
| 60814 | // Label 3328: @156509 |
| 60815 | GIM_Reject, |
| 60816 | // Label 3305: @156510 |
| 60817 | GIM_Try, /*On fail goto*//*Label 3329*/ 156533, // Rule ID 872 // |
| 60818 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 60819 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 60820 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 60821 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 60822 | // (uint_to_fp:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn) => (UCVTFv2f64:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn) |
| 60823 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFv2f64, |
| 60824 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60825 | // GIR_Coverage, 872, |
| 60826 | GIR_Done, |
| 60827 | // Label 3329: @156533 |
| 60828 | GIM_Reject, |
| 60829 | // Label 3306: @156534 |
| 60830 | GIM_Try, /*On fail goto*//*Label 3330*/ 156557, // Rule ID 868 // |
| 60831 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 60832 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 60833 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 60834 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 60835 | // (uint_to_fp:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn) => (UCVTFv4f16:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn) |
| 60836 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFv4f16, |
| 60837 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60838 | // GIR_Coverage, 868, |
| 60839 | GIR_Done, |
| 60840 | // Label 3330: @156557 |
| 60841 | GIM_Reject, |
| 60842 | // Label 3307: @156558 |
| 60843 | GIM_Try, /*On fail goto*//*Label 3331*/ 156581, // Rule ID 871 // |
| 60844 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 60845 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 60846 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 60847 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 60848 | // (uint_to_fp:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn) => (UCVTFv4f32:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn) |
| 60849 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFv4f32, |
| 60850 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60851 | // GIR_Coverage, 871, |
| 60852 | GIR_Done, |
| 60853 | // Label 3331: @156581 |
| 60854 | GIM_Reject, |
| 60855 | // Label 3308: @156582 |
| 60856 | GIM_Try, /*On fail goto*//*Label 3332*/ 156605, // Rule ID 869 // |
| 60857 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 60858 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 60859 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 60860 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 60861 | // (uint_to_fp:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn) => (UCVTFv8f16:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn) |
| 60862 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFv8f16, |
| 60863 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60864 | // GIR_Coverage, 869, |
| 60865 | GIR_Done, |
| 60866 | // Label 3332: @156605 |
| 60867 | GIM_Reject, |
| 60868 | // Label 3309: @156606 |
| 60869 | GIM_Reject, |
| 60870 | // Label 59: @156607 |
| 60871 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 3341*/ 157163, |
| 60872 | /*GILLT_s16*//*Label 3333*/ 156623, |
| 60873 | /*GILLT_s32*//*Label 3334*/ 156691, |
| 60874 | /*GILLT_s64*//*Label 3335*/ 156757, 0, |
| 60875 | /*GILLT_v2s32*//*Label 3336*/ 156823, |
| 60876 | /*GILLT_v2s64*//*Label 3337*/ 156891, |
| 60877 | /*GILLT_v4s16*//*Label 3338*/ 156959, |
| 60878 | /*GILLT_v4s32*//*Label 3339*/ 157027, 0, |
| 60879 | /*GILLT_v8s16*//*Label 3340*/ 157095, |
| 60880 | // Label 3333: @156623 |
| 60881 | GIM_Try, /*On fail goto*//*Label 3342*/ 156690, |
| 60882 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 60883 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 60884 | GIM_Try, /*On fail goto*//*Label 3343*/ 156674, // Rule ID 4106 // |
| 60885 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 60886 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 60887 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, |
| 60888 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 60889 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 60890 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 60891 | // (fabs:{ *:[f16] } (fsub:{ *:[f16] } f16:{ *:[f16] }:$Rn, f16:{ *:[f16] }:$Rm)) => (FABD16:{ *:[f16] } f16:{ *:[f16] }:$Rn, f16:{ *:[f16] }:$Rm) |
| 60892 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD16, |
| 60893 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 60894 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 60895 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 60896 | GIR_EraseFromParent, /*InsnID*/0, |
| 60897 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60898 | // GIR_Coverage, 4106, |
| 60899 | GIR_Done, |
| 60900 | // Label 3343: @156674 |
| 60901 | GIM_Try, /*On fail goto*//*Label 3344*/ 156689, // Rule ID 486 // |
| 60902 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 60903 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 60904 | // (fabs:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FABSHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) |
| 60905 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FABSHr, |
| 60906 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60907 | // GIR_Coverage, 486, |
| 60908 | GIR_Done, |
| 60909 | // Label 3344: @156689 |
| 60910 | GIM_Reject, |
| 60911 | // Label 3342: @156690 |
| 60912 | GIM_Reject, |
| 60913 | // Label 3334: @156691 |
| 60914 | GIM_Try, /*On fail goto*//*Label 3345*/ 156756, |
| 60915 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 60916 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 60917 | GIM_Try, /*On fail goto*//*Label 3346*/ 156740, // Rule ID 4107 // |
| 60918 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 60919 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, |
| 60920 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 60921 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 60922 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 60923 | // (fabs:{ *:[f32] } (fsub:{ *:[f32] } f32:{ *:[f32] }:$Rn, f32:{ *:[f32] }:$Rm)) => (FABD32:{ *:[f32] } f32:{ *:[f32] }:$Rn, f32:{ *:[f32] }:$Rm) |
| 60924 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD32, |
| 60925 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 60926 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 60927 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 60928 | GIR_EraseFromParent, /*InsnID*/0, |
| 60929 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60930 | // GIR_Coverage, 4107, |
| 60931 | GIR_Done, |
| 60932 | // Label 3346: @156740 |
| 60933 | GIM_Try, /*On fail goto*//*Label 3347*/ 156755, // Rule ID 487 // |
| 60934 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 60935 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 60936 | // (fabs:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FABSSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) |
| 60937 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FABSSr, |
| 60938 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60939 | // GIR_Coverage, 487, |
| 60940 | GIR_Done, |
| 60941 | // Label 3347: @156755 |
| 60942 | GIM_Reject, |
| 60943 | // Label 3345: @156756 |
| 60944 | GIM_Reject, |
| 60945 | // Label 3335: @156757 |
| 60946 | GIM_Try, /*On fail goto*//*Label 3348*/ 156822, |
| 60947 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 60948 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 60949 | GIM_Try, /*On fail goto*//*Label 3349*/ 156806, // Rule ID 4108 // |
| 60950 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 60951 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, |
| 60952 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 60953 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 60954 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 60955 | // (fabs:{ *:[f64] } (fsub:{ *:[f64] } f64:{ *:[f64] }:$Rn, f64:{ *:[f64] }:$Rm)) => (FABD64:{ *:[f64] } f64:{ *:[f64] }:$Rn, f64:{ *:[f64] }:$Rm) |
| 60956 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABD64, |
| 60957 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 60958 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 60959 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 60960 | GIR_EraseFromParent, /*InsnID*/0, |
| 60961 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60962 | // GIR_Coverage, 4108, |
| 60963 | GIR_Done, |
| 60964 | // Label 3349: @156806 |
| 60965 | GIM_Try, /*On fail goto*//*Label 3350*/ 156821, // Rule ID 488 // |
| 60966 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 60967 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 60968 | // (fabs:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FABSDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) |
| 60969 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FABSDr, |
| 60970 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60971 | // GIR_Coverage, 488, |
| 60972 | GIR_Done, |
| 60973 | // Label 3350: @156821 |
| 60974 | GIM_Reject, |
| 60975 | // Label 3348: @156822 |
| 60976 | GIM_Reject, |
| 60977 | // Label 3336: @156823 |
| 60978 | GIM_Try, /*On fail goto*//*Label 3351*/ 156890, |
| 60979 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 60980 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 60981 | GIM_Try, /*On fail goto*//*Label 3352*/ 156874, // Rule ID 4041 // |
| 60982 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 60983 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 60984 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, |
| 60985 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 60986 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 60987 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 60988 | // (fabs:{ *:[v2f32] } (fsub:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$Rn, v2f32:{ *:[v2f32] }:$Rm)) => (FABDv2f32:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$Rn, v2f32:{ *:[v2f32] }:$Rm) |
| 60989 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv2f32, |
| 60990 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 60991 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 60992 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 60993 | GIR_EraseFromParent, /*InsnID*/0, |
| 60994 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 60995 | // GIR_Coverage, 4041, |
| 60996 | GIR_Done, |
| 60997 | // Label 3352: @156874 |
| 60998 | GIM_Try, /*On fail goto*//*Label 3353*/ 156889, // Rule ID 655 // |
| 60999 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61000 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61001 | // (fabs:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FABSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) |
| 61002 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FABSv2f32, |
| 61003 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61004 | // GIR_Coverage, 655, |
| 61005 | GIR_Done, |
| 61006 | // Label 3353: @156889 |
| 61007 | GIM_Reject, |
| 61008 | // Label 3351: @156890 |
| 61009 | GIM_Reject, |
| 61010 | // Label 3337: @156891 |
| 61011 | GIM_Try, /*On fail goto*//*Label 3354*/ 156958, |
| 61012 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 61013 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 61014 | GIM_Try, /*On fail goto*//*Label 3355*/ 156942, // Rule ID 4043 // |
| 61015 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61016 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 61017 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, |
| 61018 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 61019 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 61020 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 61021 | // (fabs:{ *:[v2f64] } (fsub:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$Rn, v2f64:{ *:[v2f64] }:$Rm)) => (FABDv2f64:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$Rn, v2f64:{ *:[v2f64] }:$Rm) |
| 61022 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv2f64, |
| 61023 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 61024 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 61025 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 61026 | GIR_EraseFromParent, /*InsnID*/0, |
| 61027 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61028 | // GIR_Coverage, 4043, |
| 61029 | GIR_Done, |
| 61030 | // Label 3355: @156942 |
| 61031 | GIM_Try, /*On fail goto*//*Label 3356*/ 156957, // Rule ID 657 // |
| 61032 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61033 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 61034 | // (fabs:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FABSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) |
| 61035 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FABSv2f64, |
| 61036 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61037 | // GIR_Coverage, 657, |
| 61038 | GIR_Done, |
| 61039 | // Label 3356: @156957 |
| 61040 | GIM_Reject, |
| 61041 | // Label 3354: @156958 |
| 61042 | GIM_Reject, |
| 61043 | // Label 3338: @156959 |
| 61044 | GIM_Try, /*On fail goto*//*Label 3357*/ 157026, |
| 61045 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 61046 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 61047 | GIM_Try, /*On fail goto*//*Label 3358*/ 157010, // Rule ID 4044 // |
| 61048 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 61049 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 61050 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, |
| 61051 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 61052 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 61053 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 61054 | // (fabs:{ *:[v4f16] } (fsub:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$Rn, v4f16:{ *:[v4f16] }:$Rm)) => (FABDv4f16:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$Rn, v4f16:{ *:[v4f16] }:$Rm) |
| 61055 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv4f16, |
| 61056 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 61057 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 61058 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 61059 | GIR_EraseFromParent, /*InsnID*/0, |
| 61060 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61061 | // GIR_Coverage, 4044, |
| 61062 | GIR_Done, |
| 61063 | // Label 3358: @157010 |
| 61064 | GIM_Try, /*On fail goto*//*Label 3359*/ 157025, // Rule ID 653 // |
| 61065 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 61066 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61067 | // (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FABSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) |
| 61068 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FABSv4f16, |
| 61069 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61070 | // GIR_Coverage, 653, |
| 61071 | GIR_Done, |
| 61072 | // Label 3359: @157025 |
| 61073 | GIM_Reject, |
| 61074 | // Label 3357: @157026 |
| 61075 | GIM_Reject, |
| 61076 | // Label 3339: @157027 |
| 61077 | GIM_Try, /*On fail goto*//*Label 3360*/ 157094, |
| 61078 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 61079 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 61080 | GIM_Try, /*On fail goto*//*Label 3361*/ 157078, // Rule ID 4042 // |
| 61081 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61082 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 61083 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, |
| 61084 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 61085 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 61086 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 61087 | // (fabs:{ *:[v4f32] } (fsub:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$Rn, v4f32:{ *:[v4f32] }:$Rm)) => (FABDv4f32:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$Rn, v4f32:{ *:[v4f32] }:$Rm) |
| 61088 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv4f32, |
| 61089 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 61090 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 61091 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 61092 | GIR_EraseFromParent, /*InsnID*/0, |
| 61093 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61094 | // GIR_Coverage, 4042, |
| 61095 | GIR_Done, |
| 61096 | // Label 3361: @157078 |
| 61097 | GIM_Try, /*On fail goto*//*Label 3362*/ 157093, // Rule ID 656 // |
| 61098 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61099 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 61100 | // (fabs:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FABSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) |
| 61101 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FABSv4f32, |
| 61102 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61103 | // GIR_Coverage, 656, |
| 61104 | GIR_Done, |
| 61105 | // Label 3362: @157093 |
| 61106 | GIM_Reject, |
| 61107 | // Label 3360: @157094 |
| 61108 | GIM_Reject, |
| 61109 | // Label 3340: @157095 |
| 61110 | GIM_Try, /*On fail goto*//*Label 3363*/ 157162, |
| 61111 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 61112 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 61113 | GIM_Try, /*On fail goto*//*Label 3364*/ 157146, // Rule ID 4045 // |
| 61114 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 61115 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 61116 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, |
| 61117 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 61118 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 61119 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 61120 | // (fabs:{ *:[v8f16] } (fsub:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$Rn, v8f16:{ *:[v8f16] }:$Rm)) => (FABDv8f16:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$Rn, v8f16:{ *:[v8f16] }:$Rm) |
| 61121 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FABDv8f16, |
| 61122 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 61123 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 61124 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 61125 | GIR_EraseFromParent, /*InsnID*/0, |
| 61126 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61127 | // GIR_Coverage, 4045, |
| 61128 | GIR_Done, |
| 61129 | // Label 3364: @157146 |
| 61130 | GIM_Try, /*On fail goto*//*Label 3365*/ 157161, // Rule ID 654 // |
| 61131 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 61132 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 61133 | // (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FABSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) |
| 61134 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FABSv8f16, |
| 61135 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61136 | // GIR_Coverage, 654, |
| 61137 | GIR_Done, |
| 61138 | // Label 3365: @157161 |
| 61139 | GIM_Reject, |
| 61140 | // Label 3363: @157162 |
| 61141 | GIM_Reject, |
| 61142 | // Label 3341: @157163 |
| 61143 | GIM_Reject, |
| 61144 | // Label 60: @157164 |
| 61145 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 3374*/ 157448, |
| 61146 | /*GILLT_s16*//*Label 3366*/ 157180, |
| 61147 | /*GILLT_s32*//*Label 3367*/ 157212, |
| 61148 | /*GILLT_s64*//*Label 3368*/ 157244, 0, |
| 61149 | /*GILLT_v2s32*//*Label 3369*/ 157288, |
| 61150 | /*GILLT_v2s64*//*Label 3370*/ 157320, |
| 61151 | /*GILLT_v4s16*//*Label 3371*/ 157352, |
| 61152 | /*GILLT_v4s32*//*Label 3372*/ 157384, 0, |
| 61153 | /*GILLT_v8s16*//*Label 3373*/ 157416, |
| 61154 | // Label 3366: @157180 |
| 61155 | GIM_Try, /*On fail goto*//*Label 3375*/ 157211, // Rule ID 528 // |
| 61156 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 61157 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 61158 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 61159 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 61160 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 61161 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 61162 | // (fminnum:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FMINNMHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) |
| 61163 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMHrr, |
| 61164 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61165 | // GIR_Coverage, 528, |
| 61166 | GIR_Done, |
| 61167 | // Label 3375: @157211 |
| 61168 | GIM_Reject, |
| 61169 | // Label 3367: @157212 |
| 61170 | GIM_Try, /*On fail goto*//*Label 3376*/ 157243, // Rule ID 529 // |
| 61171 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 61172 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 61173 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 61174 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 61175 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 61176 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 61177 | // (fminnum:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FMINNMSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) |
| 61178 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMSrr, |
| 61179 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61180 | // GIR_Coverage, 529, |
| 61181 | GIR_Done, |
| 61182 | // Label 3376: @157243 |
| 61183 | GIM_Reject, |
| 61184 | // Label 3368: @157244 |
| 61185 | GIM_Try, /*On fail goto*//*Label 3377*/ 157287, |
| 61186 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 61187 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 61188 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 61189 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61190 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 61191 | GIM_Try, /*On fail goto*//*Label 3378*/ 157277, // Rule ID 530 // |
| 61192 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 61193 | // (fminnum:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FMINNMDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) |
| 61194 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMDrr, |
| 61195 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61196 | // GIR_Coverage, 530, |
| 61197 | GIR_Done, |
| 61198 | // Label 3378: @157277 |
| 61199 | GIM_Try, /*On fail goto*//*Label 3379*/ 157286, // Rule ID 3957 // |
| 61200 | // (fminnum:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FMINNMDrr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) |
| 61201 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMDrr, |
| 61202 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61203 | // GIR_Coverage, 3957, |
| 61204 | GIR_Done, |
| 61205 | // Label 3379: @157286 |
| 61206 | GIM_Reject, |
| 61207 | // Label 3377: @157287 |
| 61208 | GIM_Reject, |
| 61209 | // Label 3369: @157288 |
| 61210 | GIM_Try, /*On fail goto*//*Label 3380*/ 157319, // Rule ID 1018 // |
| 61211 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61212 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 61213 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 61214 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 61215 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61216 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 61217 | // (fminnum:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMINNMv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) |
| 61218 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMv2f32, |
| 61219 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61220 | // GIR_Coverage, 1018, |
| 61221 | GIR_Done, |
| 61222 | // Label 3380: @157319 |
| 61223 | GIM_Reject, |
| 61224 | // Label 3370: @157320 |
| 61225 | GIM_Try, /*On fail goto*//*Label 3381*/ 157351, // Rule ID 1020 // |
| 61226 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61227 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 61228 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 61229 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 61230 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 61231 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 61232 | // (fminnum:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMINNMv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) |
| 61233 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMv2f64, |
| 61234 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61235 | // GIR_Coverage, 1020, |
| 61236 | GIR_Done, |
| 61237 | // Label 3381: @157351 |
| 61238 | GIM_Reject, |
| 61239 | // Label 3371: @157352 |
| 61240 | GIM_Try, /*On fail goto*//*Label 3382*/ 157383, // Rule ID 1016 // |
| 61241 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 61242 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 61243 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 61244 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 61245 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61246 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 61247 | // (fminnum:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMINNMv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 61248 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMv4f16, |
| 61249 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61250 | // GIR_Coverage, 1016, |
| 61251 | GIR_Done, |
| 61252 | // Label 3382: @157383 |
| 61253 | GIM_Reject, |
| 61254 | // Label 3372: @157384 |
| 61255 | GIM_Try, /*On fail goto*//*Label 3383*/ 157415, // Rule ID 1019 // |
| 61256 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61257 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 61258 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 61259 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 61260 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 61261 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 61262 | // (fminnum:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMINNMv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) |
| 61263 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMv4f32, |
| 61264 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61265 | // GIR_Coverage, 1019, |
| 61266 | GIR_Done, |
| 61267 | // Label 3383: @157415 |
| 61268 | GIM_Reject, |
| 61269 | // Label 3373: @157416 |
| 61270 | GIM_Try, /*On fail goto*//*Label 3384*/ 157447, // Rule ID 1017 // |
| 61271 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 61272 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 61273 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 61274 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 61275 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 61276 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 61277 | // (fminnum:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMINNMv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 61278 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMINNMv8f16, |
| 61279 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61280 | // GIR_Coverage, 1017, |
| 61281 | GIR_Done, |
| 61282 | // Label 3384: @157447 |
| 61283 | GIM_Reject, |
| 61284 | // Label 3374: @157448 |
| 61285 | GIM_Reject, |
| 61286 | // Label 61: @157449 |
| 61287 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 3393*/ 157733, |
| 61288 | /*GILLT_s16*//*Label 3385*/ 157465, |
| 61289 | /*GILLT_s32*//*Label 3386*/ 157497, |
| 61290 | /*GILLT_s64*//*Label 3387*/ 157529, 0, |
| 61291 | /*GILLT_v2s32*//*Label 3388*/ 157573, |
| 61292 | /*GILLT_v2s64*//*Label 3389*/ 157605, |
| 61293 | /*GILLT_v4s16*//*Label 3390*/ 157637, |
| 61294 | /*GILLT_v4s32*//*Label 3391*/ 157669, 0, |
| 61295 | /*GILLT_v8s16*//*Label 3392*/ 157701, |
| 61296 | // Label 3385: @157465 |
| 61297 | GIM_Try, /*On fail goto*//*Label 3394*/ 157496, // Rule ID 522 // |
| 61298 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 61299 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 61300 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, |
| 61301 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 61302 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 61303 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR16RegClassID, |
| 61304 | // (fmaxnum:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FMAXNMHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) |
| 61305 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMHrr, |
| 61306 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61307 | // GIR_Coverage, 522, |
| 61308 | GIR_Done, |
| 61309 | // Label 3394: @157496 |
| 61310 | GIM_Reject, |
| 61311 | // Label 3386: @157497 |
| 61312 | GIM_Try, /*On fail goto*//*Label 3395*/ 157528, // Rule ID 523 // |
| 61313 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 61314 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 61315 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 61316 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 61317 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 61318 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR32RegClassID, |
| 61319 | // (fmaxnum:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FMAXNMSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) |
| 61320 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMSrr, |
| 61321 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61322 | // GIR_Coverage, 523, |
| 61323 | GIR_Done, |
| 61324 | // Label 3395: @157528 |
| 61325 | GIM_Reject, |
| 61326 | // Label 3387: @157529 |
| 61327 | GIM_Try, /*On fail goto*//*Label 3396*/ 157572, |
| 61328 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 61329 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 61330 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 61331 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61332 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 61333 | GIM_Try, /*On fail goto*//*Label 3397*/ 157562, // Rule ID 524 // |
| 61334 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 61335 | // (fmaxnum:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FMAXNMDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) |
| 61336 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMDrr, |
| 61337 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61338 | // GIR_Coverage, 524, |
| 61339 | GIR_Done, |
| 61340 | // Label 3397: @157562 |
| 61341 | GIM_Try, /*On fail goto*//*Label 3398*/ 157571, // Rule ID 3956 // |
| 61342 | // (fmaxnum:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FMAXNMDrr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) |
| 61343 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMDrr, |
| 61344 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61345 | // GIR_Coverage, 3956, |
| 61346 | GIR_Done, |
| 61347 | // Label 3398: @157571 |
| 61348 | GIM_Reject, |
| 61349 | // Label 3396: @157572 |
| 61350 | GIM_Reject, |
| 61351 | // Label 3388: @157573 |
| 61352 | GIM_Try, /*On fail goto*//*Label 3399*/ 157604, // Rule ID 998 // |
| 61353 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61354 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 61355 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 61356 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 61357 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61358 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 61359 | // (fmaxnum:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMAXNMv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) |
| 61360 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMv2f32, |
| 61361 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61362 | // GIR_Coverage, 998, |
| 61363 | GIR_Done, |
| 61364 | // Label 3399: @157604 |
| 61365 | GIM_Reject, |
| 61366 | // Label 3389: @157605 |
| 61367 | GIM_Try, /*On fail goto*//*Label 3400*/ 157636, // Rule ID 1000 // |
| 61368 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61369 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 61370 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 61371 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 61372 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 61373 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 61374 | // (fmaxnum:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMAXNMv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) |
| 61375 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMv2f64, |
| 61376 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61377 | // GIR_Coverage, 1000, |
| 61378 | GIR_Done, |
| 61379 | // Label 3400: @157636 |
| 61380 | GIM_Reject, |
| 61381 | // Label 3390: @157637 |
| 61382 | GIM_Try, /*On fail goto*//*Label 3401*/ 157668, // Rule ID 996 // |
| 61383 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 61384 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 61385 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 61386 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 61387 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61388 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 61389 | // (fmaxnum:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMAXNMv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 61390 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMv4f16, |
| 61391 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61392 | // GIR_Coverage, 996, |
| 61393 | GIR_Done, |
| 61394 | // Label 3401: @157668 |
| 61395 | GIM_Reject, |
| 61396 | // Label 3391: @157669 |
| 61397 | GIM_Try, /*On fail goto*//*Label 3402*/ 157700, // Rule ID 999 // |
| 61398 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61399 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 61400 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 61401 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 61402 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 61403 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 61404 | // (fmaxnum:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMAXNMv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) |
| 61405 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMv4f32, |
| 61406 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61407 | // GIR_Coverage, 999, |
| 61408 | GIR_Done, |
| 61409 | // Label 3402: @157700 |
| 61410 | GIM_Reject, |
| 61411 | // Label 3392: @157701 |
| 61412 | GIM_Try, /*On fail goto*//*Label 3403*/ 157732, // Rule ID 997 // |
| 61413 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 61414 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 61415 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 61416 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 61417 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 61418 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 61419 | // (fmaxnum:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMAXNMv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 61420 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FMAXNMv8f16, |
| 61421 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61422 | // GIR_Coverage, 997, |
| 61423 | GIR_Done, |
| 61424 | // Label 3403: @157732 |
| 61425 | GIM_Reject, |
| 61426 | // Label 3393: @157733 |
| 61427 | GIM_Reject, |
| 61428 | // Label 62: @157734 |
| 61429 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 11, /*)*//*default:*//*Label 3410*/ 157939, |
| 61430 | /*GILLT_v2s32*//*Label 3404*/ 157747, 0, |
| 61431 | /*GILLT_v4s16*//*Label 3405*/ 157779, |
| 61432 | /*GILLT_v4s32*//*Label 3406*/ 157811, |
| 61433 | /*GILLT_v8s8*//*Label 3407*/ 157843, |
| 61434 | /*GILLT_v8s16*//*Label 3408*/ 157875, |
| 61435 | /*GILLT_v16s8*//*Label 3409*/ 157907, |
| 61436 | // Label 3404: @157747 |
| 61437 | GIM_Try, /*On fail goto*//*Label 3411*/ 157778, // Rule ID 1132 // |
| 61438 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61439 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 61440 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 61441 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 61442 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61443 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 61444 | // (smin:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SMINv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 61445 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMINv2i32, |
| 61446 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61447 | // GIR_Coverage, 1132, |
| 61448 | GIR_Done, |
| 61449 | // Label 3411: @157778 |
| 61450 | GIM_Reject, |
| 61451 | // Label 3405: @157779 |
| 61452 | GIM_Try, /*On fail goto*//*Label 3412*/ 157810, // Rule ID 1130 // |
| 61453 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61454 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 61455 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 61456 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 61457 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61458 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 61459 | // (smin:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SMINv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 61460 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMINv4i16, |
| 61461 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61462 | // GIR_Coverage, 1130, |
| 61463 | GIR_Done, |
| 61464 | // Label 3412: @157810 |
| 61465 | GIM_Reject, |
| 61466 | // Label 3406: @157811 |
| 61467 | GIM_Try, /*On fail goto*//*Label 3413*/ 157842, // Rule ID 1133 // |
| 61468 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61469 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 61470 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 61471 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 61472 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 61473 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 61474 | // (smin:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SMINv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 61475 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMINv4i32, |
| 61476 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61477 | // GIR_Coverage, 1133, |
| 61478 | GIR_Done, |
| 61479 | // Label 3413: @157842 |
| 61480 | GIM_Reject, |
| 61481 | // Label 3407: @157843 |
| 61482 | GIM_Try, /*On fail goto*//*Label 3414*/ 157874, // Rule ID 1128 // |
| 61483 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61484 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 61485 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 61486 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 61487 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61488 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 61489 | // (smin:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SMINv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 61490 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMINv8i8, |
| 61491 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61492 | // GIR_Coverage, 1128, |
| 61493 | GIR_Done, |
| 61494 | // Label 3414: @157874 |
| 61495 | GIM_Reject, |
| 61496 | // Label 3408: @157875 |
| 61497 | GIM_Try, /*On fail goto*//*Label 3415*/ 157906, // Rule ID 1131 // |
| 61498 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61499 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 61500 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 61501 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 61502 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 61503 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 61504 | // (smin:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SMINv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 61505 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMINv8i16, |
| 61506 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61507 | // GIR_Coverage, 1131, |
| 61508 | GIR_Done, |
| 61509 | // Label 3415: @157906 |
| 61510 | GIM_Reject, |
| 61511 | // Label 3409: @157907 |
| 61512 | GIM_Try, /*On fail goto*//*Label 3416*/ 157938, // Rule ID 1129 // |
| 61513 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61514 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 61515 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 61516 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 61517 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 61518 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 61519 | // (smin:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SMINv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 61520 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMINv16i8, |
| 61521 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61522 | // GIR_Coverage, 1129, |
| 61523 | GIR_Done, |
| 61524 | // Label 3416: @157938 |
| 61525 | GIM_Reject, |
| 61526 | // Label 3410: @157939 |
| 61527 | GIM_Reject, |
| 61528 | // Label 63: @157940 |
| 61529 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 11, /*)*//*default:*//*Label 3423*/ 158145, |
| 61530 | /*GILLT_v2s32*//*Label 3417*/ 157953, 0, |
| 61531 | /*GILLT_v4s16*//*Label 3418*/ 157985, |
| 61532 | /*GILLT_v4s32*//*Label 3419*/ 158017, |
| 61533 | /*GILLT_v8s8*//*Label 3420*/ 158049, |
| 61534 | /*GILLT_v8s16*//*Label 3421*/ 158081, |
| 61535 | /*GILLT_v16s8*//*Label 3422*/ 158113, |
| 61536 | // Label 3417: @157953 |
| 61537 | GIM_Try, /*On fail goto*//*Label 3424*/ 157984, // Rule ID 1120 // |
| 61538 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61539 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 61540 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 61541 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 61542 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61543 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 61544 | // (smax:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SMAXv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 61545 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMAXv2i32, |
| 61546 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61547 | // GIR_Coverage, 1120, |
| 61548 | GIR_Done, |
| 61549 | // Label 3424: @157984 |
| 61550 | GIM_Reject, |
| 61551 | // Label 3418: @157985 |
| 61552 | GIM_Try, /*On fail goto*//*Label 3425*/ 158016, // Rule ID 1118 // |
| 61553 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61554 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 61555 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 61556 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 61557 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61558 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 61559 | // (smax:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SMAXv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 61560 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMAXv4i16, |
| 61561 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61562 | // GIR_Coverage, 1118, |
| 61563 | GIR_Done, |
| 61564 | // Label 3425: @158016 |
| 61565 | GIM_Reject, |
| 61566 | // Label 3419: @158017 |
| 61567 | GIM_Try, /*On fail goto*//*Label 3426*/ 158048, // Rule ID 1121 // |
| 61568 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61569 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 61570 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 61571 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 61572 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 61573 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 61574 | // (smax:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SMAXv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 61575 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMAXv4i32, |
| 61576 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61577 | // GIR_Coverage, 1121, |
| 61578 | GIR_Done, |
| 61579 | // Label 3426: @158048 |
| 61580 | GIM_Reject, |
| 61581 | // Label 3420: @158049 |
| 61582 | GIM_Try, /*On fail goto*//*Label 3427*/ 158080, // Rule ID 1116 // |
| 61583 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61584 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 61585 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 61586 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 61587 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61588 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 61589 | // (smax:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SMAXv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 61590 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMAXv8i8, |
| 61591 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61592 | // GIR_Coverage, 1116, |
| 61593 | GIR_Done, |
| 61594 | // Label 3427: @158080 |
| 61595 | GIM_Reject, |
| 61596 | // Label 3421: @158081 |
| 61597 | GIM_Try, /*On fail goto*//*Label 3428*/ 158112, // Rule ID 1119 // |
| 61598 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61599 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 61600 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 61601 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 61602 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 61603 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 61604 | // (smax:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SMAXv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 61605 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMAXv8i16, |
| 61606 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61607 | // GIR_Coverage, 1119, |
| 61608 | GIR_Done, |
| 61609 | // Label 3428: @158112 |
| 61610 | GIM_Reject, |
| 61611 | // Label 3422: @158113 |
| 61612 | GIM_Try, /*On fail goto*//*Label 3429*/ 158144, // Rule ID 1117 // |
| 61613 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61614 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 61615 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 61616 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 61617 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 61618 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 61619 | // (smax:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SMAXv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 61620 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SMAXv16i8, |
| 61621 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61622 | // GIR_Coverage, 1117, |
| 61623 | GIR_Done, |
| 61624 | // Label 3429: @158144 |
| 61625 | GIM_Reject, |
| 61626 | // Label 3423: @158145 |
| 61627 | GIM_Reject, |
| 61628 | // Label 64: @158146 |
| 61629 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 11, /*)*//*default:*//*Label 3436*/ 158351, |
| 61630 | /*GILLT_v2s32*//*Label 3430*/ 158159, 0, |
| 61631 | /*GILLT_v4s16*//*Label 3431*/ 158191, |
| 61632 | /*GILLT_v4s32*//*Label 3432*/ 158223, |
| 61633 | /*GILLT_v8s8*//*Label 3433*/ 158255, |
| 61634 | /*GILLT_v8s16*//*Label 3434*/ 158287, |
| 61635 | /*GILLT_v16s8*//*Label 3435*/ 158319, |
| 61636 | // Label 3430: @158159 |
| 61637 | GIM_Try, /*On fail goto*//*Label 3437*/ 158190, // Rule ID 1255 // |
| 61638 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61639 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 61640 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 61641 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 61642 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61643 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 61644 | // (umin:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UMINv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 61645 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMINv2i32, |
| 61646 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61647 | // GIR_Coverage, 1255, |
| 61648 | GIR_Done, |
| 61649 | // Label 3437: @158190 |
| 61650 | GIM_Reject, |
| 61651 | // Label 3431: @158191 |
| 61652 | GIM_Try, /*On fail goto*//*Label 3438*/ 158222, // Rule ID 1253 // |
| 61653 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61654 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 61655 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 61656 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 61657 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61658 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 61659 | // (umin:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UMINv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 61660 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMINv4i16, |
| 61661 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61662 | // GIR_Coverage, 1253, |
| 61663 | GIR_Done, |
| 61664 | // Label 3438: @158222 |
| 61665 | GIM_Reject, |
| 61666 | // Label 3432: @158223 |
| 61667 | GIM_Try, /*On fail goto*//*Label 3439*/ 158254, // Rule ID 1256 // |
| 61668 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61669 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 61670 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 61671 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 61672 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 61673 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 61674 | // (umin:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UMINv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 61675 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMINv4i32, |
| 61676 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61677 | // GIR_Coverage, 1256, |
| 61678 | GIR_Done, |
| 61679 | // Label 3439: @158254 |
| 61680 | GIM_Reject, |
| 61681 | // Label 3433: @158255 |
| 61682 | GIM_Try, /*On fail goto*//*Label 3440*/ 158286, // Rule ID 1251 // |
| 61683 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61684 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 61685 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 61686 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 61687 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61688 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 61689 | // (umin:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UMINv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 61690 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMINv8i8, |
| 61691 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61692 | // GIR_Coverage, 1251, |
| 61693 | GIR_Done, |
| 61694 | // Label 3440: @158286 |
| 61695 | GIM_Reject, |
| 61696 | // Label 3434: @158287 |
| 61697 | GIM_Try, /*On fail goto*//*Label 3441*/ 158318, // Rule ID 1254 // |
| 61698 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61699 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 61700 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 61701 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 61702 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 61703 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 61704 | // (umin:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UMINv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 61705 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMINv8i16, |
| 61706 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61707 | // GIR_Coverage, 1254, |
| 61708 | GIR_Done, |
| 61709 | // Label 3441: @158318 |
| 61710 | GIM_Reject, |
| 61711 | // Label 3435: @158319 |
| 61712 | GIM_Try, /*On fail goto*//*Label 3442*/ 158350, // Rule ID 1252 // |
| 61713 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61714 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 61715 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 61716 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 61717 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 61718 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 61719 | // (umin:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UMINv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 61720 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMINv16i8, |
| 61721 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61722 | // GIR_Coverage, 1252, |
| 61723 | GIR_Done, |
| 61724 | // Label 3442: @158350 |
| 61725 | GIM_Reject, |
| 61726 | // Label 3436: @158351 |
| 61727 | GIM_Reject, |
| 61728 | // Label 65: @158352 |
| 61729 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 11, /*)*//*default:*//*Label 3449*/ 158557, |
| 61730 | /*GILLT_v2s32*//*Label 3443*/ 158365, 0, |
| 61731 | /*GILLT_v4s16*//*Label 3444*/ 158397, |
| 61732 | /*GILLT_v4s32*//*Label 3445*/ 158429, |
| 61733 | /*GILLT_v8s8*//*Label 3446*/ 158461, |
| 61734 | /*GILLT_v8s16*//*Label 3447*/ 158493, |
| 61735 | /*GILLT_v16s8*//*Label 3448*/ 158525, |
| 61736 | // Label 3443: @158365 |
| 61737 | GIM_Try, /*On fail goto*//*Label 3450*/ 158396, // Rule ID 1243 // |
| 61738 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61739 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 61740 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 61741 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 61742 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61743 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 61744 | // (umax:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UMAXv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 61745 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMAXv2i32, |
| 61746 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61747 | // GIR_Coverage, 1243, |
| 61748 | GIR_Done, |
| 61749 | // Label 3450: @158396 |
| 61750 | GIM_Reject, |
| 61751 | // Label 3444: @158397 |
| 61752 | GIM_Try, /*On fail goto*//*Label 3451*/ 158428, // Rule ID 1241 // |
| 61753 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61754 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 61755 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 61756 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 61757 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61758 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 61759 | // (umax:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UMAXv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 61760 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMAXv4i16, |
| 61761 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61762 | // GIR_Coverage, 1241, |
| 61763 | GIR_Done, |
| 61764 | // Label 3451: @158428 |
| 61765 | GIM_Reject, |
| 61766 | // Label 3445: @158429 |
| 61767 | GIM_Try, /*On fail goto*//*Label 3452*/ 158460, // Rule ID 1244 // |
| 61768 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61769 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 61770 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 61771 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 61772 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 61773 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 61774 | // (umax:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UMAXv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 61775 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMAXv4i32, |
| 61776 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61777 | // GIR_Coverage, 1244, |
| 61778 | GIR_Done, |
| 61779 | // Label 3452: @158460 |
| 61780 | GIM_Reject, |
| 61781 | // Label 3446: @158461 |
| 61782 | GIM_Try, /*On fail goto*//*Label 3453*/ 158492, // Rule ID 1239 // |
| 61783 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61784 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 61785 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 61786 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 61787 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61788 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 61789 | // (umax:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UMAXv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 61790 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMAXv8i8, |
| 61791 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61792 | // GIR_Coverage, 1239, |
| 61793 | GIR_Done, |
| 61794 | // Label 3453: @158492 |
| 61795 | GIM_Reject, |
| 61796 | // Label 3447: @158493 |
| 61797 | GIM_Try, /*On fail goto*//*Label 3454*/ 158524, // Rule ID 1242 // |
| 61798 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61799 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 61800 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 61801 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 61802 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 61803 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 61804 | // (umax:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UMAXv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 61805 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMAXv8i16, |
| 61806 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61807 | // GIR_Coverage, 1242, |
| 61808 | GIR_Done, |
| 61809 | // Label 3454: @158524 |
| 61810 | GIM_Reject, |
| 61811 | // Label 3448: @158525 |
| 61812 | GIM_Try, /*On fail goto*//*Label 3455*/ 158556, // Rule ID 1240 // |
| 61813 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61814 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 61815 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 61816 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 61817 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 61818 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 61819 | // (umax:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UMAXv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 61820 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UMAXv16i8, |
| 61821 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61822 | // GIR_Coverage, 1240, |
| 61823 | GIR_Done, |
| 61824 | // Label 3455: @158556 |
| 61825 | GIM_Reject, |
| 61826 | // Label 3449: @158557 |
| 61827 | GIM_Reject, |
| 61828 | // Label 66: @158558 |
| 61829 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 11, /*)*//*default:*//*Label 3464*/ 159007, |
| 61830 | /*GILLT_s64*//*Label 3456*/ 158573, 0, |
| 61831 | /*GILLT_v2s32*//*Label 3457*/ 158611, |
| 61832 | /*GILLT_v2s64*//*Label 3458*/ 158635, |
| 61833 | /*GILLT_v4s16*//*Label 3459*/ 158735, |
| 61834 | /*GILLT_v4s32*//*Label 3460*/ 158759, |
| 61835 | /*GILLT_v8s8*//*Label 3461*/ 158859, |
| 61836 | /*GILLT_v8s16*//*Label 3462*/ 158883, |
| 61837 | /*GILLT_v16s8*//*Label 3463*/ 158983, |
| 61838 | // Label 3456: @158573 |
| 61839 | GIM_Try, /*On fail goto*//*Label 3465*/ 158610, |
| 61840 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 61841 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 61842 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61843 | GIM_Try, /*On fail goto*//*Label 3466*/ 158598, // Rule ID 1372 // |
| 61844 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61845 | // (abs:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn) => (ABSv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn) |
| 61846 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ABSv1i64, |
| 61847 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61848 | // GIR_Coverage, 1372, |
| 61849 | GIR_Done, |
| 61850 | // Label 3466: @158598 |
| 61851 | GIM_Try, /*On fail goto*//*Label 3467*/ 158609, // Rule ID 2709 // |
| 61852 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61853 | // (abs:{ *:[i64] } FPR64:{ *:[i64] }:$Rn) => (ABSv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn) |
| 61854 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ABSv1i64, |
| 61855 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61856 | // GIR_Coverage, 2709, |
| 61857 | GIR_Done, |
| 61858 | // Label 3467: @158609 |
| 61859 | GIM_Reject, |
| 61860 | // Label 3465: @158610 |
| 61861 | GIM_Reject, |
| 61862 | // Label 3457: @158611 |
| 61863 | GIM_Try, /*On fail goto*//*Label 3468*/ 158634, // Rule ID 601 // |
| 61864 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61865 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 61866 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 61867 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61868 | // (abs:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) => (ABSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) |
| 61869 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ABSv2i32, |
| 61870 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61871 | // GIR_Coverage, 601, |
| 61872 | GIR_Done, |
| 61873 | // Label 3468: @158634 |
| 61874 | GIM_Reject, |
| 61875 | // Label 3458: @158635 |
| 61876 | GIM_Try, /*On fail goto*//*Label 3469*/ 158734, |
| 61877 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 61878 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 61879 | GIM_Try, /*On fail goto*//*Label 3470*/ 158718, // Rule ID 3970 // |
| 61880 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 61881 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, |
| 61882 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 61883 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 61884 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 61885 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, |
| 61886 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 61887 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61888 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 61889 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT, |
| 61890 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s32, |
| 61891 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61892 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 61893 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 61894 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 61895 | // (abs:{ *:[v2i64] } (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$opA), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$opB))) => (UABDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$opA, V64:{ *:[v2i32] }:$opB) |
| 61896 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv2i32_v2i64, |
| 61897 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 61898 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // opA |
| 61899 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // opB |
| 61900 | GIR_EraseFromParent, /*InsnID*/0, |
| 61901 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61902 | // GIR_Coverage, 3970, |
| 61903 | GIR_Done, |
| 61904 | // Label 3470: @158718 |
| 61905 | GIM_Try, /*On fail goto*//*Label 3471*/ 158733, // Rule ID 603 // |
| 61906 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61907 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 61908 | // (abs:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn) => (ABSv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn) |
| 61909 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ABSv2i64, |
| 61910 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61911 | // GIR_Coverage, 603, |
| 61912 | GIR_Done, |
| 61913 | // Label 3471: @158733 |
| 61914 | GIM_Reject, |
| 61915 | // Label 3469: @158734 |
| 61916 | GIM_Reject, |
| 61917 | // Label 3459: @158735 |
| 61918 | GIM_Try, /*On fail goto*//*Label 3472*/ 158758, // Rule ID 599 // |
| 61919 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61920 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 61921 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 61922 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61923 | // (abs:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) => (ABSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) |
| 61924 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ABSv4i16, |
| 61925 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61926 | // GIR_Coverage, 599, |
| 61927 | GIR_Done, |
| 61928 | // Label 3472: @158758 |
| 61929 | GIM_Reject, |
| 61930 | // Label 3460: @158759 |
| 61931 | GIM_Try, /*On fail goto*//*Label 3473*/ 158858, |
| 61932 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 61933 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 61934 | GIM_Try, /*On fail goto*//*Label 3474*/ 158842, // Rule ID 3968 // |
| 61935 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 61936 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, |
| 61937 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 61938 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 61939 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 61940 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, |
| 61941 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 61942 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61943 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 61944 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT, |
| 61945 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s16, |
| 61946 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61947 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 61948 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 61949 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 61950 | // (abs:{ *:[v4i32] } (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$opA), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$opB))) => (UABDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$opA, V64:{ *:[v4i16] }:$opB) |
| 61951 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv4i16_v4i32, |
| 61952 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 61953 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // opA |
| 61954 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // opB |
| 61955 | GIR_EraseFromParent, /*InsnID*/0, |
| 61956 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61957 | // GIR_Coverage, 3968, |
| 61958 | GIR_Done, |
| 61959 | // Label 3474: @158842 |
| 61960 | GIM_Try, /*On fail goto*//*Label 3475*/ 158857, // Rule ID 602 // |
| 61961 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61962 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 61963 | // (abs:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) => (ABSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) |
| 61964 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ABSv4i32, |
| 61965 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61966 | // GIR_Coverage, 602, |
| 61967 | GIR_Done, |
| 61968 | // Label 3475: @158857 |
| 61969 | GIM_Reject, |
| 61970 | // Label 3473: @158858 |
| 61971 | GIM_Reject, |
| 61972 | // Label 3461: @158859 |
| 61973 | GIM_Try, /*On fail goto*//*Label 3476*/ 158882, // Rule ID 597 // |
| 61974 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 61975 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 61976 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 61977 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61978 | // (abs:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) => (ABSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) |
| 61979 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ABSv8i8, |
| 61980 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 61981 | // GIR_Coverage, 597, |
| 61982 | GIR_Done, |
| 61983 | // Label 3476: @158882 |
| 61984 | GIM_Reject, |
| 61985 | // Label 3462: @158883 |
| 61986 | GIM_Try, /*On fail goto*//*Label 3477*/ 158982, |
| 61987 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 61988 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 61989 | GIM_Try, /*On fail goto*//*Label 3478*/ 158966, // Rule ID 3964 // |
| 61990 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 61991 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, |
| 61992 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 61993 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 61994 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 61995 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, |
| 61996 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 61997 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 61998 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 61999 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT, |
| 62000 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s8, |
| 62001 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 62002 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 62003 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 62004 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 62005 | // (abs:{ *:[v8i16] } (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$opA), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$opB))) => (UABDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$opA, V64:{ *:[v8i8] }:$opB) |
| 62006 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UABDLv8i8_v8i16, |
| 62007 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 62008 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // opA |
| 62009 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // opB |
| 62010 | GIR_EraseFromParent, /*InsnID*/0, |
| 62011 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62012 | // GIR_Coverage, 3964, |
| 62013 | GIR_Done, |
| 62014 | // Label 3478: @158966 |
| 62015 | GIM_Try, /*On fail goto*//*Label 3479*/ 158981, // Rule ID 600 // |
| 62016 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 62017 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 62018 | // (abs:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) => (ABSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) |
| 62019 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ABSv8i16, |
| 62020 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62021 | // GIR_Coverage, 600, |
| 62022 | GIR_Done, |
| 62023 | // Label 3479: @158981 |
| 62024 | GIM_Reject, |
| 62025 | // Label 3477: @158982 |
| 62026 | GIM_Reject, |
| 62027 | // Label 3463: @158983 |
| 62028 | GIM_Try, /*On fail goto*//*Label 3480*/ 159006, // Rule ID 598 // |
| 62029 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 62030 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 62031 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 62032 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 62033 | // (abs:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) => (ABSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) |
| 62034 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ABSv16i8, |
| 62035 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62036 | // GIR_Coverage, 598, |
| 62037 | GIR_Done, |
| 62038 | // Label 3480: @159006 |
| 62039 | GIM_Reject, |
| 62040 | // Label 3464: @159007 |
| 62041 | GIM_Reject, |
| 62042 | // Label 67: @159008 |
| 62043 | GIM_Try, /*On fail goto*//*Label 3481*/ 159020, // Rule ID 211 // |
| 62044 | // MIs[0] addr |
| 62045 | GIM_CheckIsMBB, /*MI*/0, /*Op*/0, |
| 62046 | // (br (bb:{ *:[Other] }):$addr) => (B (bb:{ *:[Other] }):$addr) |
| 62047 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::B, |
| 62048 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62049 | // GIR_Coverage, 211, |
| 62050 | GIR_Done, |
| 62051 | // Label 3481: @159020 |
| 62052 | GIM_Reject, |
| 62053 | // Label 68: @159021 |
| 62054 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 3485*/ 159542, |
| 62055 | /*GILLT_s16*//*Label 3482*/ 159030, |
| 62056 | /*GILLT_s32*//*Label 3483*/ 159116, |
| 62057 | /*GILLT_s64*//*Label 3484*/ 159409, |
| 62058 | // Label 3482: @159030 |
| 62059 | GIM_Try, /*On fail goto*//*Label 3486*/ 159115, |
| 62060 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 62061 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 62062 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 62063 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 62064 | GIM_Try, /*On fail goto*//*Label 3487*/ 159081, // Rule ID 4459 // |
| 62065 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 62066 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 62067 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 62068 | // MIs[1] Operand 1 |
| 62069 | // No operand predicates |
| 62070 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 62071 | // (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) => (CPYi16:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) |
| 62072 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CPYi16, |
| 62073 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 62074 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 62075 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx |
| 62076 | GIR_EraseFromParent, /*InsnID*/0, |
| 62077 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62078 | // GIR_Coverage, 4459, |
| 62079 | GIR_Done, |
| 62080 | // Label 3487: @159081 |
| 62081 | GIM_Try, /*On fail goto*//*Label 3488*/ 159114, // Rule ID 4460 // |
| 62082 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 62083 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 62084 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 62085 | // MIs[1] Operand 1 |
| 62086 | // No operand predicates |
| 62087 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 62088 | // (vector_extract:{ *:[bf16] } V128:{ *:[v8bf16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) => (CPYi16:{ *:[bf16] } V128:{ *:[v8bf16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) |
| 62089 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CPYi16, |
| 62090 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 62091 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 62092 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx |
| 62093 | GIR_EraseFromParent, /*InsnID*/0, |
| 62094 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62095 | // GIR_Coverage, 4460, |
| 62096 | GIR_Done, |
| 62097 | // Label 3488: @159114 |
| 62098 | GIM_Reject, |
| 62099 | // Label 3486: @159115 |
| 62100 | GIM_Reject, |
| 62101 | // Label 3483: @159116 |
| 62102 | GIM_Try, /*On fail goto*//*Label 3489*/ 159161, // Rule ID 5355 // |
| 62103 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 62104 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 62105 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 62106 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 62107 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, |
| 62108 | // (extractelt:{ *:[i32] } V128:{ *:[v4i32] }:$V, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4i32] }:$V, ssub:{ *:[i32] }) |
| 62109 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 62110 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 62111 | GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/14, // V |
| 62112 | GIR_EraseFromParent, /*InsnID*/0, |
| 62113 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, |
| 62114 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, |
| 62115 | // GIR_Coverage, 5355, |
| 62116 | GIR_Done, |
| 62117 | // Label 3489: @159161 |
| 62118 | GIM_Try, /*On fail goto*//*Label 3490*/ 159206, // Rule ID 5356 // |
| 62119 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 62120 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 62121 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 62122 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 62123 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, |
| 62124 | // (extractelt:{ *:[i32] } V64:{ *:[v2i32] }:$V, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[i32] } V64:{ *:[v2i32] }:$V, ssub:{ *:[i32] }) |
| 62125 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 62126 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 62127 | GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/14, // V |
| 62128 | GIR_EraseFromParent, /*InsnID*/0, |
| 62129 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR32RegClassID, |
| 62130 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR64RegClassID, |
| 62131 | // GIR_Coverage, 5356, |
| 62132 | GIR_Done, |
| 62133 | // Label 3490: @159206 |
| 62134 | GIM_Try, /*On fail goto*//*Label 3491*/ 159257, // Rule ID 1643 // |
| 62135 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 62136 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 62137 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 62138 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 62139 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 62140 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 62141 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 62142 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexB, |
| 62143 | // MIs[1] Operand 1 |
| 62144 | // No operand predicates |
| 62145 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 62146 | // (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx) => (UMOVvi8:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$idx) |
| 62147 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi8, |
| 62148 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 62149 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 62150 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx |
| 62151 | GIR_EraseFromParent, /*InsnID*/0, |
| 62152 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62153 | // GIR_Coverage, 1643, |
| 62154 | GIR_Done, |
| 62155 | // Label 3491: @159257 |
| 62156 | GIM_Try, /*On fail goto*//*Label 3492*/ 159308, // Rule ID 1644 // |
| 62157 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 62158 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 62159 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 62160 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 62161 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 62162 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 62163 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 62164 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 62165 | // MIs[1] Operand 1 |
| 62166 | // No operand predicates |
| 62167 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 62168 | // (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) => (UMOVvi16:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$idx) |
| 62169 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi16, |
| 62170 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 62171 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 62172 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx |
| 62173 | GIR_EraseFromParent, /*InsnID*/0, |
| 62174 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62175 | // GIR_Coverage, 1644, |
| 62176 | GIR_Done, |
| 62177 | // Label 3492: @159308 |
| 62178 | GIM_Try, /*On fail goto*//*Label 3493*/ 159359, // Rule ID 1645 // |
| 62179 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 62180 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 62181 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 62182 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 62183 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 62184 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 62185 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 62186 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 62187 | // MIs[1] Operand 1 |
| 62188 | // No operand predicates |
| 62189 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 62190 | // (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) => (UMOVvi32:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$idx) |
| 62191 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi32, |
| 62192 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 62193 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 62194 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx |
| 62195 | GIR_EraseFromParent, /*InsnID*/0, |
| 62196 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62197 | // GIR_Coverage, 1645, |
| 62198 | GIR_Done, |
| 62199 | // Label 3493: @159359 |
| 62200 | GIM_Try, /*On fail goto*//*Label 3494*/ 159408, // Rule ID 4458 // |
| 62201 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 62202 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 62203 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 62204 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 62205 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 62206 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 62207 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 62208 | // MIs[1] Operand 1 |
| 62209 | // No operand predicates |
| 62210 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 62211 | // (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) => (CPYi32:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) |
| 62212 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CPYi32, |
| 62213 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 62214 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 62215 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx |
| 62216 | GIR_EraseFromParent, /*InsnID*/0, |
| 62217 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62218 | // GIR_Coverage, 4458, |
| 62219 | GIR_Done, |
| 62220 | // Label 3494: @159408 |
| 62221 | GIM_Reject, |
| 62222 | // Label 3484: @159409 |
| 62223 | GIM_Try, /*On fail goto*//*Label 3495*/ 159541, |
| 62224 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 62225 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 62226 | GIM_Try, /*On fail goto*//*Label 3496*/ 159456, // Rule ID 5354 // |
| 62227 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 62228 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 62229 | GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, |
| 62230 | // (extractelt:{ *:[i64] } V128:{ *:[v2i64] }:$V, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2i64] }:$V, dsub:{ *:[i32] }) |
| 62231 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 62232 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 62233 | GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/2, // V |
| 62234 | GIR_EraseFromParent, /*InsnID*/0, |
| 62235 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 62236 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, AArch64::FPR128RegClassID, |
| 62237 | // GIR_Coverage, 5354, |
| 62238 | GIR_Done, |
| 62239 | // Label 3496: @159456 |
| 62240 | GIM_Try, /*On fail goto*//*Label 3497*/ 159499, // Rule ID 1646 // |
| 62241 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 62242 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 62243 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 62244 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 62245 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 62246 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 62247 | // MIs[1] Operand 1 |
| 62248 | // No operand predicates |
| 62249 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 62250 | // (vector_extract:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx) => (UMOVvi64:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$idx) |
| 62251 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UMOVvi64, |
| 62252 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 62253 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 62254 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx |
| 62255 | GIR_EraseFromParent, /*InsnID*/0, |
| 62256 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62257 | // GIR_Coverage, 1646, |
| 62258 | GIR_Done, |
| 62259 | // Label 3497: @159499 |
| 62260 | GIM_Try, /*On fail goto*//*Label 3498*/ 159540, // Rule ID 4457 // |
| 62261 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 62262 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 62263 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 62264 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 62265 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 62266 | // MIs[1] Operand 1 |
| 62267 | // No operand predicates |
| 62268 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 62269 | // (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx) => (CPYi64:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx) |
| 62270 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CPYi64, |
| 62271 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 62272 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 62273 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx |
| 62274 | GIR_EraseFromParent, /*InsnID*/0, |
| 62275 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62276 | // GIR_Coverage, 4457, |
| 62277 | GIR_Done, |
| 62278 | // Label 3498: @159540 |
| 62279 | GIM_Reject, |
| 62280 | // Label 3495: @159541 |
| 62281 | GIM_Reject, |
| 62282 | // Label 3485: @159542 |
| 62283 | GIM_Reject, |
| 62284 | // Label 69: @159543 |
| 62285 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 3501*/ 159645, |
| 62286 | /*GILLT_s32*//*Label 3499*/ 159551, |
| 62287 | /*GILLT_s64*//*Label 3500*/ 159598, |
| 62288 | // Label 3499: @159551 |
| 62289 | GIM_Try, /*On fail goto*//*Label 3502*/ 159597, // Rule ID 3534 // |
| 62290 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 62291 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 62292 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 62293 | // (cttz:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) => (CLZWr:{ *:[i32] } (RBITWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)) |
| 62294 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 62295 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::RBITWr, |
| 62296 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 62297 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 62298 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 62299 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLZWr, |
| 62300 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 62301 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 62302 | GIR_EraseFromParent, /*InsnID*/0, |
| 62303 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62304 | // GIR_Coverage, 3534, |
| 62305 | GIR_Done, |
| 62306 | // Label 3502: @159597 |
| 62307 | GIM_Reject, |
| 62308 | // Label 3500: @159598 |
| 62309 | GIM_Try, /*On fail goto*//*Label 3503*/ 159644, // Rule ID 3535 // |
| 62310 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 62311 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 62312 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 62313 | // (cttz:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) => (CLZXr:{ *:[i64] } (RBITXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)) |
| 62314 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 62315 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::RBITXr, |
| 62316 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 62317 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 62318 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 62319 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLZXr, |
| 62320 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 62321 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 62322 | GIR_EraseFromParent, /*InsnID*/0, |
| 62323 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62324 | // GIR_Coverage, 3535, |
| 62325 | GIR_Done, |
| 62326 | // Label 3503: @159644 |
| 62327 | GIM_Reject, |
| 62328 | // Label 3501: @159645 |
| 62329 | GIM_Reject, |
| 62330 | // Label 70: @159646 |
| 62331 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 3512*/ 160268, |
| 62332 | /*GILLT_s32*//*Label 3504*/ 159662, |
| 62333 | /*GILLT_s64*//*Label 3505*/ 159893, 0, |
| 62334 | /*GILLT_v2s32*//*Label 3506*/ 160124, 0, |
| 62335 | /*GILLT_v4s16*//*Label 3507*/ 160148, |
| 62336 | /*GILLT_v4s32*//*Label 3508*/ 160172, |
| 62337 | /*GILLT_v8s8*//*Label 3509*/ 160196, |
| 62338 | /*GILLT_v8s16*//*Label 3510*/ 160220, |
| 62339 | /*GILLT_v16s8*//*Label 3511*/ 160244, |
| 62340 | // Label 3504: @159662 |
| 62341 | GIM_Try, /*On fail goto*//*Label 3513*/ 159892, |
| 62342 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 62343 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 62344 | GIM_Try, /*On fail goto*//*Label 3514*/ 159775, // Rule ID 3536 // |
| 62345 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 62346 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, |
| 62347 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 62348 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 62349 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 62350 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL, |
| 62351 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 62352 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 62353 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 62354 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 62355 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 62356 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 62357 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_ASHR, |
| 62358 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 62359 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64, |
| 62360 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 62361 | GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 31, |
| 62362 | // MIs[3] Rn |
| 62363 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/4, /*OtherOpIdx*/1, |
| 62364 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, |
| 62365 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, |
| 62366 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 62367 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 62368 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 62369 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 62370 | // (ctlz:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } (xor:{ *:[i32] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, 31:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn), 1:{ *:[i64] }), 1:{ *:[i32] })) => (CLSWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) |
| 62371 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSWr, |
| 62372 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 62373 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 62374 | GIR_EraseFromParent, /*InsnID*/0, |
| 62375 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62376 | // GIR_Coverage, 3536, |
| 62377 | GIR_Done, |
| 62378 | // Label 3514: @159775 |
| 62379 | GIM_Try, /*On fail goto*//*Label 3515*/ 159878, // Rule ID 7929 // |
| 62380 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 62381 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, |
| 62382 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 62383 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 62384 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 62385 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL, |
| 62386 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 62387 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 62388 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 62389 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 62390 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 62391 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 62392 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 62393 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 62394 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_ASHR, |
| 62395 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64, |
| 62396 | // MIs[4] Rn |
| 62397 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1, |
| 62398 | GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 31, |
| 62399 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, |
| 62400 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, |
| 62401 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 62402 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 62403 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 62404 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 62405 | // (ctlz:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, 31:{ *:[i64] })), 1:{ *:[i64] }), 1:{ *:[i32] })) => (CLSWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) |
| 62406 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSWr, |
| 62407 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 62408 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 62409 | GIR_EraseFromParent, /*InsnID*/0, |
| 62410 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62411 | // GIR_Coverage, 7929, |
| 62412 | GIR_Done, |
| 62413 | // Label 3515: @159878 |
| 62414 | GIM_Try, /*On fail goto*//*Label 3516*/ 159891, // Rule ID 171 // |
| 62415 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 62416 | // (ctlz:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) => (CLZWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) |
| 62417 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CLZWr, |
| 62418 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62419 | // GIR_Coverage, 171, |
| 62420 | GIR_Done, |
| 62421 | // Label 3516: @159891 |
| 62422 | GIM_Reject, |
| 62423 | // Label 3513: @159892 |
| 62424 | GIM_Reject, |
| 62425 | // Label 3505: @159893 |
| 62426 | GIM_Try, /*On fail goto*//*Label 3517*/ 160123, |
| 62427 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 62428 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 62429 | GIM_Try, /*On fail goto*//*Label 3518*/ 160006, // Rule ID 3537 // |
| 62430 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 62431 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, |
| 62432 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 62433 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 62434 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 62435 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL, |
| 62436 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 62437 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 62438 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 62439 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 62440 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64, |
| 62441 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 62442 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_ASHR, |
| 62443 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s64, |
| 62444 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64, |
| 62445 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 62446 | GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 63, |
| 62447 | // MIs[3] Rn |
| 62448 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/4, /*OtherOpIdx*/1, |
| 62449 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, |
| 62450 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, |
| 62451 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 62452 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 62453 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 62454 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 62455 | // (ctlz:{ *:[i64] } (or:{ *:[i64] } (shl:{ *:[i64] } (xor:{ *:[i64] } (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 63:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn), 1:{ *:[i64] }), 1:{ *:[i64] })) => (CLSXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) |
| 62456 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSXr, |
| 62457 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 62458 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 62459 | GIR_EraseFromParent, /*InsnID*/0, |
| 62460 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62461 | // GIR_Coverage, 3537, |
| 62462 | GIR_Done, |
| 62463 | // Label 3518: @160006 |
| 62464 | GIM_Try, /*On fail goto*//*Label 3519*/ 160109, // Rule ID 7930 // |
| 62465 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 62466 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, |
| 62467 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 62468 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 62469 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 62470 | GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL, |
| 62471 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 62472 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 62473 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 62474 | GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_XOR, |
| 62475 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64, |
| 62476 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64, |
| 62477 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 62478 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 62479 | GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_ASHR, |
| 62480 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64, |
| 62481 | // MIs[4] Rn |
| 62482 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1, |
| 62483 | GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 63, |
| 62484 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, |
| 62485 | GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, |
| 62486 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 62487 | GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 62488 | GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 62489 | GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 62490 | // (ctlz:{ *:[i64] } (or:{ *:[i64] } (shl:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 63:{ *:[i64] })), 1:{ *:[i64] }), 1:{ *:[i64] })) => (CLSXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) |
| 62491 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::CLSXr, |
| 62492 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 62493 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 62494 | GIR_EraseFromParent, /*InsnID*/0, |
| 62495 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62496 | // GIR_Coverage, 7930, |
| 62497 | GIR_Done, |
| 62498 | // Label 3519: @160109 |
| 62499 | GIM_Try, /*On fail goto*//*Label 3520*/ 160122, // Rule ID 172 // |
| 62500 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 62501 | // (ctlz:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) => (CLZXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) |
| 62502 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CLZXr, |
| 62503 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62504 | // GIR_Coverage, 172, |
| 62505 | GIR_Done, |
| 62506 | // Label 3520: @160122 |
| 62507 | GIM_Reject, |
| 62508 | // Label 3517: @160123 |
| 62509 | GIM_Reject, |
| 62510 | // Label 3506: @160124 |
| 62511 | GIM_Try, /*On fail goto*//*Label 3521*/ 160147, // Rule ID 614 // |
| 62512 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 62513 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 62514 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 62515 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 62516 | // (ctlz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) => (CLZv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) |
| 62517 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CLZv2i32, |
| 62518 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62519 | // GIR_Coverage, 614, |
| 62520 | GIR_Done, |
| 62521 | // Label 3521: @160147 |
| 62522 | GIM_Reject, |
| 62523 | // Label 3507: @160148 |
| 62524 | GIM_Try, /*On fail goto*//*Label 3522*/ 160171, // Rule ID 612 // |
| 62525 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 62526 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 62527 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 62528 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 62529 | // (ctlz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) => (CLZv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) |
| 62530 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CLZv4i16, |
| 62531 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62532 | // GIR_Coverage, 612, |
| 62533 | GIR_Done, |
| 62534 | // Label 3522: @160171 |
| 62535 | GIM_Reject, |
| 62536 | // Label 3508: @160172 |
| 62537 | GIM_Try, /*On fail goto*//*Label 3523*/ 160195, // Rule ID 615 // |
| 62538 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 62539 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 62540 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 62541 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 62542 | // (ctlz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) => (CLZv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) |
| 62543 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CLZv4i32, |
| 62544 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62545 | // GIR_Coverage, 615, |
| 62546 | GIR_Done, |
| 62547 | // Label 3523: @160195 |
| 62548 | GIM_Reject, |
| 62549 | // Label 3509: @160196 |
| 62550 | GIM_Try, /*On fail goto*//*Label 3524*/ 160219, // Rule ID 610 // |
| 62551 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 62552 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 62553 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 62554 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 62555 | // (ctlz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) => (CLZv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) |
| 62556 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CLZv8i8, |
| 62557 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62558 | // GIR_Coverage, 610, |
| 62559 | GIR_Done, |
| 62560 | // Label 3524: @160219 |
| 62561 | GIM_Reject, |
| 62562 | // Label 3510: @160220 |
| 62563 | GIM_Try, /*On fail goto*//*Label 3525*/ 160243, // Rule ID 613 // |
| 62564 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 62565 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 62566 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 62567 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 62568 | // (ctlz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) => (CLZv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) |
| 62569 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CLZv8i16, |
| 62570 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62571 | // GIR_Coverage, 613, |
| 62572 | GIR_Done, |
| 62573 | // Label 3525: @160243 |
| 62574 | GIM_Reject, |
| 62575 | // Label 3511: @160244 |
| 62576 | GIM_Try, /*On fail goto*//*Label 3526*/ 160267, // Rule ID 611 // |
| 62577 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 62578 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 62579 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 62580 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 62581 | // (ctlz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) => (CLZv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) |
| 62582 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CLZv16i8, |
| 62583 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62584 | // GIR_Coverage, 611, |
| 62585 | GIR_Done, |
| 62586 | // Label 3526: @160267 |
| 62587 | GIM_Reject, |
| 62588 | // Label 3512: @160268 |
| 62589 | GIM_Reject, |
| 62590 | // Label 71: @160269 |
| 62591 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/8, 11, /*)*//*default:*//*Label 3529*/ 160326, |
| 62592 | /*GILLT_v8s8*//*Label 3527*/ 160278, 0, |
| 62593 | /*GILLT_v16s8*//*Label 3528*/ 160302, |
| 62594 | // Label 3527: @160278 |
| 62595 | GIM_Try, /*On fail goto*//*Label 3530*/ 160301, // Rule ID 651 // |
| 62596 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 62597 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 62598 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 62599 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 62600 | // (ctpop:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) => (CNTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) |
| 62601 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CNTv8i8, |
| 62602 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62603 | // GIR_Coverage, 651, |
| 62604 | GIR_Done, |
| 62605 | // Label 3530: @160301 |
| 62606 | GIM_Reject, |
| 62607 | // Label 3528: @160302 |
| 62608 | GIM_Try, /*On fail goto*//*Label 3531*/ 160325, // Rule ID 652 // |
| 62609 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 62610 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 62611 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 62612 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 62613 | // (ctpop:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) => (CNTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) |
| 62614 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::CNTv16i8, |
| 62615 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62616 | // GIR_Coverage, 652, |
| 62617 | GIR_Done, |
| 62618 | // Label 3531: @160325 |
| 62619 | GIM_Reject, |
| 62620 | // Label 3529: @160326 |
| 62621 | GIM_Reject, |
| 62622 | // Label 72: @160327 |
| 62623 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 3534*/ 160379, |
| 62624 | /*GILLT_s32*//*Label 3532*/ 160335, |
| 62625 | /*GILLT_s64*//*Label 3533*/ 160357, |
| 62626 | // Label 3532: @160335 |
| 62627 | GIM_Try, /*On fail goto*//*Label 3535*/ 160356, // Rule ID 176 // |
| 62628 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 62629 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 62630 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 62631 | // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) => (REVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) |
| 62632 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REVWr, |
| 62633 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62634 | // GIR_Coverage, 176, |
| 62635 | GIR_Done, |
| 62636 | // Label 3535: @160356 |
| 62637 | GIM_Reject, |
| 62638 | // Label 3533: @160357 |
| 62639 | GIM_Try, /*On fail goto*//*Label 3536*/ 160378, // Rule ID 177 // |
| 62640 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 62641 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 62642 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 62643 | // (bswap:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) => (REVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) |
| 62644 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REVXr, |
| 62645 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62646 | // GIR_Coverage, 177, |
| 62647 | GIR_Done, |
| 62648 | // Label 3536: @160378 |
| 62649 | GIM_Reject, |
| 62650 | // Label 3534: @160379 |
| 62651 | GIM_Reject, |
| 62652 | // Label 73: @160380 |
| 62653 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 3539*/ 160432, |
| 62654 | /*GILLT_s32*//*Label 3537*/ 160388, |
| 62655 | /*GILLT_s64*//*Label 3538*/ 160410, |
| 62656 | // Label 3537: @160388 |
| 62657 | GIM_Try, /*On fail goto*//*Label 3540*/ 160409, // Rule ID 173 // |
| 62658 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 62659 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID, |
| 62660 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 62661 | // (bitreverse:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) => (RBITWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) |
| 62662 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::RBITWr, |
| 62663 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62664 | // GIR_Coverage, 173, |
| 62665 | GIR_Done, |
| 62666 | // Label 3540: @160409 |
| 62667 | GIM_Reject, |
| 62668 | // Label 3538: @160410 |
| 62669 | GIM_Try, /*On fail goto*//*Label 3541*/ 160431, // Rule ID 174 // |
| 62670 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 62671 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR64RegClassID, |
| 62672 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 62673 | // (bitreverse:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) => (RBITXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) |
| 62674 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::RBITXr, |
| 62675 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62676 | // GIR_Coverage, 174, |
| 62677 | GIR_Done, |
| 62678 | // Label 3541: @160431 |
| 62679 | GIM_Reject, |
| 62680 | // Label 3539: @160432 |
| 62681 | GIM_Reject, |
| 62682 | // Label 74: @160433 |
| 62683 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 3550*/ 160641, |
| 62684 | /*GILLT_s16*//*Label 3542*/ 160449, |
| 62685 | /*GILLT_s32*//*Label 3543*/ 160473, |
| 62686 | /*GILLT_s64*//*Label 3544*/ 160497, 0, |
| 62687 | /*GILLT_v2s32*//*Label 3545*/ 160521, |
| 62688 | /*GILLT_v2s64*//*Label 3546*/ 160545, |
| 62689 | /*GILLT_v4s16*//*Label 3547*/ 160569, |
| 62690 | /*GILLT_v4s32*//*Label 3548*/ 160593, 0, |
| 62691 | /*GILLT_v8s16*//*Label 3549*/ 160617, |
| 62692 | // Label 3542: @160449 |
| 62693 | GIM_Try, /*On fail goto*//*Label 3551*/ 160472, // Rule ID 504 // |
| 62694 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 62695 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 62696 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 62697 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 62698 | // (fceil:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FRINTPHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) |
| 62699 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTPHr, |
| 62700 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62701 | // GIR_Coverage, 504, |
| 62702 | GIR_Done, |
| 62703 | // Label 3551: @160472 |
| 62704 | GIM_Reject, |
| 62705 | // Label 3543: @160473 |
| 62706 | GIM_Try, /*On fail goto*//*Label 3552*/ 160496, // Rule ID 505 // |
| 62707 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 62708 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 62709 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 62710 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 62711 | // (fceil:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FRINTPSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) |
| 62712 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTPSr, |
| 62713 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62714 | // GIR_Coverage, 505, |
| 62715 | GIR_Done, |
| 62716 | // Label 3552: @160496 |
| 62717 | GIM_Reject, |
| 62718 | // Label 3544: @160497 |
| 62719 | GIM_Try, /*On fail goto*//*Label 3553*/ 160520, // Rule ID 506 // |
| 62720 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 62721 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 62722 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 62723 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 62724 | // (fceil:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FRINTPDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) |
| 62725 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTPDr, |
| 62726 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62727 | // GIR_Coverage, 506, |
| 62728 | GIR_Done, |
| 62729 | // Label 3553: @160520 |
| 62730 | GIM_Reject, |
| 62731 | // Label 3545: @160521 |
| 62732 | GIM_Try, /*On fail goto*//*Label 3554*/ 160544, // Rule ID 766 // |
| 62733 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 62734 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 62735 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 62736 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 62737 | // (fceil:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FRINTPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) |
| 62738 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTPv2f32, |
| 62739 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62740 | // GIR_Coverage, 766, |
| 62741 | GIR_Done, |
| 62742 | // Label 3554: @160544 |
| 62743 | GIM_Reject, |
| 62744 | // Label 3546: @160545 |
| 62745 | GIM_Try, /*On fail goto*//*Label 3555*/ 160568, // Rule ID 768 // |
| 62746 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 62747 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 62748 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 62749 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 62750 | // (fceil:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FRINTPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) |
| 62751 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTPv2f64, |
| 62752 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62753 | // GIR_Coverage, 768, |
| 62754 | GIR_Done, |
| 62755 | // Label 3555: @160568 |
| 62756 | GIM_Reject, |
| 62757 | // Label 3547: @160569 |
| 62758 | GIM_Try, /*On fail goto*//*Label 3556*/ 160592, // Rule ID 764 // |
| 62759 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 62760 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 62761 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 62762 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 62763 | // (fceil:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FRINTPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) |
| 62764 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTPv4f16, |
| 62765 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62766 | // GIR_Coverage, 764, |
| 62767 | GIR_Done, |
| 62768 | // Label 3556: @160592 |
| 62769 | GIM_Reject, |
| 62770 | // Label 3548: @160593 |
| 62771 | GIM_Try, /*On fail goto*//*Label 3557*/ 160616, // Rule ID 767 // |
| 62772 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 62773 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 62774 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 62775 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 62776 | // (fceil:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FRINTPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) |
| 62777 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTPv4f32, |
| 62778 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62779 | // GIR_Coverage, 767, |
| 62780 | GIR_Done, |
| 62781 | // Label 3557: @160616 |
| 62782 | GIM_Reject, |
| 62783 | // Label 3549: @160617 |
| 62784 | GIM_Try, /*On fail goto*//*Label 3558*/ 160640, // Rule ID 765 // |
| 62785 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 62786 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 62787 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 62788 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 62789 | // (fceil:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FRINTPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) |
| 62790 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTPv8f16, |
| 62791 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62792 | // GIR_Coverage, 765, |
| 62793 | GIR_Done, |
| 62794 | // Label 3558: @160640 |
| 62795 | GIM_Reject, |
| 62796 | // Label 3550: @160641 |
| 62797 | GIM_Reject, |
| 62798 | // Label 75: @160642 |
| 62799 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 3567*/ 160850, |
| 62800 | /*GILLT_s16*//*Label 3559*/ 160658, |
| 62801 | /*GILLT_s32*//*Label 3560*/ 160682, |
| 62802 | /*GILLT_s64*//*Label 3561*/ 160706, 0, |
| 62803 | /*GILLT_v2s32*//*Label 3562*/ 160730, |
| 62804 | /*GILLT_v2s64*//*Label 3563*/ 160754, |
| 62805 | /*GILLT_v4s16*//*Label 3564*/ 160778, |
| 62806 | /*GILLT_v4s32*//*Label 3565*/ 160802, 0, |
| 62807 | /*GILLT_v8s16*//*Label 3566*/ 160826, |
| 62808 | // Label 3559: @160658 |
| 62809 | GIM_Try, /*On fail goto*//*Label 3568*/ 160681, // Rule ID 513 // |
| 62810 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 62811 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 62812 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 62813 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 62814 | // (fsqrt:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FSQRTHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) |
| 62815 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTHr, |
| 62816 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62817 | // GIR_Coverage, 513, |
| 62818 | GIR_Done, |
| 62819 | // Label 3568: @160681 |
| 62820 | GIM_Reject, |
| 62821 | // Label 3560: @160682 |
| 62822 | GIM_Try, /*On fail goto*//*Label 3569*/ 160705, // Rule ID 514 // |
| 62823 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 62824 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 62825 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 62826 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 62827 | // (fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FSQRTSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) |
| 62828 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTSr, |
| 62829 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62830 | // GIR_Coverage, 514, |
| 62831 | GIR_Done, |
| 62832 | // Label 3569: @160705 |
| 62833 | GIM_Reject, |
| 62834 | // Label 3561: @160706 |
| 62835 | GIM_Try, /*On fail goto*//*Label 3570*/ 160729, // Rule ID 515 // |
| 62836 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 62837 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 62838 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 62839 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 62840 | // (fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FSQRTDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) |
| 62841 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTDr, |
| 62842 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62843 | // GIR_Coverage, 515, |
| 62844 | GIR_Done, |
| 62845 | // Label 3570: @160729 |
| 62846 | GIM_Reject, |
| 62847 | // Label 3562: @160730 |
| 62848 | GIM_Try, /*On fail goto*//*Label 3571*/ 160753, // Rule ID 786 // |
| 62849 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 62850 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 62851 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 62852 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 62853 | // (fsqrt:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FSQRTv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) |
| 62854 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTv2f32, |
| 62855 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62856 | // GIR_Coverage, 786, |
| 62857 | GIR_Done, |
| 62858 | // Label 3571: @160753 |
| 62859 | GIM_Reject, |
| 62860 | // Label 3563: @160754 |
| 62861 | GIM_Try, /*On fail goto*//*Label 3572*/ 160777, // Rule ID 788 // |
| 62862 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 62863 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 62864 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 62865 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 62866 | // (fsqrt:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FSQRTv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) |
| 62867 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTv2f64, |
| 62868 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62869 | // GIR_Coverage, 788, |
| 62870 | GIR_Done, |
| 62871 | // Label 3572: @160777 |
| 62872 | GIM_Reject, |
| 62873 | // Label 3564: @160778 |
| 62874 | GIM_Try, /*On fail goto*//*Label 3573*/ 160801, // Rule ID 784 // |
| 62875 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 62876 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 62877 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 62878 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 62879 | // (fsqrt:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FSQRTv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) |
| 62880 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTv4f16, |
| 62881 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62882 | // GIR_Coverage, 784, |
| 62883 | GIR_Done, |
| 62884 | // Label 3573: @160801 |
| 62885 | GIM_Reject, |
| 62886 | // Label 3565: @160802 |
| 62887 | GIM_Try, /*On fail goto*//*Label 3574*/ 160825, // Rule ID 787 // |
| 62888 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 62889 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 62890 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 62891 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 62892 | // (fsqrt:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FSQRTv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) |
| 62893 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTv4f32, |
| 62894 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62895 | // GIR_Coverage, 787, |
| 62896 | GIR_Done, |
| 62897 | // Label 3574: @160825 |
| 62898 | GIM_Reject, |
| 62899 | // Label 3566: @160826 |
| 62900 | GIM_Try, /*On fail goto*//*Label 3575*/ 160849, // Rule ID 785 // |
| 62901 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 62902 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 62903 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 62904 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 62905 | // (fsqrt:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FSQRTv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) |
| 62906 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FSQRTv8f16, |
| 62907 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62908 | // GIR_Coverage, 785, |
| 62909 | GIR_Done, |
| 62910 | // Label 3575: @160849 |
| 62911 | GIM_Reject, |
| 62912 | // Label 3567: @160850 |
| 62913 | GIM_Reject, |
| 62914 | // Label 76: @160851 |
| 62915 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 3584*/ 161059, |
| 62916 | /*GILLT_s16*//*Label 3576*/ 160867, |
| 62917 | /*GILLT_s32*//*Label 3577*/ 160891, |
| 62918 | /*GILLT_s64*//*Label 3578*/ 160915, 0, |
| 62919 | /*GILLT_v2s32*//*Label 3579*/ 160939, |
| 62920 | /*GILLT_v2s64*//*Label 3580*/ 160963, |
| 62921 | /*GILLT_v4s16*//*Label 3581*/ 160987, |
| 62922 | /*GILLT_v4s32*//*Label 3582*/ 161011, 0, |
| 62923 | /*GILLT_v8s16*//*Label 3583*/ 161035, |
| 62924 | // Label 3576: @160867 |
| 62925 | GIM_Try, /*On fail goto*//*Label 3585*/ 160890, // Rule ID 498 // |
| 62926 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 62927 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 62928 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 62929 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 62930 | // (ffloor:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FRINTMHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) |
| 62931 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTMHr, |
| 62932 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62933 | // GIR_Coverage, 498, |
| 62934 | GIR_Done, |
| 62935 | // Label 3585: @160890 |
| 62936 | GIM_Reject, |
| 62937 | // Label 3577: @160891 |
| 62938 | GIM_Try, /*On fail goto*//*Label 3586*/ 160914, // Rule ID 499 // |
| 62939 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 62940 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 62941 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 62942 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 62943 | // (ffloor:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FRINTMSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) |
| 62944 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTMSr, |
| 62945 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62946 | // GIR_Coverage, 499, |
| 62947 | GIR_Done, |
| 62948 | // Label 3586: @160914 |
| 62949 | GIM_Reject, |
| 62950 | // Label 3578: @160915 |
| 62951 | GIM_Try, /*On fail goto*//*Label 3587*/ 160938, // Rule ID 500 // |
| 62952 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 62953 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 62954 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 62955 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 62956 | // (ffloor:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FRINTMDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) |
| 62957 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTMDr, |
| 62958 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62959 | // GIR_Coverage, 500, |
| 62960 | GIR_Done, |
| 62961 | // Label 3587: @160938 |
| 62962 | GIM_Reject, |
| 62963 | // Label 3579: @160939 |
| 62964 | GIM_Try, /*On fail goto*//*Label 3588*/ 160962, // Rule ID 756 // |
| 62965 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 62966 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 62967 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 62968 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 62969 | // (ffloor:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FRINTMv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) |
| 62970 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTMv2f32, |
| 62971 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62972 | // GIR_Coverage, 756, |
| 62973 | GIR_Done, |
| 62974 | // Label 3588: @160962 |
| 62975 | GIM_Reject, |
| 62976 | // Label 3580: @160963 |
| 62977 | GIM_Try, /*On fail goto*//*Label 3589*/ 160986, // Rule ID 758 // |
| 62978 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 62979 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 62980 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 62981 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 62982 | // (ffloor:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FRINTMv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) |
| 62983 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTMv2f64, |
| 62984 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62985 | // GIR_Coverage, 758, |
| 62986 | GIR_Done, |
| 62987 | // Label 3589: @160986 |
| 62988 | GIM_Reject, |
| 62989 | // Label 3581: @160987 |
| 62990 | GIM_Try, /*On fail goto*//*Label 3590*/ 161010, // Rule ID 754 // |
| 62991 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 62992 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 62993 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 62994 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 62995 | // (ffloor:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FRINTMv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) |
| 62996 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTMv4f16, |
| 62997 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 62998 | // GIR_Coverage, 754, |
| 62999 | GIR_Done, |
| 63000 | // Label 3590: @161010 |
| 63001 | GIM_Reject, |
| 63002 | // Label 3582: @161011 |
| 63003 | GIM_Try, /*On fail goto*//*Label 3591*/ 161034, // Rule ID 757 // |
| 63004 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 63005 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 63006 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 63007 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 63008 | // (ffloor:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FRINTMv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) |
| 63009 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTMv4f32, |
| 63010 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63011 | // GIR_Coverage, 757, |
| 63012 | GIR_Done, |
| 63013 | // Label 3591: @161034 |
| 63014 | GIM_Reject, |
| 63015 | // Label 3583: @161035 |
| 63016 | GIM_Try, /*On fail goto*//*Label 3592*/ 161058, // Rule ID 755 // |
| 63017 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 63018 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 63019 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 63020 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 63021 | // (ffloor:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FRINTMv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) |
| 63022 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTMv8f16, |
| 63023 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63024 | // GIR_Coverage, 755, |
| 63025 | GIR_Done, |
| 63026 | // Label 3592: @161058 |
| 63027 | GIM_Reject, |
| 63028 | // Label 3584: @161059 |
| 63029 | GIM_Reject, |
| 63030 | // Label 77: @161060 |
| 63031 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 3601*/ 161268, |
| 63032 | /*GILLT_s16*//*Label 3593*/ 161076, |
| 63033 | /*GILLT_s32*//*Label 3594*/ 161100, |
| 63034 | /*GILLT_s64*//*Label 3595*/ 161124, 0, |
| 63035 | /*GILLT_v2s32*//*Label 3596*/ 161148, |
| 63036 | /*GILLT_v2s64*//*Label 3597*/ 161172, |
| 63037 | /*GILLT_v4s16*//*Label 3598*/ 161196, |
| 63038 | /*GILLT_v4s32*//*Label 3599*/ 161220, 0, |
| 63039 | /*GILLT_v8s16*//*Label 3600*/ 161244, |
| 63040 | // Label 3593: @161076 |
| 63041 | GIM_Try, /*On fail goto*//*Label 3602*/ 161099, // Rule ID 507 // |
| 63042 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 63043 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 63044 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 63045 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 63046 | // (frint:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FRINTXHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) |
| 63047 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTXHr, |
| 63048 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63049 | // GIR_Coverage, 507, |
| 63050 | GIR_Done, |
| 63051 | // Label 3602: @161099 |
| 63052 | GIM_Reject, |
| 63053 | // Label 3594: @161100 |
| 63054 | GIM_Try, /*On fail goto*//*Label 3603*/ 161123, // Rule ID 508 // |
| 63055 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 63056 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 63057 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 63058 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 63059 | // (frint:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FRINTXSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) |
| 63060 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTXSr, |
| 63061 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63062 | // GIR_Coverage, 508, |
| 63063 | GIR_Done, |
| 63064 | // Label 3603: @161123 |
| 63065 | GIM_Reject, |
| 63066 | // Label 3595: @161124 |
| 63067 | GIM_Try, /*On fail goto*//*Label 3604*/ 161147, // Rule ID 509 // |
| 63068 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 63069 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 63070 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 63071 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 63072 | // (frint:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FRINTXDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) |
| 63073 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTXDr, |
| 63074 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63075 | // GIR_Coverage, 509, |
| 63076 | GIR_Done, |
| 63077 | // Label 3604: @161147 |
| 63078 | GIM_Reject, |
| 63079 | // Label 3596: @161148 |
| 63080 | GIM_Try, /*On fail goto*//*Label 3605*/ 161171, // Rule ID 771 // |
| 63081 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 63082 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 63083 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 63084 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 63085 | // (frint:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FRINTXv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) |
| 63086 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTXv2f32, |
| 63087 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63088 | // GIR_Coverage, 771, |
| 63089 | GIR_Done, |
| 63090 | // Label 3605: @161171 |
| 63091 | GIM_Reject, |
| 63092 | // Label 3597: @161172 |
| 63093 | GIM_Try, /*On fail goto*//*Label 3606*/ 161195, // Rule ID 773 // |
| 63094 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 63095 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 63096 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 63097 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 63098 | // (frint:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FRINTXv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) |
| 63099 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTXv2f64, |
| 63100 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63101 | // GIR_Coverage, 773, |
| 63102 | GIR_Done, |
| 63103 | // Label 3606: @161195 |
| 63104 | GIM_Reject, |
| 63105 | // Label 3598: @161196 |
| 63106 | GIM_Try, /*On fail goto*//*Label 3607*/ 161219, // Rule ID 769 // |
| 63107 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 63108 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 63109 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 63110 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 63111 | // (frint:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FRINTXv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) |
| 63112 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTXv4f16, |
| 63113 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63114 | // GIR_Coverage, 769, |
| 63115 | GIR_Done, |
| 63116 | // Label 3607: @161219 |
| 63117 | GIM_Reject, |
| 63118 | // Label 3599: @161220 |
| 63119 | GIM_Try, /*On fail goto*//*Label 3608*/ 161243, // Rule ID 772 // |
| 63120 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 63121 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 63122 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 63123 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 63124 | // (frint:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FRINTXv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) |
| 63125 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTXv4f32, |
| 63126 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63127 | // GIR_Coverage, 772, |
| 63128 | GIR_Done, |
| 63129 | // Label 3608: @161243 |
| 63130 | GIM_Reject, |
| 63131 | // Label 3600: @161244 |
| 63132 | GIM_Try, /*On fail goto*//*Label 3609*/ 161267, // Rule ID 770 // |
| 63133 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 63134 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 63135 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 63136 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 63137 | // (frint:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FRINTXv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) |
| 63138 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTXv8f16, |
| 63139 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63140 | // GIR_Coverage, 770, |
| 63141 | GIR_Done, |
| 63142 | // Label 3609: @161267 |
| 63143 | GIM_Reject, |
| 63144 | // Label 3601: @161268 |
| 63145 | GIM_Reject, |
| 63146 | // Label 78: @161269 |
| 63147 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 10, /*)*//*default:*//*Label 3618*/ 161477, |
| 63148 | /*GILLT_s16*//*Label 3610*/ 161285, |
| 63149 | /*GILLT_s32*//*Label 3611*/ 161309, |
| 63150 | /*GILLT_s64*//*Label 3612*/ 161333, 0, |
| 63151 | /*GILLT_v2s32*//*Label 3613*/ 161357, |
| 63152 | /*GILLT_v2s64*//*Label 3614*/ 161381, |
| 63153 | /*GILLT_v4s16*//*Label 3615*/ 161405, |
| 63154 | /*GILLT_v4s32*//*Label 3616*/ 161429, 0, |
| 63155 | /*GILLT_v8s16*//*Label 3617*/ 161453, |
| 63156 | // Label 3610: @161285 |
| 63157 | GIM_Try, /*On fail goto*//*Label 3619*/ 161308, // Rule ID 495 // |
| 63158 | GIM_CheckFeatures, GIFBS_HasFullFP16, |
| 63159 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 63160 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 63161 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 63162 | // (fnearbyint:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FRINTIHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) |
| 63163 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTIHr, |
| 63164 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63165 | // GIR_Coverage, 495, |
| 63166 | GIR_Done, |
| 63167 | // Label 3619: @161308 |
| 63168 | GIM_Reject, |
| 63169 | // Label 3611: @161309 |
| 63170 | GIM_Try, /*On fail goto*//*Label 3620*/ 161332, // Rule ID 496 // |
| 63171 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 63172 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 63173 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 63174 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 63175 | // (fnearbyint:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FRINTISr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) |
| 63176 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTISr, |
| 63177 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63178 | // GIR_Coverage, 496, |
| 63179 | GIR_Done, |
| 63180 | // Label 3620: @161332 |
| 63181 | GIM_Reject, |
| 63182 | // Label 3612: @161333 |
| 63183 | GIM_Try, /*On fail goto*//*Label 3621*/ 161356, // Rule ID 497 // |
| 63184 | GIM_CheckFeatures, GIFBS_HasFPARMv8, |
| 63185 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 63186 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 63187 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 63188 | // (fnearbyint:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FRINTIDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) |
| 63189 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTIDr, |
| 63190 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63191 | // GIR_Coverage, 497, |
| 63192 | GIR_Done, |
| 63193 | // Label 3621: @161356 |
| 63194 | GIM_Reject, |
| 63195 | // Label 3613: @161357 |
| 63196 | GIM_Try, /*On fail goto*//*Label 3622*/ 161380, // Rule ID 751 // |
| 63197 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 63198 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 63199 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 63200 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 63201 | // (fnearbyint:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FRINTIv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) |
| 63202 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTIv2f32, |
| 63203 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63204 | // GIR_Coverage, 751, |
| 63205 | GIR_Done, |
| 63206 | // Label 3622: @161380 |
| 63207 | GIM_Reject, |
| 63208 | // Label 3614: @161381 |
| 63209 | GIM_Try, /*On fail goto*//*Label 3623*/ 161404, // Rule ID 753 // |
| 63210 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 63211 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 63212 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 63213 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 63214 | // (fnearbyint:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FRINTIv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) |
| 63215 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTIv2f64, |
| 63216 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63217 | // GIR_Coverage, 753, |
| 63218 | GIR_Done, |
| 63219 | // Label 3623: @161404 |
| 63220 | GIM_Reject, |
| 63221 | // Label 3615: @161405 |
| 63222 | GIM_Try, /*On fail goto*//*Label 3624*/ 161428, // Rule ID 749 // |
| 63223 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 63224 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 63225 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 63226 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 63227 | // (fnearbyint:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FRINTIv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) |
| 63228 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTIv4f16, |
| 63229 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63230 | // GIR_Coverage, 749, |
| 63231 | GIR_Done, |
| 63232 | // Label 3624: @161428 |
| 63233 | GIM_Reject, |
| 63234 | // Label 3616: @161429 |
| 63235 | GIM_Try, /*On fail goto*//*Label 3625*/ 161452, // Rule ID 752 // |
| 63236 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 63237 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 63238 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 63239 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 63240 | // (fnearbyint:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FRINTIv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) |
| 63241 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTIv4f32, |
| 63242 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63243 | // GIR_Coverage, 752, |
| 63244 | GIR_Done, |
| 63245 | // Label 3625: @161452 |
| 63246 | GIM_Reject, |
| 63247 | // Label 3617: @161453 |
| 63248 | GIM_Try, /*On fail goto*//*Label 3626*/ 161476, // Rule ID 750 // |
| 63249 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 63250 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 63251 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 63252 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 63253 | // (fnearbyint:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FRINTIv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) |
| 63254 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::FRINTIv8f16, |
| 63255 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63256 | // GIR_Coverage, 750, |
| 63257 | GIR_Done, |
| 63258 | // Label 3626: @161476 |
| 63259 | GIM_Reject, |
| 63260 | // Label 3618: @161477 |
| 63261 | GIM_Reject, |
| 63262 | // Label 79: @161478 |
| 63263 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 11, /*)*//*default:*//*Label 3635*/ 163056, |
| 63264 | /*GILLT_s64*//*Label 3627*/ 161493, 0, |
| 63265 | /*GILLT_v2s32*//*Label 3628*/ 161629, |
| 63266 | /*GILLT_v2s64*//*Label 3629*/ 161820, |
| 63267 | /*GILLT_v4s16*//*Label 3630*/ 162011, |
| 63268 | /*GILLT_v4s32*//*Label 3631*/ 162360, |
| 63269 | /*GILLT_v8s8*//*Label 3632*/ 162551, |
| 63270 | /*GILLT_v8s16*//*Label 3633*/ 162629, |
| 63271 | /*GILLT_v16s8*//*Label 3634*/ 162978, |
| 63272 | // Label 3627: @161493 |
| 63273 | GIM_Try, /*On fail goto*//*Label 3636*/ 161628, |
| 63274 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 63275 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 63276 | GIM_Try, /*On fail goto*//*Label 3637*/ 161550, // Rule ID 4823 // |
| 63277 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 63278 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, |
| 63279 | GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, |
| 63280 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 63281 | // MIs[1] Rn |
| 63282 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, |
| 63283 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 63284 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 63285 | // (AArch64dup:{ *:[v1i64] } (ld:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv1d:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn) |
| 63286 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv1d, |
| 63287 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt |
| 63288 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 63289 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 63290 | GIR_EraseFromParent, /*InsnID*/0, |
| 63291 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63292 | // GIR_Coverage, 4823, |
| 63293 | GIR_Done, |
| 63294 | // Label 3637: @161550 |
| 63295 | GIM_Try, /*On fail goto*//*Label 3638*/ 161597, // Rule ID 4827 // |
| 63296 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 63297 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, |
| 63298 | GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, |
| 63299 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 63300 | // MIs[1] Rn |
| 63301 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, |
| 63302 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 63303 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 63304 | // (AArch64dup:{ *:[v1f64] } (ld:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv1d:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn) |
| 63305 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv1d, |
| 63306 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt |
| 63307 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 63308 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 63309 | GIR_EraseFromParent, /*InsnID*/0, |
| 63310 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63311 | // GIR_Coverage, 4827, |
| 63312 | GIR_Done, |
| 63313 | // Label 3638: @161597 |
| 63314 | GIM_Try, /*On fail goto*//*Label 3639*/ 161612, // Rule ID 4355 // |
| 63315 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 63316 | // (AArch64dup:{ *:[v1i64] } GPR64:{ *:[i64] }:$Rn) => (COPY_TO_REGCLASS:{ *:[v1i64] } GPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i32] }) |
| 63317 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 63318 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 63319 | // GIR_Coverage, 4355, |
| 63320 | GIR_Done, |
| 63321 | // Label 3639: @161612 |
| 63322 | GIM_Try, /*On fail goto*//*Label 3640*/ 161627, // Rule ID 4356 // |
| 63323 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 63324 | // (AArch64dup:{ *:[v1f64] } FPR64:{ *:[f64] }:$Rn) => (COPY_TO_REGCLASS:{ *:[v1f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[i32] }) |
| 63325 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 63326 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, AArch64::FPR64RegClassID, |
| 63327 | // GIR_Coverage, 4356, |
| 63328 | GIR_Done, |
| 63329 | // Label 3640: @161627 |
| 63330 | GIM_Reject, |
| 63331 | // Label 3636: @161628 |
| 63332 | GIM_Reject, |
| 63333 | // Label 3628: @161629 |
| 63334 | GIM_Try, /*On fail goto*//*Label 3641*/ 161819, |
| 63335 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 63336 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 63337 | GIM_Try, /*On fail goto*//*Label 3642*/ 161686, // Rule ID 4820 // |
| 63338 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 63339 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, |
| 63340 | GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, |
| 63341 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 63342 | // MIs[1] Rn |
| 63343 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, |
| 63344 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 63345 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 63346 | // (AArch64dup:{ *:[v2i32] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv2s:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn) |
| 63347 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv2s, |
| 63348 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt |
| 63349 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 63350 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 63351 | GIR_EraseFromParent, /*InsnID*/0, |
| 63352 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63353 | // GIR_Coverage, 4820, |
| 63354 | GIR_Done, |
| 63355 | // Label 3642: @161686 |
| 63356 | GIM_Try, /*On fail goto*//*Label 3643*/ 161733, // Rule ID 4824 // |
| 63357 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 63358 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, |
| 63359 | GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, |
| 63360 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 63361 | // MIs[1] Rn |
| 63362 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, |
| 63363 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 63364 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 63365 | // (AArch64dup:{ *:[v2f32] } (ld:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv2s:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn) |
| 63366 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv2s, |
| 63367 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt |
| 63368 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 63369 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 63370 | GIR_EraseFromParent, /*InsnID*/0, |
| 63371 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63372 | // GIR_Coverage, 4824, |
| 63373 | GIR_Done, |
| 63374 | // Label 3643: @161733 |
| 63375 | GIM_Try, /*On fail goto*//*Label 3644*/ 161748, // Rule ID 1633 // |
| 63376 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 63377 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 63378 | // (AArch64dup:{ *:[v2i32] } GPR32:{ *:[i32] }:$Rn) => (DUPv2i32gpr:{ *:[v2i32] } GPR32:{ *:[i32] }:$Rn) |
| 63379 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::DUPv2i32gpr, |
| 63380 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63381 | // GIR_Coverage, 1633, |
| 63382 | GIR_Done, |
| 63383 | // Label 3644: @161748 |
| 63384 | GIM_Try, /*On fail goto*//*Label 3645*/ 161818, // Rule ID 4357 // |
| 63385 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 63386 | // (AArch64dup:{ *:[v2f32] } FPR32:{ *:[f32] }:$Rn) => (DUPv2i32lane:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rn, ssub:{ *:[i32] }), 0:{ *:[i64] }) |
| 63387 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 63388 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 63389 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 63390 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 63391 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 63392 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 63393 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 63394 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 63395 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 63396 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 63397 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 63398 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 63399 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 63400 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv2i32lane, |
| 63401 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 63402 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 63403 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 63404 | GIR_EraseFromParent, /*InsnID*/0, |
| 63405 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63406 | // GIR_Coverage, 4357, |
| 63407 | GIR_Done, |
| 63408 | // Label 3645: @161818 |
| 63409 | GIM_Reject, |
| 63410 | // Label 3641: @161819 |
| 63411 | GIM_Reject, |
| 63412 | // Label 3629: @161820 |
| 63413 | GIM_Try, /*On fail goto*//*Label 3646*/ 162010, |
| 63414 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 63415 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 63416 | GIM_Try, /*On fail goto*//*Label 3647*/ 161877, // Rule ID 4822 // |
| 63417 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 63418 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, |
| 63419 | GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, |
| 63420 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 63421 | // MIs[1] Rn |
| 63422 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, |
| 63423 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 63424 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 63425 | // (AArch64dup:{ *:[v2i64] } (ld:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv2d:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn) |
| 63426 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv2d, |
| 63427 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt |
| 63428 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 63429 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 63430 | GIR_EraseFromParent, /*InsnID*/0, |
| 63431 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63432 | // GIR_Coverage, 4822, |
| 63433 | GIR_Done, |
| 63434 | // Label 3647: @161877 |
| 63435 | GIM_Try, /*On fail goto*//*Label 3648*/ 161924, // Rule ID 4826 // |
| 63436 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 63437 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, |
| 63438 | GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, |
| 63439 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 63440 | // MIs[1] Rn |
| 63441 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, |
| 63442 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 63443 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 63444 | // (AArch64dup:{ *:[v2f64] } (ld:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv2d:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn) |
| 63445 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv2d, |
| 63446 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt |
| 63447 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 63448 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 63449 | GIR_EraseFromParent, /*InsnID*/0, |
| 63450 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63451 | // GIR_Coverage, 4826, |
| 63452 | GIR_Done, |
| 63453 | // Label 3648: @161924 |
| 63454 | GIM_Try, /*On fail goto*//*Label 3649*/ 161939, // Rule ID 1635 // |
| 63455 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 63456 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR64RegClassID, |
| 63457 | // (AArch64dup:{ *:[v2i64] } GPR64:{ *:[i64] }:$Rn) => (DUPv2i64gpr:{ *:[v2i64] } GPR64:{ *:[i64] }:$Rn) |
| 63458 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::DUPv2i64gpr, |
| 63459 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63460 | // GIR_Coverage, 1635, |
| 63461 | GIR_Done, |
| 63462 | // Label 3649: @161939 |
| 63463 | GIM_Try, /*On fail goto*//*Label 3650*/ 162009, // Rule ID 4359 // |
| 63464 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 63465 | // (AArch64dup:{ *:[v2f64] } FPR64:{ *:[f64] }:$Rn) => (DUPv2i64lane:{ *:[v2f64] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR64:{ *:[f64] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 63466 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 63467 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 63468 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 63469 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 63470 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 63471 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 63472 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 63473 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 63474 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 63475 | GIR_AddImm, /*InsnID*/1, /*Imm*/2, |
| 63476 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 63477 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 63478 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR64RegClassID, |
| 63479 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv2i64lane, |
| 63480 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 63481 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 63482 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 63483 | GIR_EraseFromParent, /*InsnID*/0, |
| 63484 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63485 | // GIR_Coverage, 4359, |
| 63486 | GIR_Done, |
| 63487 | // Label 3650: @162009 |
| 63488 | GIM_Reject, |
| 63489 | // Label 3646: @162010 |
| 63490 | GIM_Reject, |
| 63491 | // Label 3630: @162011 |
| 63492 | GIM_Try, /*On fail goto*//*Label 3651*/ 162066, // Rule ID 4828 // |
| 63493 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 63494 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 63495 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 63496 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, |
| 63497 | GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, |
| 63498 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 63499 | // MIs[1] Rn |
| 63500 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, |
| 63501 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 63502 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 63503 | // (AArch64dup:{ *:[v4f16] } (ld:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv4h:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn) |
| 63504 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv4h, |
| 63505 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt |
| 63506 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 63507 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 63508 | GIR_EraseFromParent, /*InsnID*/0, |
| 63509 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63510 | // GIR_Coverage, 4828, |
| 63511 | GIR_Done, |
| 63512 | // Label 3651: @162066 |
| 63513 | GIM_Try, /*On fail goto*//*Label 3652*/ 162121, // Rule ID 4830 // |
| 63514 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 63515 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 63516 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 63517 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, |
| 63518 | GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, |
| 63519 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 63520 | // MIs[1] Rn |
| 63521 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, |
| 63522 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 63523 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 63524 | // (AArch64dup:{ *:[v4bf16] } (ld:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv4h:{ *:[v4bf16] } GPR64sp:{ *:[i64] }:$Rn) |
| 63525 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv4h, |
| 63526 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt |
| 63527 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 63528 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 63529 | GIR_EraseFromParent, /*InsnID*/0, |
| 63530 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63531 | // GIR_Coverage, 4830, |
| 63532 | GIR_Done, |
| 63533 | // Label 3652: @162121 |
| 63534 | GIM_Try, /*On fail goto*//*Label 3653*/ 162180, // Rule ID 4818 // |
| 63535 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 63536 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 63537 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 63538 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, |
| 63539 | GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, |
| 63540 | GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, |
| 63541 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 63542 | // MIs[1] Rn |
| 63543 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, |
| 63544 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 63545 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 63546 | // (AArch64dup:{ *:[v4i16] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>) => (LD1Rv4h:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn) |
| 63547 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv4h, |
| 63548 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt |
| 63549 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 63550 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 63551 | GIR_EraseFromParent, /*InsnID*/0, |
| 63552 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63553 | // GIR_Coverage, 4818, |
| 63554 | GIR_Done, |
| 63555 | // Label 3653: @162180 |
| 63556 | GIM_Try, /*On fail goto*//*Label 3654*/ 162203, // Rule ID 1631 // |
| 63557 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 63558 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 63559 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 63560 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 63561 | // (AArch64dup:{ *:[v4i16] } GPR32:{ *:[i32] }:$Rn) => (DUPv4i16gpr:{ *:[v4i16] } GPR32:{ *:[i32] }:$Rn) |
| 63562 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::DUPv4i16gpr, |
| 63563 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63564 | // GIR_Coverage, 1631, |
| 63565 | GIR_Done, |
| 63566 | // Label 3654: @162203 |
| 63567 | GIM_Try, /*On fail goto*//*Label 3655*/ 162281, // Rule ID 4360 // |
| 63568 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 63569 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 63570 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 63571 | // (AArch64dup:{ *:[v4f16] } FPR16:{ *:[f16] }:$Rn) => (DUPv4i16lane:{ *:[v4f16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), FPR16:{ *:[f16] }:$Rn, hsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 63572 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 63573 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 63574 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 63575 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 63576 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 63577 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 63578 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 63579 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 63580 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 63581 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 63582 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 63583 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 63584 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, |
| 63585 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv4i16lane, |
| 63586 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 63587 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 63588 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 63589 | GIR_EraseFromParent, /*InsnID*/0, |
| 63590 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63591 | // GIR_Coverage, 4360, |
| 63592 | GIR_Done, |
| 63593 | // Label 3655: @162281 |
| 63594 | GIM_Try, /*On fail goto*//*Label 3656*/ 162359, // Rule ID 4361 // |
| 63595 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 63596 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 63597 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 63598 | // (AArch64dup:{ *:[v4bf16] } FPR16:{ *:[bf16] }:$Rn) => (DUPv4i16lane:{ *:[v4bf16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), FPR16:{ *:[bf16] }:$Rn, hsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 63599 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 63600 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 63601 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 63602 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 63603 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 63604 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 63605 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 63606 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 63607 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 63608 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 63609 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 63610 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 63611 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, |
| 63612 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv4i16lane, |
| 63613 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 63614 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 63615 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 63616 | GIR_EraseFromParent, /*InsnID*/0, |
| 63617 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63618 | // GIR_Coverage, 4361, |
| 63619 | GIR_Done, |
| 63620 | // Label 3656: @162359 |
| 63621 | GIM_Reject, |
| 63622 | // Label 3631: @162360 |
| 63623 | GIM_Try, /*On fail goto*//*Label 3657*/ 162550, |
| 63624 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 63625 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 63626 | GIM_Try, /*On fail goto*//*Label 3658*/ 162417, // Rule ID 4821 // |
| 63627 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 63628 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, |
| 63629 | GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, |
| 63630 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 63631 | // MIs[1] Rn |
| 63632 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, |
| 63633 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 63634 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 63635 | // (AArch64dup:{ *:[v4i32] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv4s:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn) |
| 63636 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv4s, |
| 63637 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt |
| 63638 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 63639 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 63640 | GIR_EraseFromParent, /*InsnID*/0, |
| 63641 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63642 | // GIR_Coverage, 4821, |
| 63643 | GIR_Done, |
| 63644 | // Label 3658: @162417 |
| 63645 | GIM_Try, /*On fail goto*//*Label 3659*/ 162464, // Rule ID 4825 // |
| 63646 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 63647 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, |
| 63648 | GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, |
| 63649 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 63650 | // MIs[1] Rn |
| 63651 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, |
| 63652 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 63653 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 63654 | // (AArch64dup:{ *:[v4f32] } (ld:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv4s:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn) |
| 63655 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv4s, |
| 63656 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt |
| 63657 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 63658 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 63659 | GIR_EraseFromParent, /*InsnID*/0, |
| 63660 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63661 | // GIR_Coverage, 4825, |
| 63662 | GIR_Done, |
| 63663 | // Label 3659: @162464 |
| 63664 | GIM_Try, /*On fail goto*//*Label 3660*/ 162479, // Rule ID 1634 // |
| 63665 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 63666 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 63667 | // (AArch64dup:{ *:[v4i32] } GPR32:{ *:[i32] }:$Rn) => (DUPv4i32gpr:{ *:[v4i32] } GPR32:{ *:[i32] }:$Rn) |
| 63668 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::DUPv4i32gpr, |
| 63669 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63670 | // GIR_Coverage, 1634, |
| 63671 | GIR_Done, |
| 63672 | // Label 3660: @162479 |
| 63673 | GIM_Try, /*On fail goto*//*Label 3661*/ 162549, // Rule ID 4358 // |
| 63674 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 63675 | // (AArch64dup:{ *:[v4f32] } FPR32:{ *:[f32] }:$Rn) => (DUPv4i32lane:{ *:[v4f32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rn, ssub:{ *:[i32] }), 0:{ *:[i64] }) |
| 63676 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 63677 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 63678 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 63679 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 63680 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 63681 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 63682 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 63683 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 63684 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 63685 | GIR_AddImm, /*InsnID*/1, /*Imm*/14, |
| 63686 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 63687 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 63688 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR32RegClassID, |
| 63689 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv4i32lane, |
| 63690 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 63691 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 63692 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 63693 | GIR_EraseFromParent, /*InsnID*/0, |
| 63694 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63695 | // GIR_Coverage, 4358, |
| 63696 | GIR_Done, |
| 63697 | // Label 3661: @162549 |
| 63698 | GIM_Reject, |
| 63699 | // Label 3657: @162550 |
| 63700 | GIM_Reject, |
| 63701 | // Label 3632: @162551 |
| 63702 | GIM_Try, /*On fail goto*//*Label 3662*/ 162628, |
| 63703 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 63704 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 63705 | GIM_Try, /*On fail goto*//*Label 3663*/ 162612, // Rule ID 4816 // |
| 63706 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 63707 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, |
| 63708 | GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, |
| 63709 | GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/1, |
| 63710 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 63711 | // MIs[1] Rn |
| 63712 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, |
| 63713 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 63714 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 63715 | // (AArch64dup:{ *:[v8i8] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>) => (LD1Rv8b:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn) |
| 63716 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv8b, |
| 63717 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt |
| 63718 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 63719 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 63720 | GIR_EraseFromParent, /*InsnID*/0, |
| 63721 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63722 | // GIR_Coverage, 4816, |
| 63723 | GIR_Done, |
| 63724 | // Label 3663: @162612 |
| 63725 | GIM_Try, /*On fail goto*//*Label 3664*/ 162627, // Rule ID 1629 // |
| 63726 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 63727 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 63728 | // (AArch64dup:{ *:[v8i8] } GPR32:{ *:[i32] }:$Rn) => (DUPv8i8gpr:{ *:[v8i8] } GPR32:{ *:[i32] }:$Rn) |
| 63729 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::DUPv8i8gpr, |
| 63730 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63731 | // GIR_Coverage, 1629, |
| 63732 | GIR_Done, |
| 63733 | // Label 3664: @162627 |
| 63734 | GIM_Reject, |
| 63735 | // Label 3662: @162628 |
| 63736 | GIM_Reject, |
| 63737 | // Label 3633: @162629 |
| 63738 | GIM_Try, /*On fail goto*//*Label 3665*/ 162684, // Rule ID 4829 // |
| 63739 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 63740 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 63741 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 63742 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, |
| 63743 | GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, |
| 63744 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 63745 | // MIs[1] Rn |
| 63746 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, |
| 63747 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 63748 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 63749 | // (AArch64dup:{ *:[v8f16] } (ld:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv8h:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn) |
| 63750 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv8h, |
| 63751 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt |
| 63752 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 63753 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 63754 | GIR_EraseFromParent, /*InsnID*/0, |
| 63755 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63756 | // GIR_Coverage, 4829, |
| 63757 | GIR_Done, |
| 63758 | // Label 3665: @162684 |
| 63759 | GIM_Try, /*On fail goto*//*Label 3666*/ 162739, // Rule ID 4831 // |
| 63760 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 63761 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 63762 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 63763 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, |
| 63764 | GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, |
| 63765 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 63766 | // MIs[1] Rn |
| 63767 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, |
| 63768 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 63769 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 63770 | // (AArch64dup:{ *:[v8bf16] } (ld:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv8h:{ *:[v8bf16] } GPR64sp:{ *:[i64] }:$Rn) |
| 63771 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv8h, |
| 63772 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt |
| 63773 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 63774 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 63775 | GIR_EraseFromParent, /*InsnID*/0, |
| 63776 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63777 | // GIR_Coverage, 4831, |
| 63778 | GIR_Done, |
| 63779 | // Label 3666: @162739 |
| 63780 | GIM_Try, /*On fail goto*//*Label 3667*/ 162798, // Rule ID 4819 // |
| 63781 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 63782 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 63783 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 63784 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, |
| 63785 | GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, |
| 63786 | GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/2, |
| 63787 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 63788 | // MIs[1] Rn |
| 63789 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, |
| 63790 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 63791 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 63792 | // (AArch64dup:{ *:[v8i16] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>) => (LD1Rv8h:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn) |
| 63793 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv8h, |
| 63794 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt |
| 63795 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 63796 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 63797 | GIR_EraseFromParent, /*InsnID*/0, |
| 63798 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63799 | // GIR_Coverage, 4819, |
| 63800 | GIR_Done, |
| 63801 | // Label 3667: @162798 |
| 63802 | GIM_Try, /*On fail goto*//*Label 3668*/ 162821, // Rule ID 1632 // |
| 63803 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 63804 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 63805 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 63806 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 63807 | // (AArch64dup:{ *:[v8i16] } GPR32:{ *:[i32] }:$Rn) => (DUPv8i16gpr:{ *:[v8i16] } GPR32:{ *:[i32] }:$Rn) |
| 63808 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::DUPv8i16gpr, |
| 63809 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63810 | // GIR_Coverage, 1632, |
| 63811 | GIR_Done, |
| 63812 | // Label 3668: @162821 |
| 63813 | GIM_Try, /*On fail goto*//*Label 3669*/ 162899, // Rule ID 4362 // |
| 63814 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 63815 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 63816 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 63817 | // (AArch64dup:{ *:[v8f16] } FPR16:{ *:[f16] }:$Rn) => (DUPv8i16lane:{ *:[v8f16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), FPR16:{ *:[f16] }:$Rn, hsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 63818 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 63819 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 63820 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 63821 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 63822 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 63823 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 63824 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 63825 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 63826 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 63827 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 63828 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 63829 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 63830 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, |
| 63831 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv8i16lane, |
| 63832 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 63833 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 63834 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 63835 | GIR_EraseFromParent, /*InsnID*/0, |
| 63836 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63837 | // GIR_Coverage, 4362, |
| 63838 | GIR_Done, |
| 63839 | // Label 3669: @162899 |
| 63840 | GIM_Try, /*On fail goto*//*Label 3670*/ 162977, // Rule ID 4363 // |
| 63841 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 63842 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 63843 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 63844 | // (AArch64dup:{ *:[v8bf16] } FPR16:{ *:[bf16] }:$Rn) => (DUPv8i16lane:{ *:[v8bf16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), FPR16:{ *:[bf16] }:$Rn, hsub:{ *:[i32] }), 0:{ *:[i64] }) |
| 63845 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 63846 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 63847 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 63848 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 63849 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 63850 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 63851 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 63852 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 63853 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 63854 | GIR_AddImm, /*InsnID*/1, /*Imm*/7, |
| 63855 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, AArch64::FPR128RegClassID, |
| 63856 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, AArch64::FPR128RegClassID, |
| 63857 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, AArch64::FPR16RegClassID, |
| 63858 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv8i16lane, |
| 63859 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 63860 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 63861 | GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 63862 | GIR_EraseFromParent, /*InsnID*/0, |
| 63863 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63864 | // GIR_Coverage, 4363, |
| 63865 | GIR_Done, |
| 63866 | // Label 3670: @162977 |
| 63867 | GIM_Reject, |
| 63868 | // Label 3634: @162978 |
| 63869 | GIM_Try, /*On fail goto*//*Label 3671*/ 163055, |
| 63870 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 63871 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 63872 | GIM_Try, /*On fail goto*//*Label 3672*/ 163039, // Rule ID 4817 // |
| 63873 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 63874 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LOAD, |
| 63875 | GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0, |
| 63876 | GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/1, |
| 63877 | GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 63878 | // MIs[1] Rn |
| 63879 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64, |
| 63880 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/AArch64::GPR64spRegClassID, |
| 63881 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 63882 | // (AArch64dup:{ *:[v16i8] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>) => (LD1Rv16b:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn) |
| 63883 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LD1Rv16b, |
| 63884 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vt |
| 63885 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 63886 | GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 63887 | GIR_EraseFromParent, /*InsnID*/0, |
| 63888 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63889 | // GIR_Coverage, 4817, |
| 63890 | GIR_Done, |
| 63891 | // Label 3672: @163039 |
| 63892 | GIM_Try, /*On fail goto*//*Label 3673*/ 163054, // Rule ID 1630 // |
| 63893 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 63894 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32RegClassID, |
| 63895 | // (AArch64dup:{ *:[v16i8] } GPR32:{ *:[i32] }:$Rn) => (DUPv16i8gpr:{ *:[v16i8] } GPR32:{ *:[i32] }:$Rn) |
| 63896 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::DUPv16i8gpr, |
| 63897 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63898 | // GIR_Coverage, 1630, |
| 63899 | GIR_Done, |
| 63900 | // Label 3673: @163054 |
| 63901 | GIM_Reject, |
| 63902 | // Label 3671: @163055 |
| 63903 | GIM_Reject, |
| 63904 | // Label 3635: @163056 |
| 63905 | GIM_Reject, |
| 63906 | // Label 80: @163057 |
| 63907 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/6, 10, /*)*//*default:*//*Label 3676*/ 163309, |
| 63908 | /*GILLT_v4s16*//*Label 3674*/ 163067, 0, 0, |
| 63909 | /*GILLT_v8s16*//*Label 3675*/ 163188, |
| 63910 | // Label 3674: @163067 |
| 63911 | GIM_Try, /*On fail goto*//*Label 3677*/ 163187, |
| 63912 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 63913 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 63914 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 63915 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 63916 | GIM_Try, /*On fail goto*//*Label 3678*/ 163120, // Rule ID 1639 // |
| 63917 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 63918 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 63919 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 63920 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 63921 | // MIs[1] Operand 1 |
| 63922 | // No operand predicates |
| 63923 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 63924 | // (AArch64duplane16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) => (DUPv4i16lane:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$idx) |
| 63925 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv4i16lane, |
| 63926 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 63927 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 63928 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx |
| 63929 | GIR_EraseFromParent, /*InsnID*/0, |
| 63930 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63931 | // GIR_Coverage, 1639, |
| 63932 | GIR_Done, |
| 63933 | // Label 3678: @163120 |
| 63934 | GIM_Try, /*On fail goto*//*Label 3679*/ 163153, // Rule ID 4364 // |
| 63935 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 63936 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 63937 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 63938 | // MIs[1] Operand 1 |
| 63939 | // No operand predicates |
| 63940 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 63941 | // (AArch64duplane16:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm) => (DUPv4i16lane:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm) |
| 63942 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv4i16lane, |
| 63943 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 63944 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 63945 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 63946 | GIR_EraseFromParent, /*InsnID*/0, |
| 63947 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63948 | // GIR_Coverage, 4364, |
| 63949 | GIR_Done, |
| 63950 | // Label 3679: @163153 |
| 63951 | GIM_Try, /*On fail goto*//*Label 3680*/ 163186, // Rule ID 4366 // |
| 63952 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 63953 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 63954 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 63955 | // MIs[1] Operand 1 |
| 63956 | // No operand predicates |
| 63957 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 63958 | // (AArch64duplane16:{ *:[v4bf16] } V128:{ *:[v8bf16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm) => (DUPv4i16lane:{ *:[v4bf16] } V128:{ *:[v8bf16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm) |
| 63959 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv4i16lane, |
| 63960 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 63961 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 63962 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 63963 | GIR_EraseFromParent, /*InsnID*/0, |
| 63964 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63965 | // GIR_Coverage, 4366, |
| 63966 | GIR_Done, |
| 63967 | // Label 3680: @163186 |
| 63968 | GIM_Reject, |
| 63969 | // Label 3677: @163187 |
| 63970 | GIM_Reject, |
| 63971 | // Label 3675: @163188 |
| 63972 | GIM_Try, /*On fail goto*//*Label 3681*/ 163308, |
| 63973 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 63974 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 63975 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 63976 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 63977 | GIM_Try, /*On fail goto*//*Label 3682*/ 163241, // Rule ID 1640 // |
| 63978 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 63979 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 63980 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 63981 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 63982 | // MIs[1] Operand 1 |
| 63983 | // No operand predicates |
| 63984 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 63985 | // (AArch64duplane16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) => (DUPv8i16lane:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$idx) |
| 63986 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv8i16lane, |
| 63987 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 63988 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 63989 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx |
| 63990 | GIR_EraseFromParent, /*InsnID*/0, |
| 63991 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 63992 | // GIR_Coverage, 1640, |
| 63993 | GIR_Done, |
| 63994 | // Label 3682: @163241 |
| 63995 | GIM_Try, /*On fail goto*//*Label 3683*/ 163274, // Rule ID 4365 // |
| 63996 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 63997 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 63998 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 63999 | // MIs[1] Operand 1 |
| 64000 | // No operand predicates |
| 64001 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64002 | // (AArch64duplane16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm) => (DUPv8i16lane:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm) |
| 64003 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv8i16lane, |
| 64004 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64005 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64006 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 64007 | GIR_EraseFromParent, /*InsnID*/0, |
| 64008 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64009 | // GIR_Coverage, 4365, |
| 64010 | GIR_Done, |
| 64011 | // Label 3683: @163274 |
| 64012 | GIM_Try, /*On fail goto*//*Label 3684*/ 163307, // Rule ID 4367 // |
| 64013 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 64014 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64015 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexH, |
| 64016 | // MIs[1] Operand 1 |
| 64017 | // No operand predicates |
| 64018 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64019 | // (AArch64duplane16:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm) => (DUPv8i16lane:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm) |
| 64020 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv8i16lane, |
| 64021 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64022 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64023 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 64024 | GIR_EraseFromParent, /*InsnID*/0, |
| 64025 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64026 | // GIR_Coverage, 4367, |
| 64027 | GIR_Done, |
| 64028 | // Label 3684: @163307 |
| 64029 | GIM_Reject, |
| 64030 | // Label 3681: @163308 |
| 64031 | GIM_Reject, |
| 64032 | // Label 3676: @163309 |
| 64033 | GIM_Reject, |
| 64034 | // Label 81: @163310 |
| 64035 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 8, /*)*//*default:*//*Label 3687*/ 163496, |
| 64036 | /*GILLT_v2s32*//*Label 3685*/ 163320, 0, 0, |
| 64037 | /*GILLT_v4s32*//*Label 3686*/ 163408, |
| 64038 | // Label 3685: @163320 |
| 64039 | GIM_Try, /*On fail goto*//*Label 3688*/ 163407, |
| 64040 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 64041 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 64042 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 64043 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 64044 | GIM_Try, /*On fail goto*//*Label 3689*/ 163373, // Rule ID 1637 // |
| 64045 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 64046 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 64047 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64048 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 64049 | // MIs[1] Operand 1 |
| 64050 | // No operand predicates |
| 64051 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64052 | // (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) => (DUPv2i32lane:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$idx) |
| 64053 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv2i32lane, |
| 64054 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64055 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64056 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx |
| 64057 | GIR_EraseFromParent, /*InsnID*/0, |
| 64058 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64059 | // GIR_Coverage, 1637, |
| 64060 | GIR_Done, |
| 64061 | // Label 3689: @163373 |
| 64062 | GIM_Try, /*On fail goto*//*Label 3690*/ 163406, // Rule ID 4368 // |
| 64063 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 64064 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64065 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 64066 | // MIs[1] Operand 1 |
| 64067 | // No operand predicates |
| 64068 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64069 | // (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm) => (DUPv2i32lane:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm) |
| 64070 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv2i32lane, |
| 64071 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64072 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64073 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 64074 | GIR_EraseFromParent, /*InsnID*/0, |
| 64075 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64076 | // GIR_Coverage, 4368, |
| 64077 | GIR_Done, |
| 64078 | // Label 3690: @163406 |
| 64079 | GIM_Reject, |
| 64080 | // Label 3688: @163407 |
| 64081 | GIM_Reject, |
| 64082 | // Label 3686: @163408 |
| 64083 | GIM_Try, /*On fail goto*//*Label 3691*/ 163495, |
| 64084 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 64085 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 64086 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 64087 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 64088 | GIM_Try, /*On fail goto*//*Label 3692*/ 163461, // Rule ID 1638 // |
| 64089 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 64090 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 64091 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64092 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 64093 | // MIs[1] Operand 1 |
| 64094 | // No operand predicates |
| 64095 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64096 | // (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) => (DUPv4i32lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$idx) |
| 64097 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv4i32lane, |
| 64098 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64099 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64100 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx |
| 64101 | GIR_EraseFromParent, /*InsnID*/0, |
| 64102 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64103 | // GIR_Coverage, 1638, |
| 64104 | GIR_Done, |
| 64105 | // Label 3692: @163461 |
| 64106 | GIM_Try, /*On fail goto*//*Label 3693*/ 163494, // Rule ID 4369 // |
| 64107 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 64108 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64109 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexS, |
| 64110 | // MIs[1] Operand 1 |
| 64111 | // No operand predicates |
| 64112 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64113 | // (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm) => (DUPv4i32lane:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm) |
| 64114 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv4i32lane, |
| 64115 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64116 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64117 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 64118 | GIR_EraseFromParent, /*InsnID*/0, |
| 64119 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64120 | // GIR_Coverage, 4369, |
| 64121 | GIR_Done, |
| 64122 | // Label 3693: @163494 |
| 64123 | GIM_Reject, |
| 64124 | // Label 3691: @163495 |
| 64125 | GIM_Reject, |
| 64126 | // Label 3687: @163496 |
| 64127 | GIM_Reject, |
| 64128 | // Label 82: @163497 |
| 64129 | GIM_Try, /*On fail goto*//*Label 3694*/ 163588, |
| 64130 | GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 64131 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 64132 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 64133 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 64134 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 64135 | GIM_Try, /*On fail goto*//*Label 3695*/ 163554, // Rule ID 1636 // |
| 64136 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 64137 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 64138 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64139 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 64140 | // MIs[1] Operand 1 |
| 64141 | // No operand predicates |
| 64142 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64143 | // (AArch64duplane64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx) => (DUPv2i64lane:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$idx) |
| 64144 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv2i64lane, |
| 64145 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64146 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64147 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx |
| 64148 | GIR_EraseFromParent, /*InsnID*/0, |
| 64149 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64150 | // GIR_Coverage, 1636, |
| 64151 | GIR_Done, |
| 64152 | // Label 3695: @163554 |
| 64153 | GIM_Try, /*On fail goto*//*Label 3696*/ 163587, // Rule ID 4370 // |
| 64154 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 64155 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64156 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexD, |
| 64157 | // MIs[1] Operand 1 |
| 64158 | // No operand predicates |
| 64159 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64160 | // (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$imm) => (DUPv2i64lane:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$imm) |
| 64161 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv2i64lane, |
| 64162 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64163 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64164 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 64165 | GIR_EraseFromParent, /*InsnID*/0, |
| 64166 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64167 | // GIR_Coverage, 4370, |
| 64168 | GIR_Done, |
| 64169 | // Label 3696: @163587 |
| 64170 | GIM_Reject, |
| 64171 | // Label 3694: @163588 |
| 64172 | GIM_Reject, |
| 64173 | // Label 83: @163589 |
| 64174 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/8, 11, /*)*//*default:*//*Label 3699*/ 163702, |
| 64175 | /*GILLT_v8s8*//*Label 3697*/ 163598, 0, |
| 64176 | /*GILLT_v16s8*//*Label 3698*/ 163650, |
| 64177 | // Label 3697: @163598 |
| 64178 | GIM_Try, /*On fail goto*//*Label 3700*/ 163649, // Rule ID 1641 // |
| 64179 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 64180 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 64181 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 64182 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 64183 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 64184 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 64185 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64186 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexB, |
| 64187 | // MIs[1] Operand 1 |
| 64188 | // No operand predicates |
| 64189 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64190 | // (AArch64duplane8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx) => (DUPv8i8lane:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$idx) |
| 64191 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv8i8lane, |
| 64192 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64193 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64194 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx |
| 64195 | GIR_EraseFromParent, /*InsnID*/0, |
| 64196 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64197 | // GIR_Coverage, 1641, |
| 64198 | GIR_Done, |
| 64199 | // Label 3700: @163649 |
| 64200 | GIM_Reject, |
| 64201 | // Label 3698: @163650 |
| 64202 | GIM_Try, /*On fail goto*//*Label 3701*/ 163701, // Rule ID 1642 // |
| 64203 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 64204 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 64205 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 64206 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 64207 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 64208 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 64209 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64210 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_VectorIndexB, |
| 64211 | // MIs[1] Operand 1 |
| 64212 | // No operand predicates |
| 64213 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64214 | // (AArch64duplane8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx) => (DUPv16i8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$idx) |
| 64215 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::DUPv16i8lane, |
| 64216 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64217 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64218 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx |
| 64219 | GIR_EraseFromParent, /*InsnID*/0, |
| 64220 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64221 | // GIR_Coverage, 1642, |
| 64222 | GIR_Done, |
| 64223 | // Label 3701: @163701 |
| 64224 | GIM_Reject, |
| 64225 | // Label 3699: @163702 |
| 64226 | GIM_Reject, |
| 64227 | // Label 84: @163703 |
| 64228 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 11, /*)*//*default:*//*Label 3710*/ 164526, |
| 64229 | /*GILLT_s64*//*Label 3702*/ 163718, 0, |
| 64230 | /*GILLT_v2s32*//*Label 3703*/ 163810, |
| 64231 | /*GILLT_v2s64*//*Label 3704*/ 163902, |
| 64232 | /*GILLT_v4s16*//*Label 3705*/ 163994, |
| 64233 | /*GILLT_v4s32*//*Label 3706*/ 164120, |
| 64234 | /*GILLT_v8s8*//*Label 3707*/ 164212, |
| 64235 | /*GILLT_v8s16*//*Label 3708*/ 164306, |
| 64236 | /*GILLT_v16s8*//*Label 3709*/ 164432, |
| 64237 | // Label 3702: @163718 |
| 64238 | GIM_Try, /*On fail goto*//*Label 3711*/ 163809, |
| 64239 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 64240 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 64241 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 64242 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 64243 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 64244 | GIM_Try, /*On fail goto*//*Label 3712*/ 163774, // Rule ID 4298 // |
| 64245 | // MIs[0] imm |
| 64246 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 64247 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64248 | // MIs[1] Operand 1 |
| 64249 | // No operand predicates |
| 64250 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64251 | // (AArch64ext:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, V64:{ *:[v1i64] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, V64:{ *:[v1i64] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 64252 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv8i8, |
| 64253 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64254 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64255 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 64256 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 64257 | GIR_EraseFromParent, /*InsnID*/0, |
| 64258 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64259 | // GIR_Coverage, 4298, |
| 64260 | GIR_Done, |
| 64261 | // Label 3712: @163774 |
| 64262 | GIM_Try, /*On fail goto*//*Label 3713*/ 163808, // Rule ID 4303 // |
| 64263 | // MIs[0] imm |
| 64264 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 64265 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64266 | // MIs[1] Operand 1 |
| 64267 | // No operand predicates |
| 64268 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64269 | // (AArch64ext:{ *:[v1f64] } V64:{ *:[v1f64] }:$Rn, V64:{ *:[v1f64] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v1f64] } V64:{ *:[v1f64] }:$Rn, V64:{ *:[v1f64] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 64270 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv8i8, |
| 64271 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64272 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64273 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 64274 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 64275 | GIR_EraseFromParent, /*InsnID*/0, |
| 64276 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64277 | // GIR_Coverage, 4303, |
| 64278 | GIR_Done, |
| 64279 | // Label 3713: @163808 |
| 64280 | GIM_Reject, |
| 64281 | // Label 3711: @163809 |
| 64282 | GIM_Reject, |
| 64283 | // Label 3703: @163810 |
| 64284 | GIM_Try, /*On fail goto*//*Label 3714*/ 163901, |
| 64285 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 64286 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 64287 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 64288 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 64289 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 64290 | GIM_Try, /*On fail goto*//*Label 3715*/ 163866, // Rule ID 4288 // |
| 64291 | // MIs[0] imm |
| 64292 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 64293 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64294 | // MIs[1] Operand 1 |
| 64295 | // No operand predicates |
| 64296 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64297 | // (AArch64ext:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 64298 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv8i8, |
| 64299 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64300 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64301 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 64302 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 64303 | GIR_EraseFromParent, /*InsnID*/0, |
| 64304 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64305 | // GIR_Coverage, 4288, |
| 64306 | GIR_Done, |
| 64307 | // Label 3715: @163866 |
| 64308 | GIM_Try, /*On fail goto*//*Label 3716*/ 163900, // Rule ID 4293 // |
| 64309 | // MIs[0] imm |
| 64310 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 64311 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64312 | // MIs[1] Operand 1 |
| 64313 | // No operand predicates |
| 64314 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64315 | // (AArch64ext:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 64316 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv8i8, |
| 64317 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64318 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64319 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 64320 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 64321 | GIR_EraseFromParent, /*InsnID*/0, |
| 64322 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64323 | // GIR_Coverage, 4293, |
| 64324 | GIR_Done, |
| 64325 | // Label 3716: @163900 |
| 64326 | GIM_Reject, |
| 64327 | // Label 3714: @163901 |
| 64328 | GIM_Reject, |
| 64329 | // Label 3704: @163902 |
| 64330 | GIM_Try, /*On fail goto*//*Label 3717*/ 163993, |
| 64331 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 64332 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 64333 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 64334 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 64335 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 64336 | GIM_Try, /*On fail goto*//*Label 3718*/ 163958, // Rule ID 4299 // |
| 64337 | // MIs[0] imm |
| 64338 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 64339 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64340 | // MIs[1] Operand 1 |
| 64341 | // No operand predicates |
| 64342 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64343 | // (AArch64ext:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 64344 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, |
| 64345 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64346 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64347 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 64348 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 64349 | GIR_EraseFromParent, /*InsnID*/0, |
| 64350 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64351 | // GIR_Coverage, 4299, |
| 64352 | GIR_Done, |
| 64353 | // Label 3718: @163958 |
| 64354 | GIM_Try, /*On fail goto*//*Label 3719*/ 163992, // Rule ID 4304 // |
| 64355 | // MIs[0] imm |
| 64356 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 64357 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64358 | // MIs[1] Operand 1 |
| 64359 | // No operand predicates |
| 64360 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64361 | // (AArch64ext:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 64362 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, |
| 64363 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64364 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64365 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 64366 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 64367 | GIR_EraseFromParent, /*InsnID*/0, |
| 64368 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64369 | // GIR_Coverage, 4304, |
| 64370 | GIR_Done, |
| 64371 | // Label 3719: @163992 |
| 64372 | GIM_Reject, |
| 64373 | // Label 3717: @163993 |
| 64374 | GIM_Reject, |
| 64375 | // Label 3705: @163994 |
| 64376 | GIM_Try, /*On fail goto*//*Label 3720*/ 164119, |
| 64377 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 64378 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 64379 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 64380 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 64381 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 64382 | GIM_Try, /*On fail goto*//*Label 3721*/ 164050, // Rule ID 4273 // |
| 64383 | // MIs[0] imm |
| 64384 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 64385 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64386 | // MIs[1] Operand 1 |
| 64387 | // No operand predicates |
| 64388 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64389 | // (AArch64ext:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 64390 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv8i8, |
| 64391 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64392 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64393 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 64394 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 64395 | GIR_EraseFromParent, /*InsnID*/0, |
| 64396 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64397 | // GIR_Coverage, 4273, |
| 64398 | GIR_Done, |
| 64399 | // Label 3721: @164050 |
| 64400 | GIM_Try, /*On fail goto*//*Label 3722*/ 164084, // Rule ID 4278 // |
| 64401 | // MIs[0] imm |
| 64402 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 64403 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64404 | // MIs[1] Operand 1 |
| 64405 | // No operand predicates |
| 64406 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64407 | // (AArch64ext:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 64408 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv8i8, |
| 64409 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64410 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64411 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 64412 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 64413 | GIR_EraseFromParent, /*InsnID*/0, |
| 64414 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64415 | // GIR_Coverage, 4278, |
| 64416 | GIR_Done, |
| 64417 | // Label 3722: @164084 |
| 64418 | GIM_Try, /*On fail goto*//*Label 3723*/ 164118, // Rule ID 4283 // |
| 64419 | // MIs[0] imm |
| 64420 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 64421 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64422 | // MIs[1] Operand 1 |
| 64423 | // No operand predicates |
| 64424 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64425 | // (AArch64ext:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 64426 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv8i8, |
| 64427 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64428 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64429 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 64430 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 64431 | GIR_EraseFromParent, /*InsnID*/0, |
| 64432 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64433 | // GIR_Coverage, 4283, |
| 64434 | GIR_Done, |
| 64435 | // Label 3723: @164118 |
| 64436 | GIM_Reject, |
| 64437 | // Label 3720: @164119 |
| 64438 | GIM_Reject, |
| 64439 | // Label 3706: @164120 |
| 64440 | GIM_Try, /*On fail goto*//*Label 3724*/ 164211, |
| 64441 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 64442 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 64443 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 64444 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 64445 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 64446 | GIM_Try, /*On fail goto*//*Label 3725*/ 164176, // Rule ID 4289 // |
| 64447 | // MIs[0] imm |
| 64448 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 64449 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64450 | // MIs[1] Operand 1 |
| 64451 | // No operand predicates |
| 64452 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64453 | // (AArch64ext:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 64454 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, |
| 64455 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64456 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64457 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 64458 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 64459 | GIR_EraseFromParent, /*InsnID*/0, |
| 64460 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64461 | // GIR_Coverage, 4289, |
| 64462 | GIR_Done, |
| 64463 | // Label 3725: @164176 |
| 64464 | GIM_Try, /*On fail goto*//*Label 3726*/ 164210, // Rule ID 4294 // |
| 64465 | // MIs[0] imm |
| 64466 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 64467 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64468 | // MIs[1] Operand 1 |
| 64469 | // No operand predicates |
| 64470 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64471 | // (AArch64ext:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 64472 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, |
| 64473 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64474 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64475 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 64476 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 64477 | GIR_EraseFromParent, /*InsnID*/0, |
| 64478 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64479 | // GIR_Coverage, 4294, |
| 64480 | GIR_Done, |
| 64481 | // Label 3726: @164210 |
| 64482 | GIM_Reject, |
| 64483 | // Label 3724: @164211 |
| 64484 | GIM_Reject, |
| 64485 | // Label 3707: @164212 |
| 64486 | GIM_Try, /*On fail goto*//*Label 3727*/ 164305, |
| 64487 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 64488 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 64489 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 64490 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 64491 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 64492 | GIM_Try, /*On fail goto*//*Label 3728*/ 164270, // Rule ID 1585 // |
| 64493 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 64494 | // MIs[0] imm |
| 64495 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 64496 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64497 | // MIs[1] Operand 1 |
| 64498 | // No operand predicates |
| 64499 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64500 | // (AArch64ext:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 64501 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv8i8, |
| 64502 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64503 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64504 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 64505 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 64506 | GIR_EraseFromParent, /*InsnID*/0, |
| 64507 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64508 | // GIR_Coverage, 1585, |
| 64509 | GIR_Done, |
| 64510 | // Label 3728: @164270 |
| 64511 | GIM_Try, /*On fail goto*//*Label 3729*/ 164304, // Rule ID 4268 // |
| 64512 | // MIs[0] imm |
| 64513 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 64514 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64515 | // MIs[1] Operand 1 |
| 64516 | // No operand predicates |
| 64517 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64518 | // (AArch64ext:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 64519 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv8i8, |
| 64520 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64521 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64522 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 64523 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 64524 | GIR_EraseFromParent, /*InsnID*/0, |
| 64525 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64526 | // GIR_Coverage, 4268, |
| 64527 | GIR_Done, |
| 64528 | // Label 3729: @164304 |
| 64529 | GIM_Reject, |
| 64530 | // Label 3727: @164305 |
| 64531 | GIM_Reject, |
| 64532 | // Label 3708: @164306 |
| 64533 | GIM_Try, /*On fail goto*//*Label 3730*/ 164431, |
| 64534 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 64535 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 64536 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 64537 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 64538 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 64539 | GIM_Try, /*On fail goto*//*Label 3731*/ 164362, // Rule ID 4274 // |
| 64540 | // MIs[0] imm |
| 64541 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 64542 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64543 | // MIs[1] Operand 1 |
| 64544 | // No operand predicates |
| 64545 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64546 | // (AArch64ext:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 64547 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, |
| 64548 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64549 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64550 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 64551 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 64552 | GIR_EraseFromParent, /*InsnID*/0, |
| 64553 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64554 | // GIR_Coverage, 4274, |
| 64555 | GIR_Done, |
| 64556 | // Label 3731: @164362 |
| 64557 | GIM_Try, /*On fail goto*//*Label 3732*/ 164396, // Rule ID 4279 // |
| 64558 | // MIs[0] imm |
| 64559 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 64560 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64561 | // MIs[1] Operand 1 |
| 64562 | // No operand predicates |
| 64563 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64564 | // (AArch64ext:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 64565 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, |
| 64566 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64567 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64568 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 64569 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 64570 | GIR_EraseFromParent, /*InsnID*/0, |
| 64571 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64572 | // GIR_Coverage, 4279, |
| 64573 | GIR_Done, |
| 64574 | // Label 3732: @164396 |
| 64575 | GIM_Try, /*On fail goto*//*Label 3733*/ 164430, // Rule ID 4284 // |
| 64576 | // MIs[0] imm |
| 64577 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 64578 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64579 | // MIs[1] Operand 1 |
| 64580 | // No operand predicates |
| 64581 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64582 | // (AArch64ext:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 64583 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, |
| 64584 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64585 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64586 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 64587 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 64588 | GIR_EraseFromParent, /*InsnID*/0, |
| 64589 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64590 | // GIR_Coverage, 4284, |
| 64591 | GIR_Done, |
| 64592 | // Label 3733: @164430 |
| 64593 | GIM_Reject, |
| 64594 | // Label 3730: @164431 |
| 64595 | GIM_Reject, |
| 64596 | // Label 3709: @164432 |
| 64597 | GIM_Try, /*On fail goto*//*Label 3734*/ 164525, |
| 64598 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 64599 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 64600 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 64601 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 64602 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 64603 | GIM_Try, /*On fail goto*//*Label 3735*/ 164490, // Rule ID 1586 // |
| 64604 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 64605 | // MIs[0] imm |
| 64606 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 64607 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64608 | // MIs[1] Operand 1 |
| 64609 | // No operand predicates |
| 64610 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64611 | // (AArch64ext:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 64612 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, |
| 64613 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64614 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64615 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 64616 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 64617 | GIR_EraseFromParent, /*InsnID*/0, |
| 64618 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64619 | // GIR_Coverage, 1586, |
| 64620 | GIR_Done, |
| 64621 | // Label 3735: @164490 |
| 64622 | GIM_Try, /*On fail goto*//*Label 3736*/ 164524, // Rule ID 4269 // |
| 64623 | // MIs[0] imm |
| 64624 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 64625 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 64626 | // MIs[1] Operand 1 |
| 64627 | // No operand predicates |
| 64628 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 64629 | // (AArch64ext:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 64630 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::EXTv16i8, |
| 64631 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 64632 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 64633 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm |
| 64634 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 64635 | GIR_EraseFromParent, /*InsnID*/0, |
| 64636 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64637 | // GIR_Coverage, 4269, |
| 64638 | GIR_Done, |
| 64639 | // Label 3736: @164524 |
| 64640 | GIM_Reject, |
| 64641 | // Label 3734: @164525 |
| 64642 | GIM_Reject, |
| 64643 | // Label 3710: @164526 |
| 64644 | GIM_Reject, |
| 64645 | // Label 85: @164527 |
| 64646 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/8, 11, /*)*//*default:*//*Label 3739*/ 164584, |
| 64647 | /*GILLT_v8s8*//*Label 3737*/ 164536, 0, |
| 64648 | /*GILLT_v16s8*//*Label 3738*/ 164560, |
| 64649 | // Label 3737: @164536 |
| 64650 | GIM_Try, /*On fail goto*//*Label 3740*/ 164559, // Rule ID 800 // |
| 64651 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 64652 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 64653 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 64654 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 64655 | // (AArch64rev16:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) => (REV16v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) |
| 64656 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v8i8, |
| 64657 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64658 | // GIR_Coverage, 800, |
| 64659 | GIR_Done, |
| 64660 | // Label 3740: @164559 |
| 64661 | GIM_Reject, |
| 64662 | // Label 3738: @164560 |
| 64663 | GIM_Try, /*On fail goto*//*Label 3741*/ 164583, // Rule ID 801 // |
| 64664 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 64665 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 64666 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 64667 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 64668 | // (AArch64rev16:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) => (REV16v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) |
| 64669 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV16v16i8, |
| 64670 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64671 | // GIR_Coverage, 801, |
| 64672 | GIR_Done, |
| 64673 | // Label 3741: @164583 |
| 64674 | GIM_Reject, |
| 64675 | // Label 3739: @164584 |
| 64676 | GIM_Reject, |
| 64677 | // Label 86: @164585 |
| 64678 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/6, 11, /*)*//*default:*//*Label 3746*/ 164734, |
| 64679 | /*GILLT_v4s16*//*Label 3742*/ 164596, 0, |
| 64680 | /*GILLT_v8s8*//*Label 3743*/ 164641, |
| 64681 | /*GILLT_v8s16*//*Label 3744*/ 164665, |
| 64682 | /*GILLT_v16s8*//*Label 3745*/ 164710, |
| 64683 | // Label 3742: @164596 |
| 64684 | GIM_Try, /*On fail goto*//*Label 3747*/ 164640, |
| 64685 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 64686 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 64687 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 64688 | GIM_Try, /*On fail goto*//*Label 3748*/ 164621, // Rule ID 804 // |
| 64689 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 64690 | // (AArch64rev32:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) => (REV32v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) |
| 64691 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, |
| 64692 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64693 | // GIR_Coverage, 804, |
| 64694 | GIR_Done, |
| 64695 | // Label 3748: @164621 |
| 64696 | GIM_Try, /*On fail goto*//*Label 3749*/ 164630, // Rule ID 4013 // |
| 64697 | // (AArch64rev32:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (REV32v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) |
| 64698 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, |
| 64699 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64700 | // GIR_Coverage, 4013, |
| 64701 | GIR_Done, |
| 64702 | // Label 3749: @164630 |
| 64703 | GIM_Try, /*On fail goto*//*Label 3750*/ 164639, // Rule ID 4015 // |
| 64704 | // (AArch64rev32:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn) => (REV32v4i16:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn) |
| 64705 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v4i16, |
| 64706 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64707 | // GIR_Coverage, 4015, |
| 64708 | GIR_Done, |
| 64709 | // Label 3750: @164639 |
| 64710 | GIM_Reject, |
| 64711 | // Label 3747: @164640 |
| 64712 | GIM_Reject, |
| 64713 | // Label 3743: @164641 |
| 64714 | GIM_Try, /*On fail goto*//*Label 3751*/ 164664, // Rule ID 802 // |
| 64715 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 64716 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 64717 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 64718 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 64719 | // (AArch64rev32:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) => (REV32v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) |
| 64720 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i8, |
| 64721 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64722 | // GIR_Coverage, 802, |
| 64723 | GIR_Done, |
| 64724 | // Label 3751: @164664 |
| 64725 | GIM_Reject, |
| 64726 | // Label 3744: @164665 |
| 64727 | GIM_Try, /*On fail goto*//*Label 3752*/ 164709, |
| 64728 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 64729 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 64730 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 64731 | GIM_Try, /*On fail goto*//*Label 3753*/ 164690, // Rule ID 805 // |
| 64732 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 64733 | // (AArch64rev32:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) => (REV32v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) |
| 64734 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, |
| 64735 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64736 | // GIR_Coverage, 805, |
| 64737 | GIR_Done, |
| 64738 | // Label 3753: @164690 |
| 64739 | GIM_Try, /*On fail goto*//*Label 3754*/ 164699, // Rule ID 4017 // |
| 64740 | // (AArch64rev32:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (REV32v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) |
| 64741 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, |
| 64742 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64743 | // GIR_Coverage, 4017, |
| 64744 | GIR_Done, |
| 64745 | // Label 3754: @164699 |
| 64746 | GIM_Try, /*On fail goto*//*Label 3755*/ 164708, // Rule ID 4019 // |
| 64747 | // (AArch64rev32:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn) => (REV32v8i16:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn) |
| 64748 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v8i16, |
| 64749 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64750 | // GIR_Coverage, 4019, |
| 64751 | GIR_Done, |
| 64752 | // Label 3755: @164708 |
| 64753 | GIM_Reject, |
| 64754 | // Label 3752: @164709 |
| 64755 | GIM_Reject, |
| 64756 | // Label 3745: @164710 |
| 64757 | GIM_Try, /*On fail goto*//*Label 3756*/ 164733, // Rule ID 803 // |
| 64758 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 64759 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 64760 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 64761 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 64762 | // (AArch64rev32:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) => (REV32v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) |
| 64763 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV32v16i8, |
| 64764 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64765 | // GIR_Coverage, 803, |
| 64766 | GIR_Done, |
| 64767 | // Label 3756: @164733 |
| 64768 | GIM_Reject, |
| 64769 | // Label 3746: @164734 |
| 64770 | GIM_Reject, |
| 64771 | // Label 87: @164735 |
| 64772 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 11, /*)*//*default:*//*Label 3763*/ 164958, |
| 64773 | /*GILLT_v2s32*//*Label 3757*/ 164748, 0, |
| 64774 | /*GILLT_v4s16*//*Label 3758*/ 164784, |
| 64775 | /*GILLT_v4s32*//*Label 3759*/ 164829, |
| 64776 | /*GILLT_v8s8*//*Label 3760*/ 164865, |
| 64777 | /*GILLT_v8s16*//*Label 3761*/ 164889, |
| 64778 | /*GILLT_v16s8*//*Label 3762*/ 164934, |
| 64779 | // Label 3757: @164748 |
| 64780 | GIM_Try, /*On fail goto*//*Label 3764*/ 164783, |
| 64781 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 64782 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 64783 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 64784 | GIM_Try, /*On fail goto*//*Label 3765*/ 164773, // Rule ID 810 // |
| 64785 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 64786 | // (AArch64rev64:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) => (REV64v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) |
| 64787 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, |
| 64788 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64789 | // GIR_Coverage, 810, |
| 64790 | GIR_Done, |
| 64791 | // Label 3765: @164773 |
| 64792 | GIM_Try, /*On fail goto*//*Label 3766*/ 164782, // Rule ID 4021 // |
| 64793 | // (AArch64rev64:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (REV64v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) |
| 64794 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v2i32, |
| 64795 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64796 | // GIR_Coverage, 4021, |
| 64797 | GIR_Done, |
| 64798 | // Label 3766: @164782 |
| 64799 | GIM_Reject, |
| 64800 | // Label 3764: @164783 |
| 64801 | GIM_Reject, |
| 64802 | // Label 3758: @164784 |
| 64803 | GIM_Try, /*On fail goto*//*Label 3767*/ 164828, |
| 64804 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 64805 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 64806 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 64807 | GIM_Try, /*On fail goto*//*Label 3768*/ 164809, // Rule ID 808 // |
| 64808 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 64809 | // (AArch64rev64:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) => (REV64v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) |
| 64810 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 64811 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64812 | // GIR_Coverage, 808, |
| 64813 | GIR_Done, |
| 64814 | // Label 3768: @164809 |
| 64815 | GIM_Try, /*On fail goto*//*Label 3769*/ 164818, // Rule ID 4014 // |
| 64816 | // (AArch64rev64:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (REV64v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) |
| 64817 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 64818 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64819 | // GIR_Coverage, 4014, |
| 64820 | GIR_Done, |
| 64821 | // Label 3769: @164818 |
| 64822 | GIM_Try, /*On fail goto*//*Label 3770*/ 164827, // Rule ID 4016 // |
| 64823 | // (AArch64rev64:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn) => (REV64v4i16:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn) |
| 64824 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i16, |
| 64825 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64826 | // GIR_Coverage, 4016, |
| 64827 | GIR_Done, |
| 64828 | // Label 3770: @164827 |
| 64829 | GIM_Reject, |
| 64830 | // Label 3767: @164828 |
| 64831 | GIM_Reject, |
| 64832 | // Label 3759: @164829 |
| 64833 | GIM_Try, /*On fail goto*//*Label 3771*/ 164864, |
| 64834 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 64835 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 64836 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 64837 | GIM_Try, /*On fail goto*//*Label 3772*/ 164854, // Rule ID 811 // |
| 64838 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 64839 | // (AArch64rev64:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) => (REV64v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) |
| 64840 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, |
| 64841 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64842 | // GIR_Coverage, 811, |
| 64843 | GIR_Done, |
| 64844 | // Label 3772: @164854 |
| 64845 | GIM_Try, /*On fail goto*//*Label 3773*/ 164863, // Rule ID 4022 // |
| 64846 | // (AArch64rev64:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (REV64v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) |
| 64847 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v4i32, |
| 64848 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64849 | // GIR_Coverage, 4022, |
| 64850 | GIR_Done, |
| 64851 | // Label 3773: @164863 |
| 64852 | GIM_Reject, |
| 64853 | // Label 3771: @164864 |
| 64854 | GIM_Reject, |
| 64855 | // Label 3760: @164865 |
| 64856 | GIM_Try, /*On fail goto*//*Label 3774*/ 164888, // Rule ID 806 // |
| 64857 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 64858 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 64859 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 64860 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 64861 | // (AArch64rev64:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) => (REV64v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) |
| 64862 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i8, |
| 64863 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64864 | // GIR_Coverage, 806, |
| 64865 | GIR_Done, |
| 64866 | // Label 3774: @164888 |
| 64867 | GIM_Reject, |
| 64868 | // Label 3761: @164889 |
| 64869 | GIM_Try, /*On fail goto*//*Label 3775*/ 164933, |
| 64870 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 64871 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 64872 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 64873 | GIM_Try, /*On fail goto*//*Label 3776*/ 164914, // Rule ID 809 // |
| 64874 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 64875 | // (AArch64rev64:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) => (REV64v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) |
| 64876 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, |
| 64877 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64878 | // GIR_Coverage, 809, |
| 64879 | GIR_Done, |
| 64880 | // Label 3776: @164914 |
| 64881 | GIM_Try, /*On fail goto*//*Label 3777*/ 164923, // Rule ID 4018 // |
| 64882 | // (AArch64rev64:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (REV64v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) |
| 64883 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, |
| 64884 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64885 | // GIR_Coverage, 4018, |
| 64886 | GIR_Done, |
| 64887 | // Label 3777: @164923 |
| 64888 | GIM_Try, /*On fail goto*//*Label 3778*/ 164932, // Rule ID 4020 // |
| 64889 | // (AArch64rev64:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn) => (REV64v8i16:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn) |
| 64890 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v8i16, |
| 64891 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64892 | // GIR_Coverage, 4020, |
| 64893 | GIR_Done, |
| 64894 | // Label 3778: @164932 |
| 64895 | GIM_Reject, |
| 64896 | // Label 3775: @164933 |
| 64897 | GIM_Reject, |
| 64898 | // Label 3762: @164934 |
| 64899 | GIM_Try, /*On fail goto*//*Label 3779*/ 164957, // Rule ID 807 // |
| 64900 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 64901 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 64902 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 64903 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 64904 | // (AArch64rev64:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) => (REV64v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) |
| 64905 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::REV64v16i8, |
| 64906 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64907 | // GIR_Coverage, 807, |
| 64908 | GIR_Done, |
| 64909 | // Label 3779: @164957 |
| 64910 | GIM_Reject, |
| 64911 | // Label 3763: @164958 |
| 64912 | GIM_Reject, |
| 64913 | // Label 88: @164959 |
| 64914 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 3783*/ 165040, |
| 64915 | /*GILLT_s16*//*Label 3780*/ 164968, |
| 64916 | /*GILLT_s32*//*Label 3781*/ 164992, |
| 64917 | /*GILLT_s64*//*Label 3782*/ 165016, |
| 64918 | // Label 3780: @164968 |
| 64919 | GIM_Try, /*On fail goto*//*Label 3784*/ 164991, // Rule ID 1377 // |
| 64920 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 64921 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 64922 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 64923 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 64924 | // (AArch64sitof:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (SCVTFv1i16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) |
| 64925 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFv1i16, |
| 64926 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64927 | // GIR_Coverage, 1377, |
| 64928 | GIR_Done, |
| 64929 | // Label 3784: @164991 |
| 64930 | GIM_Reject, |
| 64931 | // Label 3781: @164992 |
| 64932 | GIM_Try, /*On fail goto*//*Label 3785*/ 165015, // Rule ID 1376 // |
| 64933 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 64934 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 64935 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 64936 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 64937 | // (AArch64sitof:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (SCVTFv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) |
| 64938 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFv1i32, |
| 64939 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64940 | // GIR_Coverage, 1376, |
| 64941 | GIR_Done, |
| 64942 | // Label 3785: @165015 |
| 64943 | GIM_Reject, |
| 64944 | // Label 3782: @165016 |
| 64945 | GIM_Try, /*On fail goto*//*Label 3786*/ 165039, // Rule ID 1375 // |
| 64946 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 64947 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 64948 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 64949 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 64950 | // (AArch64sitof:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (SCVTFv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) |
| 64951 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SCVTFv1i64, |
| 64952 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64953 | // GIR_Coverage, 1375, |
| 64954 | GIR_Done, |
| 64955 | // Label 3786: @165039 |
| 64956 | GIM_Reject, |
| 64957 | // Label 3783: @165040 |
| 64958 | GIM_Reject, |
| 64959 | // Label 89: @165041 |
| 64960 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 11, /*)*//*default:*//*Label 3794*/ 165348, |
| 64961 | /*GILLT_v2s32*//*Label 3787*/ 165054, |
| 64962 | /*GILLT_v2s64*//*Label 3788*/ 165100, |
| 64963 | /*GILLT_v4s16*//*Label 3789*/ 165146, |
| 64964 | /*GILLT_v4s32*//*Label 3790*/ 165192, |
| 64965 | /*GILLT_v8s8*//*Label 3791*/ 165238, |
| 64966 | /*GILLT_v8s16*//*Label 3792*/ 165270, |
| 64967 | /*GILLT_v16s8*//*Label 3793*/ 165316, |
| 64968 | // Label 3787: @165054 |
| 64969 | GIM_Try, /*On fail goto*//*Label 3795*/ 165099, |
| 64970 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 64971 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 64972 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 64973 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 64974 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 64975 | GIM_Try, /*On fail goto*//*Label 3796*/ 165087, // Rule ID 1591 // |
| 64976 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 64977 | // (AArch64trn1:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (TRN1v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 64978 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1v2i32, |
| 64979 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64980 | // GIR_Coverage, 1591, |
| 64981 | GIR_Done, |
| 64982 | // Label 3796: @165087 |
| 64983 | GIM_Try, /*On fail goto*//*Label 3797*/ 165098, // Rule ID 2700 // |
| 64984 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 64985 | // (AArch64trn1:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (TRN1v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) |
| 64986 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1v2i32, |
| 64987 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 64988 | // GIR_Coverage, 2700, |
| 64989 | GIR_Done, |
| 64990 | // Label 3797: @165098 |
| 64991 | GIM_Reject, |
| 64992 | // Label 3795: @165099 |
| 64993 | GIM_Reject, |
| 64994 | // Label 3788: @165100 |
| 64995 | GIM_Try, /*On fail goto*//*Label 3798*/ 165145, |
| 64996 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 64997 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 64998 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 64999 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 65000 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 65001 | GIM_Try, /*On fail goto*//*Label 3799*/ 165133, // Rule ID 1593 // |
| 65002 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65003 | // (AArch64trn1:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (TRN1v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 65004 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1v2i64, |
| 65005 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65006 | // GIR_Coverage, 1593, |
| 65007 | GIR_Done, |
| 65008 | // Label 3799: @165133 |
| 65009 | GIM_Try, /*On fail goto*//*Label 3800*/ 165144, // Rule ID 2702 // |
| 65010 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65011 | // (AArch64trn1:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (TRN1v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) |
| 65012 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1v2i64, |
| 65013 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65014 | // GIR_Coverage, 2702, |
| 65015 | GIR_Done, |
| 65016 | // Label 3800: @165144 |
| 65017 | GIM_Reject, |
| 65018 | // Label 3798: @165145 |
| 65019 | GIM_Reject, |
| 65020 | // Label 3789: @165146 |
| 65021 | GIM_Try, /*On fail goto*//*Label 3801*/ 165191, |
| 65022 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 65023 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 65024 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 65025 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 65026 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 65027 | GIM_Try, /*On fail goto*//*Label 3802*/ 165179, // Rule ID 1589 // |
| 65028 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65029 | // (AArch64trn1:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (TRN1v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 65030 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1v4i16, |
| 65031 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65032 | // GIR_Coverage, 1589, |
| 65033 | GIR_Done, |
| 65034 | // Label 3802: @165179 |
| 65035 | GIM_Try, /*On fail goto*//*Label 3803*/ 165190, // Rule ID 2698 // |
| 65036 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65037 | // (AArch64trn1:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (TRN1v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 65038 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1v4i16, |
| 65039 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65040 | // GIR_Coverage, 2698, |
| 65041 | GIR_Done, |
| 65042 | // Label 3803: @165190 |
| 65043 | GIM_Reject, |
| 65044 | // Label 3801: @165191 |
| 65045 | GIM_Reject, |
| 65046 | // Label 3790: @165192 |
| 65047 | GIM_Try, /*On fail goto*//*Label 3804*/ 165237, |
| 65048 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 65049 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 65050 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 65051 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 65052 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 65053 | GIM_Try, /*On fail goto*//*Label 3805*/ 165225, // Rule ID 1592 // |
| 65054 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65055 | // (AArch64trn1:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (TRN1v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 65056 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1v4i32, |
| 65057 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65058 | // GIR_Coverage, 1592, |
| 65059 | GIR_Done, |
| 65060 | // Label 3805: @165225 |
| 65061 | GIM_Try, /*On fail goto*//*Label 3806*/ 165236, // Rule ID 2701 // |
| 65062 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65063 | // (AArch64trn1:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (TRN1v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) |
| 65064 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1v4i32, |
| 65065 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65066 | // GIR_Coverage, 2701, |
| 65067 | GIR_Done, |
| 65068 | // Label 3806: @165236 |
| 65069 | GIM_Reject, |
| 65070 | // Label 3804: @165237 |
| 65071 | GIM_Reject, |
| 65072 | // Label 3791: @165238 |
| 65073 | GIM_Try, /*On fail goto*//*Label 3807*/ 165269, // Rule ID 1587 // |
| 65074 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65075 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 65076 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 65077 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 65078 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 65079 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 65080 | // (AArch64trn1:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (TRN1v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 65081 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1v8i8, |
| 65082 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65083 | // GIR_Coverage, 1587, |
| 65084 | GIR_Done, |
| 65085 | // Label 3807: @165269 |
| 65086 | GIM_Reject, |
| 65087 | // Label 3792: @165270 |
| 65088 | GIM_Try, /*On fail goto*//*Label 3808*/ 165315, |
| 65089 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 65090 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 65091 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 65092 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 65093 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 65094 | GIM_Try, /*On fail goto*//*Label 3809*/ 165303, // Rule ID 1590 // |
| 65095 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65096 | // (AArch64trn1:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (TRN1v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 65097 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1v8i16, |
| 65098 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65099 | // GIR_Coverage, 1590, |
| 65100 | GIR_Done, |
| 65101 | // Label 3809: @165303 |
| 65102 | GIM_Try, /*On fail goto*//*Label 3810*/ 165314, // Rule ID 2699 // |
| 65103 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65104 | // (AArch64trn1:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (TRN1v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 65105 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1v8i16, |
| 65106 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65107 | // GIR_Coverage, 2699, |
| 65108 | GIR_Done, |
| 65109 | // Label 3810: @165314 |
| 65110 | GIM_Reject, |
| 65111 | // Label 3808: @165315 |
| 65112 | GIM_Reject, |
| 65113 | // Label 3793: @165316 |
| 65114 | GIM_Try, /*On fail goto*//*Label 3811*/ 165347, // Rule ID 1588 // |
| 65115 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65116 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 65117 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 65118 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 65119 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 65120 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 65121 | // (AArch64trn1:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (TRN1v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 65122 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN1v16i8, |
| 65123 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65124 | // GIR_Coverage, 1588, |
| 65125 | GIR_Done, |
| 65126 | // Label 3811: @165347 |
| 65127 | GIM_Reject, |
| 65128 | // Label 3794: @165348 |
| 65129 | GIM_Reject, |
| 65130 | // Label 90: @165349 |
| 65131 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 11, /*)*//*default:*//*Label 3819*/ 165656, |
| 65132 | /*GILLT_v2s32*//*Label 3812*/ 165362, |
| 65133 | /*GILLT_v2s64*//*Label 3813*/ 165408, |
| 65134 | /*GILLT_v4s16*//*Label 3814*/ 165454, |
| 65135 | /*GILLT_v4s32*//*Label 3815*/ 165500, |
| 65136 | /*GILLT_v8s8*//*Label 3816*/ 165546, |
| 65137 | /*GILLT_v8s16*//*Label 3817*/ 165578, |
| 65138 | /*GILLT_v16s8*//*Label 3818*/ 165624, |
| 65139 | // Label 3812: @165362 |
| 65140 | GIM_Try, /*On fail goto*//*Label 3820*/ 165407, |
| 65141 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 65142 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 65143 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 65144 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 65145 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 65146 | GIM_Try, /*On fail goto*//*Label 3821*/ 165395, // Rule ID 1598 // |
| 65147 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65148 | // (AArch64trn2:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (TRN2v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 65149 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2v2i32, |
| 65150 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65151 | // GIR_Coverage, 1598, |
| 65152 | GIR_Done, |
| 65153 | // Label 3821: @165395 |
| 65154 | GIM_Try, /*On fail goto*//*Label 3822*/ 165406, // Rule ID 4310 // |
| 65155 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65156 | // (AArch64trn2:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (TRN2v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) |
| 65157 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2v2i32, |
| 65158 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65159 | // GIR_Coverage, 4310, |
| 65160 | GIR_Done, |
| 65161 | // Label 3822: @165406 |
| 65162 | GIM_Reject, |
| 65163 | // Label 3820: @165407 |
| 65164 | GIM_Reject, |
| 65165 | // Label 3813: @165408 |
| 65166 | GIM_Try, /*On fail goto*//*Label 3823*/ 165453, |
| 65167 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 65168 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 65169 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 65170 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 65171 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 65172 | GIM_Try, /*On fail goto*//*Label 3824*/ 165441, // Rule ID 1600 // |
| 65173 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65174 | // (AArch64trn2:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (TRN2v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 65175 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2v2i64, |
| 65176 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65177 | // GIR_Coverage, 1600, |
| 65178 | GIR_Done, |
| 65179 | // Label 3824: @165441 |
| 65180 | GIM_Try, /*On fail goto*//*Label 3825*/ 165452, // Rule ID 4312 // |
| 65181 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65182 | // (AArch64trn2:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (TRN2v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) |
| 65183 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2v2i64, |
| 65184 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65185 | // GIR_Coverage, 4312, |
| 65186 | GIR_Done, |
| 65187 | // Label 3825: @165452 |
| 65188 | GIM_Reject, |
| 65189 | // Label 3823: @165453 |
| 65190 | GIM_Reject, |
| 65191 | // Label 3814: @165454 |
| 65192 | GIM_Try, /*On fail goto*//*Label 3826*/ 165499, |
| 65193 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 65194 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 65195 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 65196 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 65197 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 65198 | GIM_Try, /*On fail goto*//*Label 3827*/ 165487, // Rule ID 1596 // |
| 65199 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65200 | // (AArch64trn2:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (TRN2v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 65201 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2v4i16, |
| 65202 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65203 | // GIR_Coverage, 1596, |
| 65204 | GIR_Done, |
| 65205 | // Label 3827: @165487 |
| 65206 | GIM_Try, /*On fail goto*//*Label 3828*/ 165498, // Rule ID 4308 // |
| 65207 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65208 | // (AArch64trn2:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (TRN2v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 65209 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2v4i16, |
| 65210 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65211 | // GIR_Coverage, 4308, |
| 65212 | GIR_Done, |
| 65213 | // Label 3828: @165498 |
| 65214 | GIM_Reject, |
| 65215 | // Label 3826: @165499 |
| 65216 | GIM_Reject, |
| 65217 | // Label 3815: @165500 |
| 65218 | GIM_Try, /*On fail goto*//*Label 3829*/ 165545, |
| 65219 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 65220 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 65221 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 65222 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 65223 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 65224 | GIM_Try, /*On fail goto*//*Label 3830*/ 165533, // Rule ID 1599 // |
| 65225 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65226 | // (AArch64trn2:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (TRN2v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 65227 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2v4i32, |
| 65228 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65229 | // GIR_Coverage, 1599, |
| 65230 | GIR_Done, |
| 65231 | // Label 3830: @165533 |
| 65232 | GIM_Try, /*On fail goto*//*Label 3831*/ 165544, // Rule ID 4311 // |
| 65233 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65234 | // (AArch64trn2:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (TRN2v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) |
| 65235 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2v4i32, |
| 65236 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65237 | // GIR_Coverage, 4311, |
| 65238 | GIR_Done, |
| 65239 | // Label 3831: @165544 |
| 65240 | GIM_Reject, |
| 65241 | // Label 3829: @165545 |
| 65242 | GIM_Reject, |
| 65243 | // Label 3816: @165546 |
| 65244 | GIM_Try, /*On fail goto*//*Label 3832*/ 165577, // Rule ID 1594 // |
| 65245 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65246 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 65247 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 65248 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 65249 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 65250 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 65251 | // (AArch64trn2:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (TRN2v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 65252 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2v8i8, |
| 65253 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65254 | // GIR_Coverage, 1594, |
| 65255 | GIR_Done, |
| 65256 | // Label 3832: @165577 |
| 65257 | GIM_Reject, |
| 65258 | // Label 3817: @165578 |
| 65259 | GIM_Try, /*On fail goto*//*Label 3833*/ 165623, |
| 65260 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 65261 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 65262 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 65263 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 65264 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 65265 | GIM_Try, /*On fail goto*//*Label 3834*/ 165611, // Rule ID 1597 // |
| 65266 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65267 | // (AArch64trn2:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (TRN2v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 65268 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2v8i16, |
| 65269 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65270 | // GIR_Coverage, 1597, |
| 65271 | GIR_Done, |
| 65272 | // Label 3834: @165611 |
| 65273 | GIM_Try, /*On fail goto*//*Label 3835*/ 165622, // Rule ID 4309 // |
| 65274 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65275 | // (AArch64trn2:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (TRN2v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 65276 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2v8i16, |
| 65277 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65278 | // GIR_Coverage, 4309, |
| 65279 | GIR_Done, |
| 65280 | // Label 3835: @165622 |
| 65281 | GIM_Reject, |
| 65282 | // Label 3833: @165623 |
| 65283 | GIM_Reject, |
| 65284 | // Label 3818: @165624 |
| 65285 | GIM_Try, /*On fail goto*//*Label 3836*/ 165655, // Rule ID 1595 // |
| 65286 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65287 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 65288 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 65289 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 65290 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 65291 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 65292 | // (AArch64trn2:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (TRN2v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 65293 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::TRN2v16i8, |
| 65294 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65295 | // GIR_Coverage, 1595, |
| 65296 | GIR_Done, |
| 65297 | // Label 3836: @165655 |
| 65298 | GIM_Reject, |
| 65299 | // Label 3819: @165656 |
| 65300 | GIM_Reject, |
| 65301 | // Label 91: @165657 |
| 65302 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 3840*/ 165738, |
| 65303 | /*GILLT_s16*//*Label 3837*/ 165666, |
| 65304 | /*GILLT_s32*//*Label 3838*/ 165690, |
| 65305 | /*GILLT_s64*//*Label 3839*/ 165714, |
| 65306 | // Label 3837: @165666 |
| 65307 | GIM_Try, /*On fail goto*//*Label 3841*/ 165689, // Rule ID 1388 // |
| 65308 | GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, |
| 65309 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 65310 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR16RegClassID, |
| 65311 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR16RegClassID, |
| 65312 | // (AArch64uitof:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (UCVTFv1i16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) |
| 65313 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFv1i16, |
| 65314 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65315 | // GIR_Coverage, 1388, |
| 65316 | GIR_Done, |
| 65317 | // Label 3841: @165689 |
| 65318 | GIM_Reject, |
| 65319 | // Label 3838: @165690 |
| 65320 | GIM_Try, /*On fail goto*//*Label 3842*/ 165713, // Rule ID 1387 // |
| 65321 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65322 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 65323 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR32RegClassID, |
| 65324 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR32RegClassID, |
| 65325 | // (AArch64uitof:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (UCVTFv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) |
| 65326 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFv1i32, |
| 65327 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65328 | // GIR_Coverage, 1387, |
| 65329 | GIR_Done, |
| 65330 | // Label 3842: @165713 |
| 65331 | GIM_Reject, |
| 65332 | // Label 3839: @165714 |
| 65333 | GIM_Try, /*On fail goto*//*Label 3843*/ 165737, // Rule ID 1386 // |
| 65334 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65335 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 65336 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 65337 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 65338 | // (AArch64uitof:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (UCVTFv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) |
| 65339 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UCVTFv1i64, |
| 65340 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65341 | // GIR_Coverage, 1386, |
| 65342 | GIR_Done, |
| 65343 | // Label 3843: @165737 |
| 65344 | GIM_Reject, |
| 65345 | // Label 3840: @165738 |
| 65346 | GIM_Reject, |
| 65347 | // Label 92: @165739 |
| 65348 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 11, /*)*//*default:*//*Label 3851*/ 166046, |
| 65349 | /*GILLT_v2s32*//*Label 3844*/ 165752, |
| 65350 | /*GILLT_v2s64*//*Label 3845*/ 165798, |
| 65351 | /*GILLT_v4s16*//*Label 3846*/ 165844, |
| 65352 | /*GILLT_v4s32*//*Label 3847*/ 165890, |
| 65353 | /*GILLT_v8s8*//*Label 3848*/ 165936, |
| 65354 | /*GILLT_v8s16*//*Label 3849*/ 165968, |
| 65355 | /*GILLT_v16s8*//*Label 3850*/ 166014, |
| 65356 | // Label 3844: @165752 |
| 65357 | GIM_Try, /*On fail goto*//*Label 3852*/ 165797, |
| 65358 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 65359 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 65360 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 65361 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 65362 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 65363 | GIM_Try, /*On fail goto*//*Label 3853*/ 165785, // Rule ID 1605 // |
| 65364 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65365 | // (AArch64uzp1:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UZP1v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 65366 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1v2i32, |
| 65367 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65368 | // GIR_Coverage, 1605, |
| 65369 | GIR_Done, |
| 65370 | // Label 3853: @165785 |
| 65371 | GIM_Try, /*On fail goto*//*Label 3854*/ 165796, // Rule ID 4315 // |
| 65372 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65373 | // (AArch64uzp1:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (UZP1v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) |
| 65374 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1v2i32, |
| 65375 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65376 | // GIR_Coverage, 4315, |
| 65377 | GIR_Done, |
| 65378 | // Label 3854: @165796 |
| 65379 | GIM_Reject, |
| 65380 | // Label 3852: @165797 |
| 65381 | GIM_Reject, |
| 65382 | // Label 3845: @165798 |
| 65383 | GIM_Try, /*On fail goto*//*Label 3855*/ 165843, |
| 65384 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 65385 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 65386 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 65387 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 65388 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 65389 | GIM_Try, /*On fail goto*//*Label 3856*/ 165831, // Rule ID 1607 // |
| 65390 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65391 | // (AArch64uzp1:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (UZP1v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 65392 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1v2i64, |
| 65393 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65394 | // GIR_Coverage, 1607, |
| 65395 | GIR_Done, |
| 65396 | // Label 3856: @165831 |
| 65397 | GIM_Try, /*On fail goto*//*Label 3857*/ 165842, // Rule ID 4317 // |
| 65398 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65399 | // (AArch64uzp1:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (UZP1v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) |
| 65400 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1v2i64, |
| 65401 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65402 | // GIR_Coverage, 4317, |
| 65403 | GIR_Done, |
| 65404 | // Label 3857: @165842 |
| 65405 | GIM_Reject, |
| 65406 | // Label 3855: @165843 |
| 65407 | GIM_Reject, |
| 65408 | // Label 3846: @165844 |
| 65409 | GIM_Try, /*On fail goto*//*Label 3858*/ 165889, |
| 65410 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 65411 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 65412 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 65413 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 65414 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 65415 | GIM_Try, /*On fail goto*//*Label 3859*/ 165877, // Rule ID 1603 // |
| 65416 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65417 | // (AArch64uzp1:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UZP1v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 65418 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1v4i16, |
| 65419 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65420 | // GIR_Coverage, 1603, |
| 65421 | GIR_Done, |
| 65422 | // Label 3859: @165877 |
| 65423 | GIM_Try, /*On fail goto*//*Label 3860*/ 165888, // Rule ID 4313 // |
| 65424 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65425 | // (AArch64uzp1:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (UZP1v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 65426 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1v4i16, |
| 65427 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65428 | // GIR_Coverage, 4313, |
| 65429 | GIR_Done, |
| 65430 | // Label 3860: @165888 |
| 65431 | GIM_Reject, |
| 65432 | // Label 3858: @165889 |
| 65433 | GIM_Reject, |
| 65434 | // Label 3847: @165890 |
| 65435 | GIM_Try, /*On fail goto*//*Label 3861*/ 165935, |
| 65436 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 65437 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 65438 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 65439 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 65440 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 65441 | GIM_Try, /*On fail goto*//*Label 3862*/ 165923, // Rule ID 1606 // |
| 65442 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65443 | // (AArch64uzp1:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UZP1v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 65444 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1v4i32, |
| 65445 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65446 | // GIR_Coverage, 1606, |
| 65447 | GIR_Done, |
| 65448 | // Label 3862: @165923 |
| 65449 | GIM_Try, /*On fail goto*//*Label 3863*/ 165934, // Rule ID 4316 // |
| 65450 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65451 | // (AArch64uzp1:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (UZP1v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) |
| 65452 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1v4i32, |
| 65453 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65454 | // GIR_Coverage, 4316, |
| 65455 | GIR_Done, |
| 65456 | // Label 3863: @165934 |
| 65457 | GIM_Reject, |
| 65458 | // Label 3861: @165935 |
| 65459 | GIM_Reject, |
| 65460 | // Label 3848: @165936 |
| 65461 | GIM_Try, /*On fail goto*//*Label 3864*/ 165967, // Rule ID 1601 // |
| 65462 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65463 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 65464 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 65465 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 65466 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 65467 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 65468 | // (AArch64uzp1:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UZP1v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 65469 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1v8i8, |
| 65470 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65471 | // GIR_Coverage, 1601, |
| 65472 | GIR_Done, |
| 65473 | // Label 3864: @165967 |
| 65474 | GIM_Reject, |
| 65475 | // Label 3849: @165968 |
| 65476 | GIM_Try, /*On fail goto*//*Label 3865*/ 166013, |
| 65477 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 65478 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 65479 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 65480 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 65481 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 65482 | GIM_Try, /*On fail goto*//*Label 3866*/ 166001, // Rule ID 1604 // |
| 65483 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65484 | // (AArch64uzp1:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UZP1v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 65485 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1v8i16, |
| 65486 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65487 | // GIR_Coverage, 1604, |
| 65488 | GIR_Done, |
| 65489 | // Label 3866: @166001 |
| 65490 | GIM_Try, /*On fail goto*//*Label 3867*/ 166012, // Rule ID 4314 // |
| 65491 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65492 | // (AArch64uzp1:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (UZP1v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 65493 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1v8i16, |
| 65494 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65495 | // GIR_Coverage, 4314, |
| 65496 | GIR_Done, |
| 65497 | // Label 3867: @166012 |
| 65498 | GIM_Reject, |
| 65499 | // Label 3865: @166013 |
| 65500 | GIM_Reject, |
| 65501 | // Label 3850: @166014 |
| 65502 | GIM_Try, /*On fail goto*//*Label 3868*/ 166045, // Rule ID 1602 // |
| 65503 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65504 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 65505 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 65506 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 65507 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 65508 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 65509 | // (AArch64uzp1:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UZP1v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 65510 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP1v16i8, |
| 65511 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65512 | // GIR_Coverage, 1602, |
| 65513 | GIR_Done, |
| 65514 | // Label 3868: @166045 |
| 65515 | GIM_Reject, |
| 65516 | // Label 3851: @166046 |
| 65517 | GIM_Reject, |
| 65518 | // Label 93: @166047 |
| 65519 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 11, /*)*//*default:*//*Label 3876*/ 166354, |
| 65520 | /*GILLT_v2s32*//*Label 3869*/ 166060, |
| 65521 | /*GILLT_v2s64*//*Label 3870*/ 166106, |
| 65522 | /*GILLT_v4s16*//*Label 3871*/ 166152, |
| 65523 | /*GILLT_v4s32*//*Label 3872*/ 166198, |
| 65524 | /*GILLT_v8s8*//*Label 3873*/ 166244, |
| 65525 | /*GILLT_v8s16*//*Label 3874*/ 166276, |
| 65526 | /*GILLT_v16s8*//*Label 3875*/ 166322, |
| 65527 | // Label 3869: @166060 |
| 65528 | GIM_Try, /*On fail goto*//*Label 3877*/ 166105, |
| 65529 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 65530 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 65531 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 65532 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 65533 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 65534 | GIM_Try, /*On fail goto*//*Label 3878*/ 166093, // Rule ID 1612 // |
| 65535 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65536 | // (AArch64uzp2:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UZP2v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 65537 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2v2i32, |
| 65538 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65539 | // GIR_Coverage, 1612, |
| 65540 | GIR_Done, |
| 65541 | // Label 3878: @166093 |
| 65542 | GIM_Try, /*On fail goto*//*Label 3879*/ 166104, // Rule ID 4320 // |
| 65543 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65544 | // (AArch64uzp2:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (UZP2v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) |
| 65545 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2v2i32, |
| 65546 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65547 | // GIR_Coverage, 4320, |
| 65548 | GIR_Done, |
| 65549 | // Label 3879: @166104 |
| 65550 | GIM_Reject, |
| 65551 | // Label 3877: @166105 |
| 65552 | GIM_Reject, |
| 65553 | // Label 3870: @166106 |
| 65554 | GIM_Try, /*On fail goto*//*Label 3880*/ 166151, |
| 65555 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 65556 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 65557 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 65558 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 65559 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 65560 | GIM_Try, /*On fail goto*//*Label 3881*/ 166139, // Rule ID 1614 // |
| 65561 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65562 | // (AArch64uzp2:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (UZP2v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 65563 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2v2i64, |
| 65564 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65565 | // GIR_Coverage, 1614, |
| 65566 | GIR_Done, |
| 65567 | // Label 3881: @166139 |
| 65568 | GIM_Try, /*On fail goto*//*Label 3882*/ 166150, // Rule ID 4322 // |
| 65569 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65570 | // (AArch64uzp2:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (UZP2v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) |
| 65571 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2v2i64, |
| 65572 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65573 | // GIR_Coverage, 4322, |
| 65574 | GIR_Done, |
| 65575 | // Label 3882: @166150 |
| 65576 | GIM_Reject, |
| 65577 | // Label 3880: @166151 |
| 65578 | GIM_Reject, |
| 65579 | // Label 3871: @166152 |
| 65580 | GIM_Try, /*On fail goto*//*Label 3883*/ 166197, |
| 65581 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 65582 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 65583 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 65584 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 65585 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 65586 | GIM_Try, /*On fail goto*//*Label 3884*/ 166185, // Rule ID 1610 // |
| 65587 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65588 | // (AArch64uzp2:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UZP2v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 65589 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2v4i16, |
| 65590 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65591 | // GIR_Coverage, 1610, |
| 65592 | GIR_Done, |
| 65593 | // Label 3884: @166185 |
| 65594 | GIM_Try, /*On fail goto*//*Label 3885*/ 166196, // Rule ID 4318 // |
| 65595 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65596 | // (AArch64uzp2:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (UZP2v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 65597 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2v4i16, |
| 65598 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65599 | // GIR_Coverage, 4318, |
| 65600 | GIR_Done, |
| 65601 | // Label 3885: @166196 |
| 65602 | GIM_Reject, |
| 65603 | // Label 3883: @166197 |
| 65604 | GIM_Reject, |
| 65605 | // Label 3872: @166198 |
| 65606 | GIM_Try, /*On fail goto*//*Label 3886*/ 166243, |
| 65607 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 65608 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 65609 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 65610 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 65611 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 65612 | GIM_Try, /*On fail goto*//*Label 3887*/ 166231, // Rule ID 1613 // |
| 65613 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65614 | // (AArch64uzp2:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UZP2v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 65615 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2v4i32, |
| 65616 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65617 | // GIR_Coverage, 1613, |
| 65618 | GIR_Done, |
| 65619 | // Label 3887: @166231 |
| 65620 | GIM_Try, /*On fail goto*//*Label 3888*/ 166242, // Rule ID 4321 // |
| 65621 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65622 | // (AArch64uzp2:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (UZP2v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) |
| 65623 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2v4i32, |
| 65624 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65625 | // GIR_Coverage, 4321, |
| 65626 | GIR_Done, |
| 65627 | // Label 3888: @166242 |
| 65628 | GIM_Reject, |
| 65629 | // Label 3886: @166243 |
| 65630 | GIM_Reject, |
| 65631 | // Label 3873: @166244 |
| 65632 | GIM_Try, /*On fail goto*//*Label 3889*/ 166275, // Rule ID 1608 // |
| 65633 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65634 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 65635 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 65636 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 65637 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 65638 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 65639 | // (AArch64uzp2:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UZP2v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 65640 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2v8i8, |
| 65641 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65642 | // GIR_Coverage, 1608, |
| 65643 | GIR_Done, |
| 65644 | // Label 3889: @166275 |
| 65645 | GIM_Reject, |
| 65646 | // Label 3874: @166276 |
| 65647 | GIM_Try, /*On fail goto*//*Label 3890*/ 166321, |
| 65648 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 65649 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 65650 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 65651 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 65652 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 65653 | GIM_Try, /*On fail goto*//*Label 3891*/ 166309, // Rule ID 1611 // |
| 65654 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65655 | // (AArch64uzp2:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UZP2v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 65656 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2v8i16, |
| 65657 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65658 | // GIR_Coverage, 1611, |
| 65659 | GIR_Done, |
| 65660 | // Label 3891: @166309 |
| 65661 | GIM_Try, /*On fail goto*//*Label 3892*/ 166320, // Rule ID 4319 // |
| 65662 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65663 | // (AArch64uzp2:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (UZP2v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 65664 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2v8i16, |
| 65665 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65666 | // GIR_Coverage, 4319, |
| 65667 | GIR_Done, |
| 65668 | // Label 3892: @166320 |
| 65669 | GIM_Reject, |
| 65670 | // Label 3890: @166321 |
| 65671 | GIM_Reject, |
| 65672 | // Label 3875: @166322 |
| 65673 | GIM_Try, /*On fail goto*//*Label 3893*/ 166353, // Rule ID 1609 // |
| 65674 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65675 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 65676 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 65677 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 65678 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 65679 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 65680 | // (AArch64uzp2:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UZP2v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 65681 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::UZP2v16i8, |
| 65682 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65683 | // GIR_Coverage, 1609, |
| 65684 | GIR_Done, |
| 65685 | // Label 3893: @166353 |
| 65686 | GIM_Reject, |
| 65687 | // Label 3876: @166354 |
| 65688 | GIM_Reject, |
| 65689 | // Label 94: @166355 |
| 65690 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 11, /*)*//*default:*//*Label 3902*/ 166792, |
| 65691 | /*GILLT_s64*//*Label 3894*/ 166370, 0, |
| 65692 | /*GILLT_v2s32*//*Label 3895*/ 166456, |
| 65693 | /*GILLT_v2s64*//*Label 3896*/ 166504, |
| 65694 | /*GILLT_v4s16*//*Label 3897*/ 166552, |
| 65695 | /*GILLT_v4s32*//*Label 3898*/ 166600, |
| 65696 | /*GILLT_v8s8*//*Label 3899*/ 166648, |
| 65697 | /*GILLT_v8s16*//*Label 3900*/ 166696, |
| 65698 | /*GILLT_v16s8*//*Label 3901*/ 166744, |
| 65699 | // Label 3894: @166370 |
| 65700 | GIM_Try, /*On fail goto*//*Label 3903*/ 166455, |
| 65701 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 65702 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 65703 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 65704 | GIM_Try, /*On fail goto*//*Label 3904*/ 166419, // Rule ID 1777 // |
| 65705 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65706 | // MIs[0] imm |
| 65707 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 65708 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 65709 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 65710 | // MIs[1] Operand 1 |
| 65711 | // No operand predicates |
| 65712 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 65713 | // (AArch64vashr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (SSHRd:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 65714 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHRd, |
| 65715 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 65716 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 65717 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 65718 | GIR_EraseFromParent, /*InsnID*/0, |
| 65719 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65720 | // GIR_Coverage, 1777, |
| 65721 | GIR_Done, |
| 65722 | // Label 3904: @166419 |
| 65723 | GIM_Try, /*On fail goto*//*Label 3905*/ 166454, // Rule ID 4730 // |
| 65724 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65725 | // MIs[0] imm |
| 65726 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 65727 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 65728 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 65729 | // MIs[1] Operand 1 |
| 65730 | // No operand predicates |
| 65731 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 65732 | // (AArch64vashr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (SSHRd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) |
| 65733 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHRd, |
| 65734 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 65735 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 65736 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 65737 | GIR_EraseFromParent, /*InsnID*/0, |
| 65738 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65739 | // GIR_Coverage, 4730, |
| 65740 | GIR_Done, |
| 65741 | // Label 3905: @166454 |
| 65742 | GIM_Reject, |
| 65743 | // Label 3903: @166455 |
| 65744 | GIM_Reject, |
| 65745 | // Label 3895: @166456 |
| 65746 | GIM_Try, /*On fail goto*//*Label 3906*/ 166503, // Rule ID 1879 // |
| 65747 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65748 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 65749 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 65750 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 65751 | // MIs[0] imm |
| 65752 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 65753 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 65754 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, |
| 65755 | // MIs[1] Operand 1 |
| 65756 | // No operand predicates |
| 65757 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 65758 | // (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (SSHRv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 65759 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHRv2i32_shift, |
| 65760 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 65761 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 65762 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 65763 | GIR_EraseFromParent, /*InsnID*/0, |
| 65764 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65765 | // GIR_Coverage, 1879, |
| 65766 | GIR_Done, |
| 65767 | // Label 3906: @166503 |
| 65768 | GIM_Reject, |
| 65769 | // Label 3896: @166504 |
| 65770 | GIM_Try, /*On fail goto*//*Label 3907*/ 166551, // Rule ID 1881 // |
| 65771 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65772 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 65773 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 65774 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 65775 | // MIs[0] imm |
| 65776 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 65777 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 65778 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 65779 | // MIs[1] Operand 1 |
| 65780 | // No operand predicates |
| 65781 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 65782 | // (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (SSHRv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 65783 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHRv2i64_shift, |
| 65784 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 65785 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 65786 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 65787 | GIR_EraseFromParent, /*InsnID*/0, |
| 65788 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65789 | // GIR_Coverage, 1881, |
| 65790 | GIR_Done, |
| 65791 | // Label 3907: @166551 |
| 65792 | GIM_Reject, |
| 65793 | // Label 3897: @166552 |
| 65794 | GIM_Try, /*On fail goto*//*Label 3908*/ 166599, // Rule ID 1877 // |
| 65795 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65796 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 65797 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 65798 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 65799 | // MIs[0] imm |
| 65800 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 65801 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 65802 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, |
| 65803 | // MIs[1] Operand 1 |
| 65804 | // No operand predicates |
| 65805 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 65806 | // (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) => (SSHRv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 65807 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHRv4i16_shift, |
| 65808 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 65809 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 65810 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 65811 | GIR_EraseFromParent, /*InsnID*/0, |
| 65812 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65813 | // GIR_Coverage, 1877, |
| 65814 | GIR_Done, |
| 65815 | // Label 3908: @166599 |
| 65816 | GIM_Reject, |
| 65817 | // Label 3898: @166600 |
| 65818 | GIM_Try, /*On fail goto*//*Label 3909*/ 166647, // Rule ID 1880 // |
| 65819 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65820 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 65821 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 65822 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 65823 | // MIs[0] imm |
| 65824 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 65825 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 65826 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, |
| 65827 | // MIs[1] Operand 1 |
| 65828 | // No operand predicates |
| 65829 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 65830 | // (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (SSHRv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 65831 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHRv4i32_shift, |
| 65832 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 65833 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 65834 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 65835 | GIR_EraseFromParent, /*InsnID*/0, |
| 65836 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65837 | // GIR_Coverage, 1880, |
| 65838 | GIR_Done, |
| 65839 | // Label 3909: @166647 |
| 65840 | GIM_Reject, |
| 65841 | // Label 3899: @166648 |
| 65842 | GIM_Try, /*On fail goto*//*Label 3910*/ 166695, // Rule ID 1875 // |
| 65843 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65844 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 65845 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 65846 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 65847 | // MIs[0] imm |
| 65848 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 65849 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 65850 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, |
| 65851 | // MIs[1] Operand 1 |
| 65852 | // No operand predicates |
| 65853 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 65854 | // (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm) => (SSHRv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 65855 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHRv8i8_shift, |
| 65856 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 65857 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 65858 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 65859 | GIR_EraseFromParent, /*InsnID*/0, |
| 65860 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65861 | // GIR_Coverage, 1875, |
| 65862 | GIR_Done, |
| 65863 | // Label 3910: @166695 |
| 65864 | GIM_Reject, |
| 65865 | // Label 3900: @166696 |
| 65866 | GIM_Try, /*On fail goto*//*Label 3911*/ 166743, // Rule ID 1878 // |
| 65867 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65868 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 65869 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 65870 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 65871 | // MIs[0] imm |
| 65872 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 65873 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 65874 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, |
| 65875 | // MIs[1] Operand 1 |
| 65876 | // No operand predicates |
| 65877 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 65878 | // (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) => (SSHRv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 65879 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHRv8i16_shift, |
| 65880 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 65881 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 65882 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 65883 | GIR_EraseFromParent, /*InsnID*/0, |
| 65884 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65885 | // GIR_Coverage, 1878, |
| 65886 | GIR_Done, |
| 65887 | // Label 3911: @166743 |
| 65888 | GIM_Reject, |
| 65889 | // Label 3901: @166744 |
| 65890 | GIM_Try, /*On fail goto*//*Label 3912*/ 166791, // Rule ID 1876 // |
| 65891 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65892 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 65893 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 65894 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 65895 | // MIs[0] imm |
| 65896 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 65897 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 65898 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, |
| 65899 | // MIs[1] Operand 1 |
| 65900 | // No operand predicates |
| 65901 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 65902 | // (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm) => (SSHRv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 65903 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SSHRv16i8_shift, |
| 65904 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 65905 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 65906 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 65907 | GIR_EraseFromParent, /*InsnID*/0, |
| 65908 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65909 | // GIR_Coverage, 1876, |
| 65910 | GIR_Done, |
| 65911 | // Label 3912: @166791 |
| 65912 | GIM_Reject, |
| 65913 | // Label 3902: @166792 |
| 65914 | GIM_Reject, |
| 65915 | // Label 95: @166793 |
| 65916 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 11, /*)*//*default:*//*Label 3921*/ 167230, |
| 65917 | /*GILLT_s64*//*Label 3913*/ 166808, 0, |
| 65918 | /*GILLT_v2s32*//*Label 3914*/ 166894, |
| 65919 | /*GILLT_v2s64*//*Label 3915*/ 166942, |
| 65920 | /*GILLT_v4s16*//*Label 3916*/ 166990, |
| 65921 | /*GILLT_v4s32*//*Label 3917*/ 167038, |
| 65922 | /*GILLT_v8s8*//*Label 3918*/ 167086, |
| 65923 | /*GILLT_v8s16*//*Label 3919*/ 167134, |
| 65924 | /*GILLT_v16s8*//*Label 3920*/ 167182, |
| 65925 | // Label 3913: @166808 |
| 65926 | GIM_Try, /*On fail goto*//*Label 3922*/ 166893, |
| 65927 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 65928 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 65929 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 65930 | GIM_Try, /*On fail goto*//*Label 3923*/ 166857, // Rule ID 1785 // |
| 65931 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65932 | // MIs[0] imm |
| 65933 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 65934 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 65935 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 65936 | // MIs[1] Operand 1 |
| 65937 | // No operand predicates |
| 65938 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 65939 | // (AArch64vlshr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (USHRd:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 65940 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHRd, |
| 65941 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 65942 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 65943 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 65944 | GIR_EraseFromParent, /*InsnID*/0, |
| 65945 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65946 | // GIR_Coverage, 1785, |
| 65947 | GIR_Done, |
| 65948 | // Label 3923: @166857 |
| 65949 | GIM_Try, /*On fail goto*//*Label 3924*/ 166892, // Rule ID 4735 // |
| 65950 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65951 | // MIs[0] imm |
| 65952 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 65953 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 65954 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 65955 | // MIs[1] Operand 1 |
| 65956 | // No operand predicates |
| 65957 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 65958 | // (AArch64vlshr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (USHRd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) |
| 65959 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHRd, |
| 65960 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 65961 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 65962 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 65963 | GIR_EraseFromParent, /*InsnID*/0, |
| 65964 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65965 | // GIR_Coverage, 4735, |
| 65966 | GIR_Done, |
| 65967 | // Label 3924: @166892 |
| 65968 | GIM_Reject, |
| 65969 | // Label 3922: @166893 |
| 65970 | GIM_Reject, |
| 65971 | // Label 3914: @166894 |
| 65972 | GIM_Try, /*On fail goto*//*Label 3925*/ 166941, // Rule ID 1931 // |
| 65973 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65974 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 65975 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 65976 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 65977 | // MIs[0] imm |
| 65978 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 65979 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 65980 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, |
| 65981 | // MIs[1] Operand 1 |
| 65982 | // No operand predicates |
| 65983 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 65984 | // (AArch64vlshr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (USHRv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 65985 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHRv2i32_shift, |
| 65986 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 65987 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 65988 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 65989 | GIR_EraseFromParent, /*InsnID*/0, |
| 65990 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 65991 | // GIR_Coverage, 1931, |
| 65992 | GIR_Done, |
| 65993 | // Label 3925: @166941 |
| 65994 | GIM_Reject, |
| 65995 | // Label 3915: @166942 |
| 65996 | GIM_Try, /*On fail goto*//*Label 3926*/ 166989, // Rule ID 1933 // |
| 65997 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 65998 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 65999 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 66000 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 66001 | // MIs[0] imm |
| 66002 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 66003 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 66004 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR64, |
| 66005 | // MIs[1] Operand 1 |
| 66006 | // No operand predicates |
| 66007 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 66008 | // (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (USHRv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 66009 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHRv2i64_shift, |
| 66010 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 66011 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 66012 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 66013 | GIR_EraseFromParent, /*InsnID*/0, |
| 66014 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66015 | // GIR_Coverage, 1933, |
| 66016 | GIR_Done, |
| 66017 | // Label 3926: @166989 |
| 66018 | GIM_Reject, |
| 66019 | // Label 3916: @166990 |
| 66020 | GIM_Try, /*On fail goto*//*Label 3927*/ 167037, // Rule ID 1929 // |
| 66021 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66022 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 66023 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 66024 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 66025 | // MIs[0] imm |
| 66026 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 66027 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 66028 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, |
| 66029 | // MIs[1] Operand 1 |
| 66030 | // No operand predicates |
| 66031 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 66032 | // (AArch64vlshr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) => (USHRv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 66033 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHRv4i16_shift, |
| 66034 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 66035 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 66036 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 66037 | GIR_EraseFromParent, /*InsnID*/0, |
| 66038 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66039 | // GIR_Coverage, 1929, |
| 66040 | GIR_Done, |
| 66041 | // Label 3927: @167037 |
| 66042 | GIM_Reject, |
| 66043 | // Label 3917: @167038 |
| 66044 | GIM_Try, /*On fail goto*//*Label 3928*/ 167085, // Rule ID 1932 // |
| 66045 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66046 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 66047 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 66048 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 66049 | // MIs[0] imm |
| 66050 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 66051 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 66052 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR32, |
| 66053 | // MIs[1] Operand 1 |
| 66054 | // No operand predicates |
| 66055 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 66056 | // (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (USHRv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 66057 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHRv4i32_shift, |
| 66058 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 66059 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 66060 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 66061 | GIR_EraseFromParent, /*InsnID*/0, |
| 66062 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66063 | // GIR_Coverage, 1932, |
| 66064 | GIR_Done, |
| 66065 | // Label 3928: @167085 |
| 66066 | GIM_Reject, |
| 66067 | // Label 3918: @167086 |
| 66068 | GIM_Try, /*On fail goto*//*Label 3929*/ 167133, // Rule ID 1927 // |
| 66069 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66070 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 66071 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 66072 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 66073 | // MIs[0] imm |
| 66074 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 66075 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 66076 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, |
| 66077 | // MIs[1] Operand 1 |
| 66078 | // No operand predicates |
| 66079 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 66080 | // (AArch64vlshr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm) => (USHRv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 66081 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHRv8i8_shift, |
| 66082 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 66083 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 66084 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 66085 | GIR_EraseFromParent, /*InsnID*/0, |
| 66086 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66087 | // GIR_Coverage, 1927, |
| 66088 | GIR_Done, |
| 66089 | // Label 3929: @167133 |
| 66090 | GIM_Reject, |
| 66091 | // Label 3919: @167134 |
| 66092 | GIM_Try, /*On fail goto*//*Label 3930*/ 167181, // Rule ID 1930 // |
| 66093 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66094 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 66095 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 66096 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 66097 | // MIs[0] imm |
| 66098 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 66099 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 66100 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR16, |
| 66101 | // MIs[1] Operand 1 |
| 66102 | // No operand predicates |
| 66103 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 66104 | // (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) => (USHRv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 66105 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHRv8i16_shift, |
| 66106 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 66107 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 66108 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 66109 | GIR_EraseFromParent, /*InsnID*/0, |
| 66110 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66111 | // GIR_Coverage, 1930, |
| 66112 | GIR_Done, |
| 66113 | // Label 3930: @167181 |
| 66114 | GIM_Reject, |
| 66115 | // Label 3920: @167182 |
| 66116 | GIM_Try, /*On fail goto*//*Label 3931*/ 167229, // Rule ID 1928 // |
| 66117 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66118 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 66119 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 66120 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 66121 | // MIs[0] imm |
| 66122 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 66123 | GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 66124 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_vecshiftR8, |
| 66125 | // MIs[1] Operand 1 |
| 66126 | // No operand predicates |
| 66127 | GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 66128 | // (AArch64vlshr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm) => (USHRv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 66129 | GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::USHRv16i8_shift, |
| 66130 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd |
| 66131 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn |
| 66132 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 66133 | GIR_EraseFromParent, /*InsnID*/0, |
| 66134 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66135 | // GIR_Coverage, 1928, |
| 66136 | GIR_Done, |
| 66137 | // Label 3931: @167229 |
| 66138 | GIM_Reject, |
| 66139 | // Label 3921: @167230 |
| 66140 | GIM_Reject, |
| 66141 | // Label 96: @167231 |
| 66142 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 11, /*)*//*default:*//*Label 3939*/ 167538, |
| 66143 | /*GILLT_v2s32*//*Label 3932*/ 167244, |
| 66144 | /*GILLT_v2s64*//*Label 3933*/ 167290, |
| 66145 | /*GILLT_v4s16*//*Label 3934*/ 167336, |
| 66146 | /*GILLT_v4s32*//*Label 3935*/ 167382, |
| 66147 | /*GILLT_v8s8*//*Label 3936*/ 167428, |
| 66148 | /*GILLT_v8s16*//*Label 3937*/ 167460, |
| 66149 | /*GILLT_v16s8*//*Label 3938*/ 167506, |
| 66150 | // Label 3932: @167244 |
| 66151 | GIM_Try, /*On fail goto*//*Label 3940*/ 167289, |
| 66152 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 66153 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 66154 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 66155 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 66156 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 66157 | GIM_Try, /*On fail goto*//*Label 3941*/ 167277, // Rule ID 1619 // |
| 66158 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66159 | // (AArch64zip1:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (ZIP1v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 66160 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1v2i32, |
| 66161 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66162 | // GIR_Coverage, 1619, |
| 66163 | GIR_Done, |
| 66164 | // Label 3941: @167277 |
| 66165 | GIM_Try, /*On fail goto*//*Label 3942*/ 167288, // Rule ID 4325 // |
| 66166 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66167 | // (AArch64zip1:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (ZIP1v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) |
| 66168 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1v2i32, |
| 66169 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66170 | // GIR_Coverage, 4325, |
| 66171 | GIR_Done, |
| 66172 | // Label 3942: @167288 |
| 66173 | GIM_Reject, |
| 66174 | // Label 3940: @167289 |
| 66175 | GIM_Reject, |
| 66176 | // Label 3933: @167290 |
| 66177 | GIM_Try, /*On fail goto*//*Label 3943*/ 167335, |
| 66178 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 66179 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 66180 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 66181 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 66182 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 66183 | GIM_Try, /*On fail goto*//*Label 3944*/ 167323, // Rule ID 1621 // |
| 66184 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66185 | // (AArch64zip1:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (ZIP1v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 66186 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1v2i64, |
| 66187 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66188 | // GIR_Coverage, 1621, |
| 66189 | GIR_Done, |
| 66190 | // Label 3944: @167323 |
| 66191 | GIM_Try, /*On fail goto*//*Label 3945*/ 167334, // Rule ID 4327 // |
| 66192 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66193 | // (AArch64zip1:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (ZIP1v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) |
| 66194 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1v2i64, |
| 66195 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66196 | // GIR_Coverage, 4327, |
| 66197 | GIR_Done, |
| 66198 | // Label 3945: @167334 |
| 66199 | GIM_Reject, |
| 66200 | // Label 3943: @167335 |
| 66201 | GIM_Reject, |
| 66202 | // Label 3934: @167336 |
| 66203 | GIM_Try, /*On fail goto*//*Label 3946*/ 167381, |
| 66204 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 66205 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 66206 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 66207 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 66208 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 66209 | GIM_Try, /*On fail goto*//*Label 3947*/ 167369, // Rule ID 1617 // |
| 66210 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66211 | // (AArch64zip1:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (ZIP1v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 66212 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1v4i16, |
| 66213 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66214 | // GIR_Coverage, 1617, |
| 66215 | GIR_Done, |
| 66216 | // Label 3947: @167369 |
| 66217 | GIM_Try, /*On fail goto*//*Label 3948*/ 167380, // Rule ID 4323 // |
| 66218 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66219 | // (AArch64zip1:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (ZIP1v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 66220 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1v4i16, |
| 66221 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66222 | // GIR_Coverage, 4323, |
| 66223 | GIR_Done, |
| 66224 | // Label 3948: @167380 |
| 66225 | GIM_Reject, |
| 66226 | // Label 3946: @167381 |
| 66227 | GIM_Reject, |
| 66228 | // Label 3935: @167382 |
| 66229 | GIM_Try, /*On fail goto*//*Label 3949*/ 167427, |
| 66230 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 66231 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 66232 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 66233 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 66234 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 66235 | GIM_Try, /*On fail goto*//*Label 3950*/ 167415, // Rule ID 1620 // |
| 66236 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66237 | // (AArch64zip1:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (ZIP1v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 66238 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1v4i32, |
| 66239 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66240 | // GIR_Coverage, 1620, |
| 66241 | GIR_Done, |
| 66242 | // Label 3950: @167415 |
| 66243 | GIM_Try, /*On fail goto*//*Label 3951*/ 167426, // Rule ID 4326 // |
| 66244 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66245 | // (AArch64zip1:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (ZIP1v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) |
| 66246 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1v4i32, |
| 66247 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66248 | // GIR_Coverage, 4326, |
| 66249 | GIR_Done, |
| 66250 | // Label 3951: @167426 |
| 66251 | GIM_Reject, |
| 66252 | // Label 3949: @167427 |
| 66253 | GIM_Reject, |
| 66254 | // Label 3936: @167428 |
| 66255 | GIM_Try, /*On fail goto*//*Label 3952*/ 167459, // Rule ID 1615 // |
| 66256 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66257 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 66258 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 66259 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 66260 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 66261 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 66262 | // (AArch64zip1:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (ZIP1v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 66263 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1v8i8, |
| 66264 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66265 | // GIR_Coverage, 1615, |
| 66266 | GIR_Done, |
| 66267 | // Label 3952: @167459 |
| 66268 | GIM_Reject, |
| 66269 | // Label 3937: @167460 |
| 66270 | GIM_Try, /*On fail goto*//*Label 3953*/ 167505, |
| 66271 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 66272 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 66273 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 66274 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 66275 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 66276 | GIM_Try, /*On fail goto*//*Label 3954*/ 167493, // Rule ID 1618 // |
| 66277 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66278 | // (AArch64zip1:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (ZIP1v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 66279 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1v8i16, |
| 66280 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66281 | // GIR_Coverage, 1618, |
| 66282 | GIR_Done, |
| 66283 | // Label 3954: @167493 |
| 66284 | GIM_Try, /*On fail goto*//*Label 3955*/ 167504, // Rule ID 4324 // |
| 66285 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66286 | // (AArch64zip1:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (ZIP1v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 66287 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1v8i16, |
| 66288 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66289 | // GIR_Coverage, 4324, |
| 66290 | GIR_Done, |
| 66291 | // Label 3955: @167504 |
| 66292 | GIM_Reject, |
| 66293 | // Label 3953: @167505 |
| 66294 | GIM_Reject, |
| 66295 | // Label 3938: @167506 |
| 66296 | GIM_Try, /*On fail goto*//*Label 3956*/ 167537, // Rule ID 1616 // |
| 66297 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66298 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 66299 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 66300 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 66301 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 66302 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 66303 | // (AArch64zip1:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (ZIP1v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 66304 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP1v16i8, |
| 66305 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66306 | // GIR_Coverage, 1616, |
| 66307 | GIR_Done, |
| 66308 | // Label 3956: @167537 |
| 66309 | GIM_Reject, |
| 66310 | // Label 3939: @167538 |
| 66311 | GIM_Reject, |
| 66312 | // Label 97: @167539 |
| 66313 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 11, /*)*//*default:*//*Label 3964*/ 167846, |
| 66314 | /*GILLT_v2s32*//*Label 3957*/ 167552, |
| 66315 | /*GILLT_v2s64*//*Label 3958*/ 167598, |
| 66316 | /*GILLT_v4s16*//*Label 3959*/ 167644, |
| 66317 | /*GILLT_v4s32*//*Label 3960*/ 167690, |
| 66318 | /*GILLT_v8s8*//*Label 3961*/ 167736, |
| 66319 | /*GILLT_v8s16*//*Label 3962*/ 167768, |
| 66320 | /*GILLT_v16s8*//*Label 3963*/ 167814, |
| 66321 | // Label 3957: @167552 |
| 66322 | GIM_Try, /*On fail goto*//*Label 3965*/ 167597, |
| 66323 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, |
| 66324 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, |
| 66325 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 66326 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 66327 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 66328 | GIM_Try, /*On fail goto*//*Label 3966*/ 167585, // Rule ID 1626 // |
| 66329 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66330 | // (AArch64zip2:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (ZIP2v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) |
| 66331 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2v2i32, |
| 66332 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66333 | // GIR_Coverage, 1626, |
| 66334 | GIR_Done, |
| 66335 | // Label 3966: @167585 |
| 66336 | GIM_Try, /*On fail goto*//*Label 3967*/ 167596, // Rule ID 4330 // |
| 66337 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66338 | // (AArch64zip2:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (ZIP2v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) |
| 66339 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2v2i32, |
| 66340 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66341 | // GIR_Coverage, 4330, |
| 66342 | GIR_Done, |
| 66343 | // Label 3967: @167596 |
| 66344 | GIM_Reject, |
| 66345 | // Label 3965: @167597 |
| 66346 | GIM_Reject, |
| 66347 | // Label 3958: @167598 |
| 66348 | GIM_Try, /*On fail goto*//*Label 3968*/ 167643, |
| 66349 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 66350 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 66351 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 66352 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 66353 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 66354 | GIM_Try, /*On fail goto*//*Label 3969*/ 167631, // Rule ID 1628 // |
| 66355 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66356 | // (AArch64zip2:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (ZIP2v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) |
| 66357 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2v2i64, |
| 66358 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66359 | // GIR_Coverage, 1628, |
| 66360 | GIR_Done, |
| 66361 | // Label 3969: @167631 |
| 66362 | GIM_Try, /*On fail goto*//*Label 3970*/ 167642, // Rule ID 4332 // |
| 66363 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66364 | // (AArch64zip2:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (ZIP2v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) |
| 66365 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2v2i64, |
| 66366 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66367 | // GIR_Coverage, 4332, |
| 66368 | GIR_Done, |
| 66369 | // Label 3970: @167642 |
| 66370 | GIM_Reject, |
| 66371 | // Label 3968: @167643 |
| 66372 | GIM_Reject, |
| 66373 | // Label 3959: @167644 |
| 66374 | GIM_Try, /*On fail goto*//*Label 3971*/ 167689, |
| 66375 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, |
| 66376 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, |
| 66377 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 66378 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 66379 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 66380 | GIM_Try, /*On fail goto*//*Label 3972*/ 167677, // Rule ID 1624 // |
| 66381 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66382 | // (AArch64zip2:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (ZIP2v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) |
| 66383 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2v4i16, |
| 66384 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66385 | // GIR_Coverage, 1624, |
| 66386 | GIR_Done, |
| 66387 | // Label 3972: @167677 |
| 66388 | GIM_Try, /*On fail goto*//*Label 3973*/ 167688, // Rule ID 4328 // |
| 66389 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66390 | // (AArch64zip2:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (ZIP2v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) |
| 66391 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2v4i16, |
| 66392 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66393 | // GIR_Coverage, 4328, |
| 66394 | GIR_Done, |
| 66395 | // Label 3973: @167688 |
| 66396 | GIM_Reject, |
| 66397 | // Label 3971: @167689 |
| 66398 | GIM_Reject, |
| 66399 | // Label 3960: @167690 |
| 66400 | GIM_Try, /*On fail goto*//*Label 3974*/ 167735, |
| 66401 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 66402 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 66403 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 66404 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 66405 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 66406 | GIM_Try, /*On fail goto*//*Label 3975*/ 167723, // Rule ID 1627 // |
| 66407 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66408 | // (AArch64zip2:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (ZIP2v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) |
| 66409 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2v4i32, |
| 66410 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66411 | // GIR_Coverage, 1627, |
| 66412 | GIR_Done, |
| 66413 | // Label 3975: @167723 |
| 66414 | GIM_Try, /*On fail goto*//*Label 3976*/ 167734, // Rule ID 4331 // |
| 66415 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66416 | // (AArch64zip2:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (ZIP2v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) |
| 66417 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2v4i32, |
| 66418 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66419 | // GIR_Coverage, 4331, |
| 66420 | GIR_Done, |
| 66421 | // Label 3976: @167734 |
| 66422 | GIM_Reject, |
| 66423 | // Label 3974: @167735 |
| 66424 | GIM_Reject, |
| 66425 | // Label 3961: @167736 |
| 66426 | GIM_Try, /*On fail goto*//*Label 3977*/ 167767, // Rule ID 1622 // |
| 66427 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66428 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, |
| 66429 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, |
| 66430 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR64RegClassID, |
| 66431 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR64RegClassID, |
| 66432 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR64RegClassID, |
| 66433 | // (AArch64zip2:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (ZIP2v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) |
| 66434 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2v8i8, |
| 66435 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66436 | // GIR_Coverage, 1622, |
| 66437 | GIR_Done, |
| 66438 | // Label 3977: @167767 |
| 66439 | GIM_Reject, |
| 66440 | // Label 3962: @167768 |
| 66441 | GIM_Try, /*On fail goto*//*Label 3978*/ 167813, |
| 66442 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 66443 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 66444 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 66445 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 66446 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 66447 | GIM_Try, /*On fail goto*//*Label 3979*/ 167801, // Rule ID 1625 // |
| 66448 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66449 | // (AArch64zip2:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (ZIP2v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) |
| 66450 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2v8i16, |
| 66451 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66452 | // GIR_Coverage, 1625, |
| 66453 | GIR_Done, |
| 66454 | // Label 3979: @167801 |
| 66455 | GIM_Try, /*On fail goto*//*Label 3980*/ 167812, // Rule ID 4329 // |
| 66456 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66457 | // (AArch64zip2:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (ZIP2v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) |
| 66458 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2v8i16, |
| 66459 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66460 | // GIR_Coverage, 4329, |
| 66461 | GIR_Done, |
| 66462 | // Label 3980: @167812 |
| 66463 | GIM_Reject, |
| 66464 | // Label 3978: @167813 |
| 66465 | GIM_Reject, |
| 66466 | // Label 3963: @167814 |
| 66467 | GIM_Try, /*On fail goto*//*Label 3981*/ 167845, // Rule ID 1623 // |
| 66468 | GIM_CheckFeatures, GIFBS_HasNEON, |
| 66469 | GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 66470 | GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 66471 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::FPR128RegClassID, |
| 66472 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::FPR128RegClassID, |
| 66473 | GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::FPR128RegClassID, |
| 66474 | // (AArch64zip2:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (ZIP2v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) |
| 66475 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::ZIP2v16i8, |
| 66476 | GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 66477 | // GIR_Coverage, 1623, |
| 66478 | GIR_Done, |
| 66479 | // Label 3981: @167845 |
| 66480 | GIM_Reject, |
| 66481 | // Label 3964: @167846 |
| 66482 | GIM_Reject, |
| 66483 | // Label 98: @167847 |
| 66484 | GIM_Reject, |
| 66485 | }; |
| 66486 | return MatchTable0; |
| 66487 | } |
| 66488 | #endif // ifdef GET_GLOBALISEL_IMPL |
| 66489 | #ifdef GET_GLOBALISEL_PREDICATES_DECL |
| 66490 | PredicateBitset AvailableModuleFeatures; |
| 66491 | mutable PredicateBitset AvailableFunctionFeatures; |
| 66492 | PredicateBitset getAvailableFeatures() const { |
| 66493 | return AvailableModuleFeatures | AvailableFunctionFeatures; |
| 66494 | } |
| 66495 | PredicateBitset |
| 66496 | computeAvailableModuleFeatures(const AArch64Subtarget *Subtarget) const; |
| 66497 | PredicateBitset |
| 66498 | computeAvailableFunctionFeatures(const AArch64Subtarget *Subtarget, |
| 66499 | const MachineFunction *MF) const; |
| 66500 | void setupGeneratedPerFunctionState(MachineFunction &MF) override; |
| 66501 | #endif // ifdef GET_GLOBALISEL_PREDICATES_DECL |
| 66502 | #ifdef GET_GLOBALISEL_PREDICATES_INIT |
| 66503 | AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)), |
| 66504 | AvailableFunctionFeatures() |
| 66505 | #endif // ifdef GET_GLOBALISEL_PREDICATES_INIT |
| 66506 | |